2.

1 Multiplekser 2 ke 1 dataflow
//Design
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_2to1 is
port(

A,B : in STD_LOGIC;
S: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux_2to1;

architecture dataflow of mux_2to1 is

begin
Z <= (a and not s) or (s and b);
end dataflow;

//Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY testbench_mux IS
END testbench_mux;

ARCHITECTURE dataflow OF testbench_mux IS

COMPONENT mux_2to1
PORT(
A : IN std_logic;
B : IN std_logic;
S : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;

signal A : std_logic;
signal B : std_logic;
signal S : std_logic;
signal Z : std_logic;

BEGIN
uut: mux_2to1 PORT MAP (
A => A,
 B => B,
S => S,
Z => Z
);

stim_proc: process
begin
A <='1';
B <='0';
S <='1';
wait;
end process;
END;

//Simulasi

2.2 Multiplekser 2 ke 1 2bit dataflow

//Design
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_2to1_2bit is
port(

A,B : in STD_LOGIC_VECTOR(1 downto 0);

S: in STD_LOGIC_VECTOR(1 downto 0);
Z: out STD_LOGIC_VECTOR(1 downto 0)
);
end mux_2to1_2bit;

architecture dataflow of mux_2to1_2bit is

begin
Z <= (a and not s) or (s and b);
end dataflow;

//Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY testbench_mux1 IS
END testbench_mux1;

ARCHITECTURE dataflow OF testbench_mux1 IS

COMPONENT mux_2to1_2bit
PORT(
A : IN std_logic_vector(1 downto 0);
B : IN std_logic_vector(1 downto 0);
S : IN std_logic_vector(1 downto 0);
Z : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;

signal A : std_logic_vector(1 downto 0);

signal B : std_logic_vector(1 downto 0);
signal S : std_logic_vector(1 downto 0);
signal Z : std_logic_vector(1 downto 0);

BEGIN
uut: mux_2to1_2bit PORT MAP (
A => A,
B => B,
S => S,
Z => Z
);

stim_proc: process
begin
A <="11";
B <="01";
S <="00";
wait;
end process;
END;

//Simulasi

2.3 Multiplekser 2 ke 1 struktural

//Design
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_gate is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end and_gate;

architecture and_new of and_gate is

begin
c <= a and b;
end and_new;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity not_gate is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC
);
end not_gate;

architecture not_new of not_gate is

begin
b <= not a;
end not_new;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_gate is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end or_gate;

architecture or_new of or_gate is

begin
c <= a or b;
end or_new;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2to1_2bit is
Port ( i0,i1,i2,i3,s : in STD_LOGIC;
m1,m2 : out STD_LOGIC);
end mux2to1_2bit;

architecture mux2to1_2bit_arch of mux2to1_2bit is

component and_gate
Port ( a,b : in STD_LOGIC;
 c : out STD_LOGIC);
end component;

component or_gate
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end component;

component not_gate
Port ( a : in STD_LOGIC;
b : out STD_LOGIC
);
end component;
signal out_and1, out_and2, out_and3, out_and4, not_out1, not_out2 : STD_LOGIC;

begin
and_one : and_gate port map(
a => i0,
b => s,
c => out_and1);
not_one : not_gate port map(
a => s,
b => not_out1
);
and_two : and_gate port map(
a => i1,
b => not_out1,
c => out_and2);
and_three : and_gate port map(
a => i2,
b => s,
c => out_and3);
not_two : not_gate port map(
a => s,
b => not_out2
);
and_four : and_gate port map(
a => i3,
b => not_out2,
c => out_and4);
or_opt1 : or_gate port map(
a => out_and1,
b => out_and2,
c => m1);
or_opt2 : or_gate port map(
 a => out_and3,
b => out_and4,
c => m2);
end mux2to1_2bit_arch;

//Testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity testbench_mux is
-- Port ( );
end testbench_mux;

architecture structural of testbench_mux is

Component mux2to1_2bit
Port ( i0,i1,i2,i3,s : in STD_LOGIC;
m1,m2 : out STD_LOGIC);
End Component;

Signal m_int : STD_LOGIC_VECTOR(1 downto 0) := "00";

Signal s_int : STD_LOGIC := '0';
Signal x_int : STD_LOGIC_VECTOR(1 downto 0) := "00";
Signal y_int : STD_LOGIC_VECTOR(1 downto 0) := "00";

begin
uut: mux2to1_2bit PORT MAP (
i0 => x_int(0),
i1 => y_int(0),
i2 => x_int(1),
i3 => y_int(1),
s => s_int,
m1 => m_int(0),
m2 => m_int(1)
);

process

begin
wait for 100 ns; x_int <= "01";s_int <= '0';
wait for 100 ns; y_int <= "01";
wait for 100 ns; x_int <= "11"; y_int <= "00";
wait for 100 ns; x_int <= "10"; y_int <= "11";
wait for 100 ns; x_int <= "01";s_int <= '1';
wait for 100 ns; x_int <= "01";
wait for 100 ns; x_int <= "01";
wait for 100 ns; x_int <= "01"; y_int <= "00";
 wait for 100 ns; x_int <= "01"; y_int <= "11";
wait for 100 ns;

end process;
end structural;

//Simulasi

2.4 Multiplekser 2 ke 1 behavior

//Design
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_2to1 is
port(

A,B : in STD_LOGIC;
S: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux_2to1;

architecture behavior of mux_2to1 is

begin
process (A,B,S) is
begin
if (S ='0') then
Z <= A;
else
Z <= B;
end if;

end process;
end behavior;

//Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY testbench_mux IS
END testbench_mux;

ARCHITECTURE behavior OF testbench_mux IS

COMPONENT mux_2to1
PORT(
A : IN std_logic;
B : IN std_logic;
S : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;

signal A : std_logic;
signal B : std_logic;
signal S : std_logic;
signal Z : std_logic;

BEGIN
uut: mux_2to1 PORT MAP (
A => A,
B => B,
S => S,
Z => Z
);

stim_proc: process
begin

A <= '1';
B <= '0';

S <= '0';
wait for 100 ns;
S <= '1';
wait for 100 ns;
wait;
end process;

END;

//Simulasi
2.5 Multiplekser 2 ke 1 2bit behavior
//Design
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_2to1_2bitwide is
port(

A,B : in STD_LOGIC_VECTOR(1 downto 0);

S: in STD_LOGIC;
Z: out STD_LOGIC_VECTOR(1 downto 0)
);
end mux_2to1_2bitwide;

architecture behavior of mux_2to1_2bitwide is

begin
process (A,B,S) is
begin
if (S ='0') then
Z <= A;
else
Z <= B;
end if;

end process;
end behavior;

//Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY testbench_mux IS
END testbench_mux;

ARCHITECTURE behavior OF testbench_mux IS

COMPONENT mux_2to1_2bitwide
PORT(
A : IN std_logic_vector(1 downto 0);
 B : IN std_logic_vector(1 downto 0);
S : IN std_logic;
Z : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;

signal A : std_logic_vector(1 downto 0);

signal B : std_logic_vector(1 downto 0);
signal S : std_logic;
signal Z : std_logic_vector(1 downto 0);

BEGIN
uut: mux_2to1_2bitwide PORT MAP (
A => A,
B => B,
S => S,
Z => Z
);

stim_proc: process
begin

A <= "10";
B <= "11";

S <= '0';
wait for 100 ns;
S <= '1';
wait for 100 ns;
wait;
end process;

END;
//Simulasi

2.6 BCD to 7 segment

//Design
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity numsys is
Port(
m : in STD_LOGIC_VECTOR(3 downto 0);
a : out STD_LOGIC;
b : out STD_LOGIC;
c : out STD_LOGIC;
d : out STD_LOGIC;
e : out STD_LOGIC;
f : out STD_LOGIC;
g : out STD_LOGIC
);
end numsys;

architecture Behavioral of numsys is

begin
process(m)
begin
case m is
when "0000" => a <= '0';b <= '0';c <= '0';d <= '0';e <= '0';f <= '0';g <= '1';
when "0001" => a <= '1';b <= '0';c <= '0';d <= '1';e <= '1';f <= '1';g <= '1';
when "0010" => a <= '0';b <= '0';c <= '1';d <= '0';e <= '0';f <= '1';g <= '0';
when "0011" => a <= '0';b <= '0';c <= '0';d <= '0';e <= '1';f <= '1';g <= '0';
when "0100" => a <= '1';b <= '0';c <= '0';d <= '1';e <= '1';f <= '0';g <= '0';
when "0101" => a <= '0';b <= '1';c <= '0';d <= '0';e <= '1';f <= '0';g <= '0';
when "0110" => a <= '0';b <= '1';c <= '0';d <= '0';e <= '0';f <= '0';g <= '0';
when "0111" => a <= '0';b <= '0';c <= '0';d <= '1';e <= '1';f <= '1';g <= '1';
when "1000" => a <= '0';b <= '0';c <= '0';d <= '0';e <= '0';f <= '0';g <= '0';
when "1001" => a <= '0';b <= '0';c <= '0';d <= '0';e <= '1';f <= '0';g <= '0';
when "1010" => a <= '0';b <= '0';c <= '0';d <= '1';e <= '0';f <= '0';g <= '0';
when "1011" => a <= '1';b <= '1';c <= '0';d <= '0';e <= '0';f <= '0';g <= '0';
when "1100" => a <= '1';b <= '1';c <= '1';d <= '0';e <= '0';f <= '1';g <= '0';
when "1101" => a <= '1';b <= '0';c <= '0';d <= '0';e <= '0';f <= '1';g <= '0';
when "1110" => a <= '0';b <= '1';c <= '1';d <= '0';e <= '0';f <= '0';g <= '0';
when "1111" => a <= '0';b <= '1';c <= '1';d <= '1';e <= '0';f <= '0';g <= '0';
end case;
end process;
end Behavioral;