2017 International Conference on Intelligent Computing and Control (I2C2)

Comparative Study Of SPWM And SVPWM

Cascaded H-bridge Multilevel Inverter
Akshay S. Kale
PG Student, Department of
Electrical Engineering, SIT,
Lonavala, Maharashtra, India
er.akshaykale@gmail.com
A. V. Tamhane
Asst. Professor, Department of
Electrical Engineering, SIT,
Lonavala, Maharashtra, India
avt.sit@sinhagad.edu
Dr. A. A Kalage
Asso. Professor, Department of
Electrical Engineering, SIT,
Lonavala, Maharashtra, India
aak.sit@sinhagad.edu

Abstract- Large electric drives and utility applications
require modern power electronics converter like cascaded
H-bridge multilevel inverter (CHB) with separated DC
sources is clearly the most practical topology for use as a
power converter for medium & high power applications
due to their modularization and extensibility. The H-
bridge inverter eliminates the large number of bulky
transformers, clamping diodes and flying capacitors.
Cascaded multilevel inverter (MLI) is contemplated to be
suitable for medium & high power applications.
There are many pulse-width modulation (PWM)
techniques developed for controlling multilevel inverter,
among these, SVM is the most popular one due to its
simplicity both in hardware and software. But the SVM
becomes very difficult to achieve when the levels increases.
To simplify the SVM at high level, several improved
methods have been proposed in many literatures. In this
report, SPWM and SVPWM controlled cascaded H-
bridge multilevel inverter for large motor drives is
designed, analysed and compared with conventional
inverter, by simulating in MATLAB simulink software.
Keywords: 3 phase induction motor drives, H-bridge
multilevel inverter, pulse-width modulation (PWM)
I. INTRODUCTION
In many industrial applications, large electrical drives
require medium voltage and high power. Nowadays
power semiconductor switches support around high
voltage and current of around 6.5 kV and 2.5 kA
respectively. There are many problems like poor power
quality, high dv/dt stresses, high common mode noise
and stresses on motors with the use of conventional 2-
level inverter topologies and high-voltage
semiconductors. Multilevel power inverter structure has
been introduced in high power and medium voltage
situations. Output of MLI has good power quality. A
multilevel converter achieves high power ratings and
also improves the performance of the whole system in
terms of power quality, dv/dt stresses, and stresses in
the bearings of a motor. Several multilevel converter
topologies have been developed. The cascaded H-
bridge MLI with separated DC sources is clearly the
most practical topology for use as a power converter for
medium & high power applications due to their
modularization and extensibility. The H-bridge inverter
eliminates the large number of bulky transformers,
clamping diodes and flying capacitors. Cascaded MLI
is contemplated to be suitable for medium & high
power applications. There are many PWM based
techniques developed for controlling MLI, among
these, SVM is the most popular one due to its simplicity
both in hardware and software, and its comparatively
good performance at low modulation ratio.
II. MULTILEVEL INVERTER
The power electronics device which converts DC
power to AC power at required output voltage and
frequency level is known as inverter. Inverters can
be broadly classified into two-level inverter and
MLIs.. MLIs as compared to two-level inverters
have advantages like minimum harmonic
distortion, reduced EMI/EMC generation and can
operate on several voltage levels. A MLI is being
utilized for multipurpose applications, such as
active power filters, static VAR compensators and
machine drives. The drawbacks are the isolated
power supplies required for each one of the stages
of the MLI and it is also more expensive, to build
and to control in software. [1]
The aim of a MLI is to achieve higher power using
a series of power semiconductor switches with
many lower voltage dc sources. Inverters obtain
DC-AC power conversion by synthesizing a
staircase voltage waveform for harmonic
reduction. Capacitors, batteries, and renewable
energy sources can be accessed as the multi-point
DC voltage sources. [2] The switching of the
power switches adds these multiple dc sources in
order to achieve greater voltage at the output. The
rating of semiconductor switches depends only
upon the capacity of the dc voltage sources to
which they are connected [3-4].
 2017 International Conference on Intelligent Computing and Control (I2C2)
Fig- 1 One phase leg of an inverter with
(a) 3 levels, and (b) n levels
The attractive features of a multilevel converter
are as follows, [5-6]
1. Staircase waveform quality: reduce the dv/dt
stresses; electromagnetic compatibility (EMC)
problems are reduced.
2. Less Common-mode (CM) voltage: Multilevel
converters produce smaller CM voltage
avoiding noise;
3. Input current: Multilevel converters can draw
input current with low distortion.
4. Switching frequency: Multilevel converters can
switch at fundamental frequency and high
switching frequency PWM. It should be noted
that lower switching frequency usually means
lower switching loss and higher efficiency.
MLI do have some disadvantages. One particular
disadvantage is the greater number of power
semiconductor switches needed. Though lower
voltage rated switches can be used but each switch
requires a related gate drive circuit. This may
cause the overall system to be more expensive and
complex. [7-8] The various topologies of MLI are
Cascaded H-bridge (CHB), Diode Clamped or
Neutral Point-Clamped (NPC) and Capacitor
Clamped or Flying Capacitor (FC) [9]
III. MODULATION TECHNIQUES FOR INVERTER
The fundamental methods based on PWM are
divided into the orthodox once and recent method
by using current-regulation. Voltage-source
methods are easy to implement on digital signal
processor (DSP) or programmable logic device
(PLD). However, current controls typically depend
on event scheduling and are therefore analog
implementations which can only be reliably
operated up to a certain power level. In discrete
current-regulated methods the harmonic
performance is not as good as that of voltage-
source methods.Voltage-source modulation has
taken two major paths; sine triangle PWM
(SPWM) in the time domain and space vector
PWM (SVPWM) in the q-d stationary reference
frame. [10-11]
A. Sine PWM (SPWM)
The SPWM schemes for MLIs can be generally
classified into two categories: Phase-shifted
modulations and Level-shifted modulations. Both
modulation schemes can be applied to the
cascaded H-bridge (CHB) inverters. THD of
phase-shifted modulation is much higher than
level-shifted modulation. A n-level CHB inverter
using level-shifted multicarrier modulation scheme
requires (n-1) triangular carriers, all having
frequency fc and amplitude Ac. The reference
waveform has peak-to-peak amplitude Am, a
frequency fm. The reference is continuously
compared with each of the carrier signals. The (n-
1) triangular carriers are vertically disposed such
that the bands they occupy are contiguous. In
MLIs, the amplitude modulation index, ma, and the
frequency ratio, mf, are defined as,
ma= Am /((n-1) *Ac)
There are three alternative PWM strategies with
different phase relationships for the level-shifted
multicarrier modulation [12-13]:In-phase
disposition (IPD), Phase opposition disposition
(POD), Alternate phase disposition (APOD)
B. Space Vector PWM (SVPWM)
Among all modulation techniques for MLI,
SVPWM is the most popular one, as,
Ɣ It has simplicity both in hardware and software.
Ɣ Low current ripple.
Ɣ It directly uses the control variable given by the
control system, and identifies each switching
vector as a point in complex space.
Ɣ It is useful in improving dc link voltage
utilization.
Ɣ It has low commutation losses and THD.
Ɣ It is suitable for digital signal processing (DSP)
implementation.
Ɣ Good performance at low modulation ratio.
These features make it suitable for high-voltage
high-power applications. The SVM technique can
be easily extended to all MLI. In multi-level
inverter, SVPWM implementation is very complex
than two-level inverter. As shown in fig. 4, when
 2017 International Conference on Intelligent Computing and Control (I2C2)

level increases, the increased number of triangles,

switching states and calculation of ON-times adds
to the complexity of SVPWM for MLIs [14]. For n
level inverter,
No. of switching state = n3
No. of triangle per sector = (n-1)2
To simplify the SVM, several two level based
methods have been proposed in recent years: such
as decomposing the multilevel SVM to two-level
SVMs, implementing the SVM in a 60-degree
Fig-2 MATLAB circuit of 3-level inverter fed IM
coordinates. However, it is complex in some steps
yet, such as selection of switching-state. The
studies in [11-15] proposed a general method to
obtain ON-times for the SVPWM of MLIs. This
method is recent and has many advantages over
the other two-level based approach. Basis concept
of this method is that, any triangle in space vector
diagram of any n-level inverter is identical to a
sector of two-level inverter. So, space vector
diagram of MLIs can decompose into two-level
inverter and then ON time calculation is similar to
two-level inverter.
Fig- 3- SPWM pulse generator block
IV. SIMULATION IN MATLAB
TABLE 1- DEFINITION OF SWITCHING STATES IN 3-LEVEL
The performance of the proposed CHB-MLI fed INVERTER
adjustable-speed 2.3 kV IM drive is simulated. State Device Switching Status (Phase A) Inv
The inverter thus generates the variable-amplitude, Volt
variable frequency voltage waveforms to drive the S1 S2 S3 S4
induction motor. The MATLAB R2010b-simulink 1 On On Off Off Vdc
is used to simulate 3 and 5- level inverter fed
0 Off On On Off 0
induction motor drives. The inverter is modulated
by both SPWM and SVPWM -1 Off Off On On -Vdc

A. 3-Level inverter fed IM Drive B. 5-Level inverter fed IM Drive

The MATLAB simulation circuit of 3-phase 3-
level inverter to drive induction motor is shown in
Figure 2, Table 1 shows switching status of three-
level inverter for leg A. Leg B and leg C have the
same concept. When switching state is ‘1’, it is
indicated that means the voltage for AC terminal
with respect to the neutral point is +Vdc, whereas ‘-
1’ denotes that -Vdc. When switching state ‘0’, it
indicates that the two switches S2 and S3 are on
and output is zero. Figure-3 shows simulation
block which generates the SPWM signals.

Fig-4 Subsystem of SVPWM in 5-level inverter

Figure 4 shows MATLAB simulation circuit of 3-

phase 5-level inverter to drive an induction motor.
 2017 International Conference on Intelligent Computing and Control (I2C2)

Table-2 shows switching status of five-level

inverter for leg A. Leg B and leg C have the same
concept. When switching state is ‘2’, it is indicated
that means the voltage for AC terminal with
respect to the neutral point is +2Vdc, whereas ‘-2’
denotes that -2Vdc. When switching state ‘1’, it
indicates that the voltage for AC terminal with
respect to the neutral point is +Vdc, whereas ‘-1’
denotes that -Vdc. Figure-4 shows that MATLAB
subsystem of SPWM pulse generator block. The
MATLAB subsystem of SVPWM pulse generator Fig-5- Typical output waveforms for 3-level and 5-level
block, in which pulses are generated by using inverter fed motor drives
SVPWM algorithm.
TABLE 2- DEFINITION OF SWITCHING STATES
IN 3-LEVEL INVERTER

State Device Switching Status (Phase A) Volt

Upper HB cell Lower HB cell

S1 S2 S3 S4 S1 S2 S3 S4

2 1 1 0 0 1 1 0 0 2Vdc
Figure 6- Torque & Rotor Speed output waveforms for
1 0 1 1 0 1 1 0 0 Vdc 3-level and 5-level inverter fed motor drives.

0 0 0 1 1 1 1 0 0 0

-1 0 0 1 1 0 1 1 0 -Vdc

-2 0 0 1 1 0 0 1 1 -2Vdc

V. RESULT ANALYSIS
Figure 5 shows, a comparison between 3-level and
5-level inverter, the phase voltage, line voltage, Fig-7- FFT analysis of output voltage of, three-level
and five-level inverter by SPWM
and load current. Even with a 3-level topology, the
output voltages and currents of a MLIs is
superiority with respect to harmonics. It can be
observed that there are very few notches in the
voltage and current waveforms. The torque shown
in figures contents some ripples because of
harmonics. From figure 6 which shows that the
torque ripple gets reduced as level increases. Table
3 shows comparison between SPWM and
SVPWM for power quality of output voltage with
Fig-8 FFT analysis of output voltage of 3-level and 5-
different value of modulation index. As level
level inverter by SVPWM
increases THD will get reduced. SVPWM contains
less harmonic distortion even at low modulation TABLE 3- COMPARISON OF SPWM AND SVPWM FOR THD
OF INVERTER OUTPUT VOLTAGE
indices.
 2017 International Conference on Intelligent Computing and Control (I2C2)

SPWM SVPWM CONCLUSION

ma
MLI have matured from being an emerging
3-l 5-l 3-l 5-l
technology to a well-established and attractive
0.9 56 27 23 13 solution for medium-voltage high-power drives.
0.8 72 30 35 17 The cascaded multilevel inverters have evolved
0.7 84 35 41 17 from a theoretical concept to real applications due
to several remarkable features like a high degree
0.6 101 46 50 22
of modularity, the possibility of connecting
0.5 121 46 54 25 directly to medium voltage, low harmonic
distortion, and the control of power flow in the
regenerative version. Slip command signal is
MLIs fed 2.3kV induction motor drive is generated through P-I controller and limiter and
simulated using Matlab Simulink. The MLIs added in speed signal to generates frequency
output has reduced harmonics and it goes on command signal. Now, worldwide research on
reducing as the level increases. This reduces the MLI-related technologies is going on. The focus of
heat generated in the stator winding of the this project is limited to basic concept of different
induction motor. The torque of the motor is MLI and comparative study of different PWM
improved due to the elimination of the harmonics. generation methods and its impact on inverter
Harmonics present in output of inverter produces output.
negative torque. So, MLIs fed induction motor
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