Analog & Digital Electronics

1. Diode Circuits & Applications

(b)12.5 Ω
1. Ideal diode is characterized by (c)50 Ω
( EPDCL-10) (d)100 Ω
(a) infinite resistance
(b) zero resistance 7. Assume that D1 and D2 in figure are
(c) 10M Ω ideal diodes the value of current Is is
(d) 1KΩ (TRANSCO-AE-12)
2. The knee voltage of silicon diode is
(EPDCL-10)
(a)1.0v (b)0.7 V
(c)0.7 mV (d)0.3 V

3. The diode used in a clipping circuit

has Rf= 25 Ω and Rr=1MΩ. the
external resistor R is (APGenco-12)
(a)0 mA (B) 0.5
(a) 50 k Ω (b)5
mA
kΩ
(c)1mA (d)2
(c)1/25 MΩ
mA
(d)25MΩ
8. A voltage signal 10 sin ωt is applied
4. The dynamic resistance of a p-n
to the circuit with ideal diodes as
junction germanium diode at room
shown in figure. The max and
temperature with current of 1mA
minimum values of the output
under forward biasing is
waveform of the circuit are
(APGenco-12)
respectively(TRANSCO- AE-12)
(a)100Ω
(b)13mΩ
(c)13Ω (d)26
Ω

5. The ripple voltage of a FWR with a

100μF filter capacitor connected to a
load of 50 mA is (APSPDCL-12)
(a)2.4 V (b)1.2
V (a)+10V and -10 V
(c)4.4V (b)+4V and -4V
(d)6.6V (c) +7V and -4 V
(d) +4V and -7V
6. A diode whose terminal
characteristics are related as iD=IS 9. The cut in voltage for silicon and
(V/VT), is biased at ID=2Ma. Its germanium diodes respectively is
dynaic resistance is (HMWS-12) (EPDCL-14)
(a)25 Ω (a)0.6V , 0.2 V
 (b)0.7 V, 0.3 V
(c)0.3 V, 0.7 V (d)0.2
V, 0.6 V
10. Normally which of the following has
a negative temperature coefficient?
(APSPDCL-14)
(a) Platinum (b)
Thermostats
(c) Copper (d)
Nickel
11. The concentration of minority
carriers in an extrinsic
semiconductor under equilibrium is
(ISRO-14)
(a) Directly proportional to
the doping concentration
(b) Inversely proportional to
the doping concentration
(c) Directly proportional to
the intrinsic
(d) Inversely proportional to
the intrinsic concentration
12. Device employing the Hall effect is
used to measure (HMWS-15)
(a) Magnetic flux
(b) Magnetic flux density
(c) Electric charge
(d) Electric flux density
13. As compared to full – wave rectifier
unison two diodes, the four diode
bridge rectifier has the dominant –
advantage of : (SSC-JE- S1-14)
(a) higher current carrying
capacity
(b) lower peak inverse
voltage requirement
(c) lower ripple factor
(d) higher efficiency
14. which semiconductor device behaves
like two SCR’s? (SSC-JE- S1-14)
(a) MOSFET (b)
JFET
(c)UJT
(d) Triac
15. the current in reverse bias in P-N
junction diode may be : (SSC-JE-
S1-14)
(a) few micro or nano ampere
(b) few millim amperes
(c)between 0.2 A and 2A
(d) between 2A and 5A
16. An AC supply of 230 V is applied to
half- wave rectifier through
transformer of turns ratio10:1 as
shown in figure. Determine the peak
inverse voltage across the diode.
(SSC-JE- S1-14)
(a)37.6V (b)
32.5V
(c)23.0V
(d)14.54V
17. The potential barrier existing across
pn junction (SSC-JE-14)
(a) Prevents flows of
minority carries
(b)prevents flow of majority
carriers
(c)prevents total
recombination of holes and
electrons
(d) prevents neutralization of
acceptor and donor ions
18. In electronic circuits, for blocking
the DC component of a voltage
signal, a/an ……. Is connected in
series with the voltage source.
(SSC-JE-14)
(a) capacitor (b)
 diode
(c) resistor (d)
inductor

19. For n- type semiconductor, the

doping material is (SSC-JE-14)
(a) tetravalent (b)
penta valent
(c)trivalent (d)
bivalent
(a)0.25A
20. In a semiconductor, the resistivity (b) 0.5 A
(SSC-JE-14)
(a) depends on temperature (c)0.5 A
(b) depends on current
through it (d)
(c) depends on current
through it 22. Which of the following materials is a
(d) None of the above semiconductor?
(a) selenium (b)
21. In the figure, D is an ideal diode. If Bismuth
the rms value of the input voltage is (c)Silica (d)
50V, then the rms current through Chromium
100Ω is (SSC-JE-14)

2. BJT, JFET & MOSFET

1. Voltage gain of BJT amplifier is (c) (d)

(EPDCL-10)
2. JFET is(EPDCL-10)
(a) (b) (a) Voltage controlled device
(b) Current controlled device
 (c) Resistance controlled device
(d) Conductance controlled device
3. Thermal runway is not possible in
FET because as temperature of FET
increases (APGenco-12)
(a) Mobility increases
(b) Mobility decreases
(c) Drain current decreases
(d) Trans conductance increases
4. For the BJT shown in fig VBE=0.7 V
β=100, final IB (APGenco-12)
(a) 36.35 μA (b)19.3 mA
(c)38.6 mA (d)57 μA
5. The value of transcoductance at a
bias voltage of 0V for the JFET
which is having IDSS=9 mA and VP
=-3 V is (APSPDCL-12)
(a)6mV (b)6 ms
(c)27 s (d)3
ms
6. The pinch off voltage of a JEFT is
5.0 volts. Its cut – off voltage is
(HMWS-12)
(a)(5.0)1/2V (b)2.5 V
(c)5.0V (d)(0.5)3/2V
7. In an RC couple common emitter
amplifier, which of the following is
true? (HMWS-12)
(a) Coupling capacitance after the hF
response and bypass capacitor
affects the lF response
(b) Both coupling and bypass
capacitance affects lF response
only
(c) Both coupling and bypass
capacitance affect hF response
only
(d) Coupling capacitance affect the
lF response and bypass
capacitance affects hF response.
8. The current gain of a bipolar
transistor drops at high frequencies
because of (HMWS-12)
(a) transistor capacitance
(b) high current effects in the base
(c) parasitic inductive elements
(d) early effect
9. assume that N- channel MOSFET
shown in figure is ideal and its
threshold voltage is 1V, the voltage
Vab between nodes ‘a’ and ‘b’ is
(TRANSCO- AE -12)
(a)5V (b)2V
(c) 1V (d)0V
10. in a FET (epdcl-14)
(a) RD= μ×gm (b)
(c) (d)
11. the transistor amplifier in the
 following configuration is called
emitter follower (EPDCL-14)
(a) CB (b) CE
(c)CC (d) Cascode
12. Find the differential mode gain of the
amplifier shown in fig. if hie=2.8 K
and hfe=100.(APSPDCL-14)
(a)162 (b)254
(c) 197 (d)210
13. On the drain characteristic curve of a
JFET for VGS =0, the pinch – off
voltage is (HMWS-15)
(a) above the breakdown region
(b) between the ohmic area and the
constant current area
(c) between the constant current are
and the break down region
(d) below the ohmic are
14. in a BJT, when both junctions are
forward biased then the operating
mode is called
(a) Reverse active mode
(b) Forward active mode
(c) Saturation mode
(d) Cut – off mode
15. Two identical FETs, each
characterized by the parameters gm
and rd are connected in paralle. The
composite FET is then characterized
by the parameters. (TGenco-15)
(a)gm2/ and 2rd (b) gm/2 and
rd/2
(c) 2gm and rd/2 (d) 2gm
and 2rd
16. For an n- channel MOSFET and its
transfer curve shown in the figure,
the threshold voltage is
(TSTransco-15)
(a) IV and the device is in active
region
(b) -1V and the device is in
saturation region
(c) IV and the device is in saturation
region
(d) -1V and the device is in active
region.
17. The voltage gain of common- source
JFET amplifier deepens up on its
(Tstrancso- 15)
(a) Input impedance
(b) Amplification factor
(c) Dynamic drain resistance
(d) Drain load resistance
18. Calculate the collector current of a
silicon BJT, when dc current gain,
base current and reverse saturation
current of collector – base junction
are 100, 20 μA ans 500 nA
respectively . (TSSPDCL-15)
(a)2.051 mA (b) 2mA
(c)1.949mA (d)0.051 mA
19. Consider the circuit shown in the
figure. If the β of the transistor is 30
and the input voltage is +5V, then the
transistor would be operation in
(TSNPDCL-15)
 current of 8 mA.If the frequency of
rectangular pulse train vi is 50Hz,
then on- time of the transistor is
(SSC-JE-13)

(a) Cut off region

(b) Breakdown region
(c) Active region
(d) Saturation region

20. A BJT is said to be operating in the

saturation region, if: (SSC-JE-S1-14) (a) 20 ms (b) 6.4 ms
(a) both the junction are reverse (c)12.8 ms (d)16 ms
biased
(b) B-E junction is reverse biased 24. If the transistor having VCE=5V,
and B-C junction is forward VBE=0.7 V has β= 45, value of R is
biased
(c) B-E junction is forward biased (SSC-JE-13)
and B-C junction is reverse
biased
(d) Both the junction are forward
biased

21. The Ebers – Moll model is

applicavle to: (SSC-JE –S1-14)
(a) BJT
(b) NMOS transistor
(c) UJT
(d) JFET

22. In a CE (common emitter) transistor,

VCC=12 V and the zero signal
collector current is 1 mA. Determine
the operating point when collector (a) 85.64 k (b)63.14k
load (RC) is 6kΩ. (SSC-JE-S2-14) (c)72.15 K (d) 91.18 K
(a) 6V, 1mA (b) 6v, 2 mA
(c)12V, 1 mA (d) 12V, 2mA 25. The input resistance of a FET is of
the order of (SSC-JE-13)
23. The switching transistor as shown, (a)100 Ω (b)10KΩ
carries in the collector side an rms (c) 1MΩ (d)100MΩ
 (c)1.05 V (d)0.5V
26. FETs are
(a) none of these 28. A FET is essentially a: (SSC-JE-10)
(b) unipolar devices (a) current driven device
(c) bipolar devices (b) voltage driven device
(d) either unipolar or bipolar (c) power drive source
(d) solar device
27. a transistor is operating in common
emitter mode as shown in figure 29. an oscillator uses:
given below. The voltage VCE is (a) positive feedback
(SSC-J2E-11) (b) Negative feedback
(c) Both positive and negative
feedback
(d) No feedback

30. For active region operation of an

NPN transistor : (SSC-JE-10)
(a) Emitter is positive with respect to
base
(b) emitter is – ve with respect to
base
(c) emitter is at same voltage as base
(d) base is at same voltage as
collector
(a)10.05 V (b)1.5V

3. OP AMP
:80 dB. The common mode gain is
1. Ideal operational amplifier has given by (APGenco-12)
(EPDCL-10) (a) 1 (b)1/2
(a) Infinite input (c)2 (d)250.
resistance
(b) Infinite output 3. An amplifier has input power of 2
resistance microwatts. The power gain of the
(c) Small gain amplifier is 60 dB. The output power
(d) Small bandwidth will be (APGenco-12)
2. A differential amplifier has a (a) 2 milliwatts (b) 6
differential gain of 20,000, CMRR microwatts
 (c)2 watts (d)120
microwatts

4. The voltage gains of the amplifier

with and without feedback are 20
and 100 respectively. The percentage
of negative feedback would be
(APGenco-12)
(a)40% (b)80% (a) 6 μs (b)12 V/μs
(c)4% (d)8% (c)14V/μs (d)14μs

5. For OPAMP in differential 9. If the op- amp is ideal, then V0 is

configuration, open loop gain is
10000, and differential input voltage
is 2μ V. Power supply for OPAMP is
± 12V. then output voltage will be
(APGenco-12)
(a) +12V (b)-12V
(c)0V (d) 2 μV
6. The ideal operational amplifier has
(a) Ri= ∞, R0 = ∞
(b)Ri=0, R0= ∞
(c) Ri = ∞, R0= 0 (d)
Ri=0, R0=0
7. In the LM 741, LM stands for
(APSPDCL-12)
(a) motorola
(b) RCA
(c) Texas instruments
(d) National semiconductor
8. The output of an op- amp voltage
follower is a triangular wave as
shown in fig. for a square wave input
of frequency 2 MHz and 8V peak to
peak amplitude. The slew rate of the
op amp is (APSPDCL-12)
(HMWS-12)
(a) zero (b) (V1 – V2)
sin ωt
(c)-(V1 + V2) sin ωt (d) (V1 + V2)
sin ωt
10. Which of the following is not an
ideal op- amp characteristic?
(EPDCL-14)
(a) Infinite voltage gain
(b) Infinite output resistance
(c) Infinite input resistance
(d) Infinite band –width
11. For an op amp having a slw rate of
3V/μ sec, what is the maximum
closed loop voltage gain that can be
used when the input signal varies by
0.4 V in 12 μsec (APSPDCL-14)
(a)120 (b)90
(c) 300 (d)100

12. What is the output waveform when

Vin is given square wave? (ISRO-14)
 (c)20 log10

(d)

16. Which circuit is used as amplitude

(a) Square wave (b) sine wave comparator? (APGenco-12)
(c)triangle wave (d) saw tooth (a) Bistable (b)
wave Monostable
(c) astable (d) schmitt
13. An ideal OPAMP is used to make an trigger
inverting amplifier. The two input
terminals of the OPAMP are at the 17. The given circuit represents a (SSC-
same potential because, (ISRO-14) JE -13)
(a) the two input terminals are
directly
(b) the input impedance of the
OPAMP is infinity and CMRR is
infinity
(c) The open loop gain of the
OPAMP is infinity
(d) slew rate is very high

14. An ideal op- amp slew rate is

(HMWS-15)
(a) infinitely fast (b)
slow (a) monostable multivibrator
(c) fast (b) astable multivibrator
(d) very slow (c) Schmitt trigger
(d) Bistable multibrator
15. The common mode rejection Ratio
(CMRR) of a differential amplifier 18. In general, if a sine wave is fed into a
(where Ad= differential gain, AC= Schmitt trigger, the output will be
common mode gain) (TSTransco-15) (SSC-JE-12)
(a) a saw – tooth wave
(b) an amplified sine wave
(a) (c) a triangular wave
(d) a square wave
(b)

5. Miscellaneous
 correct
1. An oscillator uses: (SSC-JE-10) (d) Both statements 1 and 2are
(a) Positive feedback incorrect
(b) Negative feedback
(c) Both positive and negative 7. The Barkhausen crition is
feedback (EPDCL-14)
(d) No feedback (a) A = β (b) A=- β
(c)Aβ=1 (d)Aβ=-1
2. Pulse generator is (EPDCL-10)
8. The maximum conversion
3. The efficiency of a class B efficiency of a class B push pull
amplifier for a supply VCC= 24V amplifier is (EPDCL-14)
(a)10π (b)15π
with peak – to – peak output of
(c)20 π (d)25 π
6V is (APSPDCL-12)
(a) 4% (b) 48%
9. Which is a voltage to frequency
(c)19.6%
convertio multivibrator?
(d)39.2%
(EPDCL-14)
(a) Bistable (b)
4. The timing resistor 10kΩ and
Astable
timing capacitor is 200 PF for a
(c) Monostable (d) Schmntt
565 PLL. The free running
trigger
frequency is (APSPDCL-12) 10. The bandwidth of a low pass RC
(a) 500 kHz (b) 350
circuit is 1KHz. What is the rise
kHz
time of output for a step input?
(c)250 kHz
(EPDCL-14)
(d) 150 klHz
(a)0.35 ms (b)3.5
ms
5. In a monostable multivibrator (c)0.35 (d)1 ms
using 555 timer, the time delay
is 100m sec, timing resistor is
11. For the timer circuit shown, find
100kΩ, and the value of timing
the output frequency.
capacitor is (APSPDCL-12)
(APSPDCL-14)
(a)9m F (b)0.9μF
(c)9F (d)1.8μF

6. Consider the following two

statements: (HMWS-12)
1. astable multivibrator can be
used for generating square
wave
2. bistable multivibrator can be
used for storing binary
information
(a) only stamen 1 is correct
(b) Only statement 2 is correct (a)100 kHz
(c) Both statements 1 and 2 are (b)1000Hz
 (c)1500 Hz (d)
2000 Hz 16. An astable multi- vibrator has
(TSSPDCL- 15)
12. A comparator circuit is used to (a) two – quasi stable
(ISRO-14) (b) one – quasi stable state
(a) Mark the instant when an (c) two stable states
arbitrary waveform attains (d) no stable state
some reference level
(b) Mark the instant when the 17. the circuit shown is a
input voltage becomes (TSNPDCL-15)
constant
(c) Switch ON and OFF a circuit
alternately at a particular rate
(d) Switch OFF a circuit when
output becomes zero

13. Two non- inverting amplifiers,

one having a unity gain and the
other having a gain of twenty are
made using identical operational (a) Low pass filter with F3dB=
amplifiers. As compared to the
unity gain amplifier, the
amplifier with gain twenty has
(TGenco-15) (b) High pass filter with f3dB=
(a) less negative feedback
(b) greater input impedance
(c) less bandwidth
(d) more bandwidth (c) low pass filter with f3dB=

14. an amplifier has a voltage gain

of 120. To reduce distortion, 10%
negative feedback is employed. (d) high pass filter with f3dB=
The gain of the amplifier with
feedback is (TSTransco-15)
(a) 141 (b) 92.3
(c)9.23 (d) 1.41
5. Number systems & Logic Gates
15. The ac bypassing of RF by CF in a
common emitter configuration: 1. For the circuit shown in fig. the
(TSSPDCL-15) Boolean expression for the output Y
(a) Increases ac signal across in terms of inputs P, Q, R and S is
emitter – base junction (TRANSCO- AE-12)
(b) Decreases ac signal across
emitter – base junction
(c) Decreases voltage
amplification
(d) Stabilizes the Q- point
 5. The circuit shown below is
equivalent of [APSPDCL-14]

(a)

2. The gate whose output is high when

all the inputs are low and low for
other combinations of inputs is
[EPDCL-14]
(a) OR gate (b) AND gate
(c) NAND gate (d) NO gate

3. Identify the 1-bit comparator circuit

[APSPDCL-14] 6. In 2’s complement representation the
number 11100101 represents the
decimal number
[HMWS-15]
(a) -27 (b) -31
(c) +27 (d) +37

7. Binary subtraction of a decimal 15

from 43 will utilize which two’s
4. A network has the given truth table f complement? [HMWS-15]
is given by (a) 011100 (b) 11000
[APSPDCL-14] (c) 110001 (d) 101011
X1 X2 F(x1, x2)
8. The reduced form of the Boolean
0 0 1
expression
0 1 1
1 0 0
1 1 1 [TSGenco-15]

9. The minimum number of 2-input

NAND gates required to implement
the Boolean function Z = AB’C,
assuming that A,B and C are
 available is (c) 011111 (d) 111110
[TSGeneco-15]
(a) Two (b) Three 12. Which of the following gates can be
(c) five (d) six used in relative all possible
combination logic functions?
10. The Boolean expression Y(A,B,C) = [TSSpDCL-15]
A+BC is to be realized using 2-input (i) OR gate
gates of only type. What is the (ii) NOR gate
minimum number of gates required (iii) Exclusive OR gate
for the realization? (iv) NAND gate
(a) 1 (b) 2 (v) AND gate
(c) 3 (d) 4 or more
(a) (iii), (iv) and (v)
11. What is the Gray code word for the (b) (i), (iii) and (iv)
binary number 101011? (c) (ii) and (iv)
[TSTranco-15] (d) (i) and (v)
(a) 101011 (b) 110101

6. Combinations & Sequential Circuits

reliably is [APGenco-12]
1. The frequency of the clock signal (a) 16.67 MHz
applied o the rising edge triggered D (b) 17.6 MHz
flip-flop shown in Fig is 10 kHz. The (c) 12.67 MHz
frequency of the signal available at Q (d) 11.76 MHz
is [TRANSCO-AE-12]
3. The initial state of MOD 16 counter
is 0110. After 37 clock pulses, the
state of the counter will be
[HMWS-12]
(a) 1011 (b) 0110
(c) 9191 (d) 0001

4. The number of unused states in a

4-bit Johnson counter is
[HMWS-15]
(a) 12 (b) 4
(a) 10 kHZ (b) 2.5 kHz (c) 8 (d) 2
(c) 20 kHz (d) 5 kHz
5. Which of the following is not a
2. A 3-stage ripple counter has Flip Flip characteristic of a flip-flop?
with propagation delay of 25 nsec [HMWS-15]
and pulse width of strobe input 10 (a) It was one input terminal
nsec. Then the maximum operating (b) It has two outputs
frequency at which counter operates (c) It has two outputs which are
 complement of each other 400μV/0C
(d) It is a bistable device (c) 600μV/0C (d) ±
800μV/0C
6. A 4 bit modulo-16 ripple counter
uses JK flip-flop. If the progression 8. The output f of the 4-to-1 MUX
delay of each flip-clop is 50 ns, the shown in figure is [TSTrnsco-15]
maximum clock frequency that can
be used is equal to : [TSGenco-15]
(a) 20 MHz (b) 10
MHz
(c) 5 MHz (d) 4
MHz

7. A 10-bit ADC with a full scale

output voltage of 10.24 V is deigned
to have ± LSB/2 accuracy. If the
ADC is calibrated at 250c and the
operating temperature ranges from
00C to 500C. Then thee maximum net
temperature coefficient of the ADC
should not exceed [TSGenco-15]
(a) 200μV/0C (b) ±

7. AD & DA Converters
(a) 9.961V (b) 9.691 V
1. The number of comparators needed t (c) 10V (d)5V
build a 6-bi simultaneous A/D
converter [EPDCL-10] 5. The number of comparisons carried
(a) 63 (b) 7 out in a 3-bit flash –type A/D
(c) 6 (d) 64 converter is [TRANSCO-AE-12]
(a) 16 (b) 7
2. The no. of comparators needed to (c) 4 (d) 3
build a 6-bit counter type A?D
converter [EPDCL-10] 6. The percent resolution of an 8-bit
(a) 64 (b) 32 D/A converter is
(c) 6 (d) 1 [APGenco-12]
(a) 0.392 (b)
3. Which of the following is the fastest 1/256
A/D converter [EPDCL-10] (c) 1/255 (d) (a)
(a) Counter type A/D and (b) both
(b) Successive approximation
(c) Dual slope 7. Identify the logic gate family which
(d) Integrating type consumed maximum power and
which has minimum propagation
4. What is the maximum output voltage delay [HMWS-12]
of 8-bit D/A converter with 10V (a) MOS (b)
supply [EPDCl-10] TTL
 (c) ECL 14. The main advantage of the
(d) CMOS successive approximation A.D
converter over the couter-ramp A/D
8. Which of the following is a D/A converter is its [HMWS -15]
converter [EPDCL-14] (a) Shorter conversion time
(a) Flash converter (b) Less complex circuitry
(b) Weighted resistor (c) Longer conversion time
(c) Successive approximation (d) More complex circuitry
(d) Dual slope
15. The practical use of binary –
9. The ADC having highest conversion weighted digital – to-analog
speed is converters is limited to
[APSPDCL-14] [HMWS-15]
(a) Dual-slope ADC (a) op-amp comparators
(b) Successive approximation ADC (b) 4-bit D/A converters
(c) Flash ADC (c) 8-bit D/A converter
(d) Servo ADC (d) R/2R ladder D/A converters

10. The memory which needs refreshing 16. A digit voltmeter has 4 ½ digit
[APSPDCL-14] display the 1 V range can read upto
(a) ROM (b) EPROM [TSTransco-15]
(c) SRAM (d) DRAM (a) 1000 (b) 1.111
(c) 1.999 (d) 1999
11. The number of comparators required
in a 3-bit comparator type ADC is 17. For the T flip-flop Qn+1 is given by
[HMWS-15] [APSPDCL-14]
(a) 8 (b) 3
(c) 7 (d) 2

12. In a flash A/D converter, the priority

encoder is used to 18. Addressing capacity of 8085
[HMWS-15] microprocessor is
(a) Select the last input [HMWS-15]
(b) Select the highest value input (a) 16 kB (b) 64
(c) Select the lowest value input kB
(d) Select the first inpuit (c) 128 kB (d) 8 kB
13. A 4-bit R/2R ladder digital-to-analog 19. Address bus length of 8086
converter uses [HMWS-15] microprocessor is
(a) Four resistor values [HMWS-15]
(b) Three resistor values (a) 40 (b) 16
(c) Five resistor values (c) 20 (d) 8
(d) Two resistor values
 8. Microprocessors
(d) Same as initial value
1. IC 8255 programmable peripheral
interface mode 1 is 6. Choose an incorrect statement from
[EPDCL-10] the following regarding pin numbers
(a) Basic I/O mode of 8085 μp [TSSPDCL-15]
(b) Strobed I/O mode (a) Series I/O p[orts are 5 and 4
(c) BSR mode respectively
(d) Parallel processing mode (b) Reset out and CLK out are 3 and
37 respectively
2. In 8085 microprocessor memory (c) GND and Vcc are 20 and 40
write cycle takes ______ T-states respectively
[EPDCL-10] (d) RST 6.5 and RST 7.5 are 7 and
(a) 2 (b) 3 8 respectively
(c) 4 (d) 1
7. Consider the 8085 program below
3. The CALL instruction requires the MVI A BB
following T-states LXI B 2060H
[EPDCL-10] STAX B
(a) 3 (b) 18 After this program is executed, the
(c) 1 (d) 5 contents of A and the flag which is
set, are ; [TSNPDCL-15]
4. The highest priority interrupt in 8085 (a) OOH, carry flag
microprocessor system is (b) BB, AC flag
[HMWS-12] (c) OOH, zero flag
(a) RST 7.5 (b) RST 6.5 (d) BB, no flag
(c) INRT (d) TRAP
8. Addressing capacity of 8085
5. What is the status of zero flag after microprocessor is [HMWS-15]
execution of following set of (a) 16 kB (b) 16
instructions? (c) 128 kB (d) 8
LXI H, 27F0H kB
MVI C, 27H
LOOP: DCX H 9. Address bus length of 8086
MOV A, L microprocessor is
ORA H [HMWS-15]
JNZ LOOP (a) 40 (c) 16
[HMWS-12] (c) 20 (d) 8
(a) 1
(b) 0
(c) Cannot specify

1. Diode Circuits & Applications

1. Ans: (b)
2. Ans : (B) The 1 directed from N type to P-
3. Ans : (B) type (D2 – R.B) As D2 - R.B
Sol: replaced by O.C
∴I = 0

4. Ans : (D)
Sol: Given data
η=1 (Ge), IT= 1m A, vt= 26 mV

8. Ans : (D)
5. Ans : (*)
Sol: For positive half cycle
Sol: Ripple voltage (Vr ) =

Data is insufficient in the

question
∴ unable to calculate Vi

6. Ans : (A) (i) (when Vi > 4V) D2ON,

Sol: D1= off then

(ii) When Vi < 4V, D1 & D2-

OFF
⇒ V0= Vi

(iii) For negative half cycle,

7. Ans : (A)
D1 – ON, & D2 – OFF
Sol: The current always selects
the low resistance path. D1 – ON Vi-10i+10i=0

and D2- OFF.

 Where, NA is acceptor impurity

concentraton.
12. Ans : (B)
13. Ans : (B)
Sol: PIV of bridge rectifier = Vm

PIV full wave rectifier = 2Vm

14. Ans : (D)

Sol: Traic is anti paralle combination
of two SCR’S
When Vi=-10V(max.

value)

V0 + 4-10I=0

15. Ans : (A)

Sol: Current in reverse bias is due to
=-3-4 ⇒V0 =-7V minority carriers only. Os it is in

9. Ans : (A) or (B) order of few micro or nano amperes.

10. Ans : (B) 16. Ans : (B)

Sol: Thermistor ⇒NTC Sol: Given V1= 230 V

11. Ans : (A)

Sol: Concentration of minority
carriers in N- type semiconductor, For half wave rectifier,
PIV = Vm

Where, ND is donor impurity

concentration
=32.5 V
Ans: P- type semiconductor
 17. Ans: (C)
18. Ans : (A)
Sol: Capacitor is connected in series
with the voltage source because
capacitor blocks DC voltage.
19. Ans : (B)
Sol: For n- type semiconductor, the
doping material is pentavalent.
For p- type semiconductor, the
doping martial is trivalent.
20. Ans : (A)
Sol: semiconductor is negative
temperature coefficient so it is depends on
temperature.
21. Ans : (A)
Sol: Vrms=50A
Sol: BJT is a current controlled
device.
FET ans op- amp is voltage
controlled device.
3. Ans : (B)
Sol: Thermal runway is not possible
in FET because as temperature of
FET increases mobility decrease.
4. Ans : (A)
Sol: DC equivalent circuit.

22. Ans: (B)

KVL of the input loop:

2. BJT, JFET & MOSFET
20= Ib (430k)+ 0.7 + 1k (Ib + Ic)
1. Ans: (B)
19.3= Ib (430 k + 1k +100k)

Sol:

5. Ans : (B)

2. Ans (A) Sol:

 configuration.
12. Ans : (A)

6. Ans: (C) Sol: Gain =

Sol: Pinch off voltage of a JFET in

nothing but its cut- off voltage.
∴ pinch of voltage = cut- off voltage The above answer is nearly matches
= 5V option : (A)
7. Ans : (B) 13. Ans : (B)
Sol: In a multistage common emitter 14. Ans : (C)
R-C coupled amplifier coupling Sol:
capacitor and bypass capacitors limit JE JC Operating mode
low frequency response and parasitic
F.B R.B Forward active
or junctions or shunt capacitances
F.B F.B Saturation
limit the high frequency response.
R.B F.B Inverse active
8. Ans : (A)
R.B R.B Cur- off
9. Ans : (D)
Sol:
15. Ans : (C)
16. Ans : (a), (c)
Sol: Given circuit is MOSFET
Vth=1 V Vth=1 by given graph
VDS(Sat)= VGS- Vth=1 V VGS=3-1 = 2V
Due to 10V source VDS > VDS(sat)→ N- VDS= 5-1 = 4V (if VD=5V)
channel MOSFET operated in Since VDS ≥ VGS -Vt
saturation, high current flows
4> 2 -1
through drain and source so that it
4>1
acts as a SHORT CIRCUIT.
Hence Device is in Saturation region
10. Ans (c)
∴ In the circuit VD is not given
11. Ans : (C)
Hence device may be in active
Sol: Common collector configuration
region
is also called as emitter follower
17. Ans : (c), (d) Sol: For the given circuit,
18. Ans: (A) -10+ IB . RB+ 0.6 =0
Sol: Given data
β=100, IB= 20 μ A, ICB0= 500 nA

Ic= βIB + (1+ β)ICB0 IC = βIB= 3.8 mA

=100 ×20 ×101× 500×10-6 VCE= VCC – IC RC

=2.051 mA =20-(5K ×3.8 m)=1.05 V
19. Ans: (C) 28. Ans : (B)
20. Ans: (D) Sol: In JFET, output current depends
Sol: on VGS & VDS. So it is a voltage

driven device.
JE JC Operating mode 29. Ans : (A)
F.B R.B Forward active Sol: Oscillator uses positive
F.B F.B Saturation feedback
R.B F.B Inverse active 30. Ans : (B)

R.B R.B Cur- off Sol: For active region of an NPN

21. Ans : (A) Transitory conditions VB > VE

22. Ans: (A) VC > VB
Sol: Operating point = (VCE, ICC) So base is positive with repress to
VCE = VCC- IC RC=12- (1m×6k)=6V emitter

ICC=1Ma 3. OP AMP

23. Ans : (C)

1. Ans : (A)
24. Ans : (A)
Sol: Ideal op- amp characteristics
25. Ans: (D)
Ri = ∞
26. Ans: (b)
Sol: In FET devices, the current R0= 0

conduction due to either electrons or B.W = ∞

holes. so it is a unipolar device. Open loop gain = ∞
27. Ans: (C) 2. Ans : (C)
 Sol: Given data Sol: Ideal op- amp characteristics
CMRR = 80 dB Ri = ∞
Ad=20,000 R0= 0

B. w= ∞
Open loop gain = ∞
7. Ans : (D)
Sol: Designation for linear IC’s
Each manufacture uses a specific
code and assigns a specific type
number to the IC’s produced. For
AC=2
example 741 an internally
3. Ans : (A) compensated op- amp originally
manufactured by fair child is sold
as MA 741. Here MA represents

P0= 2 ×10-6 x 106 = 2W the identifying initials used by

fair child. The codes used by
4. Ans : (C)
some of well- known
Sol: Given data
manufacture of linear IIC’s are:
A = 100
1. Fair child μAF
Closed loop gain = 20
2. National semi- conductor
%β =?
LM, LH
L
F, TBA
5= 1+100β
3. Motorola
MC, MFC
4. RCA
CA, CD
5. Texas instrument
%β = 4%
SN
5. Ans: (D)
6. Signetics
6. Ans : (C)
N/s, N/ε, S/ε
 7. Burr- Brown = ACL (2πfm Vm)
BB
8. Ans : (B)
Sol:
ACL=90

12. Ans : (C)

Sol:

Apply I.L.T
9. Ans : (C)
Sol:

Given, Vin= square wave

-V1 sin ωt- V2 sin ωt= V0

V0 = - (V1 + V2) sin ωt ∴ the output waveform is Triangular

10. Ans : (B) wave.
Sol: Ideal op- amp characteristics 13. Ans : (C)
Ri = ∞ 14. Ans : (A)
Sol: For an ideal OP- amp slew rate
R0= 0
should be high i.e., infinitely fast.
B.W = ∞
15. Ans : (A)
Open loop gain = ∞
Sol:

11. Ans : (B)

16. Ans : (D)

 Sol: Schmitt trigger is used as Where , RT = Timing resistor,
amplitude comparator. CT = Timing Capacitor
17. Ans : (D)
5. Ans: (b)
Sol: Schmitt trigger is used as
Sol: T = 1.11 RC
amplitude comparator.
18. Ans : (C)
19. Ans : (D)
6. Ans: (c)
Sol: Schmitt trigger is a square wave
7. Ans: (c)
converter not a square wave generator.
Sol: Aβ = 1
∠Aβ = 00 (or) 3600
4. Miscellaneous
8. Ans: (d)
1. Ans (A)
Sol: Oscillator uses positive
feedback
2. Ans : (B)
Sol: Monostable multivibrator is
pulse generator where as, Astable
multivibrator is square wave 9. Ans: (b)
generator. Sol: A stable multivibrator is a
3. Ans : (C) voltage to frequency converter
Monostable multivibrator is a
voltage to time converter
10. Ans: (a)
Sol: Given data:
B.w = 1 kHz

11. Ans: (b)

4. Ans: (d) Sol: T = 0.693 (RA + 2RB)C

RA = 7.2 kΩ

RB = 3.6 kΩ
 C = 0.1 x 10-6 F

12. Ans: (a)

13. Ans: (a), (c)
14. Ans: (c)
Sol: Given data:

15. Ans: (a) increase from 0 at ω=0 to

16. Ans: (a) (R2/R1)
Sol:
Multivibrator Quasi Stable as ω→∞ with ω3 dB =
stable states
∴ The given circuit is HPF
states
Astable 2 0
Monostable 1 1
Bi-Stable 0 2
5. Number systems & Logic Gates
17. Ans: (b)
Sol: For the given circuit
1. Ans: (b)
Sol:
 5. Ans: (d)

6. Ans: (a)
Sol: Given number is → 11100101
In Two level logic
(2’s complement number). To get the
‘NAND – NAND’ Logic = AND –
decimal equivalent, again do 2’s
OR’ Logic
complement to given number.
2. Ans: (d)
Then 2’s complement of given
Sol:
number = (00011011)2 = (27)10
A B Output
As MSB is ‘1’ in given no result =
0 0 1
-27
0 1 0
Shortcut:
1 0 0
-(1) x 27 + 1 x 26 + 1 x 25 + 0 x 24 + 0
1 1 0
x 23 + 1 x 22 + 0 x 21 + 1 x 20
This is for NOR gate
⇒ - 27
3. Ans: (a)
7. Ans: (a)
Sol: X-OR gate is unequal
Sol: Short cut:
comparator
43 – 15 = 28
4. Ans: (c)
∴ binary equivalent of (28)10 =
Sol:
(011100)2
8. Ans: (c)
Sol: Given expression is

This equation satisfies option (c)

 = AB
9. Ans : (C) Hence ‘3’ gates required (All are of
equal type)
Sol: Z = (AC)
11. Ans : (D)
Sol: Given binary number is 101011

10. Ans : (C)

Sol:
Gray code representation for the
given binary number is 1 1 1 1 1 1 0.
12. Ans : (C)
Sol: Basic gates : AND, OR & NOT
Universal gates : NAND, NOR
Derived gates: EX –OR. EX – NOR
6. Combinations & Sequential Circuits
2. Ans : (D)
1. Ans : (D) Sol: Given data
Sol: D- FF characteristic equation is Tpd= 25 nsec, tsrobe=10 nsec
Q (t+1) = D but, from figure, D = Tconv= ntpd + tstrobe= (3×25+10) n sec

= 75 nsec

Hence Q (t+1) = => i.e FF is

Toggle mode
3. Ans : (A)
Sol:
Hence output Freq =
CLK Output
0 0110
 1 0111
2 100
3 1001 7. Ans : (A)
. . Sol: Accuracy
. .
. .
15 0101
16 0110
For every 16 clock cycles the output
is repeated
∴ 16 ×2 = 32
For 32nd clock cycle, output =0110 =±200 μV/0C
For 33rd clock cycle, output =0111 8. Ans : (B)
For 37 clock cycle, output =1011
th
Sol:
4. Ans : (C) X Y F
Sol: No. of unused state in a 4- bit 0 0 0
Johnson counter = Total no. of states 0 1 1
– no. of used state = 24 - 2×4 = 16 -8 1 0 1
=8 1 1 1
5. Ans : (A)
Sol: A flip – flop is a bitable device, 7. AD & DA Converters
which is having two outputs and are
complement to each other. 1. Ans (A)
6. Ans : (C) Sol: The number of comparators
Sol: For 4- bit modulo 16 ripple
needed to build a 6- bit simultaneous
counter has 4 J-K flip – flops whose
A/D converter = 2n-1
propagation delay is 4Td = 26-1
Total propagation delay = 64 -1
T = 4 × 50 n sec = 200 n sec = 63
∴ Maximum clock frequency 2. Ans : (D)
 Sol: the no. of comparators need to Sol:
build a 6- bit counter type A/D converter =1. 1. The order of propagation
3. Ans : (B) delay of logic families is
Sol: Speed : Flash type > successive ECL < TTL < DTL < CMOS
approximation > counter type > dual (low tpd ) (High
slope / integrating type A/D. tpd)
4. Ans : (A)
2. ECL has high power
Sol: given data
dissipation, TTL has medium
N = 8 , Vin=10 V
power dissipation and CMOS
Step size (or) has low power dissipation.
Resolution ECL > TTL > CMOS
(high) (low)
8. Ans : (B)
Sol:
A/D converter D/A
V0(max)= Resolution ×(Decimal Converte
equivalent of max binary number) r
For an 8 bit D/A converter max Flash Tupe R- 2R
count value = 2n= 256 successive Ladder
approximatio
n
5. Ans : (B) Ramp Type Inverter
Sol: N- bit Flash Type ADC R – 2R
Requires (2 -1) comparators.
N
ladder
So 2 -1 = 7 comparators required.
3
Counter Type Weighted
6. Ans : (A) resistor
Dual slope
Sol: % Resolution = integrating
9. Ans : (C)
Sol: Speed : Flash type > successive
7. Ans : (C)
 approximation > counter type > dual 14. Ans : (A)
slope / integrating type A/D. Sol: The main advantage of the
10. Ans : (D) successive – approximation A/D
Sol: converter over the counter – ramp
i. SRAM requires 6- transistors A/D converted is it has shorter
for storing one bit. conversion time.
ii. DRAM requires one 15. Ans : (B)
capacitor and one electronic Sol: The practical use of binary –
switch (BJT/FET) to store one weighted digital – to – analog
bit. converters is limited to 4- bit D/A
iii. DRAM requires memory converters
refreshing logic circuit to 16. Ans : (*)
refresh a;; the capacitor voltages No answer
where as SRAM does not 17. Ans : (A)
require memory refresh logic Sol: For T flip – flop
circuit since it designed with T Q (t+1)
transistors. 0 Q(t)
11. Ans : (C) 1 Q(t)
Sol: The number of comparators
required in a n- bit comparator type ADC is
T Q(t) Q(t+1)
2 -1.
n

0 0 0
∴for 3- bit = 23-1 ⇒7
0 1 1
12. Ans : (B)
1 0 1
Sol: The priority encoder is used to
1 1 0
select the highest value input.
Q (t+1) =T ⊕ Q(t) = T
13. Ans : (D)
Sol: Weighted resistor D/A
converters requires wide variety of 18. Ans : (B)
resistors but R/2R ladder type D/A Sol: 8085 microprocessor is having
converter requires Two resistor ‘16’ address lines. Hence addressing
values. capacity = 216 ⇒ 64
 kB (26. 210) 210 ⇒1 kB
210 ⇒ 1 kB 9. Ans : (C)
19. Ans : (C) Sol: Address bus length of 8086
Sol: Adderess bus length of 8086 microprocessor = 20
microprocessor Address bus length of 8085
= 20 microprocessor
Address bus length of 8085 = 16
microprocessor
= 16

8. Microprocessors
1. Ans : (B)
2. Ans : (B)
3. Ans : (B)
Sol: CALL address is a 3 byte
instruction
⇒OPFMC + 2T + OPIRMC +
OP2RMC + MW / MC + MW2
,C
⇒4T + 2T + 3T + 3T + 3T
⇒18T
4. Ans : (D)
5. Ans : (A)
6. Ans : (D)
7. Ans : (D)
8. Ans : (B)
Sol: 8085 microprocessor is
having ‘16’ address lines. Hence
addressing capacity = 216⇒64
kB(26. 210)