VLSIGURU DFT TRAINING COMPRESSION LAB OBSERVATIONS

EDT(COMORESSION) LABS GUIDELINES

1. EDT INSERTION STEPS

2. DIRECTORY STRUCTURE

3. TOOL USAGE

4. EDT INPUTS and OUTPUTS

5. EDT FLOW

6. TOOLS COMMANDS

7. OBSERVATIONS

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1. EDT INSERTION STEPS

Please find below steps for EDT Insertion

STEPS

Step1: - mkdir /home/<user_name>/compression/case1

Step2: - cd /home/<user_name>/compression/case1

Step3: - mkdir EDT_RTL_GENERATION SYNTHESIS

Step 4:- cd /home/<user_name>/compression/case1/EDT_RTL_GENERATION

Step 5:- mkdir netlist log output dofile

Step 6:- cd /home/<user_name>/compression/case1/ EDT_RTL_GENERATION/netlist

Step 7: - cp /home/<user_name>/scan_insertion/case1/output/case1_scan.v .

Step 8: cd /home/<user_name>/compression/case1/ EDT_RTL_GENERATION/dofile

Step 9 : - cp /home/<user_name>/scan_insertion/case1/output/case1.dofile .

Step 10 : - cp /home/<user_name>/scan_insertion/case1/output/case1.testproc .

Now open case1.dofile and give proper path to testproc.

Before change

After change

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Step 11: - cd /home/<user_name>/compression/case1/ EDT_RTL_GENERATION

Step 12 : - Create run file

Example : tessent -shell -dofile ./dofile/case1_edt.dofile -log ./log/case1_edt.log -replace -

load_warnings

Step 13 : source /home/tools/mentor/cshrc_mentor

Step 14: - source run file

Synthesis :

Step 15 : - cd /home/<user_name>/compression/case1/SYNTHESIS

Step 16 : - cp /home/<user_name>/compression/case1/
EDT_RTL_GENERATION/output/DmaWr_dc_script.scr .

Step 17 : - Add below lines to DmaWr_dc_script.scr

# Manually Added by the User

set target_library "/home/sujith/compression/case1/typical.db"

set link_library "/home/sujith/compression/case1/typical.db $target_library"

read_db $target_library

## Ends Here

Example :

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Step 18 :- create run file with below commands

dc_shell -f DmaWr_dc_script.scr

Step 19:- source /home/tools/mentor/cshrc_synopsys

Step 20:- source run file

EDT INSERTION

• Compression is reduced to test time and test data volume

• Longer Scan chains converted to Smaller scan chains based on the compression ratio

• Compression ratio= Internal Scan chains/External Scan chains

• Analyze how many channels are available for each blocks and top level.

• Additional hardware Decompressor, compactor, bypass logic and edt controller

• Analyze EDT IP RTL files and understand Each file what contains data and its functionality

• Also Analyze mask shift registers, mask hold registers, X-OR logic, bypass logic muxes and
scan chains inputs and scan chains out output.

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NOTES

Note1:- Above steps for case1 test cases. Same steps should be repeat for remaining test cases

Note2:- Don’t copy netlists from the other directories

Note3:-Understand each commands descriptions from the Manual.

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2. DIRECTORY STRUCTURE
Please find below directory structure for all test cases. There are twelve testcases in EDTinsertion
labs exercises

compression:- parent directory

case1:- Each test case directory

netlist:- This directory has Scan inserted netlist which is output from scan insertion stage .

log:- This directory consists of EDT insertion log file. Log file consists of all commands, warnings,
errors. Its mandatory needs to understand completely

dofie:- This directory is consists of EDT insertion dofile. Dofile contains set of tool commands which
execute EDT insertion flow. Dofile is always vary from all different test cases

report:- This directory consists of all report files which are dumped by the tool. It is mandatory to
understand all report files

output:- This directory consists of EDT inserted netlist and ATPG setup files for both EDT and EDT
BYPASS modes. EDT dofile should not modify because it is generated by the tool.

Compression

|____ case1

|___netlist

|___log

|___dofile

|___report

|___output

Run file

run_case1 -> run file to invoke the tool.

Problem definition file

readme -> describes the testcase problem definition

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3. TOOL USAGE

Mentor Tessent Shell tool is used for EDT insertion flow. Tessent Scan, which is Tessent Shell
operating in “dft -edt” context

Please find below command is used for source tessent shell tool

source /home/tools/mentor/cshrc_mentor

after sourcing above command, need to check tool is sourced or not. Please use below command

which tessent. It will display tool path on the terminal.

Please find below command is used for source Synopsys Design compiler tool

source /home/tools/mentor/cshrc_synopsys

after sourcing above command, need to check tool is sourced or not. Please use below command

which dc_shell. It will display tool path on the terminal.

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4. EDT INPUTS AND OUTPUTS

INPUTS

1. Scan inserted Netlist

Scan inserted netlist is input to EDT insertion. Scan inserted netlist has Scan Flip-Flops with scan
chains based on the maximum chain length. During scan insertion time should think about
compression ratio and Number of channels available

2. Library cells

It is in .mdt format. Standard cells library is released by the Standard Cell Design team. Standard cells
are based on the technologies like 22nm, 14nm, 7nm, 5nm. It has all combinational and sequential
logic gates. Observe DFF flops with cells and SDFF flops with cells with primitives

3. Tools commands

Read netlist with verilog

Read library with .mdt

Define clocks

Define reset

As per design add tool commands. Please refer tshell_ref documents for all commands and DRC
rules.

OUTPUTS

1.EDT Inserted Netlist

It is EDT inserted netlist. This netlist has decompressor, Compactor logic blocks, Bypass logic and EDT
controller logic. Also observe how many internal scan chains are present in the netlist.

2. ATPG Dofile

It has clocks and resets definitions. Also, it has all compression scan structures

Also edt bypass dofile and testproc files

3. ATPG Test proc

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It has set of procedures like test_setup, shift, load_unload

4. SCAN DEF

It has scan chain information file as per Physical design tool requirements

5. Reports

Design Rules Checking (K19, K20, K22)

Scan chain reports and Scan cells reports

Clock and reset Reports

Report dft check

Report_pin_constraints

Report edt configuration

Also dump necessary reports based on the test cases and project wise

6. Logs

Please go through complete log file and note all points. Analyse all warnings DRC and Errors

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5. EDT INPUTS AND OUTPUTS

Step1 :-Generate EDT IP RTL along with Scan inserted netlist. Create EDT insertion setup. Scan
inserted netlist, library models, ATPG setup dofile from scan insertion step as inputs to the step1.
Create case1_edt.dofile as per the problem definition. Provide proper set up of input set of scan
channels and based on the compression ratio, decide how many internal scan channels are
requires respective test cases. It generates EDT IP RTL for Decompressor, Compactor, Bypass logic
and EDT controller logic. Also observe EDT signals like edt_clock, edt_update and edt_bypass.
Analyse edt mask shift register, mask hold registers and X-OR Logic inside Compactor.

STEP2 :-Synthesize EDT IP RTL. Synthesize standalone EDT IP RTL using tool dumped dc script with
Synopsys Design compiler tool. We convert EDT IP RTL to gate level synthesis RTL format

STEP3 :- Concatenate synthesized EDT IP RTL and Scan inserted netlist. EDT top module is present
in the Scan inserted netlist. So need to do concatenate EDT top module synthesized RTL with scan
inserted netlist. Then it is EDT Inserted netlist

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6. TOOL COMMANDS

Sample Dofile for EDT RTL Generation :

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7. OBSERVATIONS

Please find below list observations from the EDT Labs

1) Understand how to decide compression ratio

2) Why Compression is required and benefits of compression logic

3) Analyze Decompressor logic, Compactor logic, EDT bypass logic with Muxes and Mask
hold/Shift registers.

4) Trace Connections between Scan input channel and internal scan chains

5) Load EDT inserted netlist to Mentor Visualizer and cross verify physical connections with
Decompressor and compactor.

6) Understand EDT operation with Waveform

7) EDT chain test

8) Additional cycles

9) EDT low power architecture

10) Basic compactor architecture

11) X-Press compactor Architecture

12) Source of X-propagation

13) X-Masking logic

14) X-OR Decoder and Basic Decoder logic

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