Sunteți pe pagina 1din 5

# B.

## TECH – IV SEMESTER – JAN-MAY 2014

DIGITAL SYSTEM DESIGN – ASSIGNEMNT QUESTIONS

## 2. Design a 4-bit binary ripple counter.

3. Design a sequential circuit which will output z=1 for the input sequence that ends in either
010 or 1001, otherwise z=0.

4. Define a function to multiply two 4-bit numbers a and b. The output is an 8-bit value. Invoke
the function by using stimulus and check results.

multiplexer.

## 9. Design a 4-bit synchronous binary counter.

10. Design a combinational circuit that has 4 inputs (a, b, c, d), which represent a bcd digit. The
circuit has two groups of 4- outputs – s,t,u,v and w,x,y,z. Each group represents a decimal
number which is five times the input number. For example, if abcd=0111 the outputs are
0011 0101. Assume that the invalid bcd digits do not occur as inputs.

## 12. Design a circuit for gray to binary code conversion.

13. Design a 5-32 line decoder using four 3-8 line decoders with enable and one 2-4 line
decoder.

## 14. Design a 4-bit bcd ripple counter.

15. Design a sequential circuit which gives the output as 1 when the number of 1’s is odd and it
has received at least 2 consecutive 0’s.

## 16.Design a divide by 6 ripple down counter.

17. A majority logic function is a boolean function that is equal to 1 if the majority of the
variables are 1. The function is 0 otherwise. Write an hdl user-defined primitive for a 3-bit
majority function.

18. Design a code converter that converts a decimal digit from the 8,4,-2,-1 code to bcd.

19. Write an hdl behavioral description of a 4-bit comparator with a 6-bit output. Bit 5 is for
equal, bit 4 for unequal, bit 3 for greater than, bit 2 for less than, bit 1 for greater than or
equal, bit 0 for less than or equal.

## 20.Design a johnson counter.

21.Design a sequence detector that detects any input sequence ending in 101 and produces an
output z=1. Overlapping is permitted.

## 25.Design a 8-bit ring counter.

26.Design a counter with the following repeated binary sequence: 0,1,2,3,4,5,6. Use jk flipflops.

## 27.Design a circuit to convert alphanumeric character to its corresponding ascii code.

28.Define a task to compute the factorial of a 4-bit number. The output is a 32-bit value. The
result is assigned to the output after a delay of 10 time units. Also design a circuit for
fibonacci series generation.

29.Write the truth table for the boolean function y=(a&b)|(c^d). Define a udp that implements
this boolean function. Assume that the inputs will never take the value x.

## 31.Design a 4-bit combinational circuit for 2’s complement.

32. Design a combinational circuit that generates the 9’s complement of a bcd digit

## 36. Design a jk counter that goes through the states 7,4,8,3,9,2,10,1,11,0,7,4….

37.Design an excess-3-to-binary decoder using the unused combinations of the code as don’t
care conditions.

38. Design a sequential circuit with two j k flip-flops a and b and two inputs e and x. If e = 0,
the circuit remains in the same state regardless of the value of x. When e = 1 and x = 1, the
circuit goes through the state transitions from 00 to 01 to 10 to 11 back to 00, and repeats.
When e = 1 and x = 0, the circuit goes through the state transitions from 00 to 11 to 10 to
01 and back to 00 , and repeats.

39. It is necessary to design an asynchronous sequential circuits with two inputs, x1 and x2, and
one output, z. Initially, both inputs and output are equal to 0. When x1 or x2 becomes 1, z
becomes 1. When the second input also becomes 1, the output changes to 0. The output stays
at 0 until the circuit goes back to the initial state.
40. Design a 5 bit synchronous binary counter using t flip flop.

41. Given a memory size 64 words, with 8 bits per word, write verilog code to swap the
contents of memory in reverse order, that is, transfer word at 0 to word at 63, word 1 to
word 62 and so on.

42. Design a circuit that will give output 1 anytime a letter within the string “digital system
design”, appears at the input in ascii code.

43. Design a gray code converter to drive a seven segment indicator. The four inputs to the
converter circuit (a, b, c, d) represent a decimal digit coded using the gray code. Assume that
only i/p combinations representing the digits 0 to 9 can occur as inputs, so that the unused
combinations are don't care terms.

44. Design a task to compute even parity of a 16-bit number. The result is a 1-bit value that is
assigned to the output after three positive edges of clock. (use a repeat statement).

## 45. Design a 8-bit jerky ring counter.

46. Design a jk counter that must go through states 0,3,6,0...if a control line is high and
0,2,4,6,0...if the control line is low.

47. Describe a generic n-bit counter with asynchronous negative level reset. Instantiate this
generic counter as a 5-bit counter. Verify this 5 – bit counter using a test bench.

48. Write a program to find the size of the largest gap between two successive 1s in a 16 – bit
word.

49. Design a circuit that can shift a 4 – bit vector w=w 3w2w1w0 one bit position to the right
when a control signal shift is equal to 1. Let the outputs of the circuit be a 4 – bit vector
y=y3y2y1y0 and a signal k, such that if shift = 1 then y 3=0, y2=w3, y1=w2, y0=w1 and k=w0. If
shift=0, then y=w and k=0.
50. Draw A sequential circuit with two d flip flops and one input x_in.
A) when x_in is 0, the state of the circuit remains the same. When x_in is 1, the circuit goes
through the state transitions 00 to 01, to 11, to 10, back to 00 and repeats.
B) when x_in is 0, the state of the circuit remains the same. When x_in is 1, the circuit goes
through the state transitions from 00 to 11, to 01, to 10, back to 00 and repeats.