A Mathematical Guideline for Designing an AC-DC

LLC Converter with PFC

Yajie Qiu1, 2, Member, IEEE; Wenbo Liu1, Student Member, IEEE; Peng Fang1, Member, IEEE; Yan-Fei Liu1,
Fellow, IEEE; Paresh C. Sen1, Life Fellow, IEEE
1. Department of Electrical and Computer Engineering 2. GaN Systems Inc
Queen’s University, Kingston, Canada Ottawa, Canada
yqiu@gansystems.com; liu.wenbo@queensu.ca; p.fang@queensu.ca; yanfei.liu@queensu.ca; senp@queensu.ca

Abstract — Although LLC topology has been applied to II. LLC RESONANT CONVERTER DESIGN GUIDELINE
AC-DC power supplies as a Power Factor Correction (PFC) FOR PFC
converter in the literature, there is no publications present
intuitive equations that simplify LLC designing in order to A. LLC Resonant Converter Voltage Gain Review
meet the PFC gain requirements. In this paper, a The half-bridge LLC resonant converter prototype is
mathematical design guideline is derived for LLC PFC shown in Fig. 1. The operating frequency range of the LLC
converter applications, proving that by carefully designing PFC is defined as fp ≤ fs ≤ fr, where below-resonance
the resonant tank gain at parallel resonant frequency at the operation is preferred to ensure the inductive impedance
peak AC voltage higher than 1, its gain will meet the PFC characteristics of the LLC resonant tank, so that the soft
requirement for other AC voltages and result in a successful switching can be achieved in both primary side switches and
single-stage PFC design with power factor over 0.99. The secondary diodes.
guideline is extended to offline wide input and output voltage
LLC PFC applications. A 240-Watt prototype of a single-stage iin
LLC LED driver with PFC has been built to verify the SH
Lr D1
n:1
feasibility of the proposed design guideline. AC
+
vin Co Io +
Lm Vo RL
Keywords — AC-DC Converter; PFC; LLC; Single-Stage; - SL _
Resonant Converter
Cr D2
I. INTRODUCTION
Massive research have been attracted and new
topologies have been studied on AC-DC power supply and Fig. 1. Prototype of Half-Bridge LLC Power Factor Correction Circuit
its control strategy [1-6], LLC topology is still popularly
used as the second stage converter to provide galvanic The maximum switching frequency is set at the series
isolation and output voltage/current regulation [3, 4]. resonant frequency fr, expressed in (1). The quality factor Q,
However, all the power is processed twice, which severely the inductance ratio K, the normalized switching frequency
sacrifices the total efficiency and power density. To fn and the total gain of the converter MLLC_total are expressed
overcome this disadvantage, single-stage resonant solutions in (2) to (5) [11-13] and n is the transformer’s turns ratio.
with PFC were discussed in [7-10]. The LLC resonant
topology has been applied to a PFC converter in [7, 8] and 1
fr = (1)
then extended to an LED driver application in [9], resulting 2π Lr Cr
in power supplies with higher efficiency and a reduced π2 Lr I out π 2 Lr 1
profile. However, the primary switches operate at an Q= ⋅ ⋅ = 2⋅ ⋅ (2)
8n 2 Cr Vout 8n Cr Rout
asymmetrical duty ratio in the this article, which not only
results in control and driving circuit complexity, but also Lm
K = (3)
introduces third harmonics into the input current, sacrificing Lr
the optimal power factor performance. In [10], using the
fr
rectifier-compensated fundamental-mode approximation fn = (4)
method, the feasibility of the LLC topology working as a fs
PFC converter is proven with 50% duty cycle switch 1 1
operation. However, there is still no intuitive mathematical M LLC _ total = ⋅
2n  2 2
design guideline to help engineers quickly design the LLC 1 1   1  (5)
1 +  1 − 2 
+ f
 n − Q
 
converter to achieve the power factor correction without  K  fn   fn  
over-designing the gain. In this paper, a peak-gain-based
mathematical model is proposed for an LLC converter that B. Single-Stage PFC Gain Requirement Analysis
will achieve power factor correction and also guarantee Fig. 2 plots the required voltage gain, Greq(θ), for an
enough gain for the entire line voltage range. LLC converter in PFC mode, according to (6).
 200V
150V 1Vin 1Vin
2Vin 2 2Vin 2Vin 2
100V
50V
vin(ɵ)=|Vinsin(ɵ)| MLLC(f=fp)
0V

8
6
4
2 Greq(ɵ)=Vo/vin(ɵ) Rout

0 Fig. 3. Normalized LLC tank gain at parallel resonant frequency under

2 different load, Rout
2 Po
1.5
1Po 1Po C. Derivation of the LLC Resonant Converter Design
1 0.5Po 0.5 Po
Guideline for PFC
0.5
The entire LLC PFC design guideline is composed of
po(ɵ)=vin(ɵ)iin(ɵ) two parts: the transformer turns ratio design, and the LLC
0 resonant tank design.
ɵ 0 30º 45º 90º 135º 150º 180º
1) Transformer Turns Ratio Design Guideline
According to (6) and (7), the minimum gain requirement
Fig. 2. Single-stage LLC PFC gain requirement for a PFC design Greqmin(θ) occurs at θ=π/2, when the
instantaneous output power is equal to twice the average
It is observed that Greq(θ) to achieve power factor output power, 2Po. The minimum gain of the LLC resonant
correction is different at each time instant, while the LLC tank in the inductive operating range occurs at the series
converter output power pout(θ) is also changing as per (7). resonant frequency, fr. Therefore, the total gain of the LLC
converter at fr is intentionally designed to be equal to the
Vout Vout minimum gain requirement of the PFC converter in (8) and
Greq (θ ) = = (6)
vin (θ ) 2Vin _ rms sin(θ ) the resulting turns ratio is expressed in (9).
pout (θ ) = pin (θ ) = vin (θ )iin (θ ) π
(7) Greq min (θ ) = Greq (θ = )
2
= 2Iin _ rmsVin _ rms ( sin(θ ) ) = 2 ( sin(θ ) ) Po
2 2

Vout Vout (8)

Assuming the AC input voltage is 120VRMS: at 90º, the = =
π 2Vin _ rms
LLC should provide two times the steady state output power 2Vin _ rms sin( )
(Ppk =2Po). At this time, the vin is at peak 2
Vin_pk=120V×1.414, which is good for providing higher N pri Vin _ RMS
n= = (9)
output power. At 45º, the LLC should provide the output N sec 2Vout
power (Po), but vin is 120V×1.414×sin(45º) =120V. The 2) LLC Resonant Tank Design Guideline
LLC converter should generate Vo at 120V input at output In PFC mode, the quality factor Qpfc changes with θ.
power level of Po. At 30º, the vin = 0.5Vin_pk, and iin = 0.5Ipk, Derived from (2), the θ-dependent quality factor, Qpfc(θ) is
the output power is 0.25Ppk =0.5Po. Therefore, the LLC shown in (10), where Qfull_load in (11) is the full load quality
converter should provide Vo at the output power level of factor when the LLC resonant converter is working at the
0.5Po. In order to achieve high power factor correction PFC average power Po, and is a constant value. The total
performance, the LLC converter must achieve different gain of the LLC resonant converter in PFC mode is shown
gains at different input voltages. in (12).
For PFC application, the output voltage is usually a Lr Lr
constant. When Pout decreases, Rout also linearly increases.
Cr Cr
Fig. 3 plots the normalized LLC tank gain at parallel = 2 ( sin(θ ) )
2
Qpfc (θ ) = (10)
frequency under different load (Rout ranges from 1 to 12). Rac (θ ) Roe _ full _ load
featuring an increasing gain when the Rout is increasing, this = 2 ( sin(θ ) ) Q full _ load
2

changing trend is in agreement with the PFC gain

requirement as shown in Fig. 2. Therefore, LLC resonant π2 Lr I out
Q full _ load = ⋅ ⋅
converter is a potential candidate for single-stage PFC 8n 2 C r Vout
operation topology. The results from (1) to (5) will be used (11)
π2 Pout Lr
later to derive the design rule for the LLC converter in PFC = ⋅
4 Vin _ RMS 2 Cr
mode.
 1
M LLC _ total ( f s , θ ) = ⋅ M LLC ( f s , θ ) Vin _ rms max
2n n=(19)
1 1 2Vout min
= ⋅ (12)
2n 
1 fr 2 
2
4  f s fr  
2
To explore the design rule of LLC PFC under all the
1 +  1 − 2   + 4 ( sin θ )  −  Q full _ load  cases of the output voltage range, we define
 K fs   f r fs  
M LLC _ total ( f s = f p , θ ) =
1
⋅ M LLC ( f s = f p , θ ) Vout = λVout max (20)
2n min
1 1 Vout
= ⋅ (13) ≤ λ ≤1 (21)
2n 
1 f 2 
2
4  f p fr  
2
Vout max
1 + 1 − r 2   + 4 ( sin θ )  −  Q full _ load 
 K  f p    f r fp   With the changing of Vout, the gain requirement for wide
Then the total gain of the LLC resonant converter at the output voltage range PFC comes into a λ-related expression
parallel resonant frequency, fs =fp, is derived in (13). With as shown in (20).
the definitions of fp in (14) and K in (3), (13) is simplified Vout max
into (15). G req _ ext (θ , λ ) = λ (22)
2Vin _ rms sin(θ )
1
fp = (14) According to (11) and (13) the LLC converter gain in λ-
2π ( Lm + Lr )Cr dependent form is obtained in (23), where Qfull_load_vomax is
M LLC _ total ( f s = f p , θ ) =
1
M LLC ( f s = f p , θ ) the quality factor when the output voltage is at Vomax.
2n
1
1 M LLC _ total _ ext ( f s , θ , λ ) = ⋅ M LLC _ ext ( f s , θ )
= (15) 2next
 K  2
2 n ⋅ ( sin θ )
2
  ⋅ 2Q full _ load 1 1
= ⋅ λ
1+ K  2next
(23)
2 2
 1 fr 
2
 4  f s fr  
If the LLC resonant tank gain for the peak input voltage 1 +  1 − 2   λ + 4 ( sin θ )   −  Q full _ load _ vo max 
2

 K fs   f r f s  
(θ=π/2) at the parallel resonant frequency MLLC(fs=fp, θ=π/2)
is designed equal to or higher than 1, as shown in (16), the
resulting total LLC resonant converter gain can be then The total gain of LLC converter at the parallel resonant
derived from (9), (11) and (15), and is shown in (17). Since frequency, fp, is derived by using (20) to replace Vout in (15).
the inequality of 1/(sinθ)2≥1/(sinθ) is always valid for 1
0≤θ≤π, the LLC converter gain at the parallel resonant M LLC _ total _ ext ( f s = f p , θ , λ ) = M LLC _ ext ( f s = f p , θ , λ )
2next
frequency, fp, will meet the PFC gain requirement (0≤θ≤π)
as per (18). In short, we only design the LLC at one phase 1 Vout max 1
= ⋅ ⋅
( sin θ )
2
θ=π/2 to meet the PFC requirement, then the requirement  K  π2
2
Pout L  2Vin min
  ⋅ ⋅ ⋅ r  (24)
for the other phase will automatically be satisfied.  1 + K   2 (Vin
min 2
) C r 
max
 π 1 Vout 1
M LLC  f s = f p ,θ =  = ⋅ ⋅
2Vin min ( sin θ )
2
 2  K 2   π 2 λ ⋅ Vo max I out L 
  ⋅ ⋅ min 2
⋅ r 
1 (16)  1 + K   2 (V in ) C r 
= ≥1
 K2  π2 Pout Lr  It is observed from (24) that the total LLC converter gain
  ⋅  ⋅ ⋅ 
 1 + K   2 Vin _ RMS
2
Cr  at fp is decreasing while the gain requirement is increasing
min
Vout 1 with the increase of λ when Voutmax ≤ λ < 1 . Therefore, we only
(
M LLC _ total f s = f p ,θ ≥ ) ⋅
2Vin _ RMS ( sin θ )
2 (17) V out

need to check the LLC converter gain considering the

Vout 1 highest output voltage (λ=1) (shown in (25)) and make sure
M LLC _ total ( f s = f p , θ ) ≥ ⋅
2Vin _ RMS ( sin θ )
2
it satisfies the gain requirement (shown in (26)).
Vout 1
(18)
≥ Greq (θ ) = ⋅ Vout max 1
2Vin _ rms sin(θ ) Greq _ driv (θ , λ = 1) = ⋅ (25)
2Vin _ rms min sin(θ )
D. Extended LLC Resonant Converter Design Guideline M LLC _ driv ( f s , θ , λ = 1)
for PFC with Wide Input and Output Voltages
1
Requirements =
2 2
The proposed design guideline can also be adapted to the  1 fr  2
4  f s fr  
1 + 1 − 2   + 4 ( sin θ )  −  Q full _ load _ vo max  (26)
PFC applications with a wide AC input voltage,  K  f s     f r f s  
Vinmin≤Vin≤Vinmax, and wide DC output voltage,
Voutmin≤Vout≤Voutmax as follows:
The LLC transformer ratio should be set based on the
minimum gain requirement which occurs at the maximum By following the derivation steps in II. C, the extended
input (Vinmax) and the minimum output (Voutmin), as shown in LLC resonant converter design guideline is obtained as
(19). follows:
 a) the transformer turns ratio value is designed to be This is demonstrated in Fig. 5, where the resulting gain
equal to Vin_RMSmax/√2 Voutmin curve for the designed LLC PFC (in green) crosses the gain
b) the gain of the LLC resonant tank at fp is higher requirement (in red) only at θ=90º when pout(θ)=2Po (the
than the product of the variation ratios of input voltage and output power curve is shown in blue), and then is always
output voltage, considering the case θ=90º when line higher than the requirement when 0<θ<180º, 0<pout(θ)<2Po.
voltage is at peak value. Fig. 6 also shows that the designed LLC gain (the colored
 π 1 (27) surface) is always higher than the PFC gain requirement (the
M LLC _ ext  f s = f p , θ =  = red surface) within the specified output voltage range (40
 2  K2 
  ⋅ 2Q full _ load _ vo max V<Vout<60 V, 0<θ< π), resulting in a successful LLC PFC
 1+ K  design.
Vin _ rms max Vout max
≥ min
×
Vin _ rms Vout min

III. DESIGN EXAMPLE

A 240 W, single-stage half-bridge LLC LED driver was
designed and built using the proposed mathematical
guideline. The specifications are shown in Table I.

TABLE I. SINGLE-STAGE LLC LED DRIVER SPECIFICATIONS

Vin VLED ILED PO fline
180~300 Vac 40~60 Vdc 4A 240 W 60 Hz
The expected transformer turns ratio for the half-bridge
LLC LED driver n is calculated in (28).
N pri 300 Vin _ RMS max
n= = = ≈ 5.3 (28)
N sec 2Vout min
2 ⋅ 40
Table II lists the minimum gain requirement value for
the desired LLC LED driver, calculated in (29).
Fig. 4. Normalized Gain Plot of the Designed LLC Resonant Converter
at heaviest load pout(θ=90º)=2PO
TABLE II. LLC TANK GAIN REQUIREMENT AT THE PARALLEL
RESONANT FREQUENCY (FP)

MLLC(fp) Vout_ma Io_max P=p(θ=π/2) = 2Po=2Voutmax×Iout MLLC(θ)

>2.5 60 V
x
4A 2×60 V×4 A=480 W Greq(θ)
max max
Vin V 300 60
min
× out min = × = 2.5 (29)
Vin Vout 180 40 Greq(θ=90º )=MLLC_total(θ=90º )
The key LLC parameters are listed in Table III. po_norm(θ)

TABLE III. KEY PARAMETERS OF DESIGNED SINGLE-STAGE LLC LED

DRIVER

Npri:Nsec 11:2
Transformer Core PQ 40
Lm 103 µH
Lr 20 µH 0 45º 90º 135º 180º
Cr FKP1O116804D00JSSD×3 (6800
pF 1 KV) θ
Output capacitor Co B43504A2108M×3
Fig. 5. Gain Requirement vs. Gain Curve of the Designed LLC Resonant
(1000 µF, 250 V) Converter Considering Vout=Voutmax=60 V
Switching frequency(fs) 100 kHz ~ 250 kHz
Switches (SH & SL) SPP11N80C3
As shown in Fig. 4, the designed LLC resonant tank Considering the entire operating range of output voltage,
features a normalized gain of 2.72 at the parallel resonant a 3-D surface plot is drawn in Fig. 6 using the PFC gain
frequency fp/fr=0.392, which is 9% higher than the requirement expression in (22) and the LLC gain expression
requirement of 2.5. According to the proposed extended at parallel resonant frequency in (24). The gain requirement
LLC PFC design guideline, once the LLC gain meets the is a red surface, while the LLC gain is an irregular colored
PFC requirement at peak AC input voltage, it will meet the surface. Both of them are changing with λ=Vo/Vomax and
requirement for the entire line voltage cycle. phase of line voltage θ. It is observed that the designed LLC
resonant tank features the gain that is always higher than the
requirement within the specified output voltage range as
well as the entire half line voltage cycle (0.667 <λ <1, 0˚< θ
<180˚), resulting in a successful LLC PFC design.

MLLC_total(θ，λ )

Fig. 7. 240W Single-Stage LLC PFC LED Driver Prototype

Greq(θ，λ) LED LAMP （40~60V 4A ）

λ=Vo/Vmax input connectors
LED bar #1
M LLC_driv_total, Greq_driv

60V
LED bar #2
50V
40V

LED voltage adjuster

LED chips

MLLC_total(θ，λ )
Fig. 8. 240W LED Lamp Load (VLED=40~60V, ILED=4A)

As shown in Fig. 9, the PFC control strategy is

Greq(θ，λ)
λ=Vo/Vmax
M LLC_driv_total , G req_driv
Fig. 6. Designed LLC Resonant Converter Gain vs. PFC Gain
Requirement in 3D Surface Plot Considering the Wide Output Voltage
(Voutmin<Vout<Voutmax)
IV. EXPERIMENTAL VERIFICATION
The pictures of the designed 240W single-stage half-
bridge LLC LED driver prototype is shown in Fig. 7 while
the LED load is shown in Fig. 8. The load is made of 2
paralleled-connected LED bars and each LED bar has 18
pieces of LED chips from Cree (XMLBWT-02-0000-
0000T5051CT) connected in series to provide enough load
ability (the LED voltage up to 60V and LED current up to
4A).
implemented using dsPIC33FJ32GS606. A linear opto-
coupler is used to transmit LED current signal to the primary
side. The LED current signal is sampled by an ADC, and
then subtracted from a reference voltage value to create an
error value. The error value is processed by a slow PI
controller and becomes one of the two essential signals to
create the input current reference. The other essential
information for the input current reference is the sinusoidal
input voltage. The rectified input voltage is firstly scaled
down to adapt the DSC analog input range and then sampled
by the second ADC. By multiplying the error value from the
first ADC and the scaled input voltage reference from the
second ADC, a rectified sinusoidal input current reference
signal is generated.
Since it is difficult to accurately obtain the average input
current value over one switching cycle in LLC resonant
topology due to the irregular current waveform and the
existence of circulation current, the input current value is
calculated by using the cycle-by-cycle average input current
sensing method proposed in [14]. This method accurately
measures the average input current over each switching
period by sensing the series resonant capacitor voltage and
the input voltage at a particular time instant and thus
provides real-time average input current information.
 Bridge Rectifier Single-Stage Half-Bridge LLC PFC Converter

T ILED 4A
D1 D2
SH Lr + +
D1
20uH Co
vin
Lm 3mF _
D2
103uH VLED
180~300 D3 D4 SL Cr 40~60V
Vac LFB
20.4nF Q1 Q2 22uH
Daux
Caux
470uF CFB
Ns2
4.7uF _
Q3 Q4

Full-Bridge Ripple Cancellation Converter

complementary signals
at 50% duty cycle
Scale Scale SH SPWM signals to Q1 ~ Q4 Current
SL
down down sensing
Gate
Drivers
Full Bridge MOSFETs
ADC ADC Drivers
vCs
Optional tHoff & tLoff Control signal
Parameters
S/H Generator
vi Cr Cj fs
Analog Implementation
Internal of Bipolar Ripple
Comparator
Counter Cancellation Control

Input Current Sensing ii

Switching
Algorithm +_ PI
Period

vi Linear Opto- coupler and

ADC
PI _+ Peripheral Circuitry
Multiplier ILED_sens
Digital Signal Controller
ILED_ref

Fig. 9. The Implementation of the Single-Stage LLC Resonant LED Driver.

The experimental prototype presents power factor 92% is achieved. The 120 Hz output ripple is cancelled by an
performance of 0.99 at 180 V AC input, as shown in Fig. 10. auxiliary ripple cancellation circuit [16, 17]. The PF and
It is noticed that there are “a blank portions” of input current efficiency data under different input and output voltages are
in the vicinity of the input voltage zero crossing points. This shown in Fig. 18 and Fig. 19.
is caused by the nonlinearity of the MOSFET output
Ch1: Input Voltage
capacitance, Coss, which is a nonlinear capacitance that varies
with the drain-to-source voltage of the MOSFET[15]. As an
average Coss value is used in the existing digital
implementation, the nonlinearity of Coss value in the real Case 6: θ=90˚
circuit results the sensing error at the light input current and Case 5: θ=60˚Ch4: Gate
Driving signals
the low input voltage. The existing prototype is using Si Ch3: Drain to Case 4: θ=45˚
MOSFET (SPP11N80C3) as the half bridge switches, Source Voltage
featuring quite high Coss value at low input voltage Case 3: θ=30˚
(Coss@Vin=30V>500pF). Using the GaN HEMTs with Case 2: θ=20˚
significantly reduced Coss (Coss@Vin=30V<150pF) will reduce the Case 1: θ=0˚
difference between the average value and the real value of Coss
and lead to the improved PF performance.

Input Voltage: 180Vac Fig. 11. Soft Switching Performance of the LLC PFC on Primary Side at
Different Phase Angle, When Vin=180 Vac, VLED≈60 V, ILED=4 A, PO=240 W

Input Current PF=0.99

Output Current: 4Adc

Fig. 10. Power factor performance of the Half-bridge LLC LED Driver,
When Vin=180 V, Iout=4 V, Vout≈60 V

Fig. 12. ZVS Performance of the LLC PFC on Primary Side at θ=0º, When
Zero voltage switching performance during the whole PFC Vin=180 Vac, VLED≈60 V, ILED=4 A, PO=240 W
operation are shown in Fig. 11 ~ Fig. 17. Also, the design
presents a cost-effective, high-efficiency solution, compared
with the two-stage LED driver solution. A peak efficiency of
Fig. 13. ZVS Performance of the LLC PFC on Primary Side at θ=20º, When
Vin=180 Vac, VLED≈60 V, ILED=4 A, PO=240 W Fig. 16. ZVS Performance of the LLC PFC on Primary Side at θ=60º, When
Vin=180 Vac, VLED≈60 V, ILED=4 A, PO=240 W

Fig. 14. ZVS Performance of the LLC PFC on Primary Side at θ=30º, When
Vin=180 Vac, VLED≈60 V, ILED=4 A, PO=240 W Fig. 17. ZVS Performance of the LLC PFC Stage on Primary Side at θ=90º,
When Vin=180 Vac, VLED≈60 V, ILED=4 A, PO=240 W

LLC PFC Power Factor (Io=4A)

0.99
0.97
1
0.95 0.90
0.93
0.9
0.92 0.82
0.90
0.8

0.7 0.78
180V 220V 300V
40V output 50V output 60V output

Fig. 15. ZVS Performance of the LLC PFC on Primary Side at θ=45º, When Fig. 18. Power factor performance of the Half-bridge LLC LED Driver at
Vin=180 Vac, VLED≈60 V, ILED=4 A, PO=240 W Different Input and Output Voltages

7
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