IC and BJT

Fabrication
CONTENTS
 IC Fabrication

What is IC ?
An integrated circuit-also called a microchip-semiconductor

wafer(substrate)-formation of R,C,Transistors along with interconnection are

formed during same time-it is light, has low power consumption, and is used to

manufacture AMPLIFIERS, OSCILLATORS, COMPUTER MEMORY etc

 How IC is produced
STEP 1------->WAFER PRODUCTION
● The wafer-- round slice--semiconductor-- Silicon--preferred characteristics
● Purified polycrystalline silicon--created--sand--heated--produce molten liquid--A small piece is dipped on the molten liquid--Then
pulled from the melt.
● The liquid cools to form single crystal ingot. A thin round wafer of silicon is cut using wafer slicer having thickness about .01 to
.025inches
● The wafers are cleaned using high purity low particle chemicals .The silicon wafers are exposed to ultra pure oxygen.

STEP 2-------->MASKING
● To protect some area--when working on another area--called photolithography
● includes application of a photoresist film is applied on the wafer. The wafer is aligned to a mask using photo aligner.
● Then--exposed to UV CAUTION Before that the wafer must be aligned with the mask.
STEP 3------->ETCHING
● Removes material selectively from the surface of wafer to create patterns.
● Etching mask defines pattern -- protect material .
● Etching :
○ isotropic ::
■ In all directions
■ Generally wet etching
■ Time control difficult
■ liquid solvents for removing materials
○ anisotropic ::
■ In one direction
■ Generally Dry etching.
■ Use gases to remove materials
■ Faster
STEP 4------->

DOPING
● Atom with one less electron than silicon such as boron and wiith one electron greater such as phosphorous are introduced
● The P-type (boron) and N-type (phosphorous) are created to reflect their conducting characteristics

ATOMIC DIFFUSION
● p and n regions are created by adding dopants into the wafer -- heated at 1500-2200°F .
● Inert gas carries dopant chemical -- Dopant and gas passed through wafers and dopant get deposited on the wafer

ION IMPLANTATION
● dopant gas (phosphine or boron trichloride) ionized -- it provides a beam of high energy dopant ions to the specified regions of
wafer. It will penetrate the wafer.
● By altering the beam energy, it is possible to control the depth of penetration of dopants into the wafer. The beam current and
time of exposure is used to control the amount of dopant.
STEP 5------->

METALLIZATION
● create contact with silicon and to make interconnections on chip
● Thin layer of aluminum deposited over the whole wafer. Aluminium is selected -- good conductor, good mechanical bond with
silicon, low resistance contact and can be applied and patterned with single deposition and etching process.
● Between components, silicon dioxide used as insulator. ( chemical vapor deposition)--make contact pads, aluminum deposited.
● It is possible to fabricate PNP and NPN transistor in the same silicon substrate. To avoid damage and contamination of circuit,
final dielectric layer (passivation) is deposited. After that, the individual IC will be tested for electrical function.

ASSEMBLY AND PACKAGING

● Each wafer contains hundreds of chips. These chips are separated and packaged by a method called scribing and cleaving
● Diamond saw cut wafer into single chips. The chips that are failed in electrical test are discarded. Before packaging, remaining
chips observed under microscope-- good chip mounted into a package.
● Thin wire is connected using ultrasonic bonding. It is then encapsulated for protection.
● 3 configurations available for packaging ::-- 1) metal can package, 2) ceramic flat package and 3) dual in line package
SYSTEMATIC DIAGRAM
VIDEO EXPLANATION
 BJT FABRICATION

What is BJT
The Bipolar junction transistor is a solid state device and in the BJTs the current flow in
two terminals, they are emitter and collector and the amount of current controlled by the
third terminal i.e. base terminal.

Advantages of BJT
● High driving capability
● High frequency operation
● Digital logic family has an emitter coupled logic used in BJTs as a digital switch

Application
Step 1 - IMPLANTATION OF BURIED LAYER(on
p-substrate)

● The objective is to reduce

collector’s resistance
Epitaxial Layer (No Mask Required)

● The objective is to provide

the proper n-type doping
in which to build the npn
BJT.
 Step 2 - P+ ISOLATION DIFFUSION

● The objective of this step is

to surround (isolate) the
npn BJT by a p+ diffusion.
These regions also permit
contact to the substrate
from the surface.
Step 3 - BASE P-TYPE DIFFUSION

● The step provides the

p-type base for the npn
BJT.
Step 4 - EMITTER N+ DIFFUSION

● This step implements the

n+ emitter of the npn BJT
and the ohmic contact to
the collector.
Step 5 - P+ OHMIC CONTACT

● This step permits ohmic

contact to the base region
if it is not doped sufficiently
high.
Step 6 - CONTACT ETCHING MASK

● This step opens up the

areas in the dielectric area
which metal will
Step 7 - METAL DEPOSTION AND ETCHING

● In this step, the metal is

deposited over the entire
wafer and removed where
it is not wanted.
Step 8 - PASSIVATION

● Covering the entire wafer

with glass and opening the
area over bond pads (which
requires another mask).
THANK YOU

SUBMITTED BY-

● BHAVYA KAPOOR
● BHAVIK MOHINDROO
● CHARANPREET SINGH