Instruction set

The PDP-11 operates on bytes and words. Bytes are specified by a register
number (identifying the register's low-order byte) or by a memory location
. Words are specified by a register number or by the memory location of th
e low-order byte, which must be an even number. In most instructions that
take operands, bit 15 is set to specify byte addressing, or clear to speci
fy word addressing. In the lists in the following two sections, the assemb
ly-language programmer appended B to the instruction symbol to specify a b
yte operation; for example, MOV became MOVB.
[edit]Double-operand instructions
The high-order 4 bits specify the operation to be performed (with bit 15 ge
nerally selecting word versus byte addressing). Two groups of 6 bits specif
y mode and register, as defined above, for each of two operands.
15 12 11 9 8 6 5 3 2 0
Opcode Mode Source Mode Destination
Opcode Mnemonic Effect
01 MOV Move: dest = src
11 MOVB
02 CMP Compare: compute src - dest, set flags only
12 CMPB
03 BIT Bit test: compute dest & src, set flags only
13 BITB
04 BIC Bit clear: dest &= ~src
14 BICB
05 BIS Bit set, a.k.a. logical OR: dest |= src
15 BISB
06 ADD Add, dest += src
16 SUB Subtract, dest -= src
The ADD and SUB instructions use word addressing, and have no byte-orien
ted variations.
Some additional two-operand instructions require a register source operand:

15 9 8 6 5 3 2 0
Opcode Register Mode Src/Dest
Where a register pair is used (written below as "(R,R+1)", the first register
contains the low-order bits and must be even. The second register contains the
high-order bits (or the remainder). An exception is the multiply instruction;
R may be odd, but if it is, the high 16 bits of the result are not stored.
Opcode Mnemonic Effect
070 MUL Multiply: (R,R+1) = R × src
071 DIV Divide: Compute (R,R+1) ÷ src; quotient in R, remainder in R+1
072 ASH Arithmetic shift: R <<= src, shift amount may be -32..31.
073 ASHC Arithmetic shift combined: (R,R+1) <<= src, shift amount may
be -32..31.
074 XOR Exclusive or: dest ^= reg (word only)
075 (floating-point operations)
076 (system instructions)
077 SOB Subtract one and branch: Decrement register, if result non-zero, b
ranch backward 0..63 words.
[edit]Single-operand instructions
The high-order 9 bits specify the operation to be performed (with bit 15 gen
erally selecting word versus byte addressing). (There are not as many operat
ions as it seems, as most combinations of the high-order 4 bits are taken by
the double-operand instructions.) A single group of 6 bits specifies mode a
nd register, as defined above, for the single operand.
15 11 10 6 5 3 2 0
B 0 0 0 1 Opcode Mode Register
Opcode Mnemonic Effect
0003 SWAB Swap bytes: rotate 8 bits
004r (Jump to subroutine)
104x (Emulator trap)
0050 CLR Clear: dest = 0
1050 CLRB
0051 COM Complement: dest = ~dest
1051 COMB
0052 INC Increment: dest += 1
1052 INCB
0053 DEC Decrement: dest -= 1
1053 DECB
0054 NEG Negate: dest = -dest
1054 NEGB
0055 ADC Add carry: dest += C
1055 ADCB
0056 SBC Subtract carry: dest -= C
1056 SBCB
0057 TST Test: Load src, set flags only
1057 TSTB
0060 ROR Rotate right 1 bit
1060 RORB
0061 ROL Rotate left 1 bit
1061 ROLB
0062 ASR Shift right: dest >>= 1
1062 ASRB
0063 ASL Shift right: dest <<= 1
1063 ASLB
0064 MARK Return from subroutine, skip 0..63 instruction words
1064 MTPS Move to status: PS = src
0065 MFPI Move from previous I space: -(SP) = src
1065 MFPI Move from previous D space: -(SP) = src
0066 MTPI Move to previous I space: dest = (SP)+
1066 MTPI Move to previous D space: dest = (SP)+
0067 SXT Sign extend: dest = (16 copies of N flag)
1067 MFPS Move from status: dest = PS

The SWAB instruction, which swaps the high-order and low-order byte of th
e specified word, does not have two variations for byte- and word-address
ing.
[edit]Conditional branch instructions
Most Branch instructions take conditional effect based on the state of the
condition codes in the PSW. A Branch instruction was typically preceded by
a two-operand CMP (compare) or BIT (bit test) or a one-operand TST (test) i
nstruction. Arithmetic and logic instructions also set the condition codes.
In contrast to Intel processors in the X86 architecture, MOV instructions
set them too, so a Branch instruction could be used to branch depending on
whether the value moved was zero or negative.
The high-order byte specifies the operation. The low-order byte is an offse
t relative to the current location of the program counter. The offset is a
number of words (so it is multiplied by 2 before being combined with the pr
ogram counter) and it is a signed number, enabling branches forward and bac
kward in the code.
15 11 10 8 7 0
x 0 0 0 0 Opcode Offset
Opcode Mnemonic Effect
0000xx (System instructions)
0004xx BR Branch unconditionally
0010xx BNE Branch if not equal (Z=0)
0014xx BEQ Branch if equal (Z=1)
0020xx BGE Branch if greater that or equal (N|V = 0)
0024xx BLT Branch if less than (N|V = 1)
0030xx BGT Branch if greater than (N^V = 1)
0034xx BLE Branch if less than or equal (N^V = 0)
1000xx BPL Branch if plus (N=0)
1004xx BMI Branch if minus (N=1)
1010xx BHI Branch if higher than (C|Z = 0)
1014xx BLOS Branch if lower or same (C|Z = 1)
1020xx BVC Branch if overflow clear (V=0)
1024xx BVS Branch if overflow set (V=1)
1030xx BCC Branch if carry clear (C=0)
BHIS Branch if higher or same (C=0)
1034xx BCS Branch if carry set (C=1)
BLO Branch of lower than (C=1)
An additional conditional branch instruction is SOB (subtract one and branch
), which is listed above under 2-operand instructions. The register operand
is decremented. If the result is non-zero, the low 6 bits are taken as an un
signed number of instructions to branch backward.
The limited range of the branch instructions meant that, as code grew,
the target addresses of some branches would become unreachable. The pro
grammer would change the one-word BR to the two-word JMP instruction fr
om the next group. As JMP has no conditional forms, the programmer woul
d change BEQ to a BNE that branched around a JMP.
[edit]Jump and subroutine instructions
JMP (jump)
JSR (jump to subroutine--see below)
RTS (return from subroutine--see below)
MARK (support of stack clean-up at return)
EMT (emulator trap)
TRAP, BPT (breakpoint trap)
IOT (input/output trap)
RTI & RTT (return from interrupt).
The JSR instruction could save any register on the stack. Programs that did
not need this feature specified PC as the register (JSR PC,address) and the
routine returned using RTS PC. If a routine were called with, for instance,
"JSR R4, address", then the old value of R4 would be on the top of the stack
and the return address (just after JSR) would be in R4. This let the routin
e gain access to values coded in-line by specifying (R4)+, or to in-line poi
nters by specifying @(R4)+. The autoincrementation moved past these data, to
the point at which the caller's code resumed. Such a routine would have to
specify RTS R4 to return to its caller.
[edit]Miscellaneous instructions
HALT, WAIT (wait for interrupt)
RESET (reset UNIBUS)
[edit]Condition-code operations
CLC, CLV, CLZ, CLN, CCC (clear relevant condition code)
SEC, SEV, SEZ, SEN, SCC (set relevant condition code).
The four condition codes in the processor status word (PSW) are
N indicating a negative value
Z indicating a zero (equal) condition
V indicating an overflow condition, and
C indicating a carry condition.
SCC and CCC respectively set and clear all four condition codes.
[edit]Optional instruction sets
Extended Instruction Set (EIS)
The EIS was an option for 11/35/40 and 11/03, and was standard on newer p
rocessors.
MUL, DIV multiply and divide integer operand to register pair
ASH, ASHC arithmetic - shift a register or a register pair. For a positive numb
er it will shift left, and right for a negative one.
Floating Instruction Set (FIS)
The FIS instruction set was an option for the PDP-11/35/40 and 11/03
FADD, FSUB, FMUL, FDIV only for single-precision operating on stack add
ressed by register operand
Floating Point Processor (FPP)
This was the optional floating point processor option for 11/45 and most su
bsequent models.
full floating point operations on single- or double-precision operands, selec
ted by single/double bit in Floating Point Status Register
single-precision floating point data format predecessor of IEEE 754 format:
sign bit, 8-bit exponent, 23-bit mantissa with hidden bit 24
Commercial Instruction Set (CIS)
The CIS was implemented by optional microcode in the 11/23/24, and by an
add-in module in the 11/44 and in one version of the 11/74. It provided s
tring and decimal instructions used by COBOL and Dibol.
Access to Processor Status Word (PSW)
The PSW was mapped to memory address 177 776, but instructions found on a
ll but the earliest PDP-11s gave programs more direct access to the regis
ter.
SPL (set priority level)
MTPS (move to Processor Status)
MFPS (move from Processor Status)
Access to other memory spaces
On PDP-11s that provided multiple instruction spaces and data spaces, a set
of non-orthogonal Move instructions gave access to other spaces. For examp
le, routines in the operating system that handled run-time service calls wo
uld use these instructions to exchange information with the caller.
MTPD (move to previous data space)
MTPI (move to previous instruction space)
MFPD (move from previous data space)
MFPI (move from previous instruction space)
[edit]Inconsistent instructions
Over the life of the PDP-11, subtle differences arose in the implementation
of instructions and combinations of addressing modes, though no implementa
tion was regarded as correct. The inconsistencies did not affect ordinary u
se of the PDP-11.
For example, the instruction MOV R5,-(R5) moves the value in a register to
the address it points to, after decrementing it by two. A microprogrammed
PDP-11 might completely evaluate the source operand before starting to ev
aluate the destination operand, so the value moved would not reflect the d
ecrementation. A PDP-11 implemented by circuitry might perform the decreme
ntation first, because doing so in general might save a memory cycle.
[edit]Interrupts

The PDP-11 operated at a priority level from 0 through 7, declared by three

bits in the Processor Status Word (PSW).
To request an interrupt, a bus device would assert one of four common bus li
nes, BR4 through BR7, until the processor responded. Higher numbers indicate
d greater urgency, perhaps that data might be lost or a desired sector might
rotate out of contact with the read/write heads unless the processor respon
ded quickly. The printer's readiness for another character was the lowest pr
iority (BR4), as it would remain ready indefinitely. If the processor were o
perating at level 5, then BR6 and BR7 would be in order. If the processor we
re operating at 3 or lower, it would grant any interrupt; if at 7, it would
grant none. Bus requests that were not granted were not lost but merely defe
rred. The device needing service would continue to assert its bus request.
Whenever an interrupt exceeded the processor's priority level, the processor
asserted the corresponding bus grant, BG4 through BG7. The bus-grant lines we
re not common lines but were a daisy chain: The input of each gate was the ou
tput of the previous gate in the chain. A gate was on each bus device, and a
device physically closer to the processor was earlier in the daisy chain. If
the device had made a request, then on sensing its bus-grant input, it could
conclude it was in control of the bus, and did not pass the grant signal to t
he next device on the bus. If the device had not made a request, it propagate
d its bus-grant input to its bus-grant output, giving the next closest device
the chance to reply. (If devices did not occupy adjacent slots to the proces
sor board, "grant continuity cards" inserted into the empty slots propagated
the bus-grant line.)
Once in control of the bus, the device dropped its bus request and placed o
n the bus the memory address of its 2-word vector. The processor saved the
program counter (PC) and PSW, and loaded new values from the specified vect
or. For a device at BR6, the new PSW in its vector would typically specify
6 as the new processor priority, so the processor would honor more urgent r
equests (BR7) during the service routine, but defer requests of the same or
 lower priority. With the new PC, the processor jumped to the service routi
ne for the interrupting device. That routine operated the device, at least
removing the condition that caused the interrupt. The routine ended with th
e RTI (ReTurn from Interrupt) instruction, which restored PC and PSW as of
just before the processor granted the interrupt.
If a bus request were made in error and no device responded to the bus gran
t, the processor timed out and performed a trap that would suggest bad hard
ware.
[edit]MACRO-11 assembly language

Punched tape used for PDP-11

MACRO-11 is the assembly language for the PDP-11. It is the successor to
PAL-11 (Program Assembler Loader), an earlier version of the PDP-11 ass
embly language without macro facilities. MACRO-11 was supported on all D
EC PDP-11 operating systems. PDP-11 Unix systems also include an assembl
er (called "as"), structurally similar to MACRO-11 but with different sy
ntax and fewer features.
[edit]PDP-11 lore

A (false) folk myth is that the instruction set architecture of the PDP-11 i
nfluenced the idiomatic use of the C programming language. The PDP-11's incr
ement and decrement addressing modes correspond to the --i and i++ construct
s in C. If i and j were both register variables, an expression such as *(--i
) = *(j++) could be compiled to a single machine instruction. A further clai
m is that the lack of different opcodes for single and double floating point
operations resulted in the mapping of single precision operations to double
precision in the language. Dennis Ritchie unambiguously contradicts this fo
lk myth.[3]