EE4620/6620, CEG4324/6324

Digital Integrated Circuit Design

with PLDs and FPGAs

VIVADO TUTORIAL

Create a VHDL project in Xilinx Vivado Design Suite

Kiran. J
Ph.D. in Electrical Engineering
Wright State University
August 2018

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A. Introduction
This document provides instructions to create a VHDL project in Xilinx Vivado and functionally verify and
validate your design along with the implementations steps to upload the design to the FPGA development
board, ZedBoard.

Given all the source files and minimum knowledge of VHDL programming, this tutorial guides you through
the design flow using Xilinx Vivado software to create a simple digital logic. A typical design flow consists
of creating models, creating user constraint files, creating a Vivado project, importing created models,
assigning created constraint files, running behavioral simulation, synthesizing design, implementing design,
generating bitstream, and finally verifying design in FPGA board. In the following tutorial, you will be
guided step-by-step through the design flow targeting the FPGA development board, ZedBoard.

B. Create a Project
Launch Vivado and create a project targeting the ZedBoard Zynq Evaluation and development kit
(xc7z020clg484-1) using VHDL. Use the provided VHDL, Full_adder.vhd, TB_Full_adder.vhd and the
constraint file, contraint.xdc from your source directory.
1. Open Vivado by clicking on the Launch icon on the desktop.

Fig 1: Vivado Desktop Icon

2. After opening Vivado, select Create New Project on the getting started page.
3. In the New Project dialog box, click on Browse button of the Project Location field and browse to
c:/users/ecslogon/Desktop/FPGA LAB. If you do not find FPGA LAB folder on the desktop then
you have to create one. Next, give a name to your project in the Project Name field. Make sure
Create project subdirectory is checked and click Next as shown in Fig 2.

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 Fig 2: Create New Project

4. Select RTL Project in the Project Type form and click Next.
5. In the Add Source form, click on Add Files button and browse to your source location, select .vhd
(your VHDL file). It is preferable that you copy your VHDL file to FPGA LAB folder. If you want to
add more one source files, click and hold Ctrl key, and select all the required files. Click OK to close
the File browser as shown in Fig. 3 and click Next.

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 Fig 3: Add Source Files

6. Click Next again to skip the Add Existing IP page since you will not be adding IP at this time.
7. On the Add Constraints pages, click Add Files browse to your source location and select
constraints.xcd file and click OK. Enable the check box to copy constraints files into project and click
Next as shown in Fig. 4.

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 Fig 4: Add Constraints

8. On the Default part select Family under select options and choose ZedBoard Zynq Evaluation and
Development Kit and click Next as shown in Fig. 5. Click Finish to close the New Project Summary
page, and create the project.

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 Fig 5: Selecting the Board

C. Working on the Project

The Vivado tool lets you add different design sources, including Verilog, VHDL, EDIF, NGC format cores,
SDC, XDC, and TCL constraints files, and simulation test benches. These files can be sorted in a different
way using the tabs at the bottom of the Sources: Hierarchy, Library or Compile Order.

In the Source Window, you should see all your source files that you have added. Under Design Sources
the file TopModule.vhd should be set as the top module indicated with three boxes next to it and the file
is highlighted in bold text as shown in Fig. 6. If the file TopModule.vhd is not set as the top module in the
source window then right click the file and select Set as Top Module. Similarly, under simulation sources
you test bench TB_Full_adder.vhd should be set as topmodule.

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 Fig 6: Project Window

D. Running Behavioral Simulation

In the Flow Navigator, under simulation click on Run Simulation and select Run Behavioral
Simulation as shown in Fig. 7.

Fig 7: Run Behavioral Simulation

Simulation window should open with the name Untitled 1. Now click Zoom to Fit in the waveform
window then you should see the test vectors with the respective outputs as shown in Fig. 8.

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 Fig 8: Waveform Window

E. Generating Bitstream

Since the XDC constraints file has LOC and IOSTANDARDs constraints set for all of the I/O ports, you
can generate a bitstream. In the Flow Navigator, select Generate Bitstream as shown in Fig. 9. Select
Launch runs on local host and click OK. Click Yes on No Implementation Results Available dialog
box.

Fig 9: Generate Bitstream

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F. Program the ZedBoard

Once the bitstream is generated, Bitstream Generation Completed dialog box will open. Select Open
Hardware Manager and click OK as shown in Fig. 10. Now, turn on you ZedBoard.

Fig 10: Open Hardware Manager

In the Hardware Manager window select Open target and click on Auto Connect as shown in Fig. 11.

Fig 11: Open Hardware Target

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Now you see you FPGA xc7z020_1 under localhost as shown in Fig. 12. Click on Program device and
select the FPGA. Program device dialog box will open. Then, click on Program. This will load the
TopModule.bit file onto the FPGA.

Fig 12: Device Under Localhost

Fig 13: Program the Device

G. Input Through the board

Once the Zedboard is programmed, a blue LED should light up next to the OLED screen. Dip
switch 1, 2 and 3 will your inputs A, B and C respectivelty and Led 4 and 5 will be your Sum

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(S) and Carry out (Co).

Fig 14: Input ABC=101 and output S=0 and Co=1

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 APPENDIX
NOTE: Please the design files with a .vhd extension.

TOPMODULE
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Kiran
-- Create Date: 08/27/2018 01:47:29 PM
-- Design Name:
-- Module Name: TopModule - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TopModule is
Port ( SW : in STD_LOGIC_VECTOR (2 downto 0);
LED : out STD_LOGIC_VECTOR (4 downto 0));
end TopModule;

architecture Behavioral of TopModule is

component Full_adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
S : out STD_LOGIC;
Co : out STD_LOGIC);
end component;

signal a, b, c, s, co : std_logic;

begin

a<=SW(0);
b<=SW(1);
c<=SW(2);

LED(0)<=a;
LED(1)<=b;
LED(2)<=c;
LED(3)<=s;
LED(4)<=co;

BB: Full_adder port map (A=>a ,B=>b, C=>c, S=>s, Co=>co);

end Behavioral;

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FULL ADDER DESGIN
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Kiran
-- Create Date: 08/27/2018 01:28:18 PM
-- Design Name:
-- Module Name: Full_adder - Behavioral
-- Project Name:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Full_adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
S : out STD_LOGIC;
Co : out STD_LOGIC);
end Full_adder;

architecture Behavioral of Full_adder is

begin

S<= A xor B xor C;

Co<= (A and B) or (B and C) or (C and A);

end Behavioral;

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TEST BENCH
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Kiran
-- Create Date: 08/27/2018 01:32:21 PM
-- Design Name:
-- Module Name: TB_Full_adder - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TB_Full_adder is
-- Port ( );
end TB_Full_adder;

architecture Behavioral of TB_Full_adder is

component Full_adder is --DECLARE COMPONENT

Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
S : out STD_LOGIC;
Co : out STD_LOGIC);
end component;

signal abc : STD_LOGIC_VECTOR(2 downto 0); --CREATE INTERNAL SIGNALS

signal s,co: STD_LOGIC;

begin
--INSTANTIATE COMPONENT FOR TEST
UUT: Full_adder port map ( A=>abc(2), B=>abc(1), C=>abc(0), S=>s, Co=>co);

process
begin
abc<="000"; --APPLY INPUT STIMULUS
wait for 100ns;
abc<="001";
wait for 100ns;
abc<="010";
wait for 100ns;
abc<="011";
wait for 100ns;
abc<="100";
wait for 100ns;
abc<="101";
wait for 100ns;
abc<="110";
wait for 100ns;
abc<="111";
wait;
end process;
end Behavioral;

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CONSTRAINT FILE

NOTE: Please save the constraint file with a .xdc extension.

#LEDS
set_property IOSTANDARD LVTTL [get_ports {LED[4]}]
set_property IOSTANDARD LVTTL [get_ports {LED[3]}]
set_property IOSTANDARD LVTTL [get_ports {LED[2]}]
set_property IOSTANDARD LVTTL [get_ports {LED[1]}]
set_property IOSTANDARD LVTTL [get_ports {LED[0]}]
set_property PACKAGE_PIN T22 [get_ports {LED[0]}]
set_property PACKAGE_PIN T21 [get_ports {LED[1]}]
set_property PACKAGE_PIN U22 [get_ports {LED[2]}]
set_property PACKAGE_PIN U21 [get_ports {LED[3]}]
set_property PACKAGE_PIN V22 [get_ports {LED[4]}]
#DIP SWITCHES
set_property IOSTANDARD LVCMOS33 [get_ports {SW[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW[0]}]
set_property PACKAGE_PIN H22 [get_ports {SW[2]}]
set_property PACKAGE_PIN G22 [get_ports {SW[1]}]
set_property PACKAGE_PIN F22 [get_ports {SW[0]}]

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