CMOS Amplifiers
Most CMOS ampliﬁers have identical bipolar counterparts and can therefore be analyzed in the same fashion. Our study in this chapter parallels the developments in Chapter 5, identifying both similarities and differences between CMOS and bipolar circuit topologies. It is recommended that the reader review Chapter 5, speciﬁcally, Section 5.1. We assume the reader is familiar with concepts such as I/O impedances, biasing, and dc and smallsignal analysis. The outline of the chapter is shown below.
General Concepts
• Biasing of MOS Stages
• Realization of Current Sources
➤
MOS Amplifiers
• Common–Source Stage
• Common–Gate Stage
• Source Follower
GENERAL CONSIDERATIONS
7.1.1 MOS Amplifier Topologies
Recall from Section 5.3 that the nine possible circuit topologies using a bipolar transistor in fact reduce to three useful conﬁgurations. The similarity of bipolar and MOS smallsignal models (i.e., a voltagecontrolled current source) suggests that the same must hold for MOS ampliﬁers. In other words, we expect three basic CMOS ampliﬁers: the “commonsource” (CS) stage, the “commongate” (CG) stage, and the “source follower.”
7.1.2 Biasing
Depending on the application, MOS circuits may incorporate biasing techniques that are quite different from those described in Chapter 5 for bipolar stages. Most of these tech niques are beyond the scope of this book and some methods are studied in Chapter 5. Nonetheless, it is still instructive to apply some of the biasing concepts of Chapter 5 to MOS stages.
309
310
Chapter 7
CMOS Amplifiers
Figure 7.1
R
D
D
^{M} 1
1 kΩ
V DD
= 1.8 V
4 kΩ
10 k _{Ω}
MOS stage with biasing.
Consider the circuit shown in Fig. 7.1, where the gate voltage is deﬁned by R _{1} and R _{2} . We assume M _{1} operates in saturation. Also, in most bias calculations, we can neglect channellength modulation. Noting that the gate current is zero, we have
Since V _{X} = V _{G}_{S} + I _{D} R _{S} ,
Also,
V X =
^{R} ^{2} R _{1} +
_{R} 2 V _{D}_{D} .
R
2
R _{1} +
_{R} 2 V _{D}_{D} = V _{G}_{S} + I _{D} R _{S} .
I D =
1
_{2}
μ n C ox
W
L
(V _{G}_{S} − V _{T}_{H} ) ^{2} .
(7.1)
(7.2)
(7.3)
Equations (7.2) and (7.3) can be solved to obtain I _{D} and V _{G}_{S} , either by iteration or by ﬁnding I _{D} from Eq. (7.2) and replacing for it in Eq. (7.3):
That is,
where
R
2
_{R} _{2} V DD − V GS
R _{1} +
1
1
=
R S
_{2}
μ n C ox
W
L
(V _{G}_{S} − V _{T}_{H} ) ^{2} .
V _{G}_{S} = −(V _{1} − V _{T}_{H} ) + (V _{1} − V _{T}_{H} ) ^{2} − V ^{2}
2R _{2}
_{R} _{1} _{+} _{R} 2 V _{1} V _{D}_{D} ,
TH ^{+}
= −(V _{1} − V _{T}_{H} ) + V
2
1
+
2V _{1}
R 2 V DD
R _{1} + R
2
− V _{T}_{H} ,
V 1 =
^{1}
μ n C ox
W
L
R S
.
(7.4)
(7.5)
(7.6)
(7.7)
This value of V _{G}_{S} can then be substituted in Eq. (7.2) to obtain I _{D} . Of course, V _{Y} must exceed V _{X} − V _{T}_{H} to ensure operation in the saturation region.
Example 
Determine the bias current of M _{1} in Fig. 7.1 assuming V _{T}_{H} = 0.5 V, μ _{n} C _{o}_{x} = 
7.1 
100 μA/V ^{2} , W/L = 5/0.18, and λ = 0. What is the maximum allowable value of R _{D} for M _{1} to remain in saturation? 
7.1
General Considerations
311
312
Chapter 7
CMOS Amplifiers
Example 
In the circuit of Example 7.1, assume M _{1} is in saturation and R _{D} = 2.5 k and compute 

7.2 
(a) 
the maximum allowable value of W/L and (b) the minimum allowable value of R _{S} 

(with W/L = 5/0.18). Assume λ = 0. 

Solution (a) As W/L becomes larger, M _{1} can carry a larger current for a given V _{G}_{S} . With R _{D} = 2.5 k and V _{X} = 1.286 V, the maximum allowable value of I _{D} is given by 

_{I} _{D} _{=} V DD − V Y 
(7.20) 

R D 

= 406 μA. 
(7.21) 

The voltage drop across R _{S} is then equal to 406 mV, yielding V _{G}_{S} = 1.286 V− 0.406 V = 0.88 V. In other words, M _{1} must carry a current of 406 μA with V _{G}_{S} = 0.88 V: 

I D = 
W 

1 _{2} μ n C ox L 
(V _{G}_{S} − V _{T}_{H} ) ^{2} (7.22) 

406 μA = (50 μA/V ^{2} ) ^{W} (0.38 V) ^{2} ; L (7.23) 

thus, 

W 
= 56.2. 
(7.24) 

L 

(b) 
With W/L = 5/0.18, the minimum allowable value of R _{S} gives a drain current of 

406 μA. Since 

V GS = V TH +

2I _{D} 
(7.25) 

W 

μ n C ox L 

= 1.041 V, 
(7.26) 

the voltage drop across R _{S} is equal to V _{X} − V _{G}_{S} = 245 mV. It follows that 

_{R} _{S} _{=} V X − V GS 
(7.27) 

I D 

= 
604 . 
(7.28) 
Exercise Repeat the above example if V _{T}_{H} = 0.35 V.
The selfbiasing technique of Fig. 5.22 can also be applied to MOS ampliﬁers. Depicted in Fig. 7.2, the circuit can be analyzed by noting that M _{1} is in saturation (why?) and the voltage drop across R _{G} is zero. Thus,
I _{D} R _{D} +
V _{G}_{S} + R _{S} I _{D} = V _{D}_{D} .
(7.29)
Finding V _{G}_{S} from this equation and substituting it in Eq. (7.3), we have
I D =
1
_{2}
μ n C ox
W
L
_{D}_{D} − (R _{S} + R _{D} )I _{D} − V _{T}_{H} ] ^{2} ,
[V
(7.30)
7.1
General Considerations
313
Figure 7.2
Selfbiased MOS stage.
V DD
R
D
D
^{M} 1
^{R} S
where channellength modulation is neglected. It follows that
(R _{S} + R _{D} ) ^{2} I _{D} − 2 ⎡
2
⎢
_{⎣}_{(}_{V} _{D}_{D} − V _{T}_{H} )(R _{S} + R _{D} ) +
^{1}
μ n C ox
W
L
⎤
⎥
_{⎦}_{I} _{D} + (V _{D}_{D} − V _{T}_{H} ) ^{2} = 0.
(7.31)
Example 
Calculate the drain current of M _{1} in Fig. 7.3 if μ _{n} C _{o}_{x} = 100 μA/V ^{2} , V _{T}_{H} = 0.5 V, and 

7.3 
λ = 0. What value of R _{D} is necessary to reduce I _{D} by a factor of two? 

^{V} DD = 1.8 V 

R
D
20 k Ω
M

1 kΩ 

W 
5 

= 

1 
L 
0.18 

200 _{Ω} 

Figure 7.3 
Example of selfbiased MOS stage. 

Solution 
Equation (7.31) gives 

I _{D} = 556 μA. 
(7.32) 

To reduce I _{D} to 278 μA, we solve Eq. (7.31) for R _{D} : 

R _{D} = 2.867 k . 
(7.33) 

Exercise 
Repeat the above example if V _{D}_{D} drops to 1.2 V. 
7.1.3 Realization of Current Sources
MOS transistors operating in saturation can act as current sources. As illustrated in Fig. 7.4(a), an NMOS device serves as a current source with one terminal tied to ground, i.e., it draws current from node X to ground. On the other hand, a PMOS transistor
314
Chapter 7
CMOS Amplifiers
^{V} b
(a)
^{V} b
(b)
(c)
^{V} b
(d)
Figure 7.4
(a) NMOS device operating as a current source, (b) PMOS device operating as a
current source, (c) PMOS topology not operating as a current source, (d) NMOS topology not operating as a current source.
[Fig. 7.4(b)] draws current from V _{D}_{D} to node Y. If λ = 0, these currents remain indepen dent of V _{X} or V _{Y} (so long as the transistors are in saturation). It is important to understand that only the drain terminal of a MOSFET can draw a dc current and still present a high impedance. Speciﬁcally, NMOS or PMOS devices conﬁgured as shown in Figs. 7.4(c) and (d) do not operate as current sources because variation of V _{X} or V _{Y} directly changes the gatesource voltage of each transistor, thus changing the drain current considerably. From another perspective, the smallsignal model of these two structures is identical to that of the diodeconnected devices in Fig. 6.34, revealing a smallsignal impedance of only 1/g _{m} (if λ = 0) rather than inﬁnity.
COMMONSOURCE STAGE
7.2.1 CS Core
Shown in Fig. 7.5(a), the basic CS stage is similar to the commonemitter topology, with the input applied to the gate and the output sensed at the drain. For small signals, M _{1} converts the input voltage variations to proportional drain current changes, and R _{D} transforms the drain currents to the output voltage. If channellength modulation is neglected, the smallsignal model in Fig. 7.5(b) yields v _{i}_{n} = v _{1} and v _{o}_{u}_{t} = −g _{m} v _{1} R _{D} . That is,
v
out
v in
=
−g _{m} R _{D} ,
(7.34)
a result similar to that obtained for the common emitter stage in Chapter 5.
Input Applied
to Gate
(a)
Figure 7.5
(a) Commonsource stage, (b) smallsignal mode.
7.2
CommonSource Stage
315
The voltage gain of the CS stage is also limited by the supply voltage. Since g _{m} =
^{} 2μ _{n} C _{o}_{x} (W/L)I _{D} , we have
A _{v} = − 2μ _{n} C _{o}_{x}
W
L
I _{D} R _{D} ,
(7.35)
concluding that if I _{D} or R _{D} is increased, so is the voltage drop across R _{D} ( = I _{D} R _{D} ). ^{1} For M _{1} to remain in saturation,
that is,
V _{D}_{D} − R _{D} I _{D} > V _{G}_{S}
−
V _{T}_{H} ,
R _{D} I _{D} < V _{D}_{D} − (V _{G}_{S} − V _{T}_{H} ).
(7.36)
(7.37)
Example 
Calculate the smallsignal voltage gain of the CS stage shown in Fig. 7.6 if I _{D} = 1 mA, 

7.4 
μ _{n} C _{o}_{x} = 100 μA/V ^{2} , V _{T}_{H} = 0.5 V, and λ = 0. Verify that M _{1} operates in saturation. 

^{V} DD 
= 1.8 V 

R
1 k
D
Ω 

v 
out 

v 
in ^{M} 1 ^{W} 10 = 

L 
0.18 

Figure 7.6 
Example of CS stage. 

Solution 
We have 

g m = 2μ n C ox W L 

I _{D} 
(7.38) 

1 

= 
(7.39) 

_{3}_{0}_{0} _{} . 

Thus, 

A _{v} = −g _{m} R _{D} 
(7.40) 

= 3.33. 
(7.41) 

To check the operation region, we ﬁrst determine the gatesource voltage: 

V GS = V TH +

2I _{D} 
(7.42) 

W 

μ n C ox 
L 

= 1.1 V. 
(7.43) 
^{1} It is possible to raise the gain to some extent by increasing W, but “subthreshold conduction” eventually limits the transconductance. This concept is beyond the scope of this book.
316
Chapter 7
CMOS Amplifiers
The drain voltage is equal to V _{D}_{D} − R _{D} I _{D} = 0.8 V. Since V _{G}_{S} − V _{T}_{H} = 0.6 V, the device indeed operates in saturation and has a margin of 0.2 V with respect to the triode region. For example, if R _{D} is doubled with the intention of doubling A _{v} , then M _{1} enters the triode region and its transconductance drops.
Exercise
What value of V _{T}_{H} places M _{1} at the edge of saturation?
Since the gate terminal of MOSFETs draws a zero current (at very low frequencies),
we say the CS ampliﬁer provides a current gain of inﬁnity. By contrast, the current gain of
a commonemitter stage is equal to β. Let us now compute the I/O impedances of the CS ampliﬁer. Since the gate current is zero (at low frequencies),
(7.44)
a point of contrast to the CE stage (whose R _{i}_{n} is equal to r _{π} ). The high input impedance of the CS topology plays a critical role in many analog circuits. The similarity between the smallsignal equivalents of CE and CS stages indicates that the output impedance of the CS ampliﬁer is simply equal to
(7.45)
R _{i}_{n} = ∞,
R _{o}_{u}_{t} = R _{D} .
This is also seen from Fig. 7.7.
Figure 7.7
v X
Output impedance of CS stage.
In practice, channellength modulation may not be negligible, especially if R _{D} is large. The smallsignal model of CS topology is therefore modiﬁed as shown in Fig. 7.8, revealing that
(7.46)
A _{v} = −g _{m} (R _{D} r _{O} )
R _{i}_{n} = ∞
(7.47)
(7.48)
In other words, channellength modulation and the Early effect impact the CS and CE stages, respectively, in a similar manner.
R _{o}_{u}_{t} = R _{D} r _{O} .
Figure 7.8
i
X
v X
Effect of channellength modulation on CS stage.
7.2
CommonSource Stage
317
Example 
Assuming M _{1} operates in saturation, determine the voltage gain of the circuit depicted 

7.5 

in Fig. 7.9(a) and plot the result as a function of the transistor channel length while other parameters remain constant. ^{V} DD A v 

M 1

v 
out 
L 

v 
in 

(a) 
(b) 

Figure 7.9 (a) CS stage with ideal current source as a load, (b) gain as a function of device 

channel length. 

Solution 
The ideal current source presents an inﬁnite smallsignal resistance, allowing the use of Eq. (7.46) with R _{D} = ∞: 

A _{v} = −g _{m} r _{O} . 
(7.49) 

This is the highest voltage gain that a single transistor can provide. Writing g _{m} = 

^{} 2μ _{n} C _{o}_{x} (W/L)I _{D} and r _{O} = (λI _{D} ) ^{−}^{1} , we have 

A v  = 2μ n C ox 
W 

L 

λ ^{√} I _{D} . (7.50) This result may imply that A _{v}  falls as L increases, but recall from Chapter 6 that λ ∝ L ^{−}^{1} : 

_{}_{A} v _{} _{∝} 2μ _{n} C _{o}_{x} WL I D 
(7.51) 

. 

Consequently, A _{v}  increases with L [Fig. 7.9(b)]. 

Exercise 
Repeat the above example if a resistor of value R _{1} is tied between the gate and drain of M _{1} . 
7.2.2 CS Stage With CurrentSource Load
As seen in the above example, the trade off between the voltage gain and the volt age headroom can be relaxed by replacing the load resistor with a current source. The observations made in relation to Fig. 7.4(b) therefore suggest the use of a PMOS de vice as the load of an NMOS CS ampliﬁer [Fig. 7.10(a)]. Let us determine the smallsignal gain and output impedance of the circuit. Having a constant gatesource voltage, M _{2} simply behaves as a resistor equal to its
Did you know?
The intrinsic gain, g _{m} r _{O} , of MOSFETs has fallen with technology scaling, i.e., as the minimum chan nel length has gone from about 10 μm in the 1960s to 25 nm today. Due to severe channellength modulation, the intrinsic gain of these short channel devices is on the order of 5 to 10, mak ing it difﬁcult to achieve a high voltage gain in many analog circuits. This issue has prompted ex tensive research on analog design using lowgain building blocks. For example, the analogtodigital converter that digitizes the image in your camera may need an op amp with a gain of 4,000 but must now be designed with a gain of only 20.
318
Chapter 7
CMOS Amplifiers
Figure 7.10
^{V} DD
(a) CS stage using a PMOS device as a current source, (b) smallsignal model.
output impedance [Fig. 7.10(b)] because v _{1} = 0 and hence g _{m}_{2} v _{1} = 0. Thus, the drain node of M _{1} sees both r _{O}_{1} and r _{O}_{2} to ac ground. Equations (7.46) and (7.48) give
(7.52)
(7.53)
A _{v} = −g _{m}_{1} (r _{O}_{1} r _{O}_{2} )
R _{o}_{u}_{t} = r _{O}_{1} r _{O}_{2} .
Example 
Figure 7.11 shows a PMOS CS stage using an NMOS current source load. Compute the 

7.6 
voltage gain of the circuit. 

v 
in ^{V} DD M 2 

M 1

v 
out 

^{V} b 

Figure 7.11 CS stage using an NMOS device as current source. 

Solution 
Transistor M _{2} generates a smallsignal current equal to g _{m}_{2} v _{i}_{n} , which then ﬂows through r _{O}_{1} r _{O}_{2} , producing v _{o}_{u}_{t} = −g _{m}_{2} v _{i}_{n} (r _{O}_{1} r _{O}_{2} ). Thus, 

A _{v} = −g _{m}_{2} (r _{O}_{1} r _{O}_{2} ). 
(7.54) 

Exercise 
Calculate the gain if the circuit drives a loads resistance equal to R _{L} . 
7.2.3 CS Stage With DiodeConnected Load
In some applications, we may use a diodeconnected MOSFET as the drain load. Illustrated in Fig. 7.12(a), such a topology exhibits only a moderate gain due to the relatively low impedance of the diodeconnected device (Section 7.1.3). With λ = 0, M _{2} acts as a small signal resistance equal to 1/g _{m}_{2} , and Eq. (7.34) yields
1
A _{v} = −g _{m}_{1} · _{g} m2
_{−} ^{} 2μ _{n} C _{o}_{x} (W/L) _{1} I _{D}
_{=}
^{} 2μ _{n} C _{o}_{x} (W/L) _{2} I _{D}
_{=}
_{−} (W/L) _{1} (W/L) _{2}
.
(7.55)
(7.56)
(7.57)
7.2
CommonSource Stage
319
V in
(a)
(b)
Figure 7.12
(a) MOS stage using a diodeconnected load, (b) bipolar counterpart,
(c) simpliﬁed circuit of (a).
Interestingly, the gain is given by the dimensions of M _{1} and M _{2} and remains independent of process parameters μ _{n} and C _{o}_{x} and the drain current, I _{D} . The reader may wonder why we did not consider a commonemitter stage with a diode connected load in Chapter 5. Shown in Fig. 7.12(b), such a circuit is not used because it provides a voltage gain of only unity:
A _{v} = −g _{m}_{1} ·
1
_{g} m2
= −
I C1
^{1}
·
V T
I C2 _{/}_{V} T
≈ −1.
(7.58)
(7.59)
(7.60)
The contrast between Eqs. (7.57) and (7.60) arises from a fundamental difference between MOS and bipolar devices: transconductance of the former depends on device dimensions whereas that of the latter does not. A more accurate expression for the gain of the stage in Fig. 7.12(a) must take channel length modulation into account. As depicted in Fig. 7.12(c), the resistance seen at the drain is now equal to (1/g _{m}_{2} )r _{O}_{2} r _{O}_{1} , and hence
A v = −g m1
_{g} m2 r _{O}_{2} r _{O}_{1} .
1
(7.61)
Similarly, the output resistance of the stage is given by
R out =
1
_{g} m2 r _{O}_{2} r _{O}_{1} .
(7.62)
Example
7.7
Determine the voltage gain of the circuit shown in Fig. 7.13(a) if λ
Figure 7.13
V
in
^{V} DD
V
out
CS stage with diodeconnected PMOS device.
= 0.
320
Chapter 7
CMOS Amplifiers
Solution
This stage is similar to that in Fig. 7.12(a), but with NMOS devices changed to PMOS transistors: M _{1} serves as a commonsource device and M _{2} as a diodeconnected load. Thus,
A v = −g m2
_{g} m1 r _{O}_{1} r _{O}_{2} .
1
(7.63)
Exercise Repeat the above example if the gate of M _{1} is tied to a constant voltage equal to 0.5 V.
7.2.4 CS Stage With Degeneration
Recall from Chapter 5 that a resistor placed in series with the emitter of a bipolar transistor alters characteristics such as gain, I/O impedances, and linearity. We expect similar results for a degenerated CS ampliﬁer.
Figure 7.14
V in
v out
(a) CS stage with degeneration, (b) smallsignal model.
Figure 7.14 depicts the stage along with its smallsignal equivalent (if λ = 0). As with the bipolar counterpart, the degeneration resistor sustains a fraction of the input voltage change. From Fig. 7.14(b), we have
and hence
v _{i}_{n} = v _{1} + g _{m} v _{1} R _{S}
v 1 =
v
in
1 + g
m _{R} S .
(7.64)
(7.65)
Since g _{m} v _{1} ﬂows through R _{D} , v _{o}_{u}_{t} = −g _{m} v _{1} R _{D} and
v
out
v
in
=
−
= −
^{g} ^{m} ^{R} ^{D} _{R} S 1 + g _{m}
^{R} ^{D}
1
g m
+
R _{S}
,
(7.66)
(7.67)
a result identical to that expressed by Eq. (5.157) for the bipolar counterpart.
7.2
CommonSource Stage
321
Example
7.8
Compute the voltage gain of the circuit shown in Fig. 7.15(a) if λ = 0.
Figure 7.15
V
in
DD
V
out
(a)
v
in
(b)
v
out
(a) Example of CS stage with degeneration, (b) simpliﬁed circuit.
Solution
Transistor M _{2} serves as a diodeconnected device, presenting an impedance of 1/g _{m}_{2} [Fig. 7.15(b)]. The gain is therefore given by Eq. (7.67) if R _{S} is replaced with 1/g _{m}_{2} :
A _{v} = −
^{R} ^{D}
1
g
m1
+
^{1}
.
g
m2
(7.68)
Exercise What happens if λ = 0 for M _{2} ?
In parallel with the developments in Chapter 5, we may study the effect of a resistor appearing in series with the gate (Fig. 7.16). However, since the gate current is zero (at low frequencies), R _{G} sustains no voltage drop and does not affect the voltage gain or the I/O impedances.
Effect of Transistor Output Impedance As with the bipolar counterparts, the inclusion of the transistor output impedance complicates the analysis and is studied in Problem 7.32. Nonetheless, the output impedance of the degenerated CS stage plays a critical role in analog design and is worth studying here. Figure 7.17 shows the smallsignal equivalent of the circuit. Since R _{S} carries a cur rent equal to i _{X} (why?), we have v _{1} = −i _{X} R _{S} . Also, the current through r _{O} is equal to
Figure 7.16
V in
CS stage with gate resistance.
322
Chapter 7
CMOS Amplifiers
Figure 7.17
v X
Output impedance of CS stage with degeneration.
i _{X} − g _{m} v _{1} = i _{X} − g _{m} (−i _{X} R _{S} ) = i _{X} + g _{m} i _{X} R _{S} . Adding the voltage drops across r _{O} and R _{S} and equating the result to v _{X} , we have
and hence
r _{O} (i _{X} + g _{m} i _{X} R _{S} ) + i _{X} R _{S} = v _{X} ,
v X
i X
= r _{O} (1 + g _{m} R _{S} ) + R _{S}
=
≈
(1 + g _{m} r _{O} )R _{S} + r _{O}
g _{m} r _{O} R _{S} + r _{O} .
(7.69)
(7.70)
(7.71)
(7.72)
Alternatively, we observe that the model in Fig. 7.17 is similar to its bipolar counterpart in Fig. 5.46(a) but with r _{π} = ∞. Letting r _{π} → ∞ in Eqs. (5.196) and (5.197) yields the same results as above. As expected from our study of the bipolar degenerated stage, the MOS version also exhibits a “boosted” output impedance.
Example
7.9
Compute the output resistance of the circuit in Fig. 7.18(a) if M _{1} and M _{2} are identical.
Figure 7.18
^{V} b
(a)
^{R} out
^{R} out
r ^{O}^{2}
(b)
(a) Example of CS stage with degeneration, (b) simpliﬁed circuit.
Solution The diodeconnected device M _{2} can be represented by a smallsignal resistance of (1/g _{m}_{2} )r _{O}_{2} ≈ 1/g _{m}_{2} . Transistor M _{1} is degenerated by this resistance, and from Eq. (7.70):
R out = r O1 1 + g m1
g m2 ^{+}
1
1
_{g} m2
(7.73)
7.2
CommonSource Stage
323
which, since g _{m}_{1} = g _{m}_{2} = g _{m} , reduces to
R out = 2r O1 +
≈ 2r _{O}_{1} .
^{1}
g m
(7.74)
(7.75)
Exercise 
Do the results remain unchanged if M _{2} is replaced with a diodeconnected PMOS device? 

Example 
Determine the output resistance of the circuit in Fig. 7.19(a) and compare the result with 

7.10 
that in the above example. Assume M _{1} and M _{2} are in saturation. 

^{V} b2 ^{V} b1
M
1
M
2

^{R} out 
^{R} out
M 1
r O2
^{r} O1 

(a) 
(b) 

Figure 7.19 (a) Example of CS stage with degeneration, (b) simpliﬁed circuit. 

Solution 
With its gatesource voltage ﬁxed, transistor M _{2} operates as a current source, introducing a resistance of r _{O}_{2} from the source of M _{1} to ground [Fig. 7.19(b)]. Equation (7.71) can therefore be written as 

R _{o}_{u}_{t} = (1 + g _{m}_{1} r _{O}_{1} )r _{O}_{2} + r _{O}_{1} 
(7.76) 

≈ 
g _{m}_{1} r _{O}_{1} r _{O}_{2} + r _{O}_{1} . 
(7.77) 

Assuming g _{m}_{1} r _{O}_{2} 1 (which is valid in practice), we have 

R _{o}_{u}_{t} ≈ g _{m}_{1} r _{O}_{1} r _{O}_{2} . 
(7.78) 

We observe that this value is quite higher than that in Eq. (7.75). 

Exercise 
Repeat the above example for the PMOS counterpart of the circuit. 
7.2.5 CS Core With Biasing
The effect of the simple biasing network shown in Fig. 7.1 is similar to that analyzed for the bipolar stage in Chapter 5. Depicted in Fig. 7.20(a) along with an input coupling capacitor (assumed a short circuit), such a circuit no longer exhibits an inﬁnite input impedance:
R _{i}_{n} = R _{1} R _{2} .
(7.79)
324
Chapter 7
CMOS Amplifiers
V
in
V
in
V
in
(a)
(b)
(c)
Figure 7.20
(a) CS stage with input coupling capacitor, (b) inclusion of gate resistance, (c) use of
bypass capacitor.
Thus, if the circuit is driven by a ﬁnite source impedance [Fig. 7.20(b)], the voltage gain falls to
(7.80)
R _{1} R _{2} 
−R _{D} 

R _{G} + R _{1} R _{2} 
_{·} 
1 
+ 
R _{S} 
, 
_{A} v _{=}
g m
where λ is assumed to be zero. As mentioned in Chapter 5, it is possible to utilize degeneration for bias point stability but eliminate its effect on the smallsignal performance by means of a bypass capacitor [Fig. 7.20(c)]. Unlike the case of bipolar realization, this does not alter the input impedance of the CS stage:
(7.81)
R _{i}_{n} = R _{1} R _{2} ,
but raises the voltage gain:
(7.82)
_{A} _{v} _{=} _{−} _{R} _{G} _{+} _{R} _{1} _{}_{}_{R} 2 g _{m} R _{D} .
R _{1} R _{2}
Example 
Design the CS stage of Fig. 7.20(c) for a voltage gain of 5, an input impedance of 50 k , 

7.11 
and a power budget of 5 mW. Assume μ _{n} C _{o}_{x} = 100 μA/V ^{2} , V _{T}_{H} = 0.5 V, λ = 0, and V _{D}_{D} = 1.8 V. Also, assume a voltage drop of 400 mV across R _{S} . 

Solution The power budget along with V _{D}_{D} = 1.8 V implies a maximum supply current of 2.78 mA. As an initial guess, we allocate 2.7 mA to M _{1} and the remaining 80 μA to R _{1} and R _{2} . It follows that 

R _{S} = 148 . 
(7.83) 

As with typical design problems, the choice of g _{m} and R _{D} is somewhat ﬂexible so long as g _{m} R _{D} = 5. However, with I _{D} known, we must ensure a reasonable value for V _{G}_{S} , e.g., V _{G}_{S} = 1 V. This choice yields 

2I _{D} 

_{g} m _{=} 
(7.84) 

V GS − 
_{V} TH 

1 

= 
(7.85) 

_{9}_{2}_{.}_{6} _{} , 
7.3
CommonGate Stage
325
Exercise
Repeat the above example for a power budget of 3 mW and V _{D}_{D} = 1.2 V.
COMMONGATE STAGE
Shown in Fig. 7.21, the CG topology resembles the commonbase stage studied in Chapter 5. Here, if the input rises by a small value, V, then the gatesource voltage of M _{1} decreases by the same amount, thereby lowering the drain current by g _{m} V and
326
Chapter 7
CMOS Amplifiers
Figure 7.21
Commongate stage.
raising V _{o}_{u}_{t} by g _{m} VR _{D} . That is, the voltage gain is positive and equal to
A _{v} = g _{m} R _{D} .
(7.95)
The CG stage suffers from voltage headroomgain tradeoffs similar to those of the CB topology. In particular, to achieve a high gain, a high I _{D} or R _{D} is necessary, but the drain voltage, V _{D}_{D} − I _{D} R _{D} , must remain above V _{b} − V _{T}_{H} to ensure M _{1} is saturated.
Example 
A 
microphone having a dc level of zero drives a CG stage biased at I _{D} = 0.5 mA. If 

7.12 
W/L = 50, μ _{n} C _{o}_{x} = 100 μA/V ^{2} , V _{T}_{H} = 0.5 V, and V _{D}_{D} = 1.8 V, determine the maxi mum allowable value of R _{D} and hence the maximum voltage gain. Neglect channel length modulation. 

Solution 
With W/L known, the gatesource voltage can be determined from 

I D = 
1 _{2} μ n C ox 
W 

L 
(V _{G}_{S} − V _{T}_{H} ) ^{2} 
(7.96) 

as 

_{G}_{S} = 0.947 V. V 
(7.97) 

For M _{1} to remain in saturation, 

V _{D}_{D} − I _{D} R _{D} > V _{b} − V _{T}_{H} 
(7.98) 

and hence 

R _{D} < 2.71 k . 
(7.99) 

Also, the above value of W/L and I _{D} yield g _{m} = (447 ) ^{−}^{1} and 

A _{v} ≤ 6.06. 
(7.100) 

Figure 7.22 summarizes the allowable signal levels in this design. The gate voltage can 

be 
generated using a resistive divider similar to that in Fig. 7.20(a). 

Exercise 
If a gain of 10 is required, what value should be chosen for W/L? 
7.3
CommonGate Stage
327
Figure 7.22
^{V}
b
–
^{V} TH
Signal levels in CG stage.
^{V} b
= 0.947 V
We now compute the I/O impedances
of the CG stage, expecting to obtain results
similar to those of the CB topology. Neglect
ing channellength modulation for now, we have from Fig. 7.23(a) v _{1} = −v _{X} and
i _{X} = −g _{m} v _{1}
= g _{m} v _{X} .
R in =
low
^{1}
,
g m
value.
(7.101)
(7.102)
That is,
(7.103)
Fig.
a
7.23(b), v _{1} = 0 and hence
relatively
Also,
from
R _{o}_{u}_{t} = R _{D} ,
(7.104)
an expected result because the circuits of Figs. 7.23(b) and 7.7 are identical. Let us study the behavior of the CG stage in the presence of a ﬁnite source impedance (Fig. 7.24) but still with λ = 0. In a manner similar to that depicted in Chapter 5 for the CB topology, we write
1
v X =
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