I2c Bus

ne NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend

//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_UNPEND1 register.
//
//*****************************************************************************
#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
//
//*****************************************************************************
#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active
#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
//
//*****************************************************************************
#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI0 register.
//
//*****************************************************************************
#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask
#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask
#define NVIC_PRI0_INT3_S 29
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_CPUID register.
//
//*****************************************************************************
#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code
#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM
#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number
#define NVIC_CPUID_CON_M 0x000F0000 // Constant
#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number
#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor
#define NVIC_CPUID_REV_M 0x0000000F // Revision Number
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_INT_CTRL register.
//
//*****************************************************************************
#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending
#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending
#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending
#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending
#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending
#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling
#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending
#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number
#define NVIC_INT_CTRL_VEC_PEN_NMI \
0x00002000 // NMI
#define NVIC_INT_CTRL_VEC_PEN_HARD \
0x00003000 // Hard fault
#define NVIC_INT_CTRL_VEC_PEN_MEM \
0x00004000 // Memory management fault
#define NVIC_INT_CTRL_VEC_PEN_BUS \
0x00005000 // Bus fault
#define NVIC_INT_CTRL_VEC_PEN_USG \
0x00006000 // Usage fault
#define NVIC_INT_CTRL_VEC_PEN_SVC \
0x0000B000 // SVCall
#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
0x0000E000 // PendSV
#define NVIC_INT_CTRL_VEC_PEN_TICK \
0x0000F000 // SysTick
#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base
#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number
#define NVIC_INT_CTRL_VEC_ACT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_VTABLE register.
//
//*****************************************************************************
#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base
#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset
#define NVIC_VTABLE_OFFSET_S 9
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_APINT register.
//
//*****************************************************************************
#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key
#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess
#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping
#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request
#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault
#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
//
//*****************************************************************************
#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending
#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable
#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
//
//*****************************************************************************
#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception
// Entry
#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and
// Fault
#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0
#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access
#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger
#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
//
//*****************************************************************************
#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority
#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority
#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority
#define NVIC_SYS_PRI1_USAGE_S 21
#define NVIC_SYS_PRI1_BUS_S 13
#define NVIC_SYS_PRI1_MEM_S 5
//*****************************************************************************
//
//
//*****************************************************************************
#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority
#define NVIC_SYS_PRI2_SVC_S 29
//*****************************************************************************
//
//
//*****************************************************************************
#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority
#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority
#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority
#define NVIC_SYS_PRI3_TICK_S 29
#define NVIC_SYS_PRI3_PENDSV_S 21
#define NVIC_SYS_PRI3_DEBUG_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
// register.
//
//*****************************************************************************
#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable
#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable
#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable
#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending
#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending
#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending
#define NVIC_SYS_HND_CTRL_USAGEP \
0x00001000 // Usage Fault Pending
#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active
#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active
#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active
#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active
#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active
#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active
#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_FAULT_STAT
// register.
//
//*****************************************************************************
#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault
#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault
#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault
#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault
#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault
#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage
// Fault
#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid
#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault
#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault
#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error
#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error
#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error
#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address
// Register Valid
#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation
#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation
#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation
#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_HFAULT_STAT
// register.
//
//*****************************************************************************
#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event
#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault
#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DEBUG_STAT
// register.
//
//*****************************************************************************
#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MM_ADDR register.
//
//*****************************************************************************
#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address
#define NVIC_MM_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_FAULT_ADDR
// register.
//
//*****************************************************************************
#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address
#define NVIC_FAULT_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
//
//*****************************************************************************
#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions
#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions
#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU
#define NVIC_MPU_TYPE_IREGION_S 16
#define NVIC_MPU_TYPE_DREGION_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
//
//*****************************************************************************
#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region
#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults
#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MPU_NUMBER
// register.
//
//*****************************************************************************
#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access
#define NVIC_MPU_NUMBER_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MPU_BASE register.
//
//*****************************************************************************
#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask
#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid
#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number
#define NVIC_MPU_BASE_ADDR_S 5
#define NVIC_MPU_BASE_REGION_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
//
//*****************************************************************************
#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes
#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable
#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege
#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access
#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none
#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only
#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw
#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none
#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro
#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask
#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits
#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable
#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask
#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes
#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes
#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes
#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes
#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes
#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes
#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes
#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes
#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes
#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes
#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes
#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes
#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes
#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes
#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes
#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes
#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
//
//*****************************************************************************
#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask
#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid
#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number
#define NVIC_MPU_BASE1_ADDR_S 5
#define NVIC_MPU_BASE1_REGION_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
//
//*****************************************************************************
#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable
#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege
#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask
#define NVIC_MPU_ATTR1_SHAREABLE \
0x00040000 // Shareable
#define NVIC_MPU_ATTR1_CACHEABLE \
0x00020000 // Cacheable
#define NVIC_MPU_ATTR1_BUFFRABLE \
0x00010000 // Bufferable
#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits
#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask
#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
//
//*****************************************************************************
#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
#define NVIC_DBG_CTRL_S_RESET_ST \
0x02000000 // Core has reset since last read
#define NVIC_DBG_CTRL_S_RETIRE_ST \
0x01000000 // Core has executed insruction
// since last read
#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
#define NVIC_DBG_CTRL_C_SNAPSTALL \
0x00000020 // Breaks a stalled load/store
#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DBG_XFER register.
//
//*****************************************************************************
#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DBG_DATA register.
//
//*****************************************************************************
#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
#define NVIC_DBG_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DBG_INT register.
//
//*****************************************************************************
#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_SW_TRIG register.
//
//*****************************************************************************
#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID
#define NVIC_SW_TRIG_INTID_S 0
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_CTL register.
//
//*****************************************************************************
#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input
#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source
#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode
#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode
#define PWM_X_CTL_MODE 0x00000002 // Counter Mode
#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_INTEN register.
//
//*****************************************************************************
#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
// Down
#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
// Down
#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
// Down
#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
// Up
#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
// Down
#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
// Up
#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_RIS register.
//
//*****************************************************************************
#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
// Status
#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
// Status
#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_ISC register.
//
//*****************************************************************************
#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_LOAD register.
//
//*****************************************************************************
#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value
#define PWM_X_LOAD_S 0
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_COUNT register.
//
//*****************************************************************************
#define PWM_X_COUNT_M 0x0000FFFF // Counter Value
#define PWM_X_COUNT_S 0
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_CMPA register.
//
//*****************************************************************************
#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value
#define PWM_X_CMPA_S 0
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_CMPB register.
//
//*****************************************************************************
#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value
#define PWM_X_CMPB_S 0
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_GENA register.
//
//*****************************************************************************
#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
#define PWM_X_GENA_ACTCMPBD_NONE \
0x00000000 // Do nothing
#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
#define PWM_X_GENA_ACTCMPBD_ZERO \
0x00000800 // Drive pwmA Low
#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
#define PWM_X_GENA_ACTCMPBU_NONE \
#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
#define PWM_X_GENA_ACTCMPBU_ZERO \
#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
#define PWM_X_GENA_ACTCMPAD_NONE \
#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
#define PWM_X_GENA_ACTCMPAD_ZERO \
#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
#define PWM_X_GENA_ACTCMPAU_NONE \
#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
#define PWM_X_GENA_ACTCMPAU_ZERO \
#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing
#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_GENB register.
//
//*****************************************************************************
#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
#define PWM_X_GENB_ACTCMPBD_NONE \
#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
#define PWM_X_GENB_ACTCMPBD_ZERO \
0x00000800 // Drive pwmB Low
#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
#define PWM_X_GENB_ACTCMPBU_NONE \
#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
#define PWM_X_GENB_ACTCMPBU_ZERO \
#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
#define PWM_X_GENB_ACTCMPAD_NONE \
#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
#define PWM_X_GENB_ACTCMPAD_ZERO \
#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
#define PWM_X_GENB_ACTCMPAU_NONE \
#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
#define PWM_X_GENB_ACTCMPAU_ZERO \
#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing
#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_DBCTL register.
//
//*****************************************************************************
#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_DBRISE register.
//
//*****************************************************************************
#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay
#define PWM_X_DBRISE_DELAY_S 0
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_DBFALL register.
//
//*****************************************************************************
#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay
#define PWM_X_DBFALL_DELAY_S 0
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_FLTSRC0 register.
//
//*****************************************************************************
#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_FLTSRC1 register.
//
//*****************************************************************************
#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_MINFLTPER register.
//
//*****************************************************************************
#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period
#define PWM_X_MINFLTPER_S 0
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_FLTSEN register.
//
//*****************************************************************************
#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_FLTSTAT0 register.
//
//*****************************************************************************
#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
//*****************************************************************************
//
// Deprecated defines for the bit fields in the PWM_O_X_FLTSTAT1 register.
//
//*****************************************************************************
#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
//*****************************************************************************
//
// Deprecated defines for the Micro Direct Memory Access register addresses.
//
//*****************************************************************************
#define UDMA_CHALT (*((volatile unsigned long *)0x400FF500))
//*****************************************************************************
//
// Deprecated defines for the bit fields in the UDMA_CHALT register.
//
//*****************************************************************************
#define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment
// Select
#endif
#endif // __LM3S5C36_H__
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
################################################################;version 1.10,
11/04/2014, Copyright 2014 P&E Microcomputer Systems, Inc. All rights reserved.
www.pemicro.com [lm3s_512k_boot]
;device TI, LM3S9DN6, 1x32x128k
;begin_cs device=$0000000, length=$00080000, ram=$20000000
WRITE_LONG=00000001/400FE0F0/ ;Flash memory at address 0x0
NO_BYTE_WRITES
NO_BASE_ADDRESS
;end_cs
BLOCKING_MASK=00000003/ ;long words only
NO_TIMING_TEST
;Pages 256-1k ($00..$FF)
USER=PE Page Erase 2Page > /00000000/000000FF/
;
S01500006C6D33735F3531326B5F626F6F742E733139EB
S315200000005C010020600100200008000000000000C4
S3152000001000000800000000009A00002000000000F8
S31520000020000000005200002000000000E200002036
S315200000300000000000000000AC00002000000000CE
S3152000004000000000000000007C00002000BE00BE72
S3152000005000BE4FF000062E60DFF8D460AE60AE68BA
S3152000006016F0040FFBD14FF400362E60DFF8C06087
S31520000070AE60AE6816F0040FFBD10EE04FF480623E
S3152000008004FB02F6DFF8B01031442960DFF8A460E3
S31520000090AE60AE6816F0060FFBD1DFF8887031F837
S315200000A0028BB84501D1921EF9D100BE00BFDFF800
S315200000B06850EFF3108072B6DFF86070DFF860608A
S315200000C0C7F83061C7F83461C7F83861C7F83C61B2
S315200000D0C7F80062C7F80462C7F80862C7F80C625E
S315200000E000BE296053F8040B6860296001F1040101
S315200000F0DFF83860AE60AE6816F0010FFBD151F81C
S31520000100046CB04202D0DFF8180000BE121FE8D1FE
S3152000011000BE024600BE000000D00F4000E00F40A7
S31520000120FFFFFFFFFFFF000060010020010042A447
S31120000130040042A4020042A400000000CB
S70520000000DA
#�b################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
####################################################################/*-------------
-----------------------------------------------------------------
* RL-ARM - USB
*------------------------------------------------------------------------------
* Name: rl_usb.h
* Purpose: Main header file
* Rev.: V4.70
*------------------------------------------------------------------------------
* This code is part of the RealView Run-Time Library.
* Copyright (c) 2004-2014 KEIL - An ARM Company. All rights reserved.
*----------------------------------------------------------------------------*/
#ifndef __RL_USB_H__
#define __RL_USB_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <..\..\RL\USB\INC\usb.h>
/***************** Functions *************************************************/
/* USB Host functions exported from USB Host Core module */

extern BOOL usbh_mem_init (U8 ctrl, U32 *ptr_pool, U32 pool_sz);
extern BOOL usbh_mem_alloc (U8 ctrl, U8 **ptr, U32 sz);
extern BOOL usbh_mem_free (U8 ctrl, U8 *ptr);
extern BOOL usbh_transfer (U8 ctrl, USBH_EP *ptr_ep, USBH_URB
*ptr_urb, U16 tout);
extern BOOL usbh_init (U8 ctrl);
extern BOOL usbh_init_all (void);
extern BOOL usbh_uninit (U8 ctrl);
extern BOOL usbh_uninit_all (void);
extern BOOL usbh_engine (U8 ctrl);
extern BOOL usbh_engine_all (void);
extern U32 usbh_get_last_error (U8 ctrl);
extern U8 *usbh_get_error_string (U32 err);
/* USB Host functions exported from USB Mass Storage Class module */
extern BOOL usbh_msc_status (U8 ctrl, U8 dev_idx);
extern BOOL usbh_msc_read (U8 ctrl, U8 dev_idx, U32 blk_adr, U8
*ptr_data, U16 blk_num);
extern BOOL usbh_msc_write (U8 ctrl, U8 dev_idx, U32 blk_adr, U8
*ptr_data, U16 blk_num);
extern BOOL usbh_msc_read_config (U8 ctrl, U8 dev_idx, U32 *tot_blk_num, U32
*blk_sz);
extern U32 usbh_msc_get_last_error (U8 ctrl, U8 dev_idx);
/* USB Host functions exported from USB Human Interface Device Class module */
extern BOOL usbh_hid_status (U8 ctrl, U8 dev_idx);
extern int usbh_hid_data_in (U8 ctrl, U8 dev_idx, U8 *ptr_data);
extern int usbh_hid_data_out (U8 ctrl, U8 dev_idx, U8 *ptr_data, U16
data_len);
extern U32 usbh_hid_get_last_error (U8 ctrl, U8 dev_idx);
/* Overridable functions */
extern void usbh_hid_parse_report_desc (U8 ctrl, U8 dev_idx, U8
*ptrHIDReportDesc);
extern void usbh_hid_data_in_callback (U8 ctrl, U8 dev_idx, U8 *ptr_data, U16
data_len);
extern int usbh_hid_kbd_getkey (U8 ctrl, U8 dev_idx);
extern BOOL usbh_hid_mouse_getdata (U8 ctrl, U8 dev_idx, U8 *btn, S8 *x, S8
*y, S8 *wheel);
/* USB Device functions exported from USB Device Core module */

extern void usbd_init (void);
extern void usbd_connect (BOOL con);
extern void usbd_reset_core (void);
extern BOOL usbd_configured (void);
/* USB Device user functions imported to USB HID Class module */

extern void usbd_hid_init (void);
extern BOOL usbd_hid_get_report_trigger(U8 rid, U8 *buf, int len);
extern int usbd_hid_get_report (U8 rtype, U8 rid, U8 *buf, U8 req);
extern void usbd_hid_set_report (U8 rtype, U8 rid, U8 *buf, int len, U8
req);
extern U8 usbd_hid_get_protocol (void);
extern void usbd_hid_set_protocol (U8 protocol);
/* USB Device user functions imported to USB Mass Storage Class module */
extern void usbd_msc_init (void);
extern void usbd_msc_read_sect (U32 block, U8 *buf, U32 num_of_blocks);
extern void usbd_msc_write_sect (U32 block, U8 *buf, U32 num_of_blocks);
extern void usbd_msc_start_stop (BOOL start);
/* USB Device user functions imported to USB Audio Class module */

extern void usbd_adc_init (void);
/* USB Device CDC ACM class functions called automatically by USBD Core module*/
extern int32_t USBD_CDC_ACM_Initialize (void);
extern int32_t USBD_CDC_ACM_Uninitialize (void);
extern int32_t USBD_CDC_ACM_Reset (void);
/* USB Device CDC ACM class user functions */
extern int32_t USBD_CDC_ACM_PortInitialize (void);
extern int32_t USBD_CDC_ACM_PortUninitialize (void);
extern int32_t USBD_CDC_ACM_PortReset (void);
extern int32_t USBD_CDC_ACM_PortSetLineCoding (CDC_LINE_CODING
*line_coding);
extern int32_t USBD_CDC_ACM_PortGetLineCoding (CDC_LINE_CODING
*line_coding);
extern int32_t USBD_CDC_ACM_PortSetControlLineState (uint16_t ctrl_bmp);
extern int32_t USBD_CDC_ACM_DataSend (const uint8_t *buf, int32_t
len);
extern int32_t USBD_CDC_ACM_PutChar (const uint8_t ch);
extern int32_t USBD_CDC_ACM_DataRead ( uint8_t *buf, int32_t
len);
extern int32_t USBD_CDC_ACM_GetChar (void);
extern int32_t USBD_CDC_ACM_DataAvailable (void);
extern int32_t USBD_CDC_ACM_Notify (uint16_t stat);
/* USB Device CDC ACM class overridable functions */
extern int32_t USBD_CDC_ACM_SendEncapsulatedCommand (void);
extern int32_t USBD_CDC_ACM_GetEncapsulatedResponse (void);
extern int32_t USBD_CDC_ACM_SetCommFeature (uint16_t feat);
extern int32_t USBD_CDC_ACM_GetCommFeature (uint16_t feat);
extern int32_t USBD_CDC_ACM_ClearCommFeature (uint16_t feat);
extern int32_t USBD_CDC_ACM_SetLineCoding (void);
extern int32_t USBD_CDC_ACM_GetLineCoding (void);
extern int32_t USBD_CDC_ACM_SetControlLineState (uint16_t ctrl_bmp);
extern int32_t USBD_CDC_ACM_SendBreak (uint16_t dur);
/* USB Device user functions imported to USB Custom Class module */

extern void usbd_cls_init (void);
extern void usbd_cls_sof (void);
extern BOOL usbd_cls_dev_req (BOOL setup);
extern BOOL usbd_cls_if_req (BOOL setup);
extern BOOL usbd_cls_ep_req (BOOL setup);
#ifdef __cplusplus
}
#endif
#endif /* __RL_USB_H__ */
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
########################################################INDX(#
#P�sg############(###�###�###############################��######h#R#####��########
��m��###��m��#c��H�V�###��m��#`#######]#######
#########a#b#s#a#c#c#.#h#######��######p#\#####��########��m��###��m��#[d�H�V�###��
m��##�#######{###### #######
#F#i#l#e#_#C#o#n#f#i#g#.#h#####��######h#V#####��########��m��###��m��##��H�V�###��
m��##p######}j###### #######
#F#i#l#e#_#l#i#b#.#c###��######p#Z#####��########��m��###��m��#�#�H�V�###��m��##�##
#####�###### #######
#N#e#t#_#C#o#n#f#i#g#.#h#######��######h#T#####��########��m��###��m��#ު�H�V�###��m
��##P######lM###### #######
#N#e#t#_#l#i#b#.#c#####��######h#R#####��########��m��###��m��#�1�H�V�###��m��##
######�#######
#########r#l#_#u#s#b#.#h#######��######`#L#####��########��m��###��m��##|
�H�V�###��m��##�#######�######
#########R#T#L#.#h#####��######h#T#####��########��m��###��m��##Q�H�V�###��m��##
######�####### #######
#R#T#X#_#C#A#N#.#h#####��######p#Z#####��########��m��###��m��#�;�H�V�###��m��#####
####{####### #######
#R#T#X#_#C#o#n#f#i#g#.#h#######��######h#T#####��########��m��###��m��#MM�H�V�###��
m��##@######N4###### #######
#R#T#X#_#l#i#b#.#c#####��######h#T#####��########��m��###��m��#>�H�V�###��m��##�###
###\�###### #######
#u#s#b#_#l#i#b#.#c#################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
#########################################################################/*--------
--------------------------------------------------------------------
* RL-ARM - A P I
*----------------------------------------------------------------------------
* Name: RTL.H
* Purpose: Application Programming Interface
* Rev.: V4.73
*----------------------------------------------------------------------------
* This code is part of the RealView Run-Time Library.
* Copyright (c) 2004-2014 KEIL - An ARM Company. All rights reserved.
*---------------------------------------------------------------------------*/
#ifndef __RTL_H__
#define __RTL_H__
/* RL-ARM version number. */

#define __RL_ARM_VER 473
#define __task __declspec(noreturn)

#define __used __attribute__((used))
#ifndef NULL
#ifdef __cplusplus
#define NULL 0
#else
#define NULL ((void *) 0)
#endif
#endif
#ifndef EOF
#define EOF (-1)
#endif
#ifndef __size_t
#define __size_t 1
typedef unsigned int size_t;
#endif
typedef signed char S8;

typedef unsigned char U8;
typedef short S16;
typedef unsigned short U16;
typedef int S32;
typedef unsigned int U32;
typedef long long S64;
typedef unsigned long long U64;
typedef unsigned char BIT;
typedef unsigned int BOOL;
#ifndef __TRUE
#define __TRUE 1
#endif
#ifndef __FALSE
#define __FALSE 0
#endif
#ifdef __BIG_ENDIAN
#define U32_LE(v) (U32)(__rev(v))
#define U16_LE(v) (U16)(__rev(v) >> 16)
#define U32_BE(v) (U32)(v)
#define U16_BE(v) (U16)(v)
#else
#define U32_BE(v) (U32)(__rev(v))
#define U16_BE(v) (U16)(__rev(v) >> 16)
#define U32_LE(v) (U32)(v)
#define U16_LE(v) (U16)(v)
#endif
#define ntohs(v) U16_BE(v)
#define ntohl(v) U32_BE(v)
#define htons(v) ntohs(v)
#define htonl(v) ntohl(v)
/*----------------------------------------------------------------------------
* RTX Kernel API
*---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
/* Definition of Semaphore type */

typedef U32 OS_SEM[2];
/* Definition of Mailbox type */

#define os_mbx_declare(name,cnt) U32 name [4 + cnt]
typedef U32 OS_MBX[];
/* Definition of Mutex type */

typedef U32 OS_MUT[4];
/* Task Identification number. */

typedef U32 OS_TID;
/* Function return of system calls returning an object identification */

typedef void *OS_ID;
/* Function return of system calls indicating an event or completion state */

typedef U32 OS_RESULT;
/* Return codes */
#define OS_R_TMO 0x01
#define OS_R_EVT 0x02
#define OS_R_SEM 0x03
#define OS_R_MBX 0x04
#define OS_R_MUT 0x05
#define OS_R_OK 0x00

#define OS_R_NOK 0xff
#define OS_TCB_SIZE 56
#define OS_TMR_SIZE 8
/* Error Codes */
#define OS_ERR_STK_OVF 1
#define OS_ERR_FIFO_OVF 2
#define OS_ERR_MBX_OVF 3
#if !(__TARGET_ARCH_6S_M || __TARGET_ARCH_7_M || __TARGET_ARCH_7E_M)
/*----------------------------------------------------------------------------
* Functions ARM
*---------------------------------------------------------------------------*/
/* Task Management */
#define os_sys_init(tsk) os_sys_init0(tsk,0,NULL)
#define os_sys_init_prio(tsk,prio) os_sys_init0(tsk,prio,NULL)
#define os_sys_init_user(tsk,prio,stk,size) \
os_sys_init0(tsk,prio|(size<<8),stk)
#define os_tsk_create(tsk,prio) os_tsk_create0(tsk,prio,NULL,NULL)
#define os_tsk_create_user(tsk,prio,stk,size) \
os_tsk_create0(tsk,prio|(size<<8),stk,NULL)
#define os_tsk_create_ex(tsk,prio,argv) os_tsk_create_ex0(tsk,prio,NULL,argv)
#define os_tsk_create_user_ex(tsk,prio,stk,size,argv) \
os_tsk_create_ex0(tsk,prio|
(size<<8),stk,argv)
#define os_tsk_delete_self() { os_tsk_delete(0); for(;;); }
#define os_tsk_prio_self(prio) os_tsk_prio(0,prio)
#define isr_tsk_get() os_tsk_self()
extern void os_sys_init0 (void (*task)(void), U32 prio_stksz, void *stk);

extern OS_TID os_tsk_create0 (void (*task)(void), U32 prio_stksz,
void *stk, void *argv);
extern OS_TID os_tsk_create_ex0 (void (*task)(void *), U32 prio_stksz,
void *stk, void *argv);
extern OS_TID os_tsk_self (void);
extern void os_tsk_pass (void);
extern OS_RESULT os_tsk_prio (OS_TID task_id, U8 new_prio);
extern OS_RESULT os_tsk_delete (OS_TID task_id);
/* Event flag Management */

#define os_evt_wait_or(wflags,tmo) os_evt_wait(wflags,tmo,__FALSE)
#define os_evt_wait_and(wflags,tmo) os_evt_wait(wflags,tmo,__TRUE)
extern OS_RESULT os_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait);

extern void os_evt_set (U16 event_flags, OS_TID task_id);
extern void os_evt_clr (U16 clear_flags, OS_TID task_id);
extern void isr_evt_set (U16 event_flags, OS_TID task_id);
extern U16 os_evt_get (void);
/* Semaphore Management */
extern void os_sem_init (OS_ID semaphore, U16 token_count);
extern OS_RESULT os_sem_send (OS_ID semaphore);
extern OS_RESULT os_sem_wait (OS_ID semaphore, U16 timeout);
extern void isr_sem_send (OS_ID semaphore);
/* Mailbox Management */
#define isr_mbx_check(mbx) os_mbx_check(mbx)
extern void os_mbx_init (OS_ID mailbox, U16 mbx_size);

extern OS_RESULT os_mbx_send (OS_ID mailbox, void *message_ptr, U16 timeout);
extern OS_RESULT os_mbx_wait (OS_ID mailbox, void **message, U16 timeout);
extern OS_RESULT os_mbx_check (OS_ID mailbox);
extern void isr_mbx_send (OS_ID mailbox, void *message_ptr);
extern OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message);
/* Mutex Management */
extern void os_mut_init (OS_ID mutex);
extern OS_RESULT os_mut_release (OS_ID mutex);
extern OS_RESULT os_mut_wait (OS_ID mutex, U16 timeout);
/* Time Management */
extern U32 os_time_get (void);
extern void os_dly_wait (U16 delay_time);
extern void os_itv_set (U16 interval_time);
extern void os_itv_wait (void);
/* User Timer Management */

extern OS_ID os_tmr_create (U16 tcnt, U16 info);
extern OS_ID os_tmr_kill (OS_ID timer);
/* System Functions */
extern U32 os_suspend (void);
extern void os_resume (U32 sleep_time);
extern void tsk_lock (void) __swi (5);
extern void tsk_unlock (void);
/* Fixed Memory Block Management Functions */
extern int _init_box (void *box_mem, U32 box_size, U32 blk_size);
extern void *_alloc_box (void *box_mem) __swi (1);
extern void *_calloc_box (void *box_mem);
extern int _free_box (void *box_mem, void *box) __swi (2);
#else
/*----------------------------------------------------------------------------
* Functions Cortex-M
*---------------------------------------------------------------------------*/
#define __SVC_0 __svc_indirect(0)
/* Task Management */
extern void os_set_env (void);
extern void rt_sys_init (void (*task)(void), U8 priority, void *stk);
extern void rt_tsk_pass (void);
extern OS_TID rt_tsk_self (void);
extern OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio);
extern OS_TID rt_tsk_create (void (*task)(void), U8 priority, void *stk, void
*argv);
extern OS_RESULT rt_tsk_delete (OS_TID task_id);
#define os_sys_init(tsk) os_set_env(); \

_os_sys_init((U32)rt_sys_init,tsk,0,NULL)
#define os_sys_init_user(tsk,prio,stk,size) \
os_set_env(); \
_os_sys_init((U32)rt_sys_init,tsk,prio|
(size<<8),stk)
#define os_sys_init_prio(tsk,prio) os_set_env(); \
_os_sys_init((U32)rt_sys_init,tsk,prio,NULL)
#define os_tsk_create(tsk,prio)
_os_tsk_create((U32)rt_tsk_create,tsk,prio,NULL,NULL)
#define os_tsk_create_user(tsk,prio,stk,size) \
_os_tsk_create((U32)rt_tsk_create,tsk,prio|
(size<<8),stk,NULL)
#define os_tsk_create_ex(tsk,prio,argv)
_os_tsk_create_ex((U32)rt_tsk_create,tsk,prio,NULL,argv)
#define os_tsk_create_user_ex(tsk,prio,stk,size,argv) \
_os_tsk_create_ex((U32)rt_tsk_create,tsk,prio|(size<<8),stk,argv)
#define os_tsk_self() _os_tsk_self((U32)rt_tsk_self)
#define os_tsk_pass() _os_tsk_pass((U32)rt_tsk_pass)
#define os_tsk_prio(task_id,new_prio)
_os_tsk_prio((U32)rt_tsk_prio,task_id,new_prio)
#define os_tsk_prio_self(prio) _os_tsk_prio((U32)rt_tsk_prio,0,prio)
#define os_tsk_delete(task_id) _os_tsk_delete((U32)rt_tsk_delete,task_id)
#define os_tsk_delete_self() { _os_tsk_delete((U32)rt_tsk_delete, 0);
for(;;); }
#define isr_tsk_get() rt_tsk_self()
extern void _os_sys_init(U32 p, void (*task)(void), U32 prio_stksz,

void *stk) __SVC_0;
extern OS_TID _os_tsk_create (U32 p, void (*task)(void), U32 prio_stksz,
void *stk, void *argv) __SVC_0;
extern OS_TID _os_tsk_create_ex (U32 p, void (*task)(void *), U32 prio_stksz,
void *stk, void *argv) __SVC_0;
extern OS_TID _os_tsk_self (U32 p) __SVC_0;
extern void _os_tsk_pass (U32 p) __SVC_0;
extern OS_RESULT _os_tsk_prio (U32 p, OS_TID task_id, U8 new_prio) __SVC_0;
extern OS_RESULT _os_tsk_delete (U32 p, OS_TID task_id) __SVC_0;
/* Event flag Management */

extern OS_RESULT rt_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait);
extern void rt_evt_set (U16 event_flags, OS_TID task_id);
extern void rt_evt_clr (U16 clear_flags, OS_TID task_id);
extern U16 rt_evt_get (void);
#define os_evt_wait_or(wflags,tmo)
_os_evt_wait((U32)rt_evt_wait,wflags,tmo,__FALSE)
#define os_evt_wait_and(wflags,tmo)
_os_evt_wait((U32)rt_evt_wait,wflags,tmo,__TRUE)
#define os_evt_set(evt_flags,task_id)
_os_evt_set((U32)rt_evt_set,evt_flags,task_id)
#define os_evt_clr(clr_flags,task_id)
_os_evt_clr((U32)rt_evt_clr,clr_flags,task_id)
#define os_evt_get() _os_evt_get((U32)rt_evt_get)
extern OS_RESULT _os_evt_wait(U32 p, U16 wait_flags, U16 timeout,

BOOL and_wait) __SVC_0;
extern void _os_evt_set (U32 p, U16 event_flags, OS_TID task_id) __SVC_0;
extern void _os_evt_clr (U32 p, U16 clear_flags, OS_TID task_id) __SVC_0;
extern U16 _os_evt_get (U32 p) __SVC_0;
extern void isr_evt_set (U16 event_flags, OS_TID task_id);
/* Semaphore Management */
extern void rt_sem_init (OS_ID semaphore, U16 token_count);
extern OS_RESULT rt_sem_send (OS_ID semaphore);
extern OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout);
#define os_sem_init(sem,t_count) _os_sem_init((U32)rt_sem_init,sem,t_count)

#define os_sem_send(sem) _os_sem_send((U32)rt_sem_send,sem)
#define os_sem_wait(sem,tmo) _os_sem_wait((U32)rt_sem_wait,sem,tmo)
extern void _os_sem_init (U32 p, OS_ID semaphore,

U16 token_count) __SVC_0;
extern OS_RESULT _os_sem_send (U32 p, OS_ID semaphore) __SVC_0;
extern OS_RESULT _os_sem_wait (U32 p, OS_ID semaphore, U16 timeout) __SVC_0;
extern void isr_sem_send (OS_ID semaphore);
/* Mailbox Management */
extern void rt_mbx_init (OS_ID mailbox, U16 mbx_size);
extern OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout);
extern OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout);
extern OS_RESULT rt_mbx_check (OS_ID mailbox);
#define os_mbx_init(mbx,mbx_size) _os_mbx_init((U32)rt_mbx_init,mbx,mbx_size)

#define os_mbx_send(mbx,p_msg,tmo) _os_mbx_send((U32)rt_mbx_send,mbx,p_msg,tmo)
#define os_mbx_wait(mbx,message,tmo)
_os_mbx_wait((U32)rt_mbx_wait,mbx,message,tmo)
#define os_mbx_check(mbx) _os_mbx_check((U32)rt_mbx_check,mbx)
#define isr_mbx_check(mbx) rt_mbx_check(mbx)
extern void _os_mbx_init (U32 p, OS_ID mailbox, U16 mbx_size) __SVC_0;

extern OS_RESULT _os_mbx_send (U32 p, OS_ID mailbox, void *message_ptr,
U16 timeout) __SVC_0;
extern OS_RESULT _os_mbx_wait (U32 p, OS_ID mailbox, void **message,
U16 timeout) __SVC_0;
extern OS_RESULT _os_mbx_check (U32 p, OS_ID mailbox) __SVC_0;
extern void isr_mbx_send (OS_ID mailbox, void *message_ptr);
extern OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message);
/* Mutex Management */
extern void rt_mut_init (OS_ID mutex);
extern OS_RESULT rt_mut_release (OS_ID mutex);
extern OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout);
#define os_mut_init(mutex) _os_mut_init((U32)rt_mut_init,mutex)

#define os_mut_release(mutex) _os_mut_release((U32)rt_mut_release,mutex)
#define os_mut_wait(mutex,timeout) _os_mut_wait((U32)rt_mut_wait,mutex,timeout)
extern void _os_mut_init (U32 p, OS_ID mutex) __SVC_0;

extern OS_RESULT _os_mut_release (U32 p, OS_ID mutex) __SVC_0;
extern OS_RESULT _os_mut_wait (U32 p, OS_ID mutex, U16 timeout) __SVC_0;
/* Time Management */
extern U32 rt_time_get (void);
extern void rt_dly_wait (U16 delay_time);
extern void rt_itv_set (U16 interval_time);
extern void rt_itv_wait (void);
#define os_time_get() _os_time_get((U32)rt_time_get)

#define os_dly_wait(delay_time) _os_dly_wait((U32)rt_dly_wait,delay_time)
#define os_itv_set(interval_time) _os_itv_set((U32)rt_itv_set,interval_time)
#define os_itv_wait() _os_itv_wait((U32)rt_itv_wait)
extern U32 _os_time_get (U32 p) __SVC_0;

extern void _os_dly_wait (U32 p, U16 delay_time) __SVC_0;
extern void _os_itv_set (U32 p, U16 interval_time) __SVC_0;
extern void _os_itv_wait (U32 p) __SVC_0;
/* User Timer Management */

extern OS_ID rt_tmr_create (U16 tcnt, U16 info);
extern OS_ID rt_tmr_kill (OS_ID timer);
#define os_tmr_create(tcnt,info) _os_tmr_create((U32)rt_tmr_create,tcnt,info)

#define os_tmr_kill(timer) _os_tmr_kill((U32)rt_tmr_kill,timer)
extern OS_ID _os_tmr_create (U32 p, U16 tcnt, U16 info) __SVC_0;

extern OS_ID _os_tmr_kill (U32 p, OS_ID timer) __SVC_0;
/* System Functions */
extern U32 rt_suspend (void);
extern void rt_resume (U32 sleep_time);
extern void rt_tsk_lock (void);
extern void rt_tsk_unlock (void);
#define os_suspend() _os_suspend((U32)rt_suspend)

#define os_resume(sleep_time) _os_resume((U32)rt_resume,sleep_time)
#define tsk_lock() _os_tsk_lock((U32)rt_tsk_lock)
#define tsk_unlock() _os_tsk_unlock((U32)rt_tsk_unlock)
extern U32 _os_suspend (U32 p) __SVC_0;

extern void _os_resume (U32 p, U32 sleep_time) __SVC_0;
extern void _os_tsk_lock (U32 p) __SVC_0;
extern void _os_tsk_unlock (U32 p) __SVC_0;
/* Fixed Memory Block Management Functions */
extern int _init_box (void *box_mem, U32 box_size, U32 blk_size);
extern void *_alloc_box (void *box_mem);
extern void *_calloc_box (void *box_mem);
extern int _free_box (void *box_mem, void *box);
#endif
#define BOX_ALIGN_8 0x80000000

#define _declare_box(pool,size,cnt) U32 pool[(((size)+3)/4)*(cnt) + 3]
#define _declare_box8(pool,size,cnt) U64 pool[(((size)+7)/8)*(cnt) + 2]
#define _init_box8(pool,size,bsize) _init_box (pool,size,bsize | BOX_ALIGN_8)
/* For compatibility with older configurations.*/

#define os_stk_overflow os_error
/*----------------------------------------------------------------------------
* Flash File System API
*---------------------------------------------------------------------------*/
/* File System Type */

typedef enum _FS_TYPE {
FS_TYPE_NONE = 0, /* No file system (volume unformatted)*/
FS_TYPE_UNKNOWN, /* File system type is unknown */
FS_TYPE_FAT12, /* File system type is FAT12 */
FS_TYPE_EFS /* File system type is EFS */
} FS_TYPE;
typedef struct { /* RL Time format (FFS, TCPnet) */

U8 hr; /* Hours [0..23] */
U8 min; /* Minutes [0..59] */
U8 sec; /* Seconds [0..59] */
U8 day; /* Day [1..31] */
U8 mon; /* Month [1..12] */
U16 year; /* Year [1980..2107] */
} RL_TIME;
typedef struct { /* Search info record */

S8 name[256]; /* Name */
U32 size; /* File size in bytes */
U16 fileID; /* System Identification */
U8 attrib; /* Attributes */
RL_TIME time; /* Create/Modify Time */
} FINFO;
/* Drive information */
typedef struct {
FS_TYPE fs_type; /* Drives file system type */
U64 capacity; /* Drives capacity in bytes */
} Drive_INFO;
extern int finit (const char *drive);

extern int funinit (const char *drive);
extern int fdelete (const char *filename);
extern int frename (const char *oldname, const char *newname);
extern int ffind (const char *pattern, FINFO *info);
extern U64 ffree (const char *drive);
extern int fformat (const char *drive);
extern int fanalyse (const char *drive);
extern int fcheck (const char *drive);
extern int fdefrag (const char *drive);
extern int fattrib (const char *par, const char *path);
extern int fvol (const char *drive, char *buf);
extern int finfo (const char *drive, Drive_INFO *info);
/* The following macros provide for common functions */

#define unlink(fn) fdelete(fn);
/*----------------------------------------------------------------------------
* TCPnet API
*---------------------------------------------------------------------------*/
/* UDP Options */
#define UDP_OPT_SEND_CS 0x01 /* Calculate Checksum for UDP send frames */
#define UDP_OPT_CHK_CS 0x02 /* Verify Checksum for received UDP frames */
/* TCP Socket Types */

#define TCP_TYPE_SERVER 0x01 /* Socket Type Server (open for listening) */
#define TCP_TYPE_CLIENT 0x02 /* Socket Type Client (initiate connect) */
#define TCP_TYPE_DELAY_ACK 0x04 /* Socket Type Delayed Acknowledge */
#define TCP_TYPE_FLOW_CTRL 0x08 /* Socket Type Flow Control */
#define TCP_TYPE_KEEP_ALIVE 0x10 /* Socket Type Keep Alive */
#define TCP_TYPE_CLIENT_SERVER (TCP_TYPE_SERVER | TCP_TYPE_CLIENT)
/* TCP Callback Events */

#define TCP_EVT_CONREQ 0 /* Connect request received event */
#define TCP_EVT_CONNECT 1 /* Connection established event */
#define TCP_EVT_CLOSE 2 /* Connection was properly closed */
#define TCP_EVT_ABORT 3 /* Connection is for some reason aborted */
#define TCP_EVT_ACK 4 /* Previously send data acknowledged */
#define TCP_EVT_DATA 5 /* Data received event */
/* TCP States */
#define TCP_STATE_FREE 0 /* Entry is free and unused */
#define TCP_STATE_CLOSED 1 /* Entry allocated, socket still closed */
#define TCP_STATE_LISTEN 2 /* Socket waiting for incoming connection */
#define TCP_STATE_SYN_REC 3 /* SYN frame received */
#define TCP_STATE_SYN_SENT 4 /* SYN packet sent to establish a connect. */
#define TCP_STATE_FINW1 5 /* Tcp_close started FIN packet was sent */
#define TCP_STATE_FINW2 6 /* Our FIN ack-ed, waiting for remote FIN */
#define TCP_STATE_CLOSING 7 /* Received FIN independently of our FIN */
#define TCP_STATE_LAST_ACK 8 /* Waiting for last ACK for our FIN */
#define TCP_STATE_TWAIT 9 /* Timed waiting for 2MSL */
#define TCP_STATE_CONNECT 10 /* TCP Connection established */
/* BSD Socket Address Family */

#define AF_UNSPEC 0 /* Unspecified */
#define AF_INET 1 /* Internet Address Family (UDP, TCP) */
#define AF_NETBIOS 2 /* NetBios-style addresses */
/* BSD Protocol families, same as address families */

#define PF_UNSPEC AF_UNSPEC
#define PF_INET AF_INET
#define PF_NETBIOS AF_NETBIOS
/* BSD Socket Type */
#define SOCK_STREAM 1 /* Stream Socket (Connection oriented) */
#define SOCK_DGRAM 2 /* Datagram Socket (Connectionless) */
/* BSD Socket Protocol */

#define IPPROTO_TCP 1 /* TCP Protocol */
#define IPPROTO_UDP 2 /* UDP Protocol */
/* BSD Internet Addresses */

#define INADDR_ANY 0x00000000 /* All IP addresses accepted */
#define INADDR_NONE 0xffffffff /* No IP address accepted */
/* BSD Socket Return values */

#define SCK_SUCCESS 0 /* Success */
#define SCK_ERROR (-1) /* General Error */
#define SCK_EINVALID (-2) /* Invalid socket descriptor */
#define SCK_EINVALIDPARA (-3) /* Invalid parameter */
#define SCK_EWOULDBLOCK (-4) /* It would have blocked. */
#define SCK_EMEMNOTAVAIL (-5) /* Not enough memory in memory pool */
#define SCK_ECLOSED (-6) /* Connection is closed or aborted */
#define SCK_ELOCKED (-7) /* Socket is locked in RTX environment */
#define SCK_ETIMEOUT (-8) /* Socket, Host Resolver timeout */
#define SCK_EINPROGRESS (-9) /* Host Name resolving in progress */
#define SCK_ENONAME (-10) /* Host Name not existing */
/* BSD Socket flags parameter */

#define MSG_DONTWAIT 0x01 /* Enables non-blocking operation */
#define MSG_PEEK 0x02 /* Peeks at the incoming data */
/* BSD Socket ioctl commands */

#define FIONBIO 1 /* Set mode (blocking/non-blocking) */
#define FIO_DELAY_ACK 2 /* Set DELAY_ACK mode for stream socket */
#define FIO_KEEP_ALIVE 3 /* Set KEEP_ALIVE mode for stream socket */
#define FIO_FLOW_CTRL 4 /* Set FLOW_CTRL mode for stream socket */
/* ICMP (ping) Callback Events */

#define ICMP_EVT_SUCCESS 0 /* Pinged Host responded */
#define ICMP_EVT_TIMEOUT 1 /* Timeout, no ping response received */
/* DNS Client Callback Events */

#define DNS_EVT_SUCCESS 0 /* Host name successfully resolved */
#define DNS_EVT_NONAME 1 /* DNS Error, no such name */
#define DNS_EVT_TIMEOUT 2 /* Timeout resolving host */
#define DNS_EVT_ERROR 3 /* Erroneous response packet */
/* DNS 'get_host_by_name()' result codes */

#define DNS_RES_OK 0 /* Resolver successfully started */
#define DNS_ERROR_BUSY 1 /* Resolver busy, can't process request */
#define DNS_ERROR_LABEL 2 /* Label in Hostname not valid */
#define DNS_ERROR_NAME 3 /* Entire Hostname not valid */
#define DNS_ERROR_NOSRV 4 /* Prim. DNS server not specified (0.0.0.0)*/
#define DNS_ERROR_PARAM 5 /* Invalid parameter */
/* SMTP Client Callback Events */

#define SMTP_EVT_SUCCESS 0 /* Email successfully sent */
#define SMTP_EVT_TIMEOUT 1 /* Timeout sending email */
#define SMTP_EVT_ERROR 2 /* Error when sending email */
/* FTP Client Commands */

#define FTPC_CMD_PUT 0 /* Puts a file on FTP server */
#define FTPC_CMD_GET 1 /* Retrieves a file from FTP server */
#define FTPC_CMD_APPEND 2 /* Append file on FTP server (with create) */
#define FTPC_CMD_DELETE 3 /* Deletes a file on FTP server */
#define FTPC_CMD_LIST 4 /* Lists files stored on FTP server */
#define FTPC_CMD_RENAME 5 /* Renames a file on FTP server */
#define FTPC_CMD_MKDIR 6 /* Makes a directory on FTP server */
#define FTPC_CMD_RMDIR 7 /* Removes an empty directory on FTP server*/
#define FTPC_CMD_NLIST 8 /* Lists file names only (short format) */
/* FTP Client Callback Events */

#define FTPC_EVT_SUCCESS 0 /* File operation successful */
#define FTPC_EVT_TIMEOUT 1 /* Timeout on file operation */
#define FTPC_EVT_LOGINFAIL 2 /* Login error, username/passw invalid */
#define FTPC_EVT_NOACCESS 3 /* File access not allowed */
#define FTPC_EVT_NOTFOUND 4 /* File not found */
#define FTPC_EVT_NOPATH 5 /* Working directory path not found */
#define FTPC_EVT_ERRLOCAL 6 /* Local file open error */
#define FTPC_EVT_ERROR 7 /* Generic FTP client error */
/* TFTP Client Callback Events */

#define TFTPC_EVT_SUCCESS 0 /* File operation successful */
#define TFTPC_EVT_TIMEOUT 1 /* Timeout on file operation */
#define TFTPC_EVT_NOACCESS 2 /* File access not allowed */
#define TFTPC_EVT_NOTFOUND 3 /* File not found */
#define TFTPC_EVT_DISKFULL 4 /* Disk full (local or remote) */
#define TFTPC_EVT_ERROR 5 /* Generic TFTP client error */
/* FTP Server Notification events */

#define FTP_EVT_LOGIN 0 /* User logged in, session is busy */
#define FTP_EVT_LOGOUT 1 /* User logged out, session is idle */
#define FTP_EVT_LOGFAIL 2 /* User login failed (invalid credentials) */
#define FTP_EVT_DOWNLOAD 3 /* File download ended */
#define FTP_EVT_UPLOAD 4 /* File upload ended */
#define FTP_EVT_DELETE 5 /* File deleted */
#define FTP_EVT_RENAME 6 /* File or directory renamed */
#define FTP_EVT_MKDIR 7 /* Directory created */
#define FTP_EVT_RMDIR 8 /* Directory removed */
#define FTP_EVT_ERRLOCAL 9 /* Local file operation error */
#define FTP_EVT_DENIED 10 /* Requested file operatined long *)0xE000EDA0))
#define NVIC_MPU_BASE1_R (*((volatile unsigned long *)0xE000EDA4))
#define NVIC_MPU_ATTR1_R (*((volatile unsigned long *)0xE000EDA8))
#define NVIC_MPU_BASE2_R (*((volatile unsigned long *)0xE000EDAC))
#define NVIC_MPU_ATTR2_R (*((volatile unsigned long *)0xE000EDB0))
#define NVIC_MPU_BASE3_R (*((volatile unsigned long *)0xE000EDB4))
#define NVIC_MPU_ATTR3_R (*((volatile unsigned long *)0xE000EDB8))
#define NVIC_DBG_CTRL_R (*((volatile unsigned long *)0xE000EDF0))
#define NVIC_DBG_XFER_R (*((volatile unsigned long *)0xE000EDF4))
#define NVIC_DBG_DATA_R (*((volatile unsigned long *)0xE000EDF8))
#define NVIC_DBG_INT_R (*((volatile unsigned long *)0xE000EDFC))
#define NVIC_SW_TRIG_R (*((volatile unsigned long *)0xE000EF00))
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_LOAD register.
//
//*****************************************************************************
#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
#define WDT_LOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_VALUE register.
//
//*****************************************************************************
#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
#define WDT_VALUE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_CTL register.
//
//*****************************************************************************
#define WDT_CTL_WRC 0x80000000 // Write Complete
#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_ICR register.
//
//*****************************************************************************
#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
#define WDT_ICR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_RIS register.
//
//*****************************************************************************
#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_MIS register.
//
//*****************************************************************************
#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_TEST register.
//
//*****************************************************************************
#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_LOCK register.
//
//*****************************************************************************
#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
#define WDT_LOCK_LOCKED 0x00000001 // Locked
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_IM register.
//
//*****************************************************************************
#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
#define GPIO_IM_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_RIS register.
//
//*****************************************************************************
#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
#define GPIO_RIS_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_MIS register.
//
//*****************************************************************************
#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
#define GPIO_MIS_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_ICR register.
//
//*****************************************************************************
#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
#define GPIO_ICR_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_LOCK register.
//
//*****************************************************************************
#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
// and may be modified
#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
// and may not be modified
#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port A.
//
//*****************************************************************************
#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 mask
#define GPIO_PCTL_PA7_I2C1SDA 0x10000000 // I2C1SDA on PA7
#define GPIO_PCTL_PA7_CCP4 0x20000000 // CCP4 on PA7
#define GPIO_PCTL_PA7_PWM1 0x40000000 // PWM1 on PA7
#define GPIO_PCTL_PA7_CAN0TX 0x60000000 // CAN0TX on PA7
#define GPIO_PCTL_PA7_USB0PFLT 0x80000000 // USB0PFLT on PA7
#define GPIO_PCTL_PA7_U1DCD 0x90000000 // U1DCD on PA7
#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 mask
#define GPIO_PCTL_PA6_I2C1SCL 0x01000000 // I2C1SCL on PA6
#define GPIO_PCTL_PA6_CAN0RX 0x06000000 // CAN0RX on PA6
#define GPIO_PCTL_PA6_USB0EPEN 0x08000000 // USB0EPEN on PA6
#define GPIO_PCTL_PA6_U1CTS 0x09000000 // U1CTS on PA6
#define GPIO_PCTL_PA5_SSI0TX 0x00100000 // SSI0TX on PA5
#define GPIO_PCTL_PA5_CAN0TX 0x00500000 // CAN0TX on PA5
#define GPIO_PCTL_PA5_I2S0TXWS 0x00900000 // I2S0TXWS on PA5
#define GPIO_PCTL_PA4_SSI0RX 0x00010000 // SSI0RX on PA4
#define GPIO_PCTL_PA4_CAN0RX 0x00050000 // CAN0RX on PA4
#define GPIO_PCTL_PA4_I2S0TXSCK 0x00090000 // I2S0TXSCK on PA4
#define GPIO_PCTL_PA3_SSI0FSS 0x00001000 // SSI0FSS on PA3
#define GPIO_PCTL_PA3_I2S0RXMCLK \
0x00009000 // I2S0RXMCLK on PA3
#define GPIO_PCTL_PA2_SSI0CLK 0x00000100 // SSI0CLK on PA2
#define GPIO_PCTL_PA2_I2S0RXSD 0x00000900 // I2S0RXSD on PA2
#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1
#define GPIO_PCTL_PA1_I2C1SDA 0x00000080 // I2C1SDA on PA1
#define GPIO_PCTL_PA1_U1TX 0x00000090 // U1TX on PA1
#define GPIO_PCTL_PA0_M 0x0000000F // PA0 mask
#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0
#define GPIO_PCTL_PA0_I2C1SCL 0x00000008 // I2C1SCL on PA0
#define GPIO_PCTL_PA0_U1RX 0x00000009 // U1RX on PA0
//*****************************************************************************
//
// port B.
//
//*****************************************************************************
#define GPIO_PCTL_PB7_M 0xF0000000 // PB7 mask
#define GPIO_PCTL_PB7_NMI 0x40000000 // NMI on PB7
#define GPIO_PCTL_PB6_M 0x0F000000 // PB6 mask
#define GPIO_PCTL_PB6_CCP1 0x01000000 // CCP1 on PB6
#define GPIO_PCTL_PB6_C0O 0x03000000 // C0O on PB6
#define GPIO_PCTL_PB6_FAULT1 0x04000000 // FAULT1 on PB6
#define GPIO_PCTL_PB6_IDX0 0x05000000 // IDX0 on PB6
#define GPIO_PCTL_PB6_I2S0TXSCK 0x09000000 // I2S0TXSCK on PB6
#define GPIO_PCTL_PB5_C0O 0x00100000 // C0O on PB5
#define GPIO_PCTL_PB5_CAN0TX 0x00500000 // CAN0TX on PB5
#define GPIO_PCTL_PB5_U1TX 0x00700000 // U1TX on PB5
#define GPIO_PCTL_PB4_U2RX 0x00040000 // U2RX on PB4
#define GPIO_PCTL_PB4_CAN0RX 0x00050000 // CAN0RX on PB4
#define GPIO_PCTL_PB3_I2C0SDA 0x00001000 // I2C0SDA on PB3
#define GPIO_PCTL_PB3_USB0PFLT 0x00008000 // USB0PFLT on PB3
#define GPIO_PCTL_PB2_I2C0SCL 0x00000100 // I2C0SCL on PB2
#define GPIO_PCTL_PB2_USB0EPEN 0x00000800 // USB0EPEN on PB2
#define GPIO_PCTL_PB1_PWM3 0x00000020 // PWM3 on PB1
#define GPIO_PCTL_PB1_U1TX 0x00000050 // U1TX on PB1
#define GPIO_PCTL_PB0_M 0x0000000F // PB0 mask
#define GPIO_PCTL_PB0_PWM2 0x00000002 // PWM2 on PB0
//*****************************************************************************
//
// port C.
//
//*****************************************************************************
#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 mask
#define GPIO_PCTL_PC7_CCP4 0x10000000 // CCP4 on PC7
#define GPIO_PCTL_PC7_PHB0 0x20000000 // PHB0 on PC7
#define GPIO_PCTL_PC7_U1TX 0x50000000 // U1TX on PC7
#define GPIO_PCTL_PC7_USB0PFLT 0x60000000 // USB0PFLT on PC7
#define GPIO_PCTL_PC7_C1O 0x70000000 // C1O on PC7
#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 mask
#define GPIO_PCTL_PC6_PHB0 0x02000000 // PHB0 on PC6
#define GPIO_PCTL_PC6_U1RX 0x05000000 // U1RX on PC6
#define GPIO_PCTL_PC6_USB0PFLT 0x07000000 // USB0PFLT on PC6
#define GPIO_PCTL_PC5_FAULT2 0x00400000 // FAULT2 on PC5
#define GPIO_PCTL_PC5_USB0EPEN 0x00600000 // USB0EPEN on PC5
#define GPIO_PCTL_PC4_PHA0 0x00020000 // PHA0 on PC4
#define GPIO_PCTL_PC3_TDO 0x00003000 // TDO on PC3
#define GPIO_PCTL_PC2_TDI 0x00000300 // TDI on PC2
#define GPIO_PCTL_PC1_TMS 0x00000030 // TMS on PC1
#define GPIO_PCTL_PC0_M 0x0000000F // PC0 mask
#define GPIO_PCTL_PC0_TCK 0x00000003 // TCK on PC0
//*****************************************************************************
//
// port D.
//
//*****************************************************************************
#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 mask
#define GPIO_PCTL_PD7_IDX0 0x10000000 // IDX0 on PD7
#define GPIO_PCTL_PD7_C0O 0x20000000 // C0O on PD7
#define GPIO_PCTL_PD7_CCP1 0x30000000 // CCP1 on PD7
#define GPIO_PCTL_PD7_I2S0TXWS 0x80000000 // I2S0TXWS on PD7
#define GPIO_PCTL_PD7_U1DTR 0x90000000 // U1DTR on PD7
#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 mask
#define GPIO_PCTL_PD6_FAULT0 0x01000000 // FAULT0 on PD6
#define GPIO_PCTL_PD6_I2S0TXSCK 0x08000000 // I2S0TXSCK on PD6
#define GPIO_PCTL_PD6_U2TX 0x09000000 // U2TX on PD6
#define GPIO_PCTL_PD5_I2S0RXMCLK \
0x00800000 // I2S0RXMCLK on PD5
#define GPIO_PCTL_PD5_U2RX 0x00900000 // U2RX on PD5
#define GPIO_PCTL_PD4_I2S0RXSD 0x00080000 // I2S0RXSD on PD4
#define GPIO_PCTL_PD4_U1RI 0x00090000 // U1RI on PD4
#define GPIO_PCTL_PD3_PWM3 0x00003000 // PWM3 on PD3
#define GPIO_PCTL_PD1_CAN0TX 0x00000020 // CAN0TX on PD1
#define GPIO_PCTL_PD1_PHA0 0x00000030 // PHA0 on PD1
#define GPIO_PCTL_PD1_I2S0RXWS 0x00000080 // I2S0RXWS on PD1
#define GPIO_PCTL_PD1_U1DCD 0x00000090 // U1DCD on PD1
#define GPIO_PCTL_PD1_CCP2 0x000000A0 // CCP2 on PD1
#define GPIO_PCTL_PD1_PHB1 0x000000B0 // PHB1 on PD1
#define GPIO_PCTL_PD0_M 0x0000000F // PD0 mask
#define GPIO_PCTL_PD0_CAN0RX 0x00000002 // CAN0RX on PD0
#define GPIO_PCTL_PD0_IDX0 0x00000003 // IDX0 on PD0
#define GPIO_PCTL_PD0_I2S0RXSCK 0x00000008 // I2S0RXSCK on PD0
#define GPIO_PCTL_PD0_U1CTS 0x00000009 // U1CTS on PD0
//*****************************************************************************
//
// port E.
//
//*****************************************************************************
#define GPIO_PCTL_PE7_M 0xF0000000 // PE7 mask
#define GPIO_PCTL_PE7_PWM5 0x10000000 // PWM5 on PE7
#define GPIO_PCTL_PE7_U1DCD 0x90000000 // U1DCD on PE7
#define GPIO_PCTL_PE6_M 0x0F000000 // PE6 mask
#define GPIO_PCTL_PE6_C1O 0x02000000 // C1O on PE6
#define GPIO_PCTL_PE6_U1CTS 0x09000000 // U1CTS on PE6
#define GPIO_PCTL_PE5_CCP5 0x00100000 // CCP5 on PE5
#define GPIO_PCTL_PE5_I2S0TXSD 0x00900000 // I2S0TXSD on PE5
#define GPIO_PCTL_PE4_FAULT0 0x00040000 // FAULT0 on PE4
#define GPIO_PCTL_PE4_U2TX 0x00050000 // U2TX on PE4
#define GPIO_PCTL_PE4_I2S0TXWS 0x00090000 // I2S0TXWS on PE4
#define GPIO_PCTL_PE3_SSI1TX 0x00002000 // SSI1TX on PE3
#define GPIO_PCTL_PE3_PHA1 0x00003000 // PHA1 on PE3
#define GPIO_PCTL_PE3_PHB0 0x00004000 // PHB0 on PE3
#define GPIO_PCTL_PE2_SSI1RX 0x00000200 // SSI1RX on PE2
#define GPIO_PCTL_PE2_PHB1 0x00000300 // PHB1 on PE2
#define GPIO_PCTL_PE2_PHA0 0x00000400 // PHA0 on PE2
#define GPIO_PCTL_PE1_SSI1FSS 0x00000020 // SSI1FSS on PE1
#define GPIO_PCTL_PE1_FAULT0 0x00000030 // FAULT0 on PE1
#define GPIO_PCTL_PE0_M 0x0000000F // PE0 mask
#define GPIO_PCTL_PE0_SSI1CLK 0x00000002 // SSI1CLK on PE0
#define GPIO_PCTL_PE0_USB0PFLT 0x00000009 // USB0PFLT on PE0
//*****************************************************************************
//
// port F.
//
//*****************************************************************************
#define GPIO_PCTL_PF7_M 0xF0000000 // PF7 mask
#define GPIO_PCTL_PF7_CCP4 0x10000000 // CCP4 on PF7
#define GPIO_PCTL_PF7_PHB0 0x40000000 // PHB0 on PF7
#define GPIO_PCTL_PF7_FAULT1 0x90000000 // FAULT1 on PF7
#define GPIO_PCTL_PF6_M 0x0F000000 // PF6 mask
#define GPIO_PCTL_PF6_PHA0 0x04000000 // PHA0 on PF6
#define GPIO_PCTL_PF6_I2S0TXMCLK \
0x09000000 // I2S0TXMCLK on PF6
#define GPIO_PCTL_PF6_U1RTS 0x0A000000 // U1RTS on PF6
#define GPIO_PCTL_PF5_C1O 0x00200000 // C1O on PF5
#define GPIO_PCTL_PF5_SSI1TX 0x00900000 // SSI1TX on PF5
#define GPIO_PCTL_PF4_C0O 0x00020000 // C0O on PF4
#define GPIO_PCTL_PF4_FAULT0 0x00040000 // FAULT0 on PF4
#define GPIO_PCTL_PF4_SSI1RX 0x00090000 // SSI1RX on PF4
#define GPIO_PCTL_PF3_PWM5 0x00002000 // PWM5 on PF3
#define GPIO_PCTL_PF3_SSI1FSS 0x00009000 // SSI1FSS on PF3
#define GPIO_PCTL_PF2_SSI1CLK 0x00000900 // SSI1CLK on PF2
#define GPIO_PCTL_PF1_CAN1TX 0x00000010 // CAN1TX on PF1
#define GPIO_PCTL_PF1_IDX1 0x00000020 // IDX1 on PF1
#define GPIO_PCTL_PF1_I2S0TXMCLK \
0x00000080 // I2S0TXMCLK on PF1
#define GPIO_PCTL_PF1_U1RTS 0x00000090 // U1RTS on PF1
#define GPIO_PCTL_PF1_CCP3 0x000000A0 // CCP3 on PF1
#define GPIO_PCTL_PF0_M 0x0000000F // PF0 mask
#define GPIO_PCTL_PF0_CAN1RX 0x00000001 // CAN1RX on PF0
#define GPIO_PCTL_PF0_PHB0 0x00000002 // PHB0 on PF0
#define GPIO_PCTL_PF0_I2S0TXSD 0x00000008 // I2S0TXSD on PF0
#define GPIO_PCTL_PF0_U1DSR 0x00000009 // U1DSR on PF0
//*****************************************************************************
//
// port G.
//
//*****************************************************************************
#define GPIO_PCTL_PG7_M 0xF0000000 // PG7 mask
#define GPIO_PCTL_PG7_PHB1 0x10000000 // PHB1 on PG7
#define GPIO_PCTL_PG7_CCP5 0x80000000 // CCP5 on PG7
#define GPIO_PCTL_PG6_M 0x0F000000 // PG6 mask
#define GPIO_PCTL_PG6_PHA1 0x01000000 // PHA1 on PG6
#define GPIO_PCTL_PG6_FAULT1 0x08000000 // FAULT1 on PG6
#define GPIO_PCTL_PG6_I2S0RXWS 0x09000000 // I2S0RXWS on PG6
#define GPIO_PCTL_PG6_U1RI 0x0A000000 // U1RI on PG6
#define GPIO_PCTL_PG5_IDX0 0x00400000 // IDX0 on PG5
#define GPIO_PCTL_PG5_I2S0RXSCK 0x00900000 // I2S0RXSCK on PG5
#define GPIO_PCTL_PG5_U1DTR 0x00A00000 // U1DTR on PG5
#define GPIO_PCTL_PG4_U1RI 0x000A0000 // U1RI on PG4
#define GPIO_PCTL_PG3_PWM1 0x00001000 // PWM1 on PG3
#define GPIO_PCTL_PG3_I2S0RXMCLK \
0x00009000 // I2S0RXMCLK on PG3
#define GPIO_PCTL_PG2_IDX1 0x00000800 // IDX1 on PG2
#define GPIO_PCTL_PG2_I2S0RXSD 0x00000900 // I2S0RXSD on PG2
#define GPIO_PCTL_PG1_U2TX 0x00000010 // U2TX on PG1
#define GPIO_PCTL_PG1_I2C1SDA 0x00000030 // I2C1SDA on PG1
#define GPIO_PCTL_PG0_M 0x0000000F // PG0 mask
#define GPIO_PCTL_PG0_U2RX 0x00000001 // U2RX on PG0
#define GPIO_PCTL_PG0_I2C1SCL 0x00000003 // I2C1SCL on PG0
#define GPIO_PCTL_PG0_USB0EPEN 0x00000007 // USB0EPEN on PG0
//*****************************************************************************
//
// port H.
//
//*****************************************************************************
#define GPIO_PCTL_PH7_M 0xF0000000 // PH7 mask
#define GPIO_PCTL_PH7_PWM5 0xA0000000 // PWM5 on PH7
#define GPIO_PCTL_PH7_SSI1TX 0xB0000000 // SSI1TX on PH7
#define GPIO_PCTL_PH6_M 0x0F000000 // PH6 mask
#define GPIO_PCTL_PH6_PWM4 0x0A000000 // PWM4 on PH6
#define GPIO_PCTL_PH6_SSI1RX 0x0B000000 // SSI1RX on PH6
#define GPIO_PCTL_PH5_FAULT2 0x00A00000 // FAULT2 on PH5
#define GPIO_PCTL_PH5_SSI1FSS 0x00B00000 // SSI1FSS on PH5
#define GPIO_PCTL_PH4_USB0PFLT 0x00040000 // USB0PFLT on PH4
#define GPIO_PCTL_PH4_SSI1CLK 0x000B0000 // SSI1CLK on PH4
#define GPIO_PCTL_PH3_PHB0 0x00001000 // PHB0 on PH3
#define GPIO_PCTL_PH3_FAULT0 0x00002000 // FAULT0 on PH3
#define GPIO_PCTL_PH3_USB0EPEN 0x00004000 // USB0EPEN on PH3
#define GPIO_PCTL_PH2_IDX1 0x00000100 // IDX1 on PH2
#define GPIO_PCTL_PH2_C1O 0x00000200 // C1O on PH2
#define GPIO_PCTL_PH2_FAULT3 0x00000400 // FAULT3 on PH2
#define GPIO_PCTL_PH1_CCP7 0x00000010 // CCP7 on PH1
#define GPIO_PCTL_PH1_PWM3 0x00000020 // PWM3 on PH1
#define GPIO_PCTL_PH0_M 0x0000000F // PH0 mask
#define GPIO_PCTL_PH0_CCP6 0x00000001 // CCP6 on PH0
//*****************************************************************************
//
// port J.
//
//*****************************************************************************
#define GPIO_PCTL_PJ2_M 0x00000F00 // PJ2 mask
#define GPIO_PCTL_PJ2_CCP0 0x00000900 // CCP0 on PJ2
#define GPIO_PCTL_PJ2_FAULT0 0x00000A00 // FAULT0 on PJ2
#define GPIO_PCTL_PJ1_M 0x000000F0 // PJ1 mask
#define GPIO_PCTL_PJ1_USB0PFLT 0x00000090 // USB0PFLT on PJ1
#define GPIO_PCTL_PJ1_PWM1 0x000000A0 // PWM1 on PJ1
#define GPIO_PCTL_PJ1_I2C1SDA 0x000000B0 // I2C1SDA on PJ1
#define GPIO_PCTL_PJ0_M 0x0000000F // PJ0 mask
#define GPIO_PCTL_PJ0_PWM0 0x0000000A // PWM0 on PJ0
#define GPIO_PCTL_PJ0_I2C1SCL 0x0000000B // I2C1SCL on PJ0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CR0 register.
//
//*****************************************************************************
#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
// Serial Frame Format
#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
#define SSI_CR0_SCR_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CR1 register.
//
//*****************************************************************************
#define SSI_CR1_EOT 0x00000010 // End of Transmission
#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable
#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
// Enable
#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_DR register.
//
//*****************************************************************************
#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
#define SSI_DR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_SR register.
//
//*****************************************************************************
#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CPSR register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
#define SSI_CPSR_CPSDVSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_IM register.
//
//*****************************************************************************
#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
// Mask
#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
// Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_RIS register.
//
//*****************************************************************************
#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
// Status
#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
// Status
#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
// Interrupt Status
#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_MIS register.
//
//*****************************************************************************
#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
// Interrupt Status
#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
// Interrupt Status
#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
// Interrupt Status
#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_ICR register.
//
//*****************************************************************************
#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
// Clear
#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
// Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_DMACTL register.
//
//*****************************************************************************
#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_DR register.
//
//*****************************************************************************
#define UART_DR_OE 0x00000800 // UART Overrun Error
#define UART_DR_BE 0x00000400 // UART Break Error
#define UART_DR_PE 0x00000200 // UART Parity Error
#define UART_DR_FE 0x00000100 // UART Framing Error
#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
#define UART_DR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_RSR register.
//
//*****************************************************************************
#define UART_RSR_OE 0x00000008 // UART Overrun Error
#define UART_RSR_BE 0x00000004 // UART Break Error
#define UART_RSR_PE 0x00000002 // UART Parity Error
#define UART_RSR_FE 0x00000001 // UART Framing Error
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ECR register.
//
//*****************************************************************************
#define UART_ECR_DATA_M 0x000000FF // Error Clear
#define UART_ECR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_FR register.
//
//*****************************************************************************
#define UART_FR_RI 0x00000100 // Ring Indicator
#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
#define UART_FR_BUSY 0x00000008 // UART Busy
#define UART_FR_DCD 0x00000004 // Data Carrier Detect
#define UART_FR_DSR 0x00000002 // Data Set Ready
#define UART_FR_CTS 0x00000001 // Clear To Send
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ILPR register.
//
//*****************************************************************************
#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
#define UART_ILPR_ILPDVSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IBRD register.
//
//*****************************************************************************
#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
#define UART_IBRD_DIVINT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_FBRD register.
//
//*****************************************************************************
#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
#define UART_FBRD_DIVFRAC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LCRH register.
//
//*****************************************************************************
#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
#define UART_LCRH_BRK 0x00000001 // UART Send Break
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_CTL register.
//
//*****************************************************************************
#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
#define UART_CTL_RTS 0x00000800 // Request to Send
#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
#define UART_CTL_RXE 0x00000200 // UART Receive Enable
#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
#define UART_CTL_LIN 0x00000040 // LIN Mode Enable
#define UART_CTL_HSE 0x00000020 // High-Speed Enable
#define UART_CTL_EOT 0x00000010 // End of Transmission
#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
#define UART_CTL_UARTEN 0x00000001 // UART Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IFLS register.
//
//*****************************************************************************
#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
// Level Select
#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
// Level Select
#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IM register.
//
//*****************************************************************************
#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask
#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
// Mask
#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
// Mask
#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
// Mask
#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
// Mask
#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
// Interrupt Mask
#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
// Interrupt Mask
#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
// Interrupt Mask
#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
// Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_RIS register.
//
//*****************************************************************************
#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
// Status
#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
// Status
#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
// Interrupt Status
#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
// Status
#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
// Status
#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
// Status
#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
// Status
#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
// Interrupt Status
#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
// Status
#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
// Status
#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
// Interrupt Status
#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
// Raw Interrupt Status
#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
// Interrupt Status
#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_MIS register.
//
//*****************************************************************************
#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
// Status
#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
// Status
#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
// Interrupt Status
#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
// Interrupt Status
#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
// Interrupt Status
#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
// Interrupt Status
#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
// Interrupt Status
#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
// Interrupt Status
#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
// Status
#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
// Status
#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
// Interrupt Status
#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
// Masked Interrupt Status
#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
// Interrupt Status
#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ICR register.
//
//*****************************************************************************
#define UART_ICR_LME5IC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LME1IC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
// Clear
#define UART_ICR_LMSBIC 0x00002000 // LIN Mode Sync Break Interrupt
// Clear
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
// Interrupt Clear
#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
// Interrupt Clear
#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
// Interrupt Clear
#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
// Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_DMACTL register.
//
//*****************************************************************************
#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LCTL register.
//
//*****************************************************************************
#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length
#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits
// (default)
#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LSS register.
//
//*****************************************************************************
#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot
#define UART_LSS_TSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LTIM register.
//
//*****************************************************************************
#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
#define UART_LTIM_TIMER_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MSA register.
//
//*****************************************************************************
#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
#define I2C_MSA_RS 0x00000001 // Receive not send
#define I2C_MSA_SA_S 1
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR register.
//
//*****************************************************************************
#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
#define I2C_SOAR_OAR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SCSR register.
//
//*****************************************************************************
#define I2C_SCSR_FBR 0x00000004 // First Byte Received
#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
#define I2C_SCSR_DA 0x00000001 // Device Active
#define I2C_SCSR_RREQ 0x00000001 // Receive Request
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCS register.
//
//*****************************************************************************
#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
#define I2C_MCS_IDLE 0x00000020 // I2C Idle
#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
#define I2C_MCS_STOP 0x00000004 // Generate STOP
#define I2C_MCS_ERROR 0x00000002 // Error
#define I2C_MCS_START 0x00000002 // Generate START
#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
#define I2C_MCS_BUSY 0x00000001 // I2C Busy
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SDR register.
//
//*****************************************************************************
#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
#define I2C_SDR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MDR register.
//
//*****************************************************************************
#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
#define I2C_MDR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MTPR register.
//
//*****************************************************************************
#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period
#define I2C_MTPR_TPR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SIMR register.
//
//*****************************************************************************
#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SRIS register.
//
//*****************************************************************************
#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
// Status
#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
// Status
#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MIMR register.
//
//*****************************************************************************
#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MRIS register.
//
//*****************************************************************************
#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SMIS register.
//
//*****************************************************************************
#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
// Status
#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
// Status
#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SICR register.
//
//*****************************************************************************
#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MMIS register.
//
//*****************************************************************************
#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MICR register.
//
//*****************************************************************************
#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCR register.
//
//*****************************************************************************
#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_CTL register.
//
//*****************************************************************************
#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_SYNC register.
//
//*****************************************************************************
#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_ENABLE register.
//
//*****************************************************************************
#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_INVERT register.
//
//*****************************************************************************
#define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_FAULT register.
//
//*****************************************************************************
#define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_INTEN register.
//
//*****************************************************************************
#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3
#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_RIS register.
//
//*****************************************************************************
#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3
#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_ISC register.
//
//*****************************************************************************
#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted
#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_STATUS register.
//
//*****************************************************************************
#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
//
//*****************************************************************************
#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_ENUPD register.
//
//*****************************************************************************
#define PWM_ENUPD_ENUPD5_M 0x00000C00 // PWM5 Enable Update Mode
#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate
#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized
#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized
#define PWM_ENUPD_ENUPD4_M 0x00000300 // PWM4 Enable Update Mode
#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized
#define PWM_ENUPD_ENUPD3_M 0x000000C0 // PWM3 Enable Update Mode
#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized
#define PWM_ENUPD_ENUPD1_M 0x0000000C // PWM1 Enable Update Mode
#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_CTL register.
//
//*****************************************************************************
#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input
#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source
#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
// the PWMnDBFALL register
#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate
#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate
#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate
#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate
#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate
#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode
#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode
#define PWM_0_CTL_MODE 0x00000002 // Counter Mode
#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_INTEN register.
//
//*****************************************************************************
#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
// Down
#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
// Up
#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
// Down
#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
// Up
#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load
#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
// B Down
#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
// B Up
#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
// A Down
#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
// A Up
#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load
#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_RIS register.
//
//*****************************************************************************
#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
// Status
#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
// Status
#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_ISC register.
//
//*****************************************************************************
#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_LOAD register.
//
//*****************************************************************************
#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value
#define PWM_0_LOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_COUNT register.
//
//*****************************************************************************
#define PWM_0_COUNT_M 0x0000FFFF // Counter Value
#define PWM_0_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_CMPA register.
//
//*****************************************************************************
#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value
#define PWM_0_CMPA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_CMPB register.
//
//*****************************************************************************
#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value
#define PWM_0_CMPB_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_GENA register.
//
//*****************************************************************************
#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
#define PWM_0_GENA_ACTCMPBD_NONE \
#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal
#define PWM_0_GENA_ACTCMPBD_ZERO \
0x00000800 // Set the output signal to 0
#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
#define PWM_0_GENA_ACTCMPBU_NONE \
#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal
#define PWM_0_GENA_ACTCMPBU_ZERO \
#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
#define PWM_0_GENA_ACTCMPAD_NONE \
#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal
#define PWM_0_GENA_ACTCMPAD_ZERO \
#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
#define PWM_0_GENA_ACTCMPAU_NONE \
#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal
#define PWM_0_GENA_ACTCMPAU_ZERO \
#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load
#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal
#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing
#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert the output signal
#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_GENB register.
//
//*****************************************************************************
#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
#define PWM_0_GENB_ACTCMPBD_NONE \
#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal
#define PWM_0_GENB_ACTCMPBD_ZERO \
#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
#define PWM_0_GENB_ACTCMPBU_NONE \
#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal
#define PWM_0_GENB_ACTCMPBU_ZERO \
#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
#define PWM_0_GENB_ACTCMPAD_NONE \
#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal
#define PWM_0_GENB_ACTCMPAD_ZERO \
#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
#define PWM_0_GENB_ACTCMPAU_NONE \
#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal
#define PWM_0_GENB_ACTCMPAU_ZERO \
#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load
#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal
#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing
#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert the output signal
#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_DBCTL register.
//
//*****************************************************************************
#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_DBRISE register.
//
//*****************************************************************************
#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay
#define PWM_0_DBRISE_DELAY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_DBFALL register.
//
//*****************************************************************************
#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay
#define PWM_0_DBFALL_DELAY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_FLTSRC0
// register.
//
//*****************************************************************************
#define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0
//*****************************************************************************
//
// register.
//
//*****************************************************************************
#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_MINFLTPER
// register.
//
//*****************************************************************************
#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period
#define PWM_0_MINFLTPER_S 0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
// Down
// Up
// Down
// Up
// B Down
// B Up
// A Down
// A Up
//*****************************************************************************
//
//
//*****************************************************************************
// Status
// Status
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
#define PWM_1_LOAD_LOAD_S 0
//*****************************************************************************
//
//
//*****************************************************************************
#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value
#define PWM_1_COUNT_COUNT_S 0
//*****************************************************************************
//
//
//*****************************************************************************
#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
#define PWM_1_CMPA_COMPA_S 0
//*****************************************************************************
//
//
//*****************************************************************************
#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
#define PWM_1_CMPB_COMPB_S 0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
#define PWM_1_DBRISE_RISEDELAY_M \
0x00000FFF // Dead-Band Rise Delay
#define PWM_1_DBRISE_RISEDELAY_S \
0
//*****************************************************************************
//
//
//*****************************************************************************
#define PWM_1_DBFALL_FALLDELAY_M \
0x00000FFF // Dead-Band Fall Delay
#define PWM_1_DBFALL_FALLDELAY_S \
0
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
#define PWM_1_MINFLTPER_MFP_S 0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
// Down
// Up
// Down
// Up
// B Down
// B Up
// A Down
// A Up
//*****************************************************************************
//
//
//*****************************************************************************
// Status
// Status
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
#define PWM_2_LOAD_LOAD_S 0
//*****************************************************************************
//
//
//*****************************************************************************
#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value
#define PWM_2_COUNT_COUNT_S 0
//*****************************************************************************
//
//
//*****************************************************************************
#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
#define PWM_2_CMPA_COMPA_S 0
//*****************************************************************************
//
//
//*****************************************************************************
#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
#define PWM_2_CMPB_COMPB_S 0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
#define PWM_2_DBRISE_RISEDELAY_M \
0x00000FFF // Dead-Band Rise Delay
#define PWM_2_DBRISE_RISEDELAY_S \
0
//*****************************************************************************
//
//
//*****************************************************************************
#define PWM_2_DBFALL_FALLDELAY_M \
0x00000FFF // Dead-Band Fall Delay
#define PWM_2_DBFALL_FALLDELAY_S \
0
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
#define PWM_2_MINFLTPER_MFP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_FLTSEN register.
//
//*****************************************************************************
#define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0
// register.
//
//*****************************************************************************
#define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
//*****************************************************************************
//
// register.
//
//*****************************************************************************
#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_CTL register.
//
//*****************************************************************************
#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count
#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter
#define QEI_CTL_STALLEN 0x00001000 // Stall QEI
#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse
#define QEI_CTL_INVB 0x00000400 // Invert PhB
#define QEI_CTL_INVA 0x00000200 // Invert PhA
#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity
#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1
#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8
#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128
#define QEI_CTL_VELEN 0x00000020 // Capture Velocity
#define QEI_CTL_RESMODE 0x00000010 // Reset Mode
#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode
#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode
#define QEI_CTL_SWAP 0x00000002 // Swap Signals
#define QEI_CTL_ENABLE 0x00000001 // Enable QEI
#define QEI_CTL_FILTCNT_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_STAT register.
//
//*****************************************************************************
#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation
#define QEI_STAT_ERROR 0x00000001 // Error Detected
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_POS register.
//
//*****************************************************************************
#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator
// Value
#define QEI_POS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_MAXPOS register.
//
//*****************************************************************************
#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator
// Value
#define QEI_MAXPOS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_LOAD register.
//
//*****************************************************************************
#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value
#define QEI_LOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_TIME register.
//
//*****************************************************************************
#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value
#define QEI_TIME_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_COUNT register.
//
//*****************************************************************************
#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count
#define QEI_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_SPEED register.
//
//*****************************************************************************
#define QEI_SPEED_M 0xFFFFFFFF // Velocity
#define QEI_SPEED_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_INTEN register.
//
//*****************************************************************************
#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable
#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt
// Enable
#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable
#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt
// Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_RIS register.
//
//*****************************************************************************
#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected
#define QEI_RIS_DIR 0x00000004 // Direction Change Detected
#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired
#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_ISC register.
//
//*****************************************************************************
#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt
#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt
#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt
#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CFG register.
//
//*****************************************************************************
#define TIMER_CFG_M 0x00000007 // GPTM Configuration
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
// counter configuration
#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The
// function is controlled by bits
// 1:0 of GPTMTAMR and GPTMTBMR
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAMR register.
//
//*****************************************************************************
#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
// Enable
#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
// Select
#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBMR register.
//
//*****************************************************************************
#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
// Enable
#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
// Select
#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CTL register.
//
//*****************************************************************************
#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
// Enable
#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
// Enable
#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable
#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_IMR register.
//
//*****************************************************************************
#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt
// Mask
#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event
// Interrupt Mask
#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match
// Interrupt Mask
#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
// Mask
#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt
// Mask
#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event
// Interrupt Mask
#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match
// Interrupt Mask
#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
// Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_RIS register.
//
//*****************************************************************************
#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt
#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event
// Raw Interrupt
#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match
// Raw Interrupt
#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
// Interrupt
#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt
#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event
// Raw Interrupt
#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match
// Raw Interrupt
#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_MIS register.
//
//*****************************************************************************
#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked
// Interrupt
#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event
// Masked Interrupt
#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match
// Masked Interrupt
#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
// Interrupt
#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked
// Interrupt
#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event
// Masked Interrupt
#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match
// Masked Interrupt
#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_ICR register.
//
//*****************************************************************************
#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt
// Clear
#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event
// Interrupt Clear
#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match
// Interrupt Clear
#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
// Clear
#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt
// Clear
#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event
// Interrupt Clear
#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match
// Interrupt Clear
#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAILR register.
//
//*****************************************************************************
#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
// Register
#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load
// Register High
#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load
// Register Low
#define TIMER_TAILR_TAILRH_S 16
#define TIMER_TAILR_TAILRL_S 0
#define TIMER_TAILR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBILR register.
//
//*****************************************************************************
#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
// Register
#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load
// Register
#define TIMER_TBILR_TBILRL_S 0
#define TIMER_TBILR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAMATCHR
// register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High
#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low
#define TIMER_TAMATCHR_TAMRH_S 16
#define TIMER_TAMATCHR_TAMRL_S 0
#define TIMER_TAMATCHR_TAMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBMATCHR
// register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low
#define TIMER_TBMATCHR_TBMR_S 0
#define TIMER_TBMATCHR_TBMRL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPR register.
//
//*****************************************************************************
#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
#define TIMER_TAPR_TAPSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPR register.
//
//*****************************************************************************
#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
#define TIMER_TBPR_TBPSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPMR register.
//
//*****************************************************************************
#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
#define TIMER_TAPMR_TAPSMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPMR register.
//
//*****************************************************************************
#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
#define TIMER_TBPMR_TBPSMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAR register.
//
//*****************************************************************************
#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High
#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low
#define TIMER_TAR_TARH_S 16
#define TIMER_TAR_TARL_S 0
#define TIMER_TAR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBR register.
//
//*****************************************************************************
#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B
#define TIMER_TBR_TBRL_S 0
#define TIMER_TBR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAV register.
//
//*****************************************************************************
#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High
#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low
#define TIMER_TAV_TAVH_S 16
#define TIMER_TAV_TAVL_S 0
#define TIMER_TAV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBV register.
//
//*****************************************************************************
#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register
#define TIMER_TBV_TBVL_S 0
#define TIMER_TBV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_ACTSS register.
//
//*****************************************************************************
#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_RIS register.
//
//*****************************************************************************
#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt
// Status
#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_IM register.
//
//*****************************************************************************
#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on
// SS3
// SS2
// SS1
// SS0
#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_ISC register.
//
//*****************************************************************************
#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt
// Status on SS3
// Status on SS2
// Status on SS1
// Status on SS0
#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_OSTAT register.
//
//*****************************************************************************
#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_EMUX register.
//
//*****************************************************************************
#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select
#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default)
#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0
#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4)
#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0
#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample)
#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select
#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample)
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_USTAT register.
//
//*****************************************************************************
#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSPRI register.
//
//*****************************************************************************
#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority
#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SPC register.
//
//*****************************************************************************
#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference
#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0
#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5
#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0
#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5
#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0
#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5
#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0
#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_PSSI register.
//
//*****************************************************************************
#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize
#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait
#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SAC register.
//
//*****************************************************************************
#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control
#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCISC register.
//
//*****************************************************************************
#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt
// Status and Clear
// Status and Clear
// Status and Clear
// Status and Clear
// Status and Clear
// Status and Clear
// Status and Clear
// Status and Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_CTL register.
//
//*****************************************************************************
#define ADC_CTL_RES 0x00000010 // Sample Resolution
#define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select
#define ADC_CTL_VREF_INTERNAL 0x00000000 // The internal reference as the
// voltage reference
#define ADC_CTL_VREF_EXT_3V 0x00000001 // A 3.0 V external VREFA input is
// the voltage reference. The ADC
// conversion range is 0.0 V to the
// external reference value
#define ADC_CTL_VREF_EXT_1V 0x00000003 // A 1.0 V external VREFA input is
// the voltage reference. The ADC
// conversion range is 0.0 V to
// three times the external
// reference value
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
//
//*****************************************************************************
#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select
#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select
#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select
#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select
#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select
#define ADC_SSMUX0_MUX7_S 28
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
//
//*****************************************************************************
#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select
#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable
#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence
#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select
#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select
#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable
#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence
#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select
#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select
#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable
#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence
#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select
#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select
#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable
#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence
#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
//
//*****************************************************************************
#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data
#define ADC_SSFIFO0_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
//
//*****************************************************************************
#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full
#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty
#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer
#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer
#define ADC_SSFSTAT0_HPTR_S 4
#define ADC_SSFSTAT0_TPTR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSOP0 register.
//
//*****************************************************************************
#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator
// Operation
// Operation
// Operation
// Operation
// Operation
// Operation
// Operation
// Operation
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSDC0 register.
//
//*****************************************************************************
#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator
// Select
#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator
// Select
// Select
// Select
// Select
// Select
// Select
#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
// Select
#define ADC_SSDC0_S6DCSEL_S 24
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
// Operation
// Operation
// Operation
// Operation
//*****************************************************************************
//
//
//*****************************************************************************
// Select
// Select
// Select
// Select
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
// Operation
// Operation
// Operation
// Operation
//*****************************************************************************
//
//
//*****************************************************************************
// Select
// Select
// Select
// Select
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
// Operation
//*****************************************************************************
//
//
//*****************************************************************************
// Select
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCRIC register.
//
//*****************************************************************************
#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7
#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
//
//*****************************************************************************
#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable
#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition
#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band
#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band
#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band
#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode
#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once
#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always
#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once
#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable
#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition
#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band
#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band
#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band
#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode
#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once
#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always
#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
//
//*****************************************************************************
#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1
#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0
#define ADC_DCCMP0_COMP1_S 16
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACMIS register.
//
//*****************************************************************************
#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
// Status
#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACRIS register.
//
//*****************************************************************************
#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status
#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACINTEN register.
//
//*****************************************************************************
#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable
#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACREFCTL
// register.
//
//*****************************************************************************
#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable
#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range
#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref
#define COMP_ACREFCTL_VREF_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
//
//*****************************************************************************
#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
//
//*****************************************************************************
#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable
#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive
#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+
#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value
#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense
#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value
#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense
#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
//
//*****************************************************************************
#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
//
//*****************************************************************************
#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable
#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive
#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+
#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
// (VIREF)
#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value
#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense
#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value
#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense
#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_CTL register.
//
//*****************************************************************************
#define CAN_CTL_TEST 0x00000080 // Test Mode Enable
#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable
#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission
#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable
#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable
#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable
#define CAN_CTL_INIT 0x00000001 // Initialization
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_STS register.
//
//*****************************************************************************
#define CAN_STS_BOFF 0x00000080 // Bus-Off Status
#define CAN_STS_EWARN 0x00000040 // Warning Status
#define CAN_STS_EPASS 0x00000020 // Error Passive
#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully
#define CAN_STS_TXOK 0x00000008 // Transmitted a Message
// Successfully
#define CAN_STS_LEC_M 0x00000007 // Last Error Code
#define CAN_STS_LEC_NONE 0x00000000 // No Error
#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error
#define CAN_STS_LEC_FORM 0x00000002 // Format Error
#define CAN_STS_LEC_ACK 0x00000003 // ACK Error
#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error
#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error
#define CAN_STS_LEC_CRC 0x00000006 // CRC Error
#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_ERR register.
//
//*****************************************************************************
#define CAN_ERR_RP 0x00008000 // Received Error Passive
#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter
#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter
#define CAN_ERR_REC_S 8
#define CAN_ERR_TEC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_BIT register.
//
//*****************************************************************************
#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point
#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point
#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width
#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler
#define CAN_BIT_TSEG2_S 12
#define CAN_BIT_TSEG1_S 8
#define CAN_BIT_SJW_S 6
#define CAN_BIT_BRP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_INT register.
//
//*****************************************************************************
#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier
#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending
#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_TST register.
//
//*****************************************************************************
#define CAN_TST_RX 0x00000080 // Receive Observation
#define CAN_TST_TX_M 0x00000060 // Transmit Control
#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control
#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point
#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low
#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High
#define CAN_TST_LBACK 0x00000010 // Loopback Mode
#define CAN_TST_SILENT 0x00000008 // Silent Mode
#define CAN_TST_BASIC 0x00000004 // Basic Mode
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_BRPE register.
//
//*****************************************************************************
#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension
#define CAN_BRPE_BRPE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
//
//*****************************************************************************
#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag
#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number
#define CAN_IF1CRQ_MNUM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
//
//*****************************************************************************
#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read
#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits
#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits
#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits
#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data
#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request
#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
//
//*****************************************************************************
#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
#define CAN_IF1MSK1_IDMSK_S 0
//*****************************************************************************
//
//
//*****************************************************************************
#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier
#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction
#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
//
//*****************************************************************************
#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier
#define CAN_IF1ARB1_ID_S 0
//*****************************************************************************
//
//
//*****************************************************************************
#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid
#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier
#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction
#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
//
//*****************************************************************************
#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data
#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost
#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending
#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask
#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable
#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable
#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request
#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer
#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code
#define CAN_IF1MCTL_DLC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
//
//*****************************************************************************
#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data
#define CAN_IF1DA1_DATA_S 0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
//
//*****************************************************************************
#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data
#define CAN_IF1DB1_DATA_S 0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
//
//*****************************************************************************
#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag
#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number
#define CAN_IF2CRQ_MNUM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
//
//*****************************************************************************
#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read
#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits
#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits
#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits
#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data
#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request
#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
//*****************************************************************************
//
//
//*****************************************************************************
#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
//*****************************************************************************
//
//
//*****************************************************************************
#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier
#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction
#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask
//*****************************************************************************
//
//
//*****************************************************************************
#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier
//*****************************************************************************
//
//
//*****************************************************************************
#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid
#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier
#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction
#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
//
//*****************************************************************************
#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data
#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost
#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending
#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask
#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable
#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable
#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request
#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer
#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code
#define CAN_IF2MCTL_DLC_S 0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
//
//*****************************************************************************
#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits
#define CAN_TXRQ1_TXRQST_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
//
//*****************************************************************************
#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits
#define CAN_TXRQ2_TXRQST_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_NWDA1 register.
//
//*****************************************************************************
#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits
#define CAN_NWDA1_NEWDAT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_NWDA2 register.
//
//*****************************************************************************
#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits
#define CAN_NWDA2_NEWDAT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG1INT register.
//
//*****************************************************************************
#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
#define CAN_MSG1INT_INTPND_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG2INT register.
//
//*****************************************************************************
#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
#define CAN_MSG2INT_INTPND_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
//
//*****************************************************************************
#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
#define CAN_MSG1VAL_MSGVAL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
//
//*****************************************************************************
#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
#define CAN_MSG2VAL_MSGVAL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FADDR register.
//
//*****************************************************************************
#define USB_FADDR_M 0x0000007F // Function Address
#define USB_FADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_POWER register.
//
//*****************************************************************************
#define USB_POWER_ISOUP 0x00000080 // Isochronous Update
#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect
#define USB_POWER_RESET 0x00000008 // RESET Signaling
#define USB_POWER_RESUME 0x00000004 // RESUME Signaling
#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode
#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXIS register.
//
//*****************************************************************************
#define USB_TXIS_EP15 0x00008000 // TX Endpoint 15 Interrupt
#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXIS register.
//
//*****************************************************************************
#define USB_RXIS_EP15 0x00008000 // RX Endpoint 15 Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXIE register.
//
//*****************************************************************************
#define USB_TXIE_EP15 0x00008000 // TX Endpoint 15 Interrupt Enable
#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
// Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXIE register.
//
//*****************************************************************************
#define USB_RXIE_EP15 0x00008000 // RX Endpoint 15 Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_IS register.
//
//*****************************************************************************
#define USB_IS_VBUSERR 0x00000080 // VBUS Error
#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST
#define USB_IS_DISCON 0x00000020 // Session Disconnect
#define USB_IS_CONN 0x00000010 // Session Connect
#define USB_IS_SOF 0x00000008 // Start of Frame
#define USB_IS_BABBLE 0x00000004 // Babble Detected
#define USB_IS_RESET 0x00000004 // RESET Signaling Detected
#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected
#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_IE register.
//
//*****************************************************************************
#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt
#define USB_IE_SESREQ 0x00000040 // Enable Session Request
#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt
#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt
#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt
#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt
#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt
#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt
#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FRAME register.
//
//*****************************************************************************
#define USB_FRAME_M 0x000007FF // Frame Number
#define USB_FRAME_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPIDX register.
//
//*****************************************************************************
#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index
#define USB_EPIDX_EPIDX_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TEST register.
//
//*****************************************************************************
#define USB_TEST_FORCEH 0x00000080 // Force Host Mode
#define USB_TEST_FIFOACC 0x00000040 // FIFO Access
#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO0 register.
//
//*****************************************************************************
#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data
#define USB_FIFO0_EPDATA_S 0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_DEVCTL register.
//
//*****************************************************************************
#define USB_DEVCTL_DEV 0x00000080 // Device Mode
#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected
#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected
#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level
#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd
#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid
#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid
#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid
#define USB_DEVCTL_HOST 0x00000004 // Host Mode
#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request
#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
//
//*****************************************************************************
#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
//
//*****************************************************************************
#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFIFOADD
// register.
//
//*****************************************************************************
#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
#define USB_TXFIFOADD_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFIFOADD
// register.
//
//*****************************************************************************
#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
#define USB_RXFIFOADD_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_CONTIM register.
//
//*****************************************************************************
#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait
#define USB_CONTIM_WTID_M 0x0000000F // Wait ID
#define USB_CONTIM_WTCON_S 4
#define USB_CONTIM_WTID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_VPLEN register.
//
//*****************************************************************************
#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length
#define USB_VPLEN_VPLEN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FSEOF register.
//
//*****************************************************************************
#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap
#define USB_FSEOF_FSEOFG_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_LSEOF register.
//
//*****************************************************************************
#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap
#define USB_LSEOF_LSEOFG_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
// register.
//
//*****************************************************************************
#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address
#define USB_TXFUNCADDR0_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR0
// register.
//
//*****************************************************************************
#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address
#define USB_TXHUBADDR0_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT0
// register.
//
//*****************************************************************************
#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port
#define USB_TXHUBPORT0_PORT_S 0
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
// register.
//
//*****************************************************************************
#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address
#define USB_RXFUNCADDR1_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR1
// register.
//
//*****************************************************************************
#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address
#define USB_RXHUBADDR1_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT1
// register.
//
//*****************************************************************************
#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port
#define USB_RXHUBPORT1_PORT_S 0
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_CSRL0 register.
//
//*****************************************************************************
#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout
#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear
#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet
#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear
#define USB_CSRL0_REQPKT 0x00000020 // Request Packet
#define USB_CSRL0_STALL 0x00000020 // Send Stall
#define USB_CSRL0_SETEND 0x00000010 // Setup End
#define USB_CSRL0_ERROR 0x00000010 // Error
#define USB_CSRL0_DATAEND 0x00000008 // Data End
#define USB_CSRL0_SETUP 0x00000008 // Setup Packet
#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled
#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready
#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_CSRH0 register.
//
//*****************************************************************************
#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable
#define USB_CSRH0_DT 0x00000002 // Data Toggle
#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_COUNT0 register.
//
//*****************************************************************************
#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count
#define USB_COUNT0_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TYPE0 register.
//
//*****************************************************************************
#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed
#define USB_TYPE0_SPEED_FULL 0x00000080 // Full
#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_NAKLMT register.
//
//*****************************************************************************
#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit
#define USB_NAKLMT_NAKLMT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
//
//*****************************************************************************
#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
#define USB_TXMAXP1_MAXLOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
//
//*****************************************************************************
#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout
#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle
#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled
#define USB_TXCSRL1_STALL 0x00000010 // Send STALL
#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet
#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO
#define USB_TXCSRL1_ERROR 0x00000004 // Error
#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun
#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty
#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
//
//*****************************************************************************
#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set
#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers
#define USB_TXCSRH1_MODE 0x00000020 // Mode
#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable
#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle
#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode
#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable
#define USB_TXCSRH1_DT 0x00000001 // Data Toggle
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
//
//*****************************************************************************
#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
#define USB_RXMAXP1_MAXLOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
//
//*****************************************************************************
#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle
#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled
#define USB_RXCSRL1_STALL 0x00000020 // Send STALL
#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet
#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO
#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error
#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout
#define USB_RXCSRL1_OVER 0x00000004 // Overrun
#define USB_RXCSRL1_ERROR 0x00000004 // Error
#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full
#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
//
//*****************************************************************************
#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear
#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request
#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers
#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable
#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET
#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error
#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode
#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable
#define USB_RXCSRH1_DT 0x00000002 // Data Toggle
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
//
//*****************************************************************************
#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count
#define USB_RXCOUNT1_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
//
//*****************************************************************************
#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed
#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default
#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full
#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low
#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol
#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control
#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk
#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt
#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
#define USB_TXTYPE1_TEP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL1
// register.
//
//*****************************************************************************
#define USB_TXINTERVAL1_NAKLMT_M \
0x000000FF // NAK Limit
#define USB_TXINTERVAL1_TXPOLL_M \
0x000000FF // TX Polling
#define USB_TXINTERVAL1_TXPOLL_S \
0
#define USB_TXINTERVAL1_NAKLMT_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
//
//*****************************************************************************
#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed
#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default
#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full
#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low
#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol
#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control
#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk
#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt
#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
#define USB_RXTYPE1_TEP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL1
// register.
//
//*****************************************************************************
#define USB_RXINTERVAL1_TXPOLL_M \
0x000000FF // RX Polling
#define USB_RXINTERVAL1_NAKLMT_M \
#define USB_RXINTERVAL1_TXPOLL_S \
0
#define USB_RXINTERVAL1_NAKLMT_S \
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT10
// register.
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
// register.
//
//*****************************************************************************
#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count
#define USB_RQPKTCOUNT1_S 0
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count
#define USB_RQPKTCOUNT4_COUNT_S 0
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
//*****************************************************************************
//
// register.
//
//*****************************************************************************
#define USB_RQPKTCOUNT10_COUNT_M \
0x0000FFFF // Block Transfer Packet Count
#define USB_RQPKTCOUNT10_COUNT_S \
0
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
//*****************************************************************************
//
// register.
//
//*****************************************************************************
0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
// register.
//
//*****************************************************************************
#define USB_RXDPKTBUFDIS_EP15 0x00008000 // EP15 RX Double-Packet Buffer
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
// register.
//
//*****************************************************************************
#define USB_TXDPKTBUFDIS_EP15 0x00008000 // EP15 TX Double-Packet Buffer
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
// Disable
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPC register.
//
//*****************************************************************************
#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action
#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged
#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate
#define USB_EPC_PFLTACT_LOW 0x00000200 // Low
#define USB_EPC_PFLTACT_HIGH 0x00000300 // High
#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable
#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense
#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable
#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable
#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable
// Configuration
#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low
#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High
#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low
#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPCRIS register.
//
//*****************************************************************************
#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPCIM register.
//
//*****************************************************************************
#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPCISC register.
//
//*****************************************************************************
#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status
// and Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_DRRIS register.
//
//*****************************************************************************
#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_DRIM register.
//
//*****************************************************************************
#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_DRISC register.
//
//*****************************************************************************
#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and
// Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_GPCS register.
//
//*****************************************************************************
#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode
#define USB_GPCS_DEVMOD 0x00000001 // Device Mode
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_VDC register.
//
//*****************************************************************************
#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_VDCRIS register.
//
//*****************************************************************************
#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_VDCIM register.
//
//*****************************************************************************
#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_VDCISC register.
//
//*****************************************************************************
#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and
// Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_IDVRIS register.
//
//*****************************************************************************
#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_IDVIM register.
//
//*****************************************************************************
#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_IDVISC register.
//
//*****************************************************************************
#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status
// and Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_DMASEL register.
//
//*****************************************************************************
#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select
#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select
#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select
#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select
#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select
#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select
#define USB_DMASEL_DMACTX_S 20
#define USB_DMASEL_DMACRX_S 16
#define USB_DMASEL_DMABTX_S 12
#define USB_DMASEL_DMABRX_S 8
#define USB_DMASEL_DMAATX_S 4
#define USB_DMASEL_DMAARX_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXFIFO register.
//
//*****************************************************************************
#define I2S_TXFIFO_M 0xFFFFFFFF // TX Data
#define I2S_TXFIFO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXFIFOCFG
// register.
//
//*****************************************************************************
#define I2S_TXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size
#define I2S_TXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXCFG register.
//
//*****************************************************************************
#define I2S_TXCFG_JST 0x20000000 // Justification of Output Data
#define I2S_TXCFG_DLY 0x10000000 // Data Delay
#define I2S_TXCFG_SCP 0x08000000 // SCLK Polarity
#define I2S_TXCFG_LRP 0x04000000 // Left/Right Clock Polarity
#define I2S_TXCFG_WM_M 0x03000000 // Write Mode
#define I2S_TXCFG_WM_DUAL 0x00000000 // Stereo mode
#define I2S_TXCFG_WM_COMPACT 0x01000000 // Compact Stereo mode
#define I2S_TXCFG_WM_MONO 0x02000000 // Mono mode
#define I2S_TXCFG_FMT 0x00800000 // FIFO Empty
#define I2S_TXCFG_MSL 0x00400000 // SCLK Master/Slave
#define I2S_TXCFG_SSZ_M 0x0000FC00 // Sample Size
#define I2S_TXCFG_SDSZ_M 0x000003F0 // System Data Size
#define I2S_TXCFG_SSZ_S 10
#define I2S_TXCFG_SDSZ_S 4
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXLIMIT register.
//
//*****************************************************************************
#define I2S_TXLIMIT_LIMIT_M 0x0000001F // FIFO Limit
#define I2S_TXLIMIT_LIMIT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXISM register.
//
//*****************************************************************************
#define I2S_TXISM_FFI 0x00010000 // Transmit FIFO Service Request
// Interrupt
#define I2S_TXISM_FFM 0x00000001 // FIFO Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXLEV register.
//
//*****************************************************************************
#define I2S_TXLEV_LEVEL_M 0x0000001F // Number of Audio Samples
#define I2S_TXLEV_LEVEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXFIFO register.
//
//*****************************************************************************
#define I2S_RXFIFO_M 0xFFFFFFFF // RX Data
#define I2S_RXFIFO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXFIFOCFG
// register.
//
//*****************************************************************************
#define I2S_RXFIFOCFG_FMM 0x00000004 // FIFO Mono Mode
#define I2S_RXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size
#define I2S_RXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXCFG register.
//
//*****************************************************************************
#define I2S_RXCFG_JST 0x20000000 // Justification of Input Data
#define I2S_RXCFG_DLY 0x10000000 // Data Delay
#define I2S_RXCFG_SCP 0x08000000 // SCLK Polarity
#define I2S_RXCFG_LRP 0x04000000 // Left/Right Clock Polarity
#define I2S_RXCFG_RM 0x01000000 // Read Mode
#define I2S_RXCFG_MSL 0x00400000 // SCLK Master/Slave
#define I2S_RXCFG_SSZ_M 0x0000FC00 // Sample Size
#define I2S_RXCFG_SDSZ_M 0x000003F0 // System Data Size
#define I2S_RXCFG_SSZ_S 10
#define I2S_RXCFG_SDSZ_S 4
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXLIMIT register.
//
//*****************************************************************************
#define I2S_RXLIMIT_LIMIT_M 0x0000001F // FIFO Limit
#define I2S_RXLIMIT_LIMIT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXISM register.
//
//*****************************************************************************
#define I2S_RXISM_FFI 0x00010000 // Receive FIFO Service Request
// Interrupt
#define I2S_RXISM_FFM 0x00000001 // FIFO Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXLEV register.
//
//*****************************************************************************
#define I2S_RXLEV_LEVEL_M 0x0000001F // Number of Audio Samples
#define I2S_RXLEV_LEVEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_CFG register.
//
//*****************************************************************************
#define I2S_CFG_RXSLV 0x00000020 // Use External I2S0RXMCLK
#define I2S_CFG_TXSLV 0x00000010 // Use External I2S0TXMCLK
#define I2S_CFG_RXEN 0x00000002 // Serial Receive Engine Enable
#define I2S_CFG_TXEN 0x00000001 // Serial Transmit Engine Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_IM register.
//
//*****************************************************************************
#define I2S_IM_RXRE 0x00000020 // Receive FIFO Read Error
#define I2S_IM_RXFSR 0x00000010 // Receive FIFO Service Request
#define I2S_IM_TXWE 0x00000002 // Transmit FIFO Write Error
#define I2S_IM_TXFSR 0x00000001 // Transmit FIFO Service Request
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RIS register.
//
//*****************************************************************************
#define I2S_RIS_RXRE 0x00000020 // Receive FIFO Read Error
#define I2S_RIS_RXFSR 0x00000010 // Receive FIFO Service Request
#define I2S_RIS_TXWE 0x00000002 // Transmit FIFO Write Error
#define I2S_RIS_TXFSR 0x00000001 // Transmit FIFO Service Request
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_MIS register.
//
//*****************************************************************************
#define I2S_MIS_RXRE 0x00000020 // Receive FIFO Read Error
#define I2S_MIS_RXFSR 0x00000010 // Receive FIFO Service Request
#define I2S_MIS_TXWE 0x00000002 // Transmit FIFO Write Error
#define I2S_MIS_TXFSR 0x00000001 // Transmit FIFO Service Request
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_IC register.
//
//*****************************************************************************
#define I2S_IC_RXRE 0x00000020 // Receive FIFO Read Error
#define I2S_IC_TXWE 0x00000002 // Transmit FIFO Write Error
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCC register.
//
//*****************************************************************************
#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
#define HIB_RTCC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCM0 register.
//
//*****************************************************************************
#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
#define HIB_RTCM0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCM1 register.
//
//*****************************************************************************
#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1
#define HIB_RTCM1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCLD register.
//
//*****************************************************************************
#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
#define HIB_RTCLD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_CTL register.
//
//*****************************************************************************
#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable
#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
#define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select
#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_IM register.
//
//*****************************************************************************
#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
// Mask
#define HIB_IM_RTCALT1 0x00000002 // RTC Alert 1 Interrupt Mask
#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RIS register.
//
//*****************************************************************************
#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
// Status
#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
// Interrupt Status
#define HIB_RIS_RTCALT1 0x00000002 // RTC Alert 1 Raw Interrupt Status
#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_MIS register.
//
//*****************************************************************************
#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
// Interrupt Status
#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
// Interrupt Status
#define HIB_MIS_RTCALT1 0x00000002 // RTC Alert 1 Masked Interrupt
// Status
#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_IC register.
//
//*****************************************************************************
#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
// Interrupt Clear
#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
// Interrupt Clear
#define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
// Clear
#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
// Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCT register.
//
//*****************************************************************************
#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
#define HIB_RTCT_TRIM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_DATA register.
//
//*****************************************************************************
#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
#define HIB_DATA_RTD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMA register.
//
//*****************************************************************************
#define FLASH_FMA_OFFSET_M 0x0007FFFF // Address Offset
#define FLASH_FMA_OFFSET_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMD register.
//
//*****************************************************************************
#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value
#define FLASH_FMD_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMC register.
//
//*****************************************************************************
#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
#define FLASH_FMC_COMT 0x00000008 // Commit Register Value
#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory
#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FCRIS register.
//
//*****************************************************************************
#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FCIM register.
//
//*****************************************************************************
#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FCMISC register.
//
//*****************************************************************************
#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
// Status and Clear
#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
// and Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMC2 register.
//
//*****************************************************************************
#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key
#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FWBVAL register.
//
//*****************************************************************************
#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FCTL register.
//
//*****************************************************************************
#define FLASH_FCTL_USDACK 0x00000002 // User Shut Down Acknowledge
#define FLASH_FCTL_USDREQ 0x00000001 // User Shut Down Request
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FWBN register.
//
//*****************************************************************************
#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_RMCTL register.
//
//*****************************************************************************
#define FLASH_RMCTL_BA 0x00000001 // Boot Alias
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_RMVER register.
//
//*****************************************************************************
#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents
#define FLASH_RMVER_CONT_LM_AES2 \
0x05000000 // Stellaris Boot Loader &
// DriverLib with AES
#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version
#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision
#define FLASH_RMVER_VER_S 8
#define FLASH_RMVER_REV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_BOOTCFG register.
//
//*****************************************************************************
#define FLASH_BOOTCFG_NW 0x80000000 // Not Written
#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port
#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A
#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B
#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C
#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D
#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E
#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F
#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G
#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H
#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin
#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0
#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3
#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7
#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity
#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable
#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1
#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERREG0 register.
//
//*****************************************************************************
#define FLASH_USERREG0_NW 0x80000000 // Not Written
#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data
#define FLASH_USERREG0_DATA_S 0
//*************************************************

I2c Bus

Încărcat de

Informații document

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

I2c Bus

Încărcat de

Drepturi de autor:

Formate disponibile

ne NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend

#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend

/***************** Functions *************************************************/

/* USB Host functions exported from USB Host Core module */

/* USB Device functions exported from USB Device Core module */

/* USB Device user functions imported to USB HID Class module */

/* USB Device user functions imported to USB Audio Class module */

/* USB Device user functions imported to USB Custom Class module */

/* RL-ARM version number. */

#define __task __declspec(noreturn)

typedef signed char S8;

/* Definition of Semaphore type */

/* Definition of Mailbox type */

/* Definition of Mutex type */

/* Task Identification number. */

/* Function return of system calls returning an object identification */

/* Function return of system calls indicating an event or completion state */

#define OS_R_OK 0x00

#if !(__TARGET_ARCH_6S_M || __TARGET_ARCH_7_M || __TARGET_ARCH_7E_M)

extern void os_sys_init0 (void (*task)(void), U32 prio_stksz, void *stk);

/* Event flag Management */

extern OS_RESULT os_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait);

extern void os_mbx_init (OS_ID mailbox, U16 mbx_size);

/* User Timer Management */

#define __SVC_0 __svc_indirect(0)

#define os_sys_init(tsk) os_set_env(); \

extern void _os_sys_init(U32 p, void (*task)(void), U32 prio_stksz,

/* Event flag Management */

extern OS_RESULT _os_evt_wait(U32 p, U16 wait_flags, U16 timeout,

#define os_sem_init(sem,t_count) _os_sem_init((U32)rt_sem_init,sem,t_count)

extern void _os_sem_init (U32 p, OS_ID semaphore,

#define os_mbx_init(mbx,mbx_size) _os_mbx_init((U32)rt_mbx_init,mbx,mbx_size)

extern void _os_mbx_init (U32 p, OS_ID mailbox, U16 mbx_size) __SVC_0;

#define os_mut_init(mutex) _os_mut_init((U32)rt_mut_init,mutex)

extern void _os_mut_init (U32 p, OS_ID mutex) __SVC_0;

#define os_time_get() _os_time_get((U32)rt_time_get)

extern U32 _os_time_get (U32 p) __SVC_0;

/* User Timer Management */

#define os_tmr_create(tcnt,info) _os_tmr_create((U32)rt_tmr_create,tcnt,info)

extern OS_ID _os_tmr_create (U32 p, U16 tcnt, U16 info) __SVC_0;

#define os_suspend() _os_suspend((U32)rt_suspend)

extern U32 _os_suspend (U32 p) __SVC_0;

#define BOX_ALIGN_8 0x80000000

/* For compatibility with older configurations.*/

/* File System Type */

typedef struct { /* RL Time format (FFS, TCPnet) */

typedef struct { /* Search info record */

extern int finit (const char *drive);

/* The following macros provide for common functions */

/* TCP Socket Types */

/* TCP Callback Events */

/* BSD Socket Address Family */

/* BSD Protocol families, same as address families */

/* BSD Socket Protocol */

/* BSD Internet Addresses */

/* BSD Socket Return values */

/* BSD Socket flags parameter */

/* BSD Socket ioctl commands */

/* ICMP (ping) Callback Events */

/* DNS Client Callback Events */

/* DNS 'get_host_by_name()' result codes */

/* SMTP Client Callback Events */

/* FTP Client Commands */

/* Functions *********************************/

#define task declspec(noreturn)

extern void os_sys_init0 (void (task)(void), U32 prio_stksz, void stk);