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Figure 14.2.8-1 Payload Slot Profile SLT3-PAY-1F4U-14.2.8 ................................................. 365
Figure 14.2.9-1 Payload Slot Profile SLT3-PAY-8U-14.2.9...................................................... 367
Figure 14.2.10-1 Payload Slot Profile SLT3-PAY-1F1U-14.2.10 ............................................. 369
Figure 14.2.11-1 Payload Slot Profile SLT3-PAY-2F4F2U-14.2.11 ......................................... 372
Figure 14.2.12-1 Payload Slot Profile SLT3-PAY-1F2U-14.2.12 ............................................. 376
Figure 14.2.13-1 Payload Slot Profile SLT3-PAY-3F2U-14.2.13 ............................................. 379
Figure 14.3.1-1 Peripheral Slot Profile SLT3-PER-2F-14.3.1 ................................................... 382
Figure 14.3.2-1 Peripheral Slot Profile SLT3-PER-1F-14.3.2 ................................................... 384
Figure 14.3.3-1 Peripheral Slot Profile SLT3-PER-1U-14.3.3 ................................................... 386
Figure 14.4.1-1 Switch Slot Profile SLT3-SWH-6F6U-14.4.1 .................................................. 388
Figure 14.4.2-1 Switch Slot Profile SLT3-SWH-8F-14.4.2 ....................................................... 392
Figure 14.4.3-1 Switch Slot Profile SLT3-SWH-2F24U-14.4.3 ................................................ 395
Figure 14.4.4-1 Switch Slot Profile SLT3-SWH-4F-14.4.4 ....................................................... 399
Figure 14.4.5-1 Switch Slot Profile SLT3-SWH-2F8U-14.4.5 .................................................. 401
Figure 14.4.6-1 Switch Slot Profile SLT3-SWH-16T-14.4.6 ..................................................... 404
Figure 14.4.7-1 Switch Slot Profile SLT3-SWH-1F14T-14.4.7................................................. 407
Figure 14.4.8-1 Switch Slot Profile SLT3-SWH-2F12T-14.4.8................................................. 410
Figure 14.4.9-1 Switch Slot Profile SLT3-SWH-6F8U-14.4.9 .................................................. 413
Figure 14.5.1-1 Storage Slot Profile SLT3-STO-2U-14.5.1....................................................... 417
Figure 14.6.1-1 Payload Slot Profile SLT3-PAY-1F1F2U4R-14.6.1 ........................................ 420
Figure 14.6.2-1 Payload Slot Profile SLT3-PAY-4F4R-14.6.2.................................................. 424
Figure 15.2.2-1 Topology of BKP3-CEN06-15.2.2-n ................................................................ 435
Figure 15.2.2-2 Expansion Plane Lanes of BKP3-CEN06-15.2.2-n .......................................... 436
Figure 15.2.3-1 Topology of BKP3-CEN07-15.2.3-n ................................................................ 441
Figure 15.2.4-1 Topology of BKP3-CEN10-15.2.4-n ................................................................ 445
Figure 15.2.4-2 Expansion Plane Lanes of BKP3-CEN10-15.2.4-n .......................................... 446
Figure 15.2.5-1 Topology of BKP3-CEN10-15.2.5-n ................................................................ 450
Figure 15.2.5-2 Expansion Plane Lanes of BKP3-CEN10-15.2.5-n .......................................... 451
Figure 15.2.6-1 Topology of BKP3-CEN12-15.2.6-n ................................................................ 456
Figure 15.2.7-1 Topology of BKP3-DIS06-15.2.7-n .................................................................. 461
Figure 15.2.8-1 Topology of 2 Slot - BKP3-DIS02-15.2.8-n ..................................................... 466
Figure 15.2.9-1 Topology of BKP3-CEN03-15.2.9-n ................................................................ 469
Figure 15.2.10-1 Topology of BKP3-CEN06-15.2.10-n ............................................................ 472
Figure 15.2.11-1 Topology of BKP3-CEN09-15.2.11-n ............................................................ 475
Figure 15.2.12-1 Topology of BKP3-CEN06-15.2.12-n ............................................................ 478
Figure 15.2.13-1 Topology of 5 Slot - BKP3-DIS05-15.2.13-n ................................................. 481
Figure 15.2.14-1 Topology of BKP3-DIS06-15.2.14-n .............................................................. 484
Figure 15.2.15-1 Topology of BKP3-CEN08-15.2.15-n ............................................................ 488
Figure 15.2.16-1 Topology of BKP3-CEN08-15.2.16-n ............................................................ 493
Figure 15.2.17-1 Topology of BKP3-CEN09-15.2.17-n ............................................................ 498
For those who contributed to the first version of this specification, see the Acknowledgements
Section of [VITA 65-2010].
The VITA 65 Technical Working Group is indebted to the following individual(s) and would
like to recognize their contribution to the successful completion of this, the second version of
the VITA 65 Specification:
• To the Working Group Members and their respective companies without their commitment
and dedication this body of work could not have been completed.
• To Pete Jha, who was the VITA 65 Technical Working Group Chair through much of the
process of creating this specification.
• To John Rynearson for his invaluable guidance during the VSO and ANSI Ratification
process.
• To the following individuals who wrote content that was incorporated into this version of
the specification – in alphabetical order:
o Steve Edwards of Curtiss-Wright Controls Embedded Computing
o Bob Ford of The Boeing Company
o Jim Goldenberg of General Electric
o Paul Mesibov of PENTEK
o Mike Munroe of Elma Bustronic Corp.
o Greg Rocco of Mercury Computer Systems
o David Slaton of General Electric
o Serge Tissot of Kontron
Greg Rocco
Mercury Computer Systems
VITA 65 Technical Working Group Chair and Lead Editor
Feb. 28, 2012
Name Company
David Hinkle Elma Electronic, Inc.
Chris Eckert General Electric
Steve Edwards Curtiss-Wright Controls Embedded Computing
Fred Fons Foxconn Electronics
Robert Ford The Boeing Company
Scott Goedeke Northrop Grumman
Jim Goldenberg General Electric
Jay Grandin Annapolis Micro Systems, Inc.
Paul Griffith Concurrent Technologies
Val Gueorguiev
Pete Jha Curtiss-Wright Controls Embedded Computing
Paul Mesibov PENTEK INC
Michael Munroe Elma Bustronic Corp.
Greg Rocco Mercury Computer Systems
John Rynearson VITA
Pat Shaw General Dynamics Canada
Andrew Shieh CSPI
David Slaton General Electric
Bob Sullivan Curtiss-Wright Controls Embedded Computing
Michael Thompson Pentair
Kevin Thorson Lockheed Martin
Serge Tissot Kontron Modular Computers S.A.S
Dan Toohey Mercury Computer Systems
Ben Winder Curtiss-Wright Controls Embedded Computing
Anyone wishing to provide comments, corrections and/or additions to this standard please direct
them to the VITA Technical Director:
John Rynearson, Technical Director
VITA
PO Box 19658
Fountain Hills, AZ 85269
Ph: 480 837 7486
Email: techdir@vita.com
Should anyone want information on other ANSI/VITA standards, the VME Handbook, or
general information on the embedded market, please contact the VITA office at the address,
telephone number, or URL shown on the front cover.
The change bars in this document show changes from [VITA 65-2010], with the exception of
very minor changes such as formatting and punctuation.
This section does not highlight all changes. Here are examples of changes that are not
specifically listed in this section:
• Formatting changes are not listed (these are also not indicated by change bars).
• Minor changes to informative text are not listed.
• There were several places where there were minor problems with Section headers, table
titles or figure titles, these are not listed. For example Figure 10.3.1-1, had been labeled as
a “Payload Slot Profile” but the title of the Section it is labeled “Peripheral Slot Profile”.
With Sections that were re-written, in order to keep the reference numbers, for the requirements,
in the new version of this document, unique from the numbers used to reference requirements in
the previous version, the sequence numbers in sections that are re-written start with a sequence
number that is larger than the largest number in the previous version of the section. Here is the
section that was re-written:
• Section 5.3 — This section was re-written. The Working Group decided that the PCIe
topology information that was included in [VITA 65-2010] was confusing. We decided to
make the issues of PCIe topology, that were being covered in Section 5.3 of
[VITA 65-2010], beyond the scope of this document. Also, the re-write allows for a
Common Reference Clock whereas [VITA 65-2010] did not.
Some errors with [VITA 65-2010] were found. With the exception of the re-write of Section 5.3,
requirements that were deleted, that had other requirements following them, in the same section,
were left in place, with “***Deleted***”, inserted at the beginning of the requirement. This
preserves requirement number, so the numbering of other requirements does not change and to
makes it clear that the requirement was deleted, in case it was referenced by an external
document. The text of the deleted requirement is struck through. Here is a list of corrections
and other changes:
• Updated Section 1.2 to reflect sections that were added to accommodate new protocols and
connector types.
• With Section 1.3.2, the following terms were added to the Glossary:
o IB (InfiniBand)
o PCIe Common Reference clock
o TFP (Triple Fat Pipe)
• With Section 1.3.2, the following terms were removed from the Glossary:
o System Root Complex
• Updated Section 1.3.3, to reflect the construction of Profile names including VITA 67
connectors.
• Section 1.3.4 (Backplane Profile Topologies) added text and figures to better defined the
terminology used to refer to topologies.
• Section 1.4 was re-written to not refer to the VITA internal documentation concerning the
maintenance of VITA 65.
• Section 1.5 gives the references. In [VITA 65-2010] the revision of references was not
included. Now it is. In addition to adding revisions to references, text was added to the
introduction of Section 1.5 to explain that references might be out of date.
• Observation 2.1.1-1 was deleted. This was mentioning a template for compliance that has
not been implemented.
• Rules, associated with resistance value, were re-worded to make it so that a resistance,
within a tolerance range is required, as opposed to requiring a particular value and
tolerance of a resistor. For example instead of saying “a 4.7 Kohm +/- 5% resistor” is
required, we say a “resistance of 4.7 Kohm +/- 5%” is required. These changes did not
change the resistance value that was required to meet the requirement. Here is a list of the
Rules changed in this way: Rule 3.4.3-3, Rule 3.4.4-2, Rule 3.4.4-3, Rule 3.6-2, and Rule
3.6-4.
• It was felt that Recommendation 3.4.3-1 was not clear and was not adding enough value,
so it was deleted.
• With Permission 5.1.2-2, Observation 5.1.2-1, and Observation 5.1.2-2; changed
“1000BASE-KX4” to “10GBASE-KX4”. The “1000BASE-KX4” was there in error.
• There was redundancy between Rule 7.4-1 and Rule 7.4-2. Deleted Rule 7.4-2 and
reworded Rule 7.4-1.
• The beginnings of the Backplane Profiles Sections; Sections 11 and 15 were reorganized
and additional tables were added to the start of Section 15, to account for the addition of
Profiles that include other than VITA 46.0 connectors.
• With Rule 11.2.1.2.4-6 and Rule 15.2.1.2.4-6 there is a note saying the physical slot
numbers can be different from the ones in this document. To make it more clear changed
“the Slot numbers in this document” to “the logical Slot numbers in this document”.
• Rule 11.2.2.3-4 was changed to correct a signal name from “CSutp16” to “CPutp16”.
• The following Observations were changed to make them consistent with the re-write of
Section 5.3: Observation 11.2.2.4-1, Observation 11.2.3.4-1, Observation 11.2.4.4-1,
Observation 11.2.5.4-1, Observation 11.2.6.4-1, Observation 11.2.7.4-1, Observation
11.2.8.4-1, Observation 11.2.9.4-1,
Section 1.2 gives an overview other structure and explains that this document is structured in a
way to allow new content to be added without disturbing existing content. Here is a list of new
sections:
• Section 3.4.9 Auxiliary Resets (AXreset*)
• Slot Thermal
Module • Slot Mechanical Chassis
• Pitch
• Height
• Other Functions
• Functional API Enclosure:
• Sys Management API • Mechanical
Application • Thermal
• Power
The OpenVPX standard acknowledges, but does not define the interfaces between the
Application and the Module or Chassis (Grayed out text and lines).
Figure 1-1 System Interoperability Diagram with interface content