A B C D E

1 1

QIQY5
2
Whisky3.0 (Y400S) 2

NM-A141 Rev0.2 Schematic

Intel IVY Bridge Processor with DDRIII + Panther Point PCH

3
nVIDIA N14P GT + 2nd VGA N14P GT 3

2012-10-25-Rev0.2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 COVER PAGE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 1 of 65
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 A B C D E

PCI-Express 16X Gen3

PEG 8~15 PEG 0~7
Intel CPU
Ivy Bridge Memory BUS (DDRIII) DDR3-SO-DIMM X2
2nd VGA, N14P-GT1 N14P-GT1 Dual Channel
1 BANK 0, 1, 2, 3 1

VRAM 64*32 VRAM 64*32

rPGA-989
37.5mm*37.5mm 1.5V DDRIII 1066/1333/1600 MT/s
GDDR5* 8 GDDR5* 8 UP TO 16G

Sub/B Page 32 Page 23,24,25,26,27,28,29,30,31

Page 5,6,7,8,9,10,11

FDI *8 DMI *4
2.7GT/s 5GT/s

HDMI Conn. CRT Conn. LVDS Conn. USB Left USB Right
Page 36 Page 35 Page 34 USB 2.0 4x
USB 2.0 Port 2 USB 2.0 Port 9
HDMI1.4b 5V 480MHz USB 3.0 Port 2 USB 2.0 Port 5, Cha
Page 48 Sub/B Page 49
2
Intel PCH USB 3.0 2x Int. Camera BT
2

Atheros Panther Point 5V 5GT/s USB 3.0 Port 0

Page 34
USB 2.0 Port 13
Page 47
AR8161 1G PCIe Gen1 1x
RJ45 Conn. 1.5V 5GT/s
Page 39 AR8151 1G
PCIe port 1 Page 38 USB 2.0 1x
PCIeMini Card mSATA SSD
FCBGA-989 Balls 5V 480MHz WLAN
PCIe Port 2 SATA Port 0
25mm*25mm PCIe Gen1 1x page 37 page 37
CardReader 5V 480MHz
JMB38C PCIe Gen1 1x PCIeMini Card
1.5V 5GT/s SATA Gen3 Port 0 WLAN
SD/MMC/MS/XD USB Port 10
page 37
5V 6GHz(600MB/s)
PCIe port 4 Page 44

SATA Gen3 Port 1 SATA HDD

5V 6GHz(600MB/s) SATA Port 1
3
SPI ROM SPI BUS page 41 3

(4MB+2MB) 3.3V 33MHz

Page 14 SATA Gen1 Port2 SATA ODD
Page 14,15,16,17,18,19,20,21,22 5V 3GHz(300MB/s) SATA Port 1
page 41

HD Audio
LPC BUS
3.3V 33MHz
3.3V 24MHz

Debug Port EC Codec AMP

Page 45 ITE IT8580E-HX ALC269Q-VC3 MAX98400B SPK Conn.
Page 43
Page 42 Page 43
Page 45
Power Circuit DC/DC
Page 52,53,54,55,56,57,
58,59,60,61,62

4 DC/DC Interface CKT. RTC CKT. Thermal Sensor Int. MIC Conn. 4

Page 51 Page 52 Touch Pad Int.KBD (JCMOS Conn.) Ext. MIC Conn. HP Conn.
EMC 1403 Page 34 Page 49 Page 49
Page 46 Page 46 Page 40
Sub/B Sub/B
POWER/B Conn. AUDIO, USB/B Conn.
Page 40 Page 49 Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 BlOCK DIAGRAM

ODD/B Conn. NOVO/B Conn. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
page 41 Page 40 DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Y400S-NM-A141 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Monday, January 14, 2013 Sheet 2 of 65
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 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.5VS
+VCCSA S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1
+V1.5S_VCCP 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+CPU_CORE
+3VALW
+VGA_CORE S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
B+ +1.5V
+GFX_CORE
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+5VALW +1.8VS
+1.05VS
State +0.75VS
+3.3VS_VGA
+1.5VS_VGA
+1.05VS_VGA
USB Port Table BOM Structure Table
4 External BOM Structure BTO Item
USB 2.0 USB 3.0 Port USB Port
HDMI@ HDMI part
S0 O O O O Camera
0
1
XHCI 1 CHG@ USB charger part
2 NOCHG@ No USB charger part
S3 O O O X EHCI1
2 USB Port (Left Side) CMOS@ CMOS Camera part
3
2 3 8161@ AR8161 LAN part 2
4 8151@ AR8151 LAN part
S5 S4/AC Only O O X X 4
8161S@ AR8161 LAN surge part
5 USB Port (Right Side) AR8151 LAN surge part
8151S@
6
S5 S4 SURGE@ AR8151&8161 LAN surge part --> Delete (201200627)

O X X X 7 X76 P/N for AR8161

Battery only 61@
8 51@ X76 P/N for AR8151
EHCI2
9 USB Port (Right Side) X76@ X76 Level part for VRAM
S5 S4 10 Mini Card(WLAN)
GC6@ NV CG6 support part
AC & Battery X X X X 11
NOGC6@ NV no CG6 support part
don't exist 12 AOAC@ AOAC support part
13 Blue Tooth K/B Light part
KBL@
ME@ ME part
SMBUS Control Table OPT@ For optimus function part

Main 2nd WLAN Thermal TP PCIE PORT LIST SLI@ For SLI function part
SOURCE BATT IT8580E SODIMM PCH Deep S3 support part
VGA VGA WiMAX Sensor Module Port Device DS3@
3 S3@ For S3 function part 3

1 LAN GT@ NV chip part

EC_SMB_CK1 IT8580E
X X V X X X X X X 2 WLAN @ Unpop
EC_SMB_DA1 +3VALW
+3VALW 3
4 Card Reader
EC_SMB_CK2 IT8580E
V V X X X X V V X 5
EC_SMB_DA2 +3VS +3VS +3VS +3VS +3V_PCH 6
7
SMB_CLK_S3 PCH
SMB_DATA_S3 X X X X V V X V V 8
+3VS +3VS +3VS +3V_PCH +3VS

Address
EC SM Bus1 address EC SM Bus2 address PCH SM Bus address ZZZ1
4 4

Device Device Address Device Address

Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_101xb DDR DIMM0 1001 000Xb
DAZ00200100
Master VGA 0x9E DDR DIMM2 1001 010Xb
Slave VGA 0x9C
Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 NOTES LIST

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Tuesday, March 12, 2013 Sheet 3 of 65
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 5 4 3 2 1

Hot plug detect for IFP link E

Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
FBVDDQ PCI Express I/O and I/O and Other
VGA and GDDR5 Voltage Rails (N13Px GPIO) GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO I/O ACTIVE Function Description Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)

GPIO0 OUT - FB_CLAMP N13X

128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
D
1GB D
GPIO1 OUT - GDDR5

GPIO2 OUT - VGA_BL_PWM Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO3 OUT - VGA_ENVDD ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
GPIO4 OUT - VGA_ENBKL ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO5 OUT -
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO6 OUT - FB_CLAMP_TOGGLE_REQ# STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO7 OUT - STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO8 I/O - OVERT# STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
GPIO9 OUT - VGA_ALERT#
Device ID setting I2C Slave addrees ID
GPIO10 OUT - Memory VREF Control N13P-GT SMB_ALT_ADDR
(28nm) 0x0FDB 0 0x9E
(ROM_SO Bit 1)
GPIO11 OUT - NVVDD PWM_VID
C C
1 0x9C
GPIO12 IN VGA_AC_DET_R (10K pull High)

GPIO13 OUT - DPRSLPVR_VGA

GPIO14 OUT -
GPU ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
GPIO15 IN N/A
PU 10K PU 25K PU 45K PD 35K PD 10K PU 5K PD 10K Master
GPIO16 OUT - N13P-GT1
28nm PU 20K PU 25K PU 45K PD 35K PD 10K PD 5K PD 10K Slave
GPIO17 IN N/A

GPIO18 IN - dGPU_HDMI_HPD

GPIO19 IN -
GPU N13P-GT

FB Memory (GDDR5) ROM_SI

Samsung K4G10325FG-HC04
B
+3VS_VGA 2500MHz B

32Mx32 PD 45K
+VGA_CORE
Hynix H5GQ1H24BFR-T2C
tNVVDD >0 2500MHz
+1.5VS_VGA 32Mx32 PD 35K
tFBVDDQ >0
Samsung K4G20325FD-FC04
+1.05VS_VGA 2500MHz
tPEX_VDD >0 64Mx32 PD 30K

Hynix H5GQ2H24MFR-T2C
1. all power rail ramp up time should be larger than 40us
2500MHz
64Mx32 PD 25K

Other Power rail

+3VS_VGA
A A

Tpower-off <10ms

Security Classification LC Future Center Secret Data Title

1.all GPU power rails should be turned off within 10ms

Issued Date 2011/11/01 Deciphered Date 2012/12/31 VGA NOTES LIST
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 4 of 65
5 4 3 2 1
 5 4 3 2 1

D D

1. PEG_ICOMPI and RCOMPO signals should be shorted and routed with

a. max length = 500 mils
b. typical impedance = 43 mohms
2. PEG_ICOMPO signals should be routed with
+1.05VS a. max length = 500 mils
JCPU1A ME@ R1 b. typical impedance = 14.5 mohms
J22 PEG_COMP 2 1
PEG_ICOMPI J21
DMI_CRX_PTX_N0 B27 PEG_ICOMPO H22 24.9_0402_1%
<16> DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO
DMI_CRX_PTX_N1 B25
<16> DMI_CRX_PTX_N1 DMI_RX#[1]
DMI_CRX_PTX_N2 A25
<16> DMI_CRX_PTX_N2 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] <23,32>
DMI_CRX_PTX_N3 B24 K33 PCIE_CRX_GTX_N0
<16> DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0] M35 PCIE_CRX_GTX_N1
DMI_CRX_PTX_P0 B28 PEG_RX#[1] L34 PCIE_CRX_GTX_N2
<16> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2]
DMI_CRX_PTX_P1 B26 J35 PCIE_CRX_GTX_N3 PEG Static Lane Reversal - CFG2 is for the 16x
<16> DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3]
DMI_CRX_PTX_P2 A24 J32 PCIE_CRX_GTX_N4
<16> DMI_CRX_PTX_P2

DMI
DMI_CRX_PTX_P3 B23 DMI_RX[2] PEG_RX#[4] H34 PCIE_CRX_GTX_N5
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] H31 PCIE_CRX_GTX_N6 1: Normal Operation; Lane # definition matches
G21 PEG_RX#[6] G33
<16> DMI_CTX_PRX_N0
DMI_CTX_PRX_N0
DMI_TX#[0] PEG_RX#[7]
PCIE_CRX_GTX_N7 CFG2 socket pin map definition
DMI_CTX_PRX_N1 E22 G30 PCIE_CRX_GTX_N8
<16> DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 F21 DMI_TX#[1] PEG_RX#[8] F35 PCIE_CRX_GTX_N9
<16> DMI_CTX_PRX_N2 D21 DMI_TX#[2] PEG_RX#[9] E34
DMI_CTX_PRX_N3 PCIE_CRX_GTX_N10 0:Lane Reversed
<16>

<16>
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P0 G22
D22
DMI_TX#[3]

DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
D31
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_N12 *
DMI_CTX_PRX_P1 PCIE_CRX_GTX_N13
<16> DMI_CTX_PRX_P1 F20 DMI_TX[1] PEG_RX#[13] B33
DMI_CTX_PRX_P2 PCIE_CRX_GTX_N14
<16> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]

PCI EXPRESS* - GRAPHICS

DMI_CTX_PRX_P3 C21 C32 PCIE_CRX_GTX_N15
<16> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
C PCIE_CRX_GTX_P[0..15] <23,32> C
J33 PCIE_CRX_GTX_P0
PEG_RX[0] L35 PCIE_CRX_GTX_P1
PEG_RX[1] K34 PCIE_CRX_GTX_P2
FDI_CTX_PRX_N0 A21 PEG_RX[2] H35 PCIE_CRX_GTX_P3
<16> FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 H19 FDI0_TX#[0] PEG_RX[3] H32 PCIE_CRX_GTX_P4
<16> FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 E19 FDI0_TX#[1] PEG_RX[4] G34 PCIE_CRX_GTX_P5
<16> FDI_CTX_PRX_N2 F18 FDI0_TX#[2] PEG_RX[5] G31
FDI_CTX_PRX_N3 PCIE_CRX_GTX_P6
<16> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]

Intel(R) FDI
FDI_CTX_PRX_N4 B21 F33 PCIE_CRX_GTX_P7
<16> FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 C20 FDI1_TX#[0] PEG_RX[7] F30 PCIE_CRX_GTX_P8
<16> FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 D18 FDI1_TX#[1] PEG_RX[8] E35 PCIE_CRX_GTX_P9
<16> FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 E17 FDI1_TX#[2] PEG_RX[9] E33 PCIE_CRX_GTX_P10
<16> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] F32 PCIE_CRX_GTX_P11
PEG_RX[11] D34 PCIE_CRX_GTX_P12
FDI_CTX_PRX_P0 A22 PEG_RX[12] E31 PCIE_CRX_GTX_P13
<16> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 G19 FDI0_TX[0] PEG_RX[13] C33 PCIE_CRX_GTX_P14
<16> FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 E20 FDI0_TX[1] PEG_RX[14] B32 PCIE_CRX_GTX_P15
<16> FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 G18 FDI0_TX[2] PEG_RX[15]
<16> FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 B20 FDI0_TX[3] M29 PCIE_CTX_GRX_C_N0 1 2 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_N[0..15] <23,32>
C1 0.22U_0402_10V6K
<16> FDI_CTX_PRX_P4 C19 FDI1_TX[0] PEG_TX#[0] M32 1 2
FDI_CTX_PRX_P5 PCIE_CTX_GRX_C_N1 C2 0.22U_0402_10V6K PCIE_CTX_GRX_N1
<16> FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 D19 FDI1_TX[1] PEG_TX#[1] M31 PCIE_CTX_GRX_C_N2 1 2 PCIE_CTX_GRX_N2
C3 0.22U_0402_10V6K
<16> FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 F17 FDI1_TX[2] PEG_TX#[2] L32 PCIE_CTX_GRX_C_N3 1 2 PCIE_CTX_GRX_N3
C4 0.22U_0402_10V6K
<16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] L29 PCIE_CTX_GRX_C_N4 1 2 PCIE_CTX_GRX_N4
C5 0.22U_0402_10V6K
FDI_FSYNC0 J18 PEG_TX#[4] K31 PCIE_CTX_GRX_C_N5 C6 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N5
<16> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
FDI_FSYNC1 J17 K28 PCIE_CTX_GRX_C_N6 C7 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N6
<16> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] J30 PCIE_CTX_GRX_C_N7 C8 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N7
FDI_INT H20 PEG_TX#[7] J28 PCIE_CTX_GRX_C_N8 SLI@ C9 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N8
<16> FDI_INT FDI_INT PEG_TX#[8] H29 PCIE_CTX_GRX_C_N9 SLI@ C10 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N9
FDI_LSYNC0 J19 PEG_TX#[9] G27 PCIE_CTX_GRX_C_N10 SLI@ C11 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N10
<16> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
FDI_LSYNC1 H17 E29 PCIE_CTX_GRX_C_N11 SLI@ C12 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N11
<16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] F27 PCIE_CTX_GRX_C_N12 SLI@ C13 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N12
PEG_TX#[12] D28 PCIE_CTX_GRX_C_N13 SLI@ C14 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N13
+1.05VS PEG_TX#[13] F26 PCIE_CTX_GRX_C_N14 SLI@ C15 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N14
B R7 PEG_TX#[14] E25 PCIE_CTX_GRX_C_N15 SLI@ C16 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N15 B
1 2 EDP_COMP A18 PEG_TX#[15]
A17 eDP_COMPIO M28 PCIE_CTX_GRX_C_P0 1 2 PCIE_CTX_GRX_P0 PCIE_CTX_GRX_P[0..15] <23,32>
C20 0.22U_0402_10V6K
24.9_0402_1% B16 eDP_ICOMPO PEG_TX[0] M33 PCIE_CTX_GRX_C_P1 C23 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P1
eDP_HPD# PEG_TX[1] M30 PCIE_CTX_GRX_C_P2 C25 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P2
PEG_TX[2] L31 PCIE_CTX_GRX_C_P3 1 2 PCIE_CTX_GRX_P3
eDP_COMPIO and ICOMPO signals PEG_TX[3]
C30 0.22U_0402_10V6K
should be shorted near balls C15 L28 PCIE_CTX_GRX_C_P4 C18 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P4
D15 eDP_AUX PEG_TX[4] K30 PCIE_CTX_GRX_C_P5 C22 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P5
and routed with typical eDP_AUX# PEG_TX[5]
impedance <25 mohms K27 PCIE_CTX_GRX_C_P6 C28 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P6
eDP

PEG_TX[6] J29 PCIE_CTX_GRX_C_P7 C32 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P7

C17 PEG_TX[7] J27 PCIE_CTX_GRX_C_P8 SLI@ C19 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P8
F16 eDP_TX[0] PEG_TX[8] H28 PCIE_CTX_GRX_C_P9 SLI@ C24 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P9
C16 eDP_TX[1] PEG_TX[9] G28 PCIE_CTX_GRX_C_P10 SLI@ C29 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P10
G15 eDP_TX[2] PEG_TX[10] E28 PCIE_CTX_GRX_C_P11 SLI@ C17 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P11
eDP_TX[3] PEG_TX[11] F28 PCIE_CTX_GRX_C_P12 SLI@ C21 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P12
C18 PEG_TX[12] D27 PCIE_CTX_GRX_C_P13 SLI@ C27 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P13
E16 eDP_TX#[0] PEG_TX[13] E26 PCIE_CTX_GRX_C_P14 SLI@ C26 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P14
D16 eDP_TX#[1] PEG_TX[14] D25 PCIE_CTX_GRX_C_P15 SLI@ C31 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P15
F15 eDP_TX#[2] PEG_TX[15]
eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PROCESSOR(1/7) DMI,FDI,PEG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 5 of 65
5 4 3 2 1
 5 4 3 2 1

JCPU1B ME@
D D

A28 CLK_CPU_DMI
H_SNB_IVB# C26 BCLK A27 CLK_CPU_DMI# CLK_CPU_DMI <15>

MISC

CLOCKS
<19> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>
H : Sandy Bridge
PROC_SEL AN34
SKTOCC# A16 R12 2 1 1K_0402_5% +1.05VS
L : IVY Bridge DPLL_REF_CLK A15 R13 2 1 1K_0402_5%
DPLL_REF_CLK#

T14 PAD H_CATERR# AL33

CATERR#

THERMAL
H_PECI AN33 R8 H_DRAMRST#
+1.05VS <45> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>

DDR3
MISC
1 R9 2 1 R15 2 AL32 AK1 2 1 140_0402_1%
H_PROCHOT# <45,53> H_PROCHOT# H_PROCHOT# H_PROCHOT#_R SM_RCOMP0 R16
PROCHOT# SM_RCOMP[0] A5 SM_RCOMP1 R17 2 1 25.5_0402_1%
62_0402_5% 56_0402_5% SM_RCOMP[1] A4 SM_RCOMP2 2 1 200_0402_1%
R18
SM_RCOMP[2]
H_THRMTRIP# AN32
<19> H_THRMTRIP# THERMTRIP#
DDR3 Compensation Signals

AP29 +1.05VS
PRDY# AP27
PREQ#
C AR26 XDP_TCK XDP_TMS R20 2 1 51_0402_5% C
TCK AR27 XDP_TMS XDP_TDI R21 2 1 51_0402_5%
R22

PWR MANAGEMENT
TMS

JTAG & BPM

H_PM_SYNC 1 2 H_PM_SYNC_R AM34 AP30 XDP_TRST# XDP_TDO R23 2 1 51_0402_5%
<16> H_PM_SYNC PM_SYNC TRST# @
R_short 0_0402_5% AR28 XDP_TDI XDP_TCK 2 1
R24 51_0402_5%
TDI AP26 XDP_TDO XDP_TRST# R25 2 1 51_0402_5%
1 R26 2 AP33 TDO
<19> H_CPUPWRGD H_CPUPWRGD H_CPUPWRGD_R
UNCOREPWRGOOD
R_short 0_0402_5%
2

1 AL35 PU/PD for JTAG signals

PM_SYS_PWRGD_BUF 1 R29 2 PM_DRAM_PWRGD_R V8 DBR#
C550 R27 SM_DRAMPWROK
100P_0402_50V8J 130_0402_5% AT28
10K_0402_5%
2 BPM#[0] AR29
1

BPM#[1] AR30
9/23 ESD Request BPM#[2]
BUF_CPU_RST# AR33 AT30
RESET# BPM#[3] AP32
BPM#[4] AR31
BPM#[5] AT31
BPM#[6] AR32
BPM#[7]

TYCO_2013620-2_IVY BRIDGE

B B

Buffered Reset to CPU

+1.05VS +3VS
+3VS +3VALW +1.5V_CPU_VDDQ
2

1
1 1
R338 C33 R30 R32 C34
10K_0402_5% 0.1U_0402_16V4Z 200_0402_5% 75_0402_5% 0.1U_0402_16V4Z
2 2
1

2
5

5
1 2 0_0402_5% 1
1.05V 1
R65 @ This is NC pin
P

P
<16> SYS_PWROK B R34 NC
4 PM_SYS_PWRGD_BUF BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 3V
2 O Y 2 PLT_RST#
<16> PM_DRAM_PWRGD A 43_0402_1% A PLT_RST# <18,23,32,37,38,44,45>
G

G
1
U1
74AHC1G09GW_TSSOP5 U2
3

3
R35 @ SN74LVC1G07DCKR_SC70-5
0_0402_5%
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PROCESSOR(2/7) PM,XDP,CLK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 6 of 65
5 4 3 2 1
 5 4 3 2 1

JCPU1C ME@ JCPU1D ME@

AB6 AE2
<12> DDR_A_D[0..63] SA_CK[0] AA6 M_CLK_DDR0 <12> <13> DDR_B_D[0..63] SB_CK[0] AD2 M_CLK_DDR2 <13>
DDR_A_D0 C5 SA_CLK#[0] V9 M_CLK_DDR#0 <12> DDR_B_D0 C9 SB_CLK#[0] R9 M_CLK_DDR#2 <13>
DDR_A_D1 D5 SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> DDR_B_D1 A7 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
D DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D4 A9 SB_DQ[3] AE1 D
DDR_A_D5 C6 SA_DQ[4] SA_CK[1] AB5 M_CLK_DDR1 <12> DDR_B_D5 A8 SB_DQ[4] SB_CK[1] AD1 M_CLK_DDR3 <13>
DDR_A_D6 C2 SA_DQ[5] SA_CLK#[1] V10 M_CLK_DDR#1 <12> DDR_B_D6 D9 SB_DQ[5] SB_CLK#[1] R10 M_CLK_DDR#3 <13>
DDR_A_D7 C3 SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> DDR_B_D7 D8 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13>
DDR_A_D8 F10 SA_DQ[7] DDR_B_D8 G4 SB_DQ[7]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D11 G9 SA_DQ[10] SA_CK[2] AA4 DDR_B_D11 G1 SB_DQ[10] SB_CK[2] AA2
DDR_A_D12 F9 SA_DQ[11] SA_CLK#[2] W9 DDR_B_D12 G5 SB_DQ[11] SB_CLK#[2] T9
DDR_A_D13 F7 SA_DQ[12] SA_CKE[2] DDR_B_D13 F5 SB_DQ[12] SB_CKE[2]
DDR_A_D14 G8 SA_DQ[13] DDR_B_D14 F2 SB_DQ[13]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D17 K5 SA_DQ[16] SA_CK[3] AA3 DDR_B_D17 J8 SB_DQ[16] SB_CK[3] AB1
DDR_A_D18 K1 SA_DQ[17] SA_CLK#[3] W10 DDR_B_D18 K10 SB_DQ[17] SB_CLK#[3] T10
DDR_A_D19 J1 SA_DQ[18] SA_CKE[3] DDR_B_D19 K9 SB_DQ[18] SB_CKE[3]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D22 K8 SB_DQ[21] AD3
DDR_A_D23 K2 SA_DQ[22] SA_CS#[0] AL3 DDR_CS0_DIMMA# <12> DDR_B_D23 K7 SB_DQ[22] SB_CS#[0] AE3 DDR_CS2_DIMMB# <13>
M8 SA_DQ[23] SA_CS#[1] AG1 DDR_CS1_DIMMA# <12> M5 SB_DQ[23] SB_CS#[1] AD6 DDR_CS3_DIMMB# <13>
DDR_A_D24 DDR_B_D24
DDR_A_D25 N10 SA_DQ[24] SA_CS#[2] AH1 DDR_B_D25 N4 SB_DQ[24] SB_CS#[2] AE6
DDR_A_D26 N8 SA_DQ[25] SA_CS#[3] DDR_B_D26 N2 SB_DQ[25] SB_CS#[3]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N1 SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D29 M9 SA_DQ[28] AH3 DDR_B_D29 N5 SB_DQ[28] AE4
DDR_A_D30 N9 SA_DQ[29] SA_ODT[0] AG3 M_ODT0 <12> DDR_B_D30 M2 SB_DQ[29] SB_ODT[0] AD4 M_ODT2 <13>
SA_DQ[30] SA_ODT[1] M_ODT1 <12> SB_DQ[30] M_ODT3 <13>

DDR SYSTEM MEMORY B

DDR_A_D31 M7 AG2 DDR_B_D31 M1 SB_ODT[1] AD5

DDR SYSTEM MEMORY A

DDR_A_D32 AG6 SA_DQ[31] SA_ODT[2] AH2 DDR_B_D32 AM5 SB_DQ[31] SB_ODT[2] AE5
DDR_A_D33 AG5 SA_DQ[32] SA_ODT[3] DDR_B_D33 AM6 SB_DQ[32] SB_ODT[3]
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D34 AR3 SB_DQ[33]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
C DDR_A_D36 AH5 SA_DQ[35] DDR_B_D36 AN3 SB_DQ[35] C
DDR_A_D37 AH6 SA_DQ[36] C4 DDR_A_DQS#0 DDR_A_DQS#[0..7] <12> DDR_B_D37 AN2 SB_DQ[36] D7 DDR_B_DQS#0 DDR_B_DQS#[0..7] <13>
DDR_A_D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[37] SB_DQS#[0] F3 DDR_B_DQS#1
DDR_A_D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR_A_DQS#2 DDR_B_D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_B_DQS#2
DDR_A_D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_B_DQS#3
DDR_A_D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR_A_D45 AH9 SA_DQ[44] SA_DQS#[7] DDR_B_D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D46 AR6 SB_DQ[45]
DDR_A_D47 AL8 SA_DQ[46] DDR_B_D47 AR5 SB_DQ[46]
DDR_A_D48 AP11 SA_DQ[47] DDR_B_D48 AR9 SB_DQ[47]
AN11 SA_DQ[48] D4 DDR_A_DQS[0..7] <12> AJ11 SB_DQ[48] C7 DDR_B_DQS[0..7] <13>
DDR_A_D49 DDR_A_DQS0 DDR_B_D49 DDR_B_DQS0
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D50 AT8 SB_DQ[49] SB_DQS[0] G3 DDR_B_DQS1
DDR_A_D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR_A_DQS2 DDR_B_D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_B_DQS2
DDR_A_D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR_A_DQS3 DDR_B_D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_B_DQS3
DDR_A_D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR_A_DQS4 DDR_B_D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_B_DQS4
DDR_A_D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR_A_DQS5 DDR_B_D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_B_DQS5
DDR_A_D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR_A_DQS6 DDR_B_D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_B_DQS6
DDR_A_D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR_A_DQS7 DDR_B_D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_B_DQS7
DDR_A_D57 AH14 SA_DQ[56] SA_DQS[7] DDR_B_D57 AN14 SB_DQ[56] SB_DQS[7]
DDR_A_D58 AL15 SA_DQ[57] DDR_B_D58 AR14 SB_DQ[57]
DDR_A_D59 AK15 SA_DQ[58] DDR_B_D59 AT14 SB_DQ[58]
DDR_A_D60 AL14 SA_DQ[59] DDR_B_D60 AT12 SB_DQ[59]
DDR_A_D61 AK14 SA_DQ[60] AD10 DDR_A_MA0 DDR_A_MA[0..15] <12> DDR_B_D61 AN15 SB_DQ[60] AA8 DDR_B_MA0 DDR_B_MA[0..15] <13>
DDR_A_D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR_A_MA1 DDR_B_D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_B_MA1
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] W7 DDR_A_MA3 SB_DQ[63] SB_MA[2] T6 DDR_B_MA3
SA_MA[3] V3 DDR_A_MA4 SB_MA[3] T2 DDR_B_MA4
SA_MA[4] V2 DDR_A_MA5 SB_MA[4] T4 DDR_B_MA5
SA_MA[5] W3 DDR_A_MA6 SB_MA[5] T3 DDR_B_MA6
B AE10 SA_MA[6] W6 DDR_A_MA7 AA9 SB_MA[6] R2 DDR_B_MA7 B
<12> DDR_A_BS0 AF10 SA_BS[0] SA_MA[7] V1 DDR_A_MA8 <13> DDR_B_BS0 AA7 SB_BS[0] SB_MA[7] T5 DDR_B_MA8
<12> DDR_A_BS1 V6 SA_BS[1] SA_MA[8] W5 DDR_A_MA9 <13> DDR_B_BS1 R6 SB_BS[1] SB_MA[8] R3 DDR_B_MA9
<12> DDR_A_BS2 SA_BS[2] SA_MA[9] AD8 DDR_A_MA10 <13> DDR_B_BS2 SB_BS[2] SB_MA[9] AB7 DDR_B_MA10
SA_MA[10] V4 DDR_A_MA11 SB_MA[10] R1 DDR_B_MA11
SA_MA[11] W4 DDR_A_MA12 SB_MA[11] T1 DDR_B_MA12
AE8 SA_MA[12] AF8 DDR_A_MA13 AA10 SB_MA[12] AB10 DDR_B_MA13
<12> DDR_A_CAS# AD9 SA_CAS# SA_MA[13] V5 DDR_A_MA14 <13> DDR_B_CAS# AB8 SB_CAS# SB_MA[13] R5 DDR_B_MA14
<12> DDR_A_RAS# AF9 SA_RAS# SA_MA[14] V7 DDR_A_MA15 <13> DDR_B_RAS# AB9 SB_RAS# SB_MA[14] R4 DDR_B_MA15
<12> DDR_A_WE# SA_WE# SA_MA[15] <13> DDR_B_WE# SB_WE# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

+1.5V
1

R37
1K_0402_5%
2

3 1 1 R38 2
S

H_DRAMRST# DDR3_DRAMRST#_R
<6> H_DRAMRST# DDR3_DRAMRST# <12,13>
1K_0402_5%
2

Q2
R39 BSS138_NL_SOT23-3
G
2

4.99K_0402_1%
A A
1

1 @ 2 DRAMRST_CNTRL
<15> DRAMRST_CNTRL_PCH
R40 0_0402_5% 1
<10> DRAMRST_CNTRL
C35 Title
1 DS3@2 0.047U_0402_16V4Z
Security Classification LC Future Center Secret Data
<45> DRAMRST_CNTRL_EC 2
R64 0_0402_5%
Reserve for Deep S3
Issued Date 2011/11/01 Deciphered Date 2012/12/31 PROCESSOR(3/7) DDRIII
Module design used 0.047u THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 7 of 65
5 4 3 2 1
 5 4 3 2 1

D D

JCPU1E ME@
CFG Straps for Processor
AH27
AK28 VCC_DIE_SENSE AH26
AK29 CFG[0] VSS
CFG2 AL26 CFG[1] CFG2
AL27 CFG[2]
CFG[3] PEG Static Lane Reversal - CFG2 is for the 16x
AK26 L7
CFG[4] RSVD28

1
CFG5 AL29 AG7
CFG[5] RSVD29
CFG6
CFG7
AL30
AM31
AM32
CFG[6]
CFG[7]
RSVD30
RSVD31
AE7
AK2 @
R41
1K_0402_1% CFG2 * 1: Normal Operation; Lane #
socket pin map definition
definition matches

AM30 CFG[8] W8

CFG

2
AM28 CFG[9] RSVD32
CFG[10] 0:Lane Reversed
AM26
AN28 CFG[11] AT26
AN31 CFG[12] RSVD33 AM33
AN26 CFG[13] RSVD34 AJ27
AM27 CFG[14] RSVD35
AK31 CFG[15]
AN29 CFG[16]
CFG[17]
Display Port Presence Strap
T8
RSVD37 J16 1 : Disabled; No Physical Display Port
C T56
T57
PAD
PAD
AJ31
AH31
AJ33
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
RSVD38
RSVD39
RSVD40
H16
G16
CFG4 * attached to Embedded Display Port C

T58 PAD AH33 VCC_VAL_SENSE

T59 PAD VSS_VAL_SENSE 0 : Enabled; An external Display Port device is
11/24 --> Intel recommend
connected to the Embedded Display Port
to reserve test point AJ26 AR35
RSVD5 RSVD_NCTF1 AT34
RSVD_NCTF2
RESERVED

AT33
RSVD_NCTF3 AP35
RSVD_NCTF4 AR34
RSVD_NCTF5
CFG6
F25 PCIE Port Bifurcation Straps
F24 RSVD8 CFG5
F23 RSVD9
RSVD10

1
D24 B34 11: (Default) x16 - Device 1 functions 1 and 2 disabled
G25 RSVD11 RSVD_NCTF6 A33
RSVD12 RSVD_NCTF7 R43 R44
G24
E23
D23
RSVD13
RSVD14
RSVD_NCTF8
RSVD_NCTF9
A34
B35
C35
1K_0402_1%
@
1K_0402_1% CFG[6:5]
*10: disabled
x8, x8 - Device 1 function 1 enabled ; function 2

2
C30 RSVD15 RSVD_NCTF10
RSVD16 01: Reserved - (Device 1 function 1 disabled ; function
A31
B30 RSVD17 2 enabled)
B29 RSVD18
RSVD19 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
D30 AJ32
B31 RSVD20 RSVD51 AK32
A30 RSVD21 RSVD52
C29 RSVD22
RSVD23
AN35
J20 BCLK_ITP AM35 CFG7
B18 RSVD24 BCLK_ITP#
RSVD25 PEG DEFER TRAINING

1
B B

R45
@
1K_0402_1% 1: (Default) PEG Train immediately following xxRESETB
J15 AT2 CFG7
RSVD27 RSVD_NCTF11 AT1 de assertion

2
RSVD_NCTF12 AR1
RSVD_NCTF13
0: PEG Wait for BIOS for training

B1
KEY

TYCO_2013620-2_IVY BRIDGE

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PROCESSOR(4/7) RSVD,CFG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 8 of 65
5 4 3 2 1
 5 4 3 2 1

JCPU1F ME@ POWER

+VCC_CORE +1.05VS
QC=94A
D DC=53A AG35 D
AG34 VCC1 AH13 8.5A
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
AG31 VCC4 VCCIO3 AC10
AG30 VCC5 VCCIO4 Y10
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
AF34 VCC11 VCCIO10 J12
AF33 VCC12 VCCIO11 J11
AF32 VCC13 VCCIO12 H14
AF31 VCC14 VCCIO13 H12
AF30 VCC15 VCCIO14 H11
AF29 VCC16 VCCIO15 G14
AF28 VCC17 VCCIO16 G13
AF27 VCC18 VCCIO17 G12

PEG AND DDR

AF26 VCC19 VCCIO18 F14
AD35 VCC20 VCCIO19 F13
AD34 VCC21 VCCIO20 F12
AD33 VCC22 VCCIO21 F11
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
AD27 VCC28 VCCIO26 D13
AD26 VCC29 VCCIO27 D12
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
C AC33 VCC32 VCCIO30 C13 C
AC32 VCC33 VCCIO31 C12
AC31 VCC34 VCCIO32 C11
AC30 VCC35 VCCIO33 B14
AC29 VCC36 VCCIO34 B12
AC28 VCC37 VCCIO35 A14
AC27 VCC38 VCCIO36 A13
AC26 VCC39 VCCIO37 A12
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23
AA32 VCC43 VCCIO40
AA31 VCC44
AA30 VCC45
AA29 VCC46 +1.05VS
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
CORE SUPPLY

VCC51

1
Y34 1
Y33 VCC52
Y32 VCC53 C36 @ R46
Y31 VCC54 0.1U_0402_10V7K 75_0402_5%
Y30 VCC55 2

2
Y29 VCC56
Y28 VCC57
VCC58
Reserve 0.1u to avoid noise Place the PU resistor close to CPU
Y27
Y26 VCC59
V35 VCC60
V34 VCC61 AJ29 H_CPU_SVIDALRT# R47 1 2 43_0402_5%
SVID

V33 VCC62 VIDALERT# AJ30 H_CPU_SVIDCLK 1 2 R_short 0_0402_5% VR_SVID_ALRT# <59>

R48
V32 VCC63 VIDSCLK AJ28 1 2 R_short 0_0402_5% VR_SVID_CLK <59>
H_CPU_SVIDDAT R49
B V31 VCC64 VIDSOUT VR_SVID_DAT <59> B
V30 VCC65 R50 2 1 130_0402_5%
VCC66 +1.05VS
V29
V28 VCC67
VCC68
Place the PU resistor close to CPU
V27
V26 VCC69
U35 VCC70
U34 VCC71
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77
U27 VCC78
U26 VCC79 +VCC_CORE
R35 VCC80
R34 VCC81
R33 VCC82
VCC83

1
R32
R31 VCC84 R51
R30 VCC85
VCC86 100_0402_1%
R29 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
R28 VCC87

2
SENSE LINES

R27 VCC88 AJ35 VCCSENSE_R R52 1 2 R_short 0_0402_5% VCCSENSE

R26 VCC89 VCC_SENSE AJ34 VSSSENSE_R 1 2 R_short 0_0402_5% VSSSENSE VCCSENSE <59>
R53
P35 VCC90 VSS_SENSE VSSSENSE <59>
P34 VCC91 +1.05VS
VCC92

1
P33 R1294 2 1 10_0402_1%
P32 VCC93 B10 VCCIO_SENSE R54
P31 VCC94 VCCIO_SENSE A10 VSSIO_SENSE 2 1 10_0402_1% VCCIO_SENSE <57>
R1297 100_0402_1%
P30 VCC95 VSS_SENSE_VCCIO
VCC96
VSS_SENCE 100ohm +-1% pull-down to GND near processor
A P29 A

2
P28 VCC97
P27 VCC98
P26 VCC99
VCC100

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PROCESSOR(5/7) PWR,BYPASS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
TYCO_2013620-2_IVY BRIDGE Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 9 of 65
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V_CPU_VDDQ
+1.5V_CPU_VDDQ C287 1 2 0.1U_0402_10V6K

C286 1 2 0.1U_0402_10V6K DRAMRST_CNTRL

<7> DRAMRST_CNTRL

2
1 2 0.1U_0402_10V6K Q8 BSS138_SOT23

G
C96
For Deep S3
C95 1 2 0.1U_0402_10V6K 1 3

S
+3VALW +VSB U3
8 1
D 7 2 R74 1 @ 2 0_0402_5% +V_DDR_REFA_R D
R56 need to check on SDV +VREF_DQ_DIMMA

1
6 3 R75 1 @ 2 0_0402_5% +V_DDR_REFB_R
+VREF_DQ_DIMMB
5

1
R1537 @ R56

1
100K_0402_5% 100K_0402_5% AO4304L_SO8

4
AO4304L @ R1487 1 3

S
2

2
Vgs=10V,Id=18A, 470_0603_5% R139 @ @ R132
RUN_ON_CPU1.5VS3 1 R1349 2
Rds<6.7m ohm Q7 BSS138_SOT23 1K_0402_1% 1K_0402_1%

2
P/N: SB00000RV00

G
470K_0402_5%

2
DRAMRST_CNTRL

3
D D
R1538 2

1
1 2 1 5 SUSP
<37,51,55,57> SUSP G G
R_short 0_0402_5%

1
D R57 C97
2 S Q4A 470K_0402_5% 0.01U 50V K X7R 0603 S

4
<45> CPU1.5V_S3_GATE @ 2
G
2N7002KDWH_SOT363-6
Q4B 6/8: Add M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

2
Q156 2N7002KDWH_SOT363-6
S

3
2N7002_SOT23

+VCC_GFXCORE_AXG
VCC_AXG_SENSE R66 2 OPT@ 1 100_0402_1%

+VCC_GFXCORE_AXG JCPU1G
POWER VSS_AXG_SENSE R90 2 OPT@ 1 100_0402_1%

C 46A AT24 AK35 VCC_AXG_SENSE_R R1488 1 OPT@ 2 0_0402_5% C

SENSE
LINES
AT23 VAXG1 VAXG_SENSE AK34 VSS_AXG_SENSE_R 1 2 0_0402_5% VCC_AXG_SENSE <59>
R1489
VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <59>
2

AT21 OPT@
AT20 VAXG3 +1.5V_CPU_VDDQ
RV174 AT18 VAXG4
SLI@ VAXG5

1
0_0402_5% AT17
AR24 VAXG6 R77
1

AR23 VAXG7 1K_0402_1%

AR21 VAXG8
AR20 VAXG9

2
AR18 VAXG10 AL1 +V_SM_VREF_CNT
AR17 VAXG11 SM_VREF
VAXG12 1

1
AP24

VREF
AP23 VAXG13 C114 R88
AP21 VAXG14 0.1U_0402_16V4Z 1K_0402_1%
AP20 VAXG15 B4 +V_DDR_REFA_R 2
AP18 VAXG16 SA_DIMM_VREFDQ D1 +V_DDR_REFB_R

2
AP17 VAXG17 SB_DIMM_VREFDQ
VAXG18 Place the PU/PD resistor close to CPU within 2 inch
AN24
AN23 VAXG19 (Reserve power side)
AN21 VAXG20
AN20 VAXG21
AN18 VAXG22 +1.5V_CPU_VDDQ
VAXG23 5A
DDR3 -1.5V RAILS

AN17
AM24 VAXG24 AF7
GRAPHICS

VAXG25 VDDQ1

330U_D2_2.5VY_R9M
AM23 AF4
VAXG26 VDDQ2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
AM21 AF1 1
VAXG27 VDDQ3

C117

C118

C119

C120

C121

C122

C123
AM20 AC7 1 1 1 1 1 1
AM18 VAXG28 VDDQ4 AC4 @ +
AM17 VAXG29 VDDQ5 AC1
AL24 VAXG30 VDDQ6 Y7
AL23 VAXG31 VDDQ7 Y4 2 2 2 2 2 2 2
B AL21 VAXG32 VDDQ8 Y1 B
AL20 VAXG33 VDDQ9 U7
AL18 VAXG34 VDDQ10 U4
AL17 VAXG35 VDDQ11 U1
AK24 VAXG36 VDDQ12 P7
AK23 VAXG37 VDDQ13 P4
AK21 VAXG38 VDDQ14 P1
AK20 VAXG39 VDDQ15
AK18 VAXG40
AK17 VAXG41
AJ24 VAXG42
AJ23 VAXG43
AJ21 VAXG44
AJ20 VAXG45 +VCCSA
AJ18 VAXG46 6A
AJ17 VAXG47 M27 +VCCSA
VAXG48 VCCSA1

330U_D2_2.5VY_R9M
AH24 M26
SA RAIL

VAXG49 VCCSA2
10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C128
AH23 L26 1
VAXG50 VCCSA3
C124

C125

C126

C127
AH21 J26 1 1 1 1
AH20 VAXG51 VCCSA4 J25 @ @ +
AH18 VAXG52 VCCSA5 J24
AH17 VAXG53 VCCSA6 H26
VAXG54 VCCSA7 H25 2 2 2 2 2
VCCSA8
1.8V RAIL

H23 +VCCSA_SENSE R68 1 @ 2 0_0402_5%

+1.8VS VCCSA_SENSE +VCCSA_SENSE <56>

1 R67 2 B6
10U_0805_6.3V6M 1U_0402_6.3V6K +1.8VS_VCCPLL
A A6 VCCPLL1 C22 A
1
MISC

R_short 0_0805_5% A2 VCCPLL2 VCCSA_VID[0] C24 H_VCCSA_VID0 <56>

1 1 1 VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <56>
C279 + @ C130 C131 C132
6/3 modify for VCCSA 4-Level voltage
2 2 2 2 A19
VCCIO_SEL
330U_B2_2.5VM_R15M 1U_0402_6.3V6K Title
TYCO_2013620-2_IVY BRIDGE Security Classification LC Future Center Secret Data
11/24 change 22U X2 to 330U B2 size Issued Date 2011/11/01 Deciphered Date 2012/12/31 PROCESSOR(6/7) PWR
ME@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 10 of 65
5 4 3 2 1
 5 4 3 2 1

JCPU1H JCPU1I
D AT35 AJ22 D
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30
AT22 VSS5 VSS85 AJ7 T32 VSS163 VSS236 E27
AT19 VSS6 VSS86 AJ4 T31 VSS164 VSS237 E24
AT16 VSS7 VSS87 AJ3 T30 VSS165 VSS238 E21
AT13 VSS8 VSS88 AJ2 T29 VSS166 VSS239 E18
AT10 VSS9 VSS89 AJ1 T28 VSS167 VSS240 E15
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13
AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10
AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8
AR22 VSS14 VSS94 AH29 P6 VSS172 VSS245 E7
AR19 VSS15 VSS95 AH28 P5 VSS173 VSS246 E6
AR16 VSS16 VSS96 AH25 P3 VSS174 VSS247 E5
AR13 VSS17 VSS98 AH22 P2 VSS175 VSS248 E4
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3
AR7 VSS19 VSS100 AH16 N34 VSS177 VSS250 E2
AR4 VSS20 VSS101 AH7 N33 VSS178 VSS251 E1
AR2 VSS21 VSS102 AH4 N32 VSS179 VSS252 D35
AP34 VSS22 VSS103 AG9 N31 VSS180 VSS253 D32
AP31 VSS23 VSS104 AG8 N30 VSS181 VSS254 D29
AP28 VSS24 VSS105 AG4 N29 VSS182 VSS255 D26
AP25 VSS25 VSS106 AF6 N28 VSS183 VSS256 D20
AP22 VSS26 VSS107 AF5 N27 VSS184 VSS257 D17
AP19 VSS27 VSS108 AF3 N26 VSS185 VSS258 C34
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28
AP10 VSS30 VSS111 AE34 L30 VSS188 VSS261 C27
AP7 VSS31 VSS112 AE33 L27 VSS189 VSS262 C25
C AP4 VSS32 VSS113 AE32 L9 VSS190 VSS263 C23 C
AP1 VSS33 VSS114 AE31 L8 VSS191 VSS264 C10
AN30 VSS34 VSS115 AE30 L6 VSS192 VSS265 C1
AN27 VSS35 VSS116 AE29 L5 VSS193 VSS266 B22
AN25 VSS36 VSS117 AE28 L4 VSS194 VSS267 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE9 L1 B13
AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11
AN10 VSS41 VSS122 AC9 K32 VSS199 VSS272 B9
AN7 VSS42 VSS123 AC8 K29 VSS200 VSS273 B8
AN4 VSS43 VSS124 AC6 K26 VSS201 VSS274 B7
AM29 VSS44 VSS125 AC5 J34 VSS202 VSS275 B5
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3
AM22 VSS46 VSS127 AC2 H33 VSS204 VSS277 B2
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35
AM16 VSS48 VSS129 AB34 H27 VSS206 VSS279 A32
AM13 VSS49 VSS130 AB33 H24 VSS207 VSS280 A29
AM10 VSS50 VSS131 AB32 H21 VSS208 VSS281 A26
AM7 VSS51 VSS132 AB31 H18 VSS209 VSS282 A23
AM4 VSS52 VSS133 AB30 H15 VSS210 VSS283 A20
AM3 VSS53 VSS134 AB29 H13 VSS211 VSS284 A3
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285
AM1 VSS55 VSS136 AB27 H9 VSS213
AL34 VSS56 VSS137 AB26 H8 VSS214
AL31 VSS57 VSS138 Y9 H7 VSS215
AL28 VSS58 VSS139 Y8 H6 VSS216
AL25 VSS59 VSS140 Y6 H5 VSS217
AL22 VSS60 VSS141 Y5 H4 VSS218
AL19 VSS61 VSS142 Y3 H3 VSS219
AL16 VSS62 VSS143 Y2 H2 VSS220
AL13 VSS63 VSS144 W35 H1 VSS221
B AL10 VSS64 VSS145 W34 G35 VSS222 B
AL7 VSS65 VSS146 W33 G32 VSS223
AL4 VSS66 VSS147 W32 G29 VSS224
AL2 VSS67 VSS148 W31 G26 VSS225
AK33 VSS68 VSS149 W30 G23 VSS226
AK30 VSS69 VSS150 W29 G20 VSS227
AK27 VSS70 VSS151 W28 G17 VSS228
AK25 VSS71 VSS152 W27 G11 VSS229
AK22 VSS72 VSS153 W26 F34 VSS230
AK19 VSS73 VSS154 U9 F31 VSS231
AK16 VSS74 VSS155 U8 F29 VSS232
AK13 VSS75 VSS156 U6 VSS233
AK10 VSS76 VSS157 U5
AK7 VSS77 VSS158 U3
AK4 VSS78 VSS159 U2
AJ25 VSS79 VSS160
VSS80

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

ME@ ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PROCESSOR(7/7) VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 11 of 65
5 4 3 2 1
 5 4 3 2 1

DDR3 SO-DIMM A
+1.5V +1.5V +1.5V

1
R78
1K_0402_1% +VREF_DQ_DIMMA
3A@1.5V
For RF request
JDIMM1 ME@

2
+VREF_DQ_DIMMA 1 2
VREF_DQ VSS1 DDR_A_D[0..63] <7>
3 4 DDR_A_D4
VSS2 DQ4

0.047U_0402_16V4Z

0.047U_0402_16V4Z

0.047U_0402_16V4Z
DDR_A_D0 5 6 DDR_A_D5
DDR_A_DQS[0..7] <7>

0.1U_0402_10V6K
2.2U_0603_6.3V6K
D DDR_A_D1 7 DQ0 DQ5 8 D
1 1 DQ1 VSS3 1 1 1
R79 C141 C140 9 10 DDR_A_DQS#0 C51 C52 C53
VSS4 DQS#0 DDR_A_DQS#[0..7] <7>
1K_0402_1% 11 12 DDR_A_DQS0 @ @ @
13 DM0 DQS0 14
DDR_A_MA[0..15] <7>
2

2 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6 2 2 2

DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
19 DQ3 DQ7 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <13,7>
31 32
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
C 71 DQ27 DQ31 72 C
VSS25 VSS26

<7> DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA

CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4 Layout Note:
OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2 Place near DIMM (10uF_0603_6.3V)*8
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100 (0.1uF_402_10V)*4
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<7> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <7>
M_CLK_DDR#0 103 104 M_CLK_DDR#1
<7> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <7>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <7>
<7> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# +1.5V +1.5V
BA0 RAS# DDR_A_RAS# <7>
111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA#
<7> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>

1
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <7>
117 118

10U_0603_6.3V6M

10U_0603_6.3V6M
1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
10U_0603_6.3V6M

10U_0603_6.3V6M
VDD15 VDD16 R80
DDR_A_MA13 119 120 M_ODT1
A13 ODT1 M_ODT1 <7> 1K_0402_1% C151 1 C142 1 C143 1 C152 1 C144 1 C145 1 C153 1 C146 1 C154 1 C155 1 C147 1 C156 1 + C148
<7> DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
123 S1# NC2 124 220U_6.3V_M
@ @

2
125 VDD17 VDD18 126 +VREF_CA
127 NCTEST VREF_CA 128 2 2 2 2 2 2 2 2 2 2 2 2 2
VSS27 VSS28
0.1U_0402_10V6K

2.2U_0603_6.3V6K
B DDR_A_D32 129 130 DDR_A_D36 B
DQ32 DQ36

1
DDR_A_D33 131 132 DDR_A_D37 1 1
133 DQ33 DQ37 134 C149 C150
DDR_A_DQS#4 135 VSS29 VSS30 136 R81
DDR_A_DQS4 137 DQS#4 DM4 138 1K_0402_1%
139 DQS4 VSS31 140 DDR_A_D38 2 2

2
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
Layout Note: Layout Note:
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46 Place near DIMM Place near DIMM
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
DDR_A_DQS#6 169 VSS41 VSS42 170 +0.75VS
DQS#6 DM6 DDR_A_DM[0:7] connect to GND
DDR_A_DQS6 171 172
173 DQS6 VSS43 174 DDR_A_D54
DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178
DQ51 VSS45

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
179 180 DDR_A_D60
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
DQ56 DQ61 1 1 1 1
DDR_A_D57 183 184 C288 C158 C159 C160
185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190 2 2 2 2
DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D62
A DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 A
195 DQ59 DQ63 196
R82 VSS51 VSS52
1 2 197 198
10K_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 <13,15,37,46>
201 202 SMB_CLK_S3
SA1 SCL SMB_CLK_S3 <13,15,37,46>
1

1 1 203 204
VTT1 VTT2 +0.75VS
C290 C162 R83 205 206 0.65A@0.75V
G1 G2 Security Classification LC Future Center Secret Data Title
2.2U_0603_6.3V6K 0.1U_0402_10V6K 10K_0402_5%
2 2 LCN_DAN06-K4806-0103
Issued Date 2011/11/01 Deciphered Date 2012/12/31 DDRIII-SODIMM SLOT1
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 12 of 65
5 4 3 2 1
 5 4 3 2 1

DDR3 SO-DIMM B
+1.5V
+1.5V +1.5V

1
R84
1K_0402_1% +VREF_DQ_DIMMB
3A@1.5V
For RF request
JDIMM2 ME@
DDR_B_D[0..63] <7>

2
+VREF_DQ_DIMMB 1 2
3 VREF_DQ VSS1 4 DDR_B_D4
VSS2 DQ4 DDR_B_DQS[0..7] <7>

0.047U_0402_16V4Z

0.047U_0402_16V4Z

0.047U_0402_16V4Z
DDR_B_D0 5 6 DDR_B_D5

0.1U_0402_10V6K
DQ0 DQ5

2.2U_0603_6.3V6K
1 1 DDR_B_D1 7 8 1 1 1
DQ1 VSS3 DDR_B_DQS#[0..7] <7>
R85 C289 C157 9 10 DDR_B_DQS#0 C54 C55 C56
D 1K_0402_1% 11 VSS4 DQS#0 12 DDR_B_DQS0 @ @ @ D
DM0 DQS0 DDR_B_MA[0..15] <7>
13 14
2
2 2 DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6 2 2 2
DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
19 DQ3 DQ7 20
DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <12,7>
31 32
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14
DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
37 DQ11 DQ15 38
DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D26 67 VSS23 VSS24 68 DDR_B_D30
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
71 DQ27 DQ31 72
VSS25 VSS26
C C

<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<7> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94 Layout Note:
(10uF_0603_6.3V)*8
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0 Place near DIMM (0.1uF_402_10V)*4
99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<7> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <7>
<7> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 <7>
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <7>
<7> DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS# +1.5V
BA0 RAS# DDR_B_RAS# <7>
111 112 +1.5V
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB#
<7> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>

1
<7> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2
CAS# ODT0 M_ODT2 <7>
117 118
VDD15 VDD16 R86
DDR_B_MA13 119 120 M_ODT3

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
10U_0603_6.3V6M

10U_0603_6.3V6M
A13 ODT1 M_ODT3 <7> 1K_0402_1%
DDR_CS3_DIMMB# 121 122
<7> DDR_CS3_DIMMB# S1# NC2 C161 1 C282 1 C163 1 C164 1 C165 1 C166 1 C167 1 C168 1 C169 1 C170 1 C171 1 C172 1
123 124

2
125 VDD17 VDD18 126 +VREF_CB
NCTEST VREF_CA @ @
127 128
VSS27 VSS28 2 2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_10V6K

2.2U_0603_6.3V6K
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36

1
DDR_B_D33 131 132 DDR_B_D37 1 1
B 133 DQ33 DQ37 134 C280 C281 B
DDR_B_DQS#4 135 VSS29 VSS30 136 R87
DDR_B_DQS4 137 DQS#4 DM4 138 1K_0402_1%
139 DQS4 VSS31 140 DDR_B_D38 2 2

2
DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
157 VSS37 VSS38 158
Layout Note: Layout Note:
DDR_B_D42 DDR_B_D46
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47 Place near DIMM Place near DIMM
161 DQ43 DQ47 162
DDR_B_D48 163 VSS39 VSS40 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS41 VSS42 170
DDR_B_DQS6 171 DQS#6 DM6 172 +0.75VS
DQS6 VSS43 DDR_B_DM[0:7] connect to GND
173 174 DDR_B_D54
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60
VSS46 DQ60

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 183 DQ56 DQ61 184
DQ57 VSS47 1 1 1 1
185 186 DDR_B_DQS#7 C173 C174 C175 C176
187 VSS48 DQS#7 188 DDR_B_DQS7
189 DM7 DQS7 190
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62 2 2 2 2
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
195 DQ59 DQ63 196
A R95 VSS51 VSS52 A
1 2 197 198
10K_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
VDDSPD SDA SMB_DATA_S3 <12,15,37,46>
1 2 201 202 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 <12,15,37,46>
R97 10K_0402_5% 203 204 +0.75VS
VTT1 VTT2
1 1
205
G1 G2
206 0.65A@0.75V
C177 C178
2.2U_0603_6.3V6K 0.1U_0402_10V6K TYCO_2-2013287-1 Title
2 2 Security Classification LC Future Center Secret Data
Issued Date 2011/11/01 Deciphered Date 2012/12/31 DDRIII-SODIMM SLOT2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 13 of 65
5 4 3 2 1
 5 4 3 2 1

W=20mils W=20mils
+RTCBATT +RTCVCC CMOS U4A
EC and Mini card debug port
2 R99 1 +RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <37,45>

1
1 C183 JCMOS A38 LPC_AD1
1K_0402_5% FWH1 / LAD1 LPC_AD1 <37,45>

LPC
1U_0603_10V4Z @ SHORT PADS PCH_RTCX2 C20 B37 LPC_AD2
C179 RTCX2 FWH2 / LAD2 C37 LPC_AD3 LPC_AD2 <37,45>
1U_0603_10V4Z LPC_AD3 <37,45>

2
R103 1 2 20K_0402_5% 2 PCH_RTCRST# D20 FWH3 / LAD3
2 RTCRST# D36 LPC_FRAME#
FWH4 / LFRAME# LPC_FRAME# <37,45>
R100 1 2 20K_0402_5% PCH_SRTCRST# G22
SRTCRST# E36
1 LDRQ0#

1
D K22 K36 R104 2 1 10K_0402_5% D

RTC
C182 SM_INTRUDER# +3VS
1U_0603_10V4Z @ JME INTRUDER# LDRQ1# / GPIO23
SHORT PADS PCH_INTVRMEN C17 V5 SERIRQ
SERIRQ <45>

2
2 INTVRMEN SERIRQ
+RTCVCC
AM3 SATA_DTX_C_IRX_N0 SSD
SATA0RXN SATA_DTX_C_IRX_N0 <37>
R101 1 2 1M_0402_5% SM_INTRUDER# HDA_BIT_CLK N34 AM1 SATA_DTX_C_IRX_P0
SATA_DTX_C_IRX_P0 <37>
HDA_BCLK SATA0RXP AP7 SATA_ITX_C_DRX_N0 C184 2 1 0.01U_0402_16V7K SATA_ITX_DRX_N0

SATA 6G
SATA0TXN SATA_ITX_DRX_N0 <37>
R102 1 2 330K_0402_5% PCH_INTVRMEN HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 C185 2 1 0.01U_0402_16V7K SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 <37>
HDA_SYNC SATA0TXP
HDA_SPKR T10 AM10 SATA_DTX_C_IRX_N1 HDD
<42> HDA_SPKR SPKR SATA1RXN SATA_DTX_C_IRX_N1 <41>
AM8 SATA_DTX_C_IRX_P1
INTVRMEN
：：Integrated
SATA1RXP SATA_DTX_C_IRX_P1 <41>
HDA_RST# K34 AP11 SATA_ITX_C_DRX_N1 C273 2 1 0.01U_0402_16V7K SATA_ITX_DRX_N1
HDA_RST# SATA1TXN AP10 SATA_ITX_DRX_N1 <41>
H VRM enable (Default) SATA_ITX_C_DRX_P1 C272 2 1 0.01U_0402_16V7K SATA_ITX_DRX_P1
* L Integrated VRM disable SATA1TXP SATA_ITX_DRX_P1 <41>
HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 ODD
<42> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 <41>
(INTVRMEN should always be pull high.) AD5 SATA_DTX_C_IRX_P2
SATA2RXP SATA_DTX_C_IRX_P2 <41>
G34 AH5 SATA_ITX_C_DRX_N2 C186 2 1 0.01U_0402_16V7K SATA_ITX_DRX_N2_CONN
HDA_SDIN1 SATA2TXN AH4 SATA_ITX_DRX_N2_CONN <41>
SATA_ITX_C_DRX_P2 C187 2 1 0.01U_0402_16V7K SATA_ITX_DRX_P2_CONN
C34 SATA2TXP SATA_ITX_DRX_P2_CONN <41>
HDA_SDIN2 AB8

IHDA
A34 SATA3RXN AB10
HDA_SDIN3 SATA3RXP AF3
+3VS SATA3TXN AF1
ME_FLASH R109 1 2 R_short 0_0402_5%HDA_SDOUT A36 SATA3TXP
<45> ME_FLASH HDA_SDO
R105 1 2 1K_0402_5% HDA_SPKR Y7

SATA
@
SATA4RXN Y5
R107 1 2 1K_0402_1% PCH_GPIO33 C36 SATA4RXP AD3
HIGH= Enable ( No Reboot ) @
HDA_DOCK_EN# / GPIO33 SATA4TXN
LOW= Disable (Default) AD1
* +3V_PCH R317 2 @ 1 10K_0402_5% PCH_GPIO13 N32
HDA_DOCK_RST# / GPIO13
SATA4TXP
Y3
SATA5RXN Y1
C SATA5RXP AB3 C
R110 2 1 51_0402_5% PCH_JTAG_TCK J3 SATA5TXN AB1
JTAG_TCK SATA5TXP
+3V_PCH PCH_JTAG_TMS H7 Y11 +1.05VS_VCC_SATA
JTAG_TMS SATAICOMPO

JTAG
R106 2 @ 1 1K_0402_5% HDA_SDOUT PCH_JTAG_TDI K5 Y10 SATA_COMP R111 1 2 37.4_0402_1%
JTAG_TDI SATAICOMPI
Low = Disabled (Default) PCH_JTAG_TDO H1
* High = Enabled
JTAG_TDO
SATA3RCOMPO
AB12 +1.05VS_SATA3
[Flash Descriptor Security Overide]
AB13 SATA3_COMP R113 1 2 49.9_0402_1%
SATA3COMPI
SPI_CLK_PCH_0 R298 1 2 33_0402_5%
SPI_CLK_PCH_1 R299 1 2 33_0402_5% SPI_CLK_PCH T3 AH1 RBIAS_SATA3 R115 1 2 750_0402_1%
SPI_CLK SATA3RBIAS
+3V_PCH SPI_SB_CS0#_R R130 2 1 R_short 0_0402_5% SPI_SB_CS0# Y14
SPI_CS0#
HDD_LED# <47>
R108 2 1 1K_0402_5% HDA_SYNC SPI_CS1#_R R303 2 1 R_short 0_0402_5% SPI_CS1# T1
SPI_CS1#

SPI
P3 HDD_LED# R120 2 1 10K_0402_5%
SATALED# +3VS
This signal has a weak internal pull-down SPI_SI_R R133 1 2 33_0402_5%
SPI_SI_R1 R204 1 2 33_0402_5% SPI_SI V4 V14 PCH_GPIO21 R119 2 1 10K_0402_5%
+3VS
SPI_MOSI SATA0GP / GPIO21
On Die PLL VR Select is supplied by
1.5V when smapled high (Default) SPI_SO_L R131 2 1 33_0402_5% SPI_SO_R U3 P1 SATA_DET# R316 2 1 10K_0402_5%
+3VS
SPI_SO_L1 R294 2 1 33_0402_5% SPI_MISO SATA1GP / GPIO19
* 1.8V when sampled low
Needs to be pulled High for Chief River platfrom SATA_DET# <37>
PANTHER-POINT_FCBGA989

B PCH_RTCX1 B
For EMI
HDA AUDIO 1 R98 2 PCH_RTCX2
+5VS SPI_CLK_PCH
10M_0402_5%

1
<42> HDA_BITCLK_AUDIO R112 1 2 HDA_BIT_CLK Y1
2
G

33_0402_5% 1 2
R124 @
<42> HDA_SYNC_AUDIO R114 1 2 HDA_SYNC_R 3 1 HDA_SYNC 32.768KHZ_12.5PF_CM31532768DZFT 33_0402_5%
33_0402_5%
S

1 1

2
1

Q10
C180 C181
<42> HDA_RST_AUDIO# R116 1 2 HDA_RST# BSS138_NL_SOT23-3 C190 @
18P_0402_50V8J 18P_0402_50V8J
33_0402_5% R1353 22P_0402_50V8J
1M_0402_5% 2 2
<42> HDA_SDOUT_AUDIO R118 1 2 HDA_SDOUT
2

33_0402_5%

4MB P/N : SA00005P500 2MB P/N : SA00003FO10

+3VS +3VS
+3V_PCH +3V_PCH +3V_PCH

R127 1 2 3.3K_0402_5% SPI_WP# R292 1 2 3.3K_0402_5% SPI_WP#_1

1

R129 1 2 3.3K_0402_5% SPI_HOLD# R246 1 2 3.3K_0402_5% SPI_HOLD#_1

R121 R122 R123
@ 200_0402_5% @ 200_0402_5% @ 200_0402_5% +3VS +3VS
U5 U9
A SPI_SB_CS0#_R 1 8 SPI_CS1#_R 1 8 A
1 1
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI SPI_SO_L 2 CS# VCC 7 SPI_HOLD# SPI_SO_L1 2 CS# VCC 7 SPI_HOLD#_1
SPI_WP# 3 DO HOLD# 6 SPI_CLK_PCH_0 C191 SPI_WP#_1 3 DO(IO1) HOLD#(IO3) 6 SPI_CLK_PCH_1 C275
WP# CLK WP#(IO2) CLK
1

4 5 SPI_SI_R 0.1U_0402_16V4Z 4 5 SPI_SI_R1 0.1U_0402_16V4Z

R125 R128 GND DI 2 GND DI(IO0) 2
R126
@ 100_0402_1% @ 100_0402_1% @ 100_0402_1% W25Q32BVSSIG_SO8 W25Q16BVSSIG_SO8

Security Classification LC Future Center Secret Data Title

2

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (1/9) SATA,HDA,SPI, LPC, XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 14 of 65
5 4 3 2 1
 5 4 3 2 1

DIMM1, DIMM2, Mini CARD, TP

+3VS
U4B
1 R136 2 2.2K_0402_5% 2N7002KDWH 2 R137 1
+3V_PCH 2.2K_0402_5%
PCIE_PRX_DTX_N1 BG34 Vth= min 1V, max 2.5V

2
<38> PCIE_PRX_DTX_N1 PERN1 R135 ESD 2KV R138 1
PCIE_PRX_DTX_P1 BJ34 E12 PCH_GPIO11 1 2 2.2K_0402_5% 2 2.2K_0402_5%

G
<38> PCIE_PRX_DTX_P1 PERP1 SMBALERT# / GPIO11
LAN C192 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 AV32
<38> PCIE_PTX_C_DRX_N1 1 2 0.1U_0402_10V7K PETN1
C193 PCIE_PTX_DRX_P1 AU32 H14 PCH_SMBCLK 20120731 --> change to +3VS
<38> PCIE_PTX_C_DRX_P1 PETP1 SMBCLK PCH_SMBCLK 6 1 SMB_CLK_S3
PCIE_PRX_DTX_N2 BE34 C9 PCH_SMBDATA SMB_CLK_S3 <12,13,37,46>

S
5
<37> PCIE_PRX_DTX_N2 PERN2 SMBDATA
PCIE_PRX_DTX_P2 BF34 Q60A

G
<37> PCIE_PRX_DTX_P2 PERP2
WLAN C194 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2 BB32 2N7002KDWH_SOT363-6
<37> PCIE_PTX_C_DRX_N2 1 2 0.1U_0402_10V7K PETN2
C195 PCIE_PTX_DRX_P2 AY32
D <37> PCIE_PTX_C_DRX_P2 PETP2 A12 3 4 D

SMBUS
PCH_SMBDATA SMB_DATA_S3
BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7> SMB_DATA_S3 <12,13,37,46>
Q60B

S
BJ36 PERN3 C8 SML0CLK 2N7002KDWH_SOT363-6
AV34 PERP3 SML0CLK
AU34 PETN3 G12 SML0DATA
PETP3 SML0DATA
PCIE_PRX_DTX_N4 BF36
<44> PCIE_PRX_DTX_N4 PERN4
PCIE_PRX_DTX_P4 BE36
<44> PCIE_PRX_DTX_P4 PERP4
Card Reader C277 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 AY34 C13 PCH_HOT# VGA, EC, Thermal Sensor
<44> PCIE_PTX_C_DRX_N4 1 2 0.1U_0402_10V7K PETN4 SML1ALERT# / PCHHOT# / GPIO74
C276 PCIE_PTX_DRX_P4 BB34
<44> PCIE_PTX_C_DRX_P4 PETP4 E14 SML1CLK
BG37 SML1CLK / GPIO58 1 R141 2 2.2K_0402_5%

PCI-E*
PERN5 +3V_PCH +3VS
BH37 M16 SML1DATA

2
AY36 PERP5 SML1DATA / GPIO75 1 R142 2 2.2K_0402_5% 20120731 --> change to +3VS

G
BB36 PETN5
PETP5
BJ38 SML1CLK 6 1 EC_SMB_CK2
BG38 PERN6 EC_SMB_CK2 <23,32,40,45>

S
5
AU36 PERP6 M7 Q61A

Controller

G
AV36 PETN6 CL_CLK1 2N7002KDWH_SOT363-6
PETP6
BG40 T11 SML1DATA 3 4 EC_SMB_DA2

Link
BJ40 PERN7 CL_DATA1 EC_SMB_DA2 <23,32,40,45>
Q61B

S
AY40 PERP7 2N7002KDWH_SOT363-6
BB40 PETN7 P10
PETP7 CL_RST1#
BE38
BC38 PERN8
AW38 PERP8
AY38 PETN8
PETP8
M10 CLK_REQ_GPU#_R +3V_PCH
C PEG_A_CLKRQ# / GPIO47 CLK_REQ_GPU#_R <23> C
CLK_PCIE_LAN# Y40
<38> CLK_PCIE_LAN# CLK_PCIE_LAN Y39 CLKOUT_PCIE0N
<38> CLK_PCIE_LAN CLKOUT_PCIE0P AB37 2 R134 1
LAN CLK_PCIE_VGA# PCH_GPIO11 10K_0402_5%
CLKREQ_LAN# J2 CLKOUT_PEG_A_N AB38 CLK_PCIE_VGA CLK_PCIE_VGA# <23>

CLOCKS
<38> CLKREQ_LAN# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA <23> R329
DRAMRST_CNTRL_PCH 2 1 1K_0402_5%

AB49 AV22 1 R335 2

CLK_PCIE_WLAN1# CLK_CPU_DMI# SML0CLK 2.2K_0402_5%
<37> CLK_PCIE_WLAN1# CLK_PCIE_WLAN1 AB47 CLKOUT_PCIE1N CLKOUT_DMI_N AU22 CLK_CPU_DMI CLK_CPU_DMI# <6>
<37> CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6> SML0DATA 1 R336 2
WLAN 2.2K_0402_5%
WLAN_CLKREQ1# M1
<37> WLAN_CLKREQ1# PCIECLKRQ1# / GPIO18 R140
AM12 PCH_HOT# 2 1 10K_0402_5%
CLKOUT_DP_N AM13
AA48 CLKOUT_DP_P CLK_REQ_GPU#_R 1 R202 2 10K_0402_5%
AA47 CLKOUT_PCIE2N
CLKOUT_PCIE2P BF18 CLK_BUF_CPU_DMI# R155 1 2 10K_0402_5%
PCH_GPIO20 V10 CLKIN_DMI_N BE18 CLK_BUF_CPU_DMI R157 1 2 10K_0402_5%
Only for 15" TV function PCIECLKRQ2# / GPIO20 CLKIN_DMI_P

CLK_PCIE_CARD_PCH# Y37 BJ30 CLKIN_DMI2# R159 1 2 10K_0402_5%

<44> CLK_PCIE_CARD_PCH# Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30
Card Reader CLK_PCIE_CARD_PCH CLKIN_DMI2 R160 1 2 10K_0402_5%
<44> CLK_PCIE_CARD_PCH CLKOUT_PCIE3P CLKIN_GND1_P XTAL25_IN
PCH_GPIO25 A8
PCIECLKRQ3# / GPIO25 G24 R169
CLK_BUF_DREF_96M# R162 1 2 10K_0402_5% XTAL25_OUT 1 2
CLKIN_DOT_96N E24 CLK_BUF_DREF_96M R163 1 2 10K_0402_5%
Y43 CLKIN_DOT_96P 1M_0402_5%
Y45 CLKOUT_PCIE4N
CLKOUT_PCIE4P AK7 CLK_BUF_PCIE_SATA# R164 1 2 10K_0402_5% Y2
PCH_GPIO26 L12 CLKIN_SATA_N AK5 CLK_BUF_PCIE_SATA R166 1 2 10K_0402_5%
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P 1 3
1 3
V45 K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5% GND GND
V46 CLKOUT_PCIE5N REFCLK14IN
B CLKOUT_PCIE5P 2 4 B
PCH_GPIO44 L14 H45 CLK_PCI_LPBACK 1 25MHZ_10PF_7V25000014 1
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <18>
C196 C197
CLK_PCIE_2VGA# AB42 V47 XTAL25_IN 10P_0402_50V8J 10P_0402_50V8J
<32> CLK_PCIE_2VGA# CLK_PCIE_2VGA AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT 2 2
2nd VGA <32> CLK_PCIE_2VGA CLKOUT_PEG_B_P XTAL25_OUT
<32> CLK2_REQ_GPU#_R CLK2_REQ_GPU#_R E6 +1.05VS_VCCDIFFCLKN
PEG_B_CLKRQ# / GPIO56 20120816 --->
Y47 XCLK_RCOMP R171 1 2 90.9_0402_1% 1. change P/N to 7V2500014(10pf), SJ10000E80J
+3V_PCH V40 XCLK_RCOMP 2. C196, C197 change to 10pf
V42 CLKOUT_PCIE6N
CLKOUT_PCIE6P
R152 2 1 10K_0402_5% CLKREQ_LAN# PCH_GPIO45 T13
PCIECLKRQ6# / GPIO45
R168 2 1 10K_0402_5% PCH_GPIO25 V38 K43 +3VS
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS

R165 2 1 10K_0402_5% PCH_GPIO26 CLKOUT_PCIE7P F47 R182 2 1 10K_0402_5%

PCH_GPIO46 K12 CLKOUTFLEX1 / GPIO65
R147 2 1 10K_0402_5% PCH_GPIO44 PCIECLKRQ7# / GPIO46 H47 S_DGPU_RST_R R1504 1 2 0_0402_5%
CLKOUTFLEX2 / GPIO66 S_DGPU_RST <18,32>
AK14
R170 2 1 10K_0402_5% CLK2_REQ_GPU#_R AK13 CLKOUT_ITPXDP_N K49 PCH_GPIO67
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 PCH_GPIO67 <19>
R172 2 1 10K_0402_5% PCH_GPIO45 Reserve for EMI please close to
PANTHER-POINT_FCBGA989
BIOS Request SKU ID PCH
R174 2 1 10K_0402_5% PCH_GPIO46

@ R175 @ C198
GPIO64, 65 that only for GC6 33_0402_5% 22P_0402_50V8J
+3VS CLK_BUF_ICH_14M 2 1 1 2
1. GPIO64 : S_DGPU_GC6_EN
2. GPIO65 : S_DGPU_PWROK
A R158 2 1 10K_0402_5% WLAN_CLKREQ1# A
@ R176 @ C199
R308 2 1 10K_0402_5% PCH_GPIO20 33_0402_5% 22P_0402_50V8J
CLK_PCI_LPBACK 2 1 1 2

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (2/9) PCIE, SMBUS, CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 15 of 65
5 4 3 2 1
 5 4 3 2 1

D D

U4C

DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

<5> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <5>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <5>
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
<5> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <5>
DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
<5> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <5>
BC12 FDI_CTX_PRX_N4
FDI_RXN4 FDI_CTX_PRX_N4 <5>
DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5
<5> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <5>
DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
<5> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <5>
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
<5> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <5>
DMI_CTX_PRX_P3 BJ20
<5> DMI_CTX_PRX_P3 DMI3RXP BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 <5>
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1
<5> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <5> +RTCVCC
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<5> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <5>
+3VS DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3
<5> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <5>
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4
<5> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <5>

1
DMI
FDI
BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <5>
1 DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 R179
<5> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <5>
C1060 DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 330K_0402_5%
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <5>
0.1U_0402_16V4Z DMI_CRX_PTX_P2 AY18
<5> DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 AU18 DMI2TXP
<5> DMI_CRX_PTX_P3

2
2 DMI3TXP AW16 FDI_INT
FDI_INT FDI_INT <5>
DSWODVREN
R177
5

1 2 DMI_IRCOMP BJ24 AV12 FDI_FSYNC0

+1.05VS DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5>
VGATE 2
P

<59> VGATE B 49.9_0402_1%

1
4 BG25 BC10 FDI_FSYNC1

：：
1 Y SYS_PWROK <6> DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5>
PCH_PWROK DSWODVREN - On Die DSW VR Enable R183
A R178 *
G

1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 H Enable @ 330K_0402_5%

DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5>
L Disable
3

C 750_0402_1% BB10 FDI_LSYNC1 C

U6 @ R180
FDI_LSYNC1 <5>

2
FDI_LSYNC1
MC74VHC1G08DFT2G SC70 5P 100K_0402_1% 4mil width and place
within 500mil of the PCH
2

A18 DSWODVREN
DSWVRMEN

System Power Management

For Deep S3 R1457 2 1 R_short 0_0402_5% SUSACK#_R C12 E22 PCH_DPWROK_R R181 1 2 R_short 0_0402_5% DPWROK_EC For Deep S3
<45> SUSACK# SUSACK# DPWROK DPWROK_EC <45>

R184 2 1 10K_0402_5% SYS_RST# K3 B9 WAKE# R185 1 2 R_short 0_0402_5% PCIE_WAKE#

+3VS SYS_RESET# WAKE# PCIE_WAKE# <19,37,38>

SYS_PWROK P12 N3 PM_CLKRUN# R253 1 2 10K_0402_5%

SYS_PWROK CLKRUN# / GPIO32
+3V_PCH
2 R190 1 PWROK L22 G8 SUS_STAT#
<45> PCH_PWROK PWROK SUS_STAT# / GPIO61 PAD T60 WAKE# R186 1 2 10K_0402_5%
R_short 0_0402_5%
APWROK can be connect to R191
PWROK if iAMT disable 2 1 APWROK L10 N14 SUSCLK
APWROK SUSCLK / GPIO62 PAD T61
R_short 0_0402_5%
PM_DRAM_PWRGD B13 D10 PM_SLP_S5#
<6> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PAD T62

R193 1 2 R_short 0_0402_5% PCH_RSMRST#_R C21 H4 PM_SLP_S4#

<45> EC_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <45>

For Deep S3 R1455 2 1 R_short 0_0402_5% SUSWARN#_R K16 F4 PM_SLP_S3#

<45> SUSWARN# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <45>

R198 1 2 R_short 0_0402_5% PBTN_OUT#_R E20 G10 Can be left NC when IAMT is not support on the platfrom
B <45> PBTN_OUT# PWRBTN# SLP_A# B

R208 1 2 R_short 0_0402_5% AC_PRESENT_R H20 G16 PM_SLP_SUS#_R R1447 2 1 R_short 0_0402_5% For Deep S3
<45> AC_PRESENT ACPRESENT / GPIO31 SLP_SUS# PM_SLP_SUS# <45,51>

R200 1 2 8.2K_0402_5% PCH_GPIO72 E10 AP14 H_PM_SYNC

BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6>

R201 2 1 10K_0402_5% RI# A10 K14 PCH_GPIO29

+3V_PCH RI# SLP_LAN# / GPIO29 PAD T74
Can be left NC if no use integrated LAN.
PANTHER-POINT_FCBGA989 10/06 Test point request

+3V_PCH
+3VS

R192 2 1 200_0402_5% PM_DRAM_PWRGD R1290 2 @ 1 200_0402_5% PM_DRAM_PWRGD

R194 2 1 10K_0402_5% SUSWARN# 7/28 Modify follow Module Design.

+3VALW

R195 2 1 200K_0402_5% AC_PRESENT_R R197 2 1 10K_0402_5% PCH_RSMRST#_R

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (3/9) DMI,FDI,PM,

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 16 of 65
5 4 3 2 1
 5 4 3 2 1

D D

+3VS

U4D
OPT@ EDID_CLK PCH_ENBKL J47 AP43
R836 2.2K_0402_5%
<34> PCH_ENBKL PCH_ENVDD M45 L_BKLTEN SDVO_TVCLKINN AP45
OPT@ EDID_DATA <34> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
R835 2.2K_0402_5%
PCH_PWM P45 AM42
<34> PCH_PWM L_BKLTCTL SDVO_STALLN AM40
EDID_CLK T40 SDVO_STALLP
OPT@ <34> EDID_CLK L_DDC_CLK +3VS
R205 1 2 2.2K_0402_5% CTRL_CLK EDID_DATA K47 AP39
<34> EDID_DATA L_DDC_DATA SDVO_INTN AP40
OPT@ SDVO_INTP
R261 1 2 2.2K_0402_5% CTRL_DATA CTRL_CLK T45
CTRL_DATA P39 L_CTRL_CLK HDMICLK R203 2 OPT@ 1 2.2K_0402_5%
L_CTRL_DATA
LVDS_IBG AF37 P38 HDMICLK
HDMICLK <36>
AF36 LVD_IBG SDVO_CTRLCLK M39 HDMIDAT HDMIDAT R267 2 OPT@ 1 2.2K_0402_5%
OPT@ LVD_VBG SDVO_CTRLDATA HDMIDAT <36>
R257 2 1 2.37K_0402_1% LVDS_IBG
AE48
AE47 LVD_VREFH AT49
Remove netname LVD_REF LVD_VREFL DDPB_AUXN AT47
DDPB_AUXP AT40 TMDS_B_HPD
LVDS_ACLK# AK39 DDPB_HPD TMDS_B_HPD <36>
<34> LVDS_ACLK# LVDSA_CLK#

LVDS
LVDS_ACLK AK40 AV42 TMDS_B_DATA2#_PCH
<34> LVDS_ACLK LVDSA_CLK DDPB_0N AV40 TMDS_B_DATA2_PCH TMDS_B_DATA2#_PCH <36>
LVDS_A0# AN48 DDPB_0P AV45 TMDS_B_DATA1#_PCH TMDS_B_DATA2_PCH <36>
C <34> LVDS_A0# LVDS_A1# AM47 LVDSA_DATA#0 DDPB_1N AV46 TMDS_B_DATA1_PCH TMDS_B_DATA1#_PCH <36> C
<34> LVDS_A1# LVDSA_DATA#1 DDPB_1P TMDS_B_DATA1_PCH <36>

Digital Display Interface

LVDS_A2# AK47 AU48 TMDS_B_DATA0#_PCH
<34> LVDS_A2# AJ48 LVDSA_DATA#2 DDPB_2N AU47 TMDS_B_DATA0#_PCH <36>
TMDS_B_DATA0_PCH
LVDSA_DATA#3 DDPB_2P AV47 TMDS_B_CLK#_PCH TMDS_B_DATA0_PCH <36>
LVDS_A0 AN47 DDPB_3N AV49 TMDS_B_CLK_PCH TMDS_B_CLK#_PCH <36>
<34> LVDS_A0 LVDS_A1 AM49 LVDSA_DATA0 DDPB_3P TMDS_B_CLK_PCH <36>
<34> LVDS_A1 AK49 LVDSA_DATA1
LVDS_A2
<34> LVDS_A2 AJ47 LVDSA_DATA2 P46
LVDSA_DATA3 DDPC_CTRLCLK P42
DDPC_CTRLDATA
AF40
AF39 LVDSB_CLK# AP47
LVDSB_CLK DDPC_AUXN AP49
AH45 DDPC_AUXP AT38
AH47 LVDSB_DATA#0 DDPC_HPD
AF49 LVDSB_DATA#1 AY47
AF45 LVDSB_DATA#2 DDPC_0N AY49
LVDSB_DATA#3 DDPC_0P AY43
AH43 DDPC_1N AY45
AH49 LVDSB_DATA0 DDPC_1P BA47
OPT@ LVDSB_DATA1 DDPC_2N
R266 2 1 150_0402_1% DAC_BLU AF47 BA48
AF43 LVDSB_DATA2 DDPC_2P BB47
LVDSB_DATA3 DDPC_3N BB49
OPT@ DDPC_3P
R264 2 1 150_0402_1% DAC_GRN

DAC_BLU N48 M43

OPT@ <35> DAC_BLU CRT_BLUE DDPD_CTRLCLK
R262 2 1 150_0402_1% DAC_RED DAC_GRN P49 M36
<35> DAC_GRN T49 CRT_GREEN DDPD_CTRLDATA
DAC_RED
<35> DAC_RED CRT_RED
AT45
T39 DDPD_AUXN AT43

CRT
CRT_DDC_CLK
<35> CRT_DDC_CLK M40 CRT_DDC_CLK DDPD_AUXP BH41
CRT_DDC_DATA
B <35> CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD B
+3VS BB43
CRT_HSYNC M47 DDPD_0N BB45
<35> CRT_HSYNC CRT_VSYNC M49 CRT_HSYNC DDPD_0P BF44
OPT@ <35> CRT_VSYNC CRT_VSYNC DDPD_1N
R848 1 2 2.2K_0402_5% CRT_DDC_CLK BE44
DDPD_1P BF42
CRT_IREF T43 DDPD_2N BE42
OPT@ DAC_IREF DDPD_2P
1

R849 1 2 2.2K_0402_5% CRT_DDC_DATA T42 BJ42

CRT_IRTN DDPD_3N BG42
R211 DDPD_3P
1K_0402_1% PANTHER-POINT_FCBGA989
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (4/9) LVDS,CRT,DP,HDMI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 17 of 65
5 4 3 2 1
 5 4 3 2 1

+3VS
RP2
8 1 PCI_PIRQA#
7 2 PCI_PIRQD#
6 3 PCI_PIRQC#
5 4 PCI_PIRQB# U4E
AY7
8.2K_0804_8P4R_5% RSVD1 AV7
BG26 RSVD2 AU3
RP1 BJ26 TP1 RSVD3 BG4
8 1 PCH_GPIO2 BH25 TP2 RSVD4
7 2 DGPU_PWR_EN BJ16 TP3 AT10
D 6 3 PCH_GPIO4 BG16 TP4 RSVD5 BC8 D
5 4 ODD_DA#_R AH38 TP5 RSVD6
AH37 TP6 AU2
8.2K_0804_8P4R_5% AK43 TP7 RSVD7 AT4
AK45 TP8 RSVD8 AT3
C18 TP9 RSVD9 AT1
+3VS N30 TP10 RSVD10 AY3
PPT EDS DOC#474146 TP11 RSVD11
H3 AT5
R305 1 @ 2 8.2K_0402_5% PCH_GPIO51 AH12 TP12 RSVD12 AV3
AM4 TP13 RSVD13 AV1
TP14 RSVD14
R297 1 @ 2 8.2K_0402_5% DGPU_GC6_EN USB3.0 AM5
Y13 TP15 RSVD15
BB1
BA3
R213 1 2 8.2K_0402_5% PCH_GPIO5 K24 TP16 RSVD16 BB5
L24 TP17 RSVD17 BB3
Port1 TP18 RSVD18
R225 1 2 8.2K_0402_5% PCH_WL_OFF# AB46 BB7
AB45 TP19 RSVD19 BE8
1 2 NVDD_PWR_EN TP20 RSVD20 BD4

RSVD
R212 8.2K_0402_5% Port2 RSVD21 BF6
R252 1 2 8.2K_0402_5% DGPU_HOLD_RST# RSVD22
Port3 LEFT USB B21 AV5
M20 TP21 RSVD23 AV10
AY16 TP22 RSVD24
R306 1 2 8.2K_0402_5% DGPU_GC6_EN BG46 TP23 AT8
@ Port4 TP24 RSVD25
R214 1 @ 2 8.2K_0402_5% DGPU_HOLD_RST# AY5
RSVD26 BA2
BE28 RSVD27
BC30 USB3Rn1 AT12
USB30_RX_N3 BE32 USB3Rn2 RSVD28 BF3
<48> USB30_RX_N3 BJ32 USB3Rn3 RSVD29
BC28 USB3Rn4
USB3Rp1 USB DEBUG = PORT1 AND PORT9
R215 2 @ 1 1K_0402_5% PCH_WL_OFF# BE30
C USB30_RX_P3 BF32 USB3Rp2 C
<48> USB30_RX_P3 BG32 USB3Rp3 C24 USB20_N0
USB20_N0 <34>
AV26 USB3Rp4
USB3Tn1
USBP0N
USBP0P
A24 USB20_P0
USB20_P0 <34>
Camera
BB26 C25
USB30_TX_N3 AU28 USB3Tn2 USBP1N B25
A16 swap overide Strap/Top-Block <48> USB30_TX_N3 USB3Tn3 USBP1P
AY30 C26 USB20_N2
Swap Override jumper AU26 USB3Tn4 USBP2N A26 USB20_P2
USB20_N2 <48>
LEFT USB
AY26 USB3Tp1 USBP2P K28 USB20_P2 <48>
USB30_TX_P3 AV28 USB3Tp2 USBP3N H28
<48> USB30_TX_P3 AW30 USB3Tp3 USBP3P E28
Low = A16 swap USB3Tp4 USBP4N D28
override/Top-Block USBP4P C28 USB20_N5
PCI_GNT3# USB20_N5 <49>
Swap Override enabled USBP5N
USBP5P
A28 USB20_P5
USB20_P5 <49>
RIGHT USB 1 (CHARGER PORT, SUB/B)
C29
USBP6N B29
**High=Default PCI_PIRQA# K40 USBP6P N28
* PCI_PIRQB# K38 PIRQA#
PIRQB#
USBP7N
USBP7P
M28 Some PCH config not support USB port 6 & 7.

PCI
PCI_PIRQC# H38 L30
PCI_PIRQD# G38 PIRQC# USBP8N K30
<23> DGPU_HOLD_RST# PIRQD# USBP8P G30 USB20_N9
USB20_N9 <49>
<15,32> S_DGPU_RST
R1505 1 @ 2 0_0402_5% DGPU_HOLD_RST# C46
REQ1# / GPIO50
USBP9N
USBP9P
E30 USB20_P9
USB20_P9 <49>
RIGHT USB 2 (SUB/B)
C44 C30

USB
NVDD_PWR_EN USB20_N10
<58> NVDD_PWR_EN USB20_N10 <37>
<23,51> DGPU_PWR_EN
DGPU_PWR_EN E40 REQ2# / GPIO52
REQ3# / GPIO54
USBP10N
USBP10P
A30 USB20_P10
USB20_P10 <37>
WLAN
L32
PCH_GPIO51 D47 USBP11N K32
DGPU_GC6_EN E42 GNT1# / GPIO51 USBP11P G32
GPIO53 => This Signal has a weak internal pull-up. <27> DGPU_GC6_EN GNT2# / GPIO53 USBP12N
PCH_WL_OFF# F46 E32
NOTE: The internal pull-up is disabled after <37> PCH_WL_OFF# GNT3# / GPIO55 USBP12P C32 USB20_N13
USB20_N13 <47>
PLTRST# deasserts. USBP13N
USBP13P
A32 USB20_P13
USB20_P13 <47>
BT
PCH_GPIO2 G42
ODD_DA#_R G40 PIRQE# / GPIO2
<41> ODD_DA#_R C42 PIRQF# / GPIO3 C33 1 R218 2 +3V_PCH
PCH_GPIO4 USBRBIAS
B PCH_GPIO5 D44 PIRQG# / GPIO4 USBRBIAS# B
PIRQH# / GPIO5 Within 500 mils 22.6_0402_1%
RP3
B33 USB_OC5# 4 5
K10 USBRBIAS USB_OC2# 3 6
20111024 Del PCI_PME# PME# USB_OC7# 2 7
PLT_RST# C6 A14 USB_OC0# USB_OC0# 1 8
<23,32,37,38,44,45,6> PLT_RST# PLTRST# OC0# / GPIO59 K20 USB_OC1#
OC1# / GPIO40 B17 USB_OC2# USB_OC1# <48> USB3 Port3, USB2 Port2 10K_1206_8P4R_5%
1 2 CLK_PCI_LPBACK_R H49 OC2# / GPIO41 C16 USB_OC3# USB_OC2# <49> USB2 Port5, Charger Port
R219 22_0402_5%
<15> CLK_PCI_LPBACK 1 2 CLK_PCI_EC_R H43 CLKOUT_PCI0 OC3# / GPIO42 L16 USB_OC4#
R220 22_0402_5%
<45> CLK_PCI_EC 2 1 CLK_PCI_DB_R J48 CLKOUT_PCI1 OC4# / GPIO43 A16 USB_OC5# USB_OC4# <49> USB2 Port9, Right USB (Sub/B)
R173 22_0402_5%
<37> CLK_PCI_DB K42 CLKOUT_PCI2 OC5# / GPIO9 D14
@ USB_OC6# RP4
H40 CLKOUT_PCI3 OC6# / GPIO10 C14 USB_OC7# USB_OC6# 4 5
CLKOUT_PCI4 OC7# / GPIO14 USB_OC1# 3 6
USB_OC4# 2 7
PANTHER-POINT_FCBGA989 USB_OC3# 1 8

10K_1206_8P4R_5%

PCH_GPIO51 R221 1 @ 2 1K_0402_5%

PLT_RST#
1

Boot BIOS Strap bit1 BBS1

R223
Boot BIOS 100K_0402_5%
Destination
2

Bit11 Bit10
A
0 1 Reserved A
GNT1#/
GPIO51 1 0 Reserved
1 1 * SPI (Default)
0 0 LPC
Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (5/9) PCI, USB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 18 of 65
5 4 3 2 1
 5 4 3 2 1

SKU ID +3VS

Function PCH_GPIO38 PCH_GPIO67 PCH_GPIO70

R711 R708 R704

Optimus 0 0 X

SLI@ 2

2
10K_0402_5%

10K_0402_5%

10K_0402_5%
Reserve 0 1 X @ @

1
DIS PCH_GPIO38
(SLI) 1 0 X
PCH_GPIO67
<15> PCH_GPIO67
D Reserve 1 1 X PCH_GPIO70 D

14" X X 0
+3VS
@
15" X X 1 R712 R709 R706

2
10K_0402_5%

10K_0402_5%

10K_0402_5%
R1493 2 1 10K_0402_5% EC_SCI# 0_0402_5% 2 1 R234 GC6_EVENT#_R
<23,32,45> GC6_EVENT#

OPT@
+3V_PCH R233 1 2 10K_0402_5%
+3VS

1
R235 2 1 10K_0402_5% EC_SMI# U4F

T7 C40 S_DGPU_PWROK
BMBUSY# / GPIO0 TACH4 / GPIO68 S_DGPU_PWROK <32>
R227 1 2 10K_0402_5% PCH_GPIO1 A42 B41 S_DGPU_PWR_EN
TACH1 / GPIO1 TACH5 / GPIO69 S_DGPU_PWR_EN <32,51> +3VS
R228 1 2 10K_0402_5% PCH_GPIO6 H36 C41 PCH_GPIO70 9/18 Reseve for SKU ID
+3VS TACH2 / GPIO6 TACH6 / GPIO70 S_DGPU_PWR_EN R268 1 2 10K_0402_5%
EC_SCI# E38 A40 S_NVDD_PWR_EN
<45> EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71 S_NVDD_PWR_EN <32>
GPIO28 S_NVDD_PWR_EN R237 1 2 10K_0402_5%
On-Die PLL Voltage Regulator EC_SMI# C10
<45> EC_SMI# GPIO8
This signal has a weak internal pull up

* H
L
：：On-Die voltage regulator enable
On-Die PLL Voltage Regulator disable
+3V_PCH R229

R230
1

1
@ 2 10K_0402_5%

2 10K_0402_5%
PCH_GPIO12

EC_LID_OUT#
C4

G2
LAN_PHY_PWR_CTRL / GPIO12
P4
R236 1 2 10K_0402_5% +3VS
GPIO15 A20GATE GATEA20 <45>
1 2 1K_0402_5% PCH_GPIO28 <45> EC_LID_OUT# AU16
R240 @
R231 1 2 10K_0402_5% PCH_GPIO16 U2 PECI
+3VS SATA4GP / GPIO16
R232 1 2 10K_0402_1% P5 KBRST#
RCIN# KBRST# <45>
@
C DGPU_PWROK D40 AY11 C

GPIO
<27,55,58> DGPU_PWROK TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <6>

CPU/MISC
R238 1 2 10K_0402_5% PCH_BT_DISABLE# T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP#
+3VS SCLOCK / GPIO22 THRMTRIP# H_THRMTRIP# <6>
R239 390_0402_5%
<37> PCH_BT_DISABLE# ODD_EN E8 T14
* PCH_GPIO27 (Have internal Pull-High) <41> ODD_EN GPIO24 INIT3_3V#
High: VCCVRM VR Enable @ PCH_THRMTRIP#_R <23,32>
0_0402_5% 2 1 R224 DS3_WAKE#_R E16 AY1 NV_CLE
Low: VCCVRM VR Disable <16,37,38> PCIE_WAKE# GPIO27 DF_TVS

+3V_PCH R241 1 <BOM 2Structure>

10K_0402_5% PCH_GPIO28 P8
GPIO28 AH8 INIT3_3V
<37,47> PCH_BT_ON# TS_VSS1 +3VS
1 2 10K_0402_5% PCH_BT_ON# K1
+3VS STP_PCI# / GPIO34
R242 AK11 This signal has weak internal
+3VALW R243 1 2 10K_0402_5% PCH_GPIO35 K4 TS_VSS2 S_DGPU_PWROK R255 1 2 10K_0402_5%
GPIO35 PU, can't pull low
AH10
ODD_DETECT# V8 TS_VSS3 KBRST# R226 1 2 10K_0402_5%
<41> ODD_DETECT# SATA2GP / GPIO36 AK10
DS3@
R207 2 1 10K_0402_5% PCH_GPIO37 M5 TS_VSS4 PCH_THRMTRIP#_R R244 1 2 10K_0402_5%
SATA3GP / GPIO37
Intel schematic reviwe recommand.
PCH_GPIO38 N2 P37
R245 1 @ 2 10K_0402_5% DS3_WAKE#_R SLOAD / GPIO38 NC_1
R247 1 2 10K_0402_5% PCH_GPIO39 M3
+3VS SDATAOUT0 / GPIO39
R248 1 2 10K_0402_5% PCH_GPIO48 V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
R249 1 2 10K_0402_5% PCH_GPIO49 V3 BG48
+3VS SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
SLAVE_PRESENT# D6 BH3
<32> SLAVE_PRESENT# GPIO57 VSS_NCTF_17

+3VS R250 1 2 200K_0402_5% ODD_DETECT# BH47

VSS_NCTF_18
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
B R251 A44 BJ44 H : Sandy Bridge B
1 2 10K_0402_5% SLAVE_PRESENT# VSS_NCTF_2 VSS_NCTF_20
+3V_PCH PROC_SEL
A45 BJ45 L : IVY Bridge
VSS_NCTF_3 VSS_NCTF_21
A46 BJ46

NCTF
VSS_NCTF_4 VSS_NCTF_22 +1.8VS
R259 1 2 10K_0402_5% PCH_GPIO37 A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
A6 BJ6
VSS_NCTF_6 VSS_NCTF_24 R216
B3 C2 2.2K_0402_5%
VSS_NCTF_7 VSS_NCTF_25
B47 C48
VSS_NCTF_8 VSS_NCTF_26 NV_CLE 1 2
H_SNB_IVB# <6>
BD1 D1 R217 1K_0402_5%
VSS_NCTF_9 VSS_NCTF_27
BD49 D49 CLOSE TO THE BRANCHING POINT
VSS_NCTF_10 VSS_NCTF_28
BE1 E1
VSS_NCTF_11 VSS_NCTF_29
BE49 E49
VSS_NCTF_12 VSS_NCTF_30
BF1 F1
VSS_NCTF_13 VSS_NCTF_31
BF49 F49
VSS_NCTF_14 VSS_NCTF_32

PANTHER-POINT_FCBGA989

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (6/9) GPIO, CPU, MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 19 of 65
5 4 3 2 1
 5 4 3 2 1

POWER L1 change to 1 ohm P/N

U4G PCH Power Rail Table
+1.05VS S RES 1/10W 1 +-1% 0603 +3VS
1700mA L1
Refer to CPU EDS R1.5
+1.05VS AA23 U48 +VCCADAC 2 1
AC23 VCCCORE[1] 63mA VCCADAC
VCCCORE[2] 1 1 1 1_0603_1% S0 Iccmax

10U_0603_6.3V6M
C209

1U_0402_6.3V6K
C210

1U_0402_6.3V6K
C211

1U_0402_6.3V6K
C212
1 1 1 1 AD21 Voltage Rail Voltage Current (A)

CRT
AD23 VCCCORE[3] U47 C213 C214 C215
AF21 VCCCORE[4] VSSADAC 0.01U_0402_16V7K 0.1U_0402_10V7K 10U_0603_6.3V6M

VCC CORE
AF23 VCCCORE[5] 2 2 2
VCCCORE[6]
V_PROC_IO 1.05 0.001
D 2 2 2 2 AG21 +3VS D
AG23 VCCCORE[7]
AG24 VCCCORE[8] AK36 +VCCA_LVDS 2 R295 1
VCCCORE[9] 1mA VCCALVDS
V5REF 5 0.001
AG26
AG27 VCCCORE[10] AK37 R_short 0_0603_5%
AG29 VCCCORE[11] VSSALVDS
VCCCORE[12]
V5REF_Sus 5 0.001
AJ23 +1.8VS
AJ26 VCCCORE[13] AM37

LVDS
L2
AJ27 VCCCORE[14] VCCTX_LVDS[1]
VCCCORE[15]
0.1UH_MLF1608DR10KT_10%_1608 Vcc3_3 3.3 0.228
AJ29 AM38 +VCCTX_LVDS 2 1
AJ31 VCCCORE[16] VCCTX_LVDS[2]
VCCCORE[17] 1 1 1 0.1uH inductor, 200mA
AP36 VccADAC 3.3 0.063
+1.05VS
40mA VCCTX_LVDS[3] C216 C217 C218
AP37 0.01U_0402_16V7K 0.01U_0402_16V7K 22U_0805_6.3V6M
2 1 +1.05VS_VCCDPLLEXP AN19 VCCTX_LVDS[4] 2 2 2
R254 R_short 0_0603_5%
VCCIO[28]
VccADPLLA 1.05 0.08

+VCCAPLLEXP BJ22 +3VS VccADPLLB 1.05 0.08

PAD T47 @ VCCAPLLEXP
V33 +3VS_VCC3_3_6 2 R256 1
This pin can be left as no connect in AN16 VCC3_3[6]
VccCore

HVCMOS
1 1.05 1.7
On-Die VR enabled mode (default). VCCIO[15] R_short 0_0603_5%
AN17 C219
VCCIO[16] V34
VCC3_3[7]
0.1U_0402_10V7K VccDMI 1.05 0.047
2
AN21
VCCIO[17]
VccIO 1.05 3.711
AN26
VCCIO[18]
3711mA
AN27 AT16 +VCCAFDI_VRM VccASW 1.05 0.903
VCCIO[19] VCCVRM[3]
+1.05VS AP21 +VCCP_VCCDMI +1.05VS
C VCCIO[20] C
R258 VccSPI 3.3 0.01
+1.05VS AP23 AT20 +VCCP_VCCDMI 2 1
VCCIO[21] VCCDMI[1]
1 R_short 0_0603_5%
+1.05VS
10U_0603_6.3V6M
C221

1U_0402_6.3V6K
C222

1U_0402_6.3V6K
C223

1U_0402_6.3V6K
C224

1U_0402_6.3V6K
C225

DMI
Del R296 for 14' 1 1 1 1 1 AP24 VccDSW 3.3 0.001
VCCIO[22]

VCCIO
layout C220
AP26 AB36 +1.05VS_VCC_DMI_CCI 2 R300 1
70mA 1U_0402_6.3V6K
VCCIO[23] VCCCLKDMI 2
1 R_short 0_0603_5% VccDFTERM 1.8 0.002
2 2 2 2 2 AT24
VCCIO[24] C226
1U_0402_6.3V6K VccRTC 3.3 6 uA
AN33 2
VCCIO[25]
AN34 AG16 VccSus3_3 3.3 0.095
+3VS VCCIO[26] VCCDFTERM[1]

1 R260 2 +3VS_VCCA3GBG BH29 AG17 +1.8VS

VCC3_3[3] 190mA VCCDFTERM[2] VccSusHDA 3.3 / 1.5 0.01

DFT / SPI
R_short 0_0603_5% 1
C227
AJ16 2 R293 1
0.1U_0402_10V7K +VCCPNAND VccVRM 1.8 / 1.5 0.167
VCCDFTERM[3]
2 1 R_short 0_0603_5%
+VCCAFDI_VRM AP16
VCCVRM[2] AJ17
VCCDFTERM[4]
C228 VccCLKDMI 1.05 0.07
0.1U_0402_10V7K
+1.05VS_VCCAPLL_FDI BG6 2
+1.05VS PAD T48 @ VccAFDIPLL +3VS VccSSC 1.05 0.095
1 R263 2 +1.05VS_VCCDPLL_FDI AP17
VCCIO[27] V1 2 R399 1
+3V_VCCPSPI VccDIFFCLKN 1.05 0.055
FDI

R_short 0_0603_5% 10mA VCCSPI

1 R_short 0_0603_5%
AU20
+VCCP_VCCDMI VCCDMI[2] C230 VccALVDS 3.3 0.001
1U_0402_6.3V6K
B PANTHER-POINT_FCBGA989 2 B
VccTX_LVDS 1.8 0.04

+1.5VS +VCCAFDI_VRM

2 R265 1 +VCCAFDI_VRM
R_short 0_0603_5%

Intel recommand VCCVRM==>1.5V FOR MOBILE

stuff R265 and unstuff R266 VCCVRM==>1.8V FOR DESKTOP

VCCVRM = 160mA detal waiting for newest spec

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (7/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 20 of 65
5 4 3 2 1
 5 4 3 2 1

Have internal VRM

+3VS
VCC3_3 = 266mA detal waiting for newest spec
VCCDMI = 42mA detal waiting for newest spec

2 R280 1 +3VS_VCC_CLKF33
R_short 0_0603_5% 1 1 U4J POWER +1.05VS

10U_0805_10V4Z
C231

1U_0402_6.3V6K
C232
AD49 N26 +1.05VS_VCCUSBCORE 2 R270 1
+3VALW VCCACLK VCCIO[29]
2 2 1 R_short 0_0603_5%
P26
2 R269 1 T16 VCCIO[30]
1 +VCCPDSW C233
D VCCDSW3_3 1mA P28 1U_0402_6.3V6K D
R_short 0_0603_5% VCCIO[31] 2
C234
0.1U_0402_10V7K V12 T27
2 DCPSUSBYP VCCIO[32]
T29
+3VS_VCC_CLKF33 T38 VCCIO[33] +3V_PCH
VCC3_3[5]

：On-Die PLL voltage regulator enable T23 +3V_VCCPUSB 2 R272 1

On-Die PLL Voltage Regulator 228mA VCCSUS3_3[7]
H +1.05VS BH23
VCCAPLLDMI2 R_short 0_0603_5%

0.1U_0402_10V7K
C236
T24 1
2 R271 1 +VCCDPLL_CPY AL29 VCCSUS3_3[8] +3V_PCH +5V_PCH +3V_PCH
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 VCCIO[14] R273
V23 +3V_VCCAUBG 2 1
,VCCAPLLSATA R_short 0_0603_5% VCCSUS3_3[9]

USB
1 R_short 0_0603_5%

2
+VCCSUS1 AL24 V24 2
DCPSUS[3] VCCSUS3_3[10]

1
1 C238 D1
P24 0.1U_0402_10V7K R275 CH751H-40PT_SOD323-2
@ C239 VCCSUS3_3[6] 2 +1.05VS 10_0402_5%
1U_0402_6.3V6K AA19
R276

1
2 VCCASW[1] T26 +1.05VS_VCCAUPLL 2 1 +PCH_V5REF_SUS

2
+1.05VS AA21 VCCIO[34]
VCCASW[2]
903mA R_short 0_0603_5% 1
1 R277 2 +1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS C240
VCCASW[3] 1mA V5REF_SUS 0.1U_0603_25V7K
R_short 0_0805_5% 1 1 2

22U_0805_6.3V6M
C241

22U_0805_6.3V6M
C242
AA26

Clock and Miscellaneous

VCCASW[4] AN23 +VCCA_USBSUS C243 @1 2 1U_0402_6.3V6K
AA27 DCPSUS[4]
2 2 VCCASW[5] AN24 +3V_VCCPSUS
AA29 VCCSUS3_3[1]
VCCASW[6]
+1.05VS AA31 +5VS +3VS
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN +3V_PCH
VCCASW[8] 1mA V5REF

2
C C
1 1 1 R278

1U_0402_6.3V6K
C244

1U_0402_6.3V6K
C245

1U_0402_6.3V6K
C246
L5 AC27 2 1 R279 D2
1 2 +1.05VS_VCCA_A_DPL VCCASW[9] N20 +3V_VCCPSUS CH751H-40PT_SOD323-2
VCCSUS3_3[2] 1 R_short 0_0603_5% 10_0402_5%
AC29

PCI/GPIO/LPC
BLM18PG181SN1D_0603
2 2 2 VCCASW[10] N22 C247

1
AC31 VCCSUS3_3[3] 1U_0402_6.3V +PCH_V5REF_RUN
VCCASW[11] P20 2 +3VS
VCCSUS3_3[4] 1
L6 AD29
1 2 +1.05VS_VCCA_B_DPL VCCASW[12] P22 2 R281 1 C248
BLM18PG181SN1D_0603 AD31 VCCSUS3_3[5] 1U_0603_10V6K
VCCASW[13] 1 R_short 0_0603_5% 2
C249
W21 AA16 +3VS_VCCPCORE 0.1U_0402_10V7K
VCCASW[14] VCC3_3[1]
1
22U_0805_6.3V6M
C250

2 +3VS
1U_0402_6.3V6K
C251

1U_0402_6.3V6K
C253

1 W23 W16
22U_0805_6.3V6M
C252

VCCASW[15] VCC3_3[8]
1 1 R282
W24 T34 +3VS_VCCPPCI 2 1
2 VCCASW[16] VCC3_3[4]
2 1 R_short 0_0603_5%
W26
2 2 VCCASW[17] C254
W29 +3VS 0.1U_0402_10V7K
VCCASW[18] 2
W31 AJ2 +VCC3_3_2 2 R283 1
VCCASW[19] VCC3_3[2] +1.05VS_SATA3 +1.05VS
Before gerber out change to 22u_0805 1 R_short 0_0603_5%
W33
VCCASW[20] AF13 2 R285 1
VCCIO[5] C255
2 0.1U_0402_10V7K 1 R_short 0_0603_5%
+VCCRTCEXT N16
DCPRTC AH13 C257
1 VCCIO[12]
C258 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
VCCVRM[4] VCCIO[13]
2
B AF14 B
2 R274 1 +1.05VS_VCCA_A_DPL BD47 VCCIO[6]

：On-Die PLL voltage regulator enable

+1.05VS VCCADPLLA 80mA AK1

SATA
R_short 0_0603_5% VCCAPLLSATA On-Die PLL Voltage Regulator
1 +1.05VS_VCCA_B_DPL BF47 H
C256 VCCADPLLB 80mA +VCCAFDI_VRM
1U_0402_6.3V6K AF11 +VCCAFDI_VRM VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
+1.05VS_VCCDIFFCLKN +VCCDIFFCLK AF17 VCCVRM[1] +1.05VS_VCC_SATA +1.05VS
2 AF33 VCCIO[7] ,VCCAPLLSATA
AF34 VCCDIFFCLKN[1] AC16 +1.05VS_VCC_SATA 2 R288 1
R304
55mA
VCCDIFFCLKN[2] VCCIO[2]
2 1 +1.05VS_VCCDIFFCLKN AG34
+1.05VS VCCDIFFCLKN[3] R_short 0_0603_5%
1 AC17 1
R_short 0_0603_5% VCCIO[3] C261
C259 +1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
2 2
+VCCSST V16 +1.05VS
DCPSST
R284 1
2 1 C263
+1.05VS
1 0.1U_0402_10V7K T17 T21
R_short 0_0603_5% V19 DCPSUS[1] VCCASW[22]
C262 2 DCPSUS[2]
MISC

1U_0402_6.3V6K +1.05VS V21

2 VCCASW[23]
2 R286 1 +V_CPU_IO BJ8
CPU

V_PROC_IO 1mA T19

R_short 0_0603_5% VCCASW[21]
1 1 1
+RTCVCC +3V_PCH
4.7U_0603_6.3V6K
C265

0.1U_0402_10V7K
C266

0.1U_0402_10V7K
C267

A22 P32 +VCCSUSHDA 2 R287 1

10mA VCCSUSHDA
RTC

2 2 2 VCCRTC
HDA

@
R_short 0_0603_5%
1U_0402_6.3V6K
C268

0.1U_0402_10V7K
C269

0.1U_0402_10V7K
C270

1 1 1 1
PANTHER-POINT_FCBGA989 C271
A 0.1U_0402_16V4Z A
@
2 2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (8/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 21 of 65
5 4 3 2 1
 5 4 3 2 1

U4H U4I
H5
VSS[0] AY4 H46
AA17 AK38 AY42 VSS[159] VSS[259] K18
AA2 VSS[1] VSS[80] AK4 AY46 VSS[160] VSS[260] K26
AA3 VSS[2] VSS[81] AK42 AY8 VSS[161] VSS[261] K39
AA33 VSS[3] VSS[82] AK46 B11 VSS[162] VSS[262] K46
D AA34 VSS[4] VSS[83] AK8 B15 VSS[163] VSS[263] K7 D
AB11 VSS[5] VSS[84] AL16 B19 VSS[164] VSS[264] L18
AB14 VSS[6] VSS[85] AL17 B23 VSS[165] VSS[265] L2
AB39 VSS[7] VSS[86] AL19 B27 VSS[166] VSS[266] L20
AB4 VSS[8] VSS[87] AL2 B31 VSS[167] VSS[267] L26
AB43 VSS[9] VSS[88] AL21 B35 VSS[168] VSS[268] L28
AB5 VSS[10] VSS[89] AL23 B39 VSS[169] VSS[269] L36
AB7 VSS[11] VSS[90] AL26 B7 VSS[170] VSS[270] L48
AC19 VSS[12] VSS[91] AL27 F45 VSS[171] VSS[271] M12
AC2 VSS[13] VSS[92] AL31 BB12 VSS[172] VSS[272] P16
AC21 VSS[14] VSS[93] AL33 BB16 VSS[173] VSS[273] M18
AC24 VSS[15] VSS[94] AL34 BB20 VSS[174] VSS[274] M22
AC33 VSS[16] VSS[95] AL48 BB22 VSS[175] VSS[275] M24
AC34 VSS[17] VSS[96] AM11 BB24 VSS[176] VSS[276] M30
AC48 VSS[18] VSS[97] AM14 BB28 VSS[177] VSS[277] M32
AD10 VSS[19] VSS[98] AM36 BB30 VSS[178] VSS[278] M34
AD11 VSS[20] VSS[99] AM39 BB38 VSS[179] VSS[279] M38
AD12 VSS[21] VSS[100] AM43 BB4 VSS[180] VSS[280] M4
AD13 VSS[22] VSS[101] AM45 BB46 VSS[181] VSS[281] M42
AD19 VSS[23] VSS[102] AM46 BC14 VSS[182] VSS[282] M46
AD24 VSS[24] VSS[103] AM7 BC18 VSS[183] VSS[283] M8
AD26 VSS[25] VSS[104] AN2 BC2 VSS[184] VSS[284] N18
AD27 VSS[26] VSS[105] AN29 BC22 VSS[185] VSS[285] P30
AD33 VSS[27] VSS[106] AN3 BC26 VSS[186] VSS[286] N47
AD34 VSS[28] VSS[107] AN31 BC32 VSS[187] VSS[287] P11
AD36 VSS[29] VSS[108] AP12 BC34 VSS[188] VSS[288] P18
AD37 VSS[30] VSS[109] AP19 BC36 VSS[189] VSS[289] T33
AD38 VSS[31] VSS[110] AP28 BC40 VSS[190] VSS[290] P40
AD39 VSS[32] VSS[111] AP30 BC42 VSS[191] VSS[291] P43
AD4 VSS[33] VSS[112] AP32 BC48 VSS[192] VSS[292] P47
AD40 VSS[34] VSS[113] AP38 BD46 VSS[193] VSS[293] P7
AD42 VSS[35] VSS[114] AP4 BD5 VSS[194] VSS[294] R2
C AD43 VSS[36] VSS[115] AP42 BE22 VSS[195] VSS[295] R48 C
AD45 VSS[37] VSS[116] AP46 BE26 VSS[196] VSS[296] T12
AD46 VSS[38] VSS[117] AP8 BE40 VSS[197] VSS[297] T31
AD8 VSS[39] VSS[118] AR2 BF10 VSS[198] VSS[298] T37
AE2 VSS[40] VSS[119] AR48 BF12 VSS[199] VSS[299] T4
AE3 VSS[41] VSS[120] AT11 BF16 VSS[200] VSS[300] W34
AF10 VSS[42] VSS[121] AT13 BF20 VSS[201] VSS[301] T46
AF12 VSS[43] VSS[122] AT18 BF22 VSS[202] VSS[302] T47
AD14 VSS[44] VSS[123] AT22 BF24 VSS[203] VSS[303] T8
AD16 VSS[45] VSS[124] AT26 BF26 VSS[204] VSS[304] V11
AF16 VSS[46] VSS[125] AT28 BF28 VSS[205] VSS[305] V17
AF19 VSS[47] VSS[126] AT30 BD3 VSS[206] VSS[306] V26
AF24 VSS[48] VSS[127] AT32 BF30 VSS[207] VSS[307] V27
AF26 VSS[49] VSS[128] AT34 BF38 VSS[208] VSS[308] V29
AF27 VSS[50] VSS[129] AT39 BF40 VSS[209] VSS[309] V31
AF29 VSS[51] VSS[130] AT42 BF8 VSS[210] VSS[310] V36
AF31 VSS[52] VSS[131] AT46 BG17 VSS[211] VSS[311] V39
AF38 VSS[53] VSS[132] AT7 BG21 VSS[212] VSS[312] V43
AF4 VSS[54] VSS[133] AU24 BG33 VSS[213] VSS[313] V7
AF42 VSS[55] VSS[134] AU30 BG44 VSS[214] VSS[314] W17
AF46 VSS[56] VSS[135] AV16 BG8 VSS[215] VSS[315] W19
AF5 VSS[57] VSS[136] AV20 BH11 VSS[216] VSS[316] W2
AF7 VSS[58] VSS[137] AV24 BH15 VSS[217] VSS[317] W27
AF8 VSS[59] VSS[138] AV30 BH17 VSS[218] VSS[318] W48
AG19 VSS[60] VSS[139] AV38 BH19 VSS[219] VSS[319] Y12
AG2 VSS[61] VSS[140] AV4 H10 VSS[220] VSS[320] Y38
AG31 VSS[62] VSS[141] AV43 BH27 VSS[221] VSS[321] Y4
AG48 VSS[63] VSS[142] AV8 BH31 VSS[222] VSS[322] Y42
AH11 VSS[64] VSS[143] AW14 BH33 VSS[223] VSS[323] Y46
AH3 VSS[65] VSS[144] AW18 BH35 VSS[224] VSS[324] Y8
AH36 VSS[66] VSS[145] AW2 BH39 VSS[225] VSS[325] BG29
AH39 VSS[67] VSS[146] AW22 BH43 VSS[226] VSS[328] N24
B AH40 VSS[68] VSS[147] AW26 BH7 VSS[227] VSS[329] AJ3 B
AH42 VSS[69] VSS[148] AW28 D3 VSS[228] VSS[330] AD47
AH46 VSS[70] VSS[149] AW32 D12 VSS[229] VSS[331] B43
AH7 VSS[71] VSS[150] AW34 D16 VSS[230] VSS[333] BE10
AJ19 VSS[72] VSS[151] AW36 D18 VSS[231] VSS[334] BG41
AJ21 VSS[73] VSS[152] AW40 D22 VSS[232] VSS[335] G14
AJ24 VSS[74] VSS[153] AW48 D24 VSS[233] VSS[337] H16
AJ33 VSS[75] VSS[154] AV11 D26 VSS[234] VSS[338] T36
AJ34 VSS[76] VSS[155] AY12 D30 VSS[235] VSS[340] BG22
AK12 VSS[77] VSS[156] AY22 D32 VSS[236] VSS[342] BG24
AK3 VSS[78] VSS[157] AY28 D34 VSS[237] VSS[343] C22
VSS[79] VSS[158] D38 VSS[238] VSS[344] AP13
PANTHER-POINT_FCBGA989 D42 VSS[239] VSS[345] M14
D8 VSS[240] VSS[346] AP3
E18 VSS[241] VSS[347] AP1
E26 VSS[242] VSS[348] BE16
G18 VSS[243] VSS[349] BC16
G20 VSS[244] VSS[350] BG28
G26 VSS[245] VSS[351] BJ28
G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
A A

PANTHER-POINT_FCBGA989

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (9/9) VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 22 of 65
5 4 3 2 1
 5 4 3 2 1

UV1A
PCIE_CTX_GRX_N[0..15] +3VS_VGA
<32,5> PCIE_CTX_GRX_N[0..15] PCIE_CTX_GRX_P7 AN12 +3VS_VGA
Part 1 of 7 @
PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_N7 AM12 PEX_RX0 P6 1
FB_CLAMP_MON 2
<32,5> PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_P6 AN14 PEX_RX0_N GPIO0 M3 FB_CLAMP <23,27,45>
RV138 0_0402_5%
PEX_RX1 GPIO1

10K_0402_5%
PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_N6 AM14 L6 VGA_BL_PWM PCH_THRMTRIP#_R
<32,5> PCIE_CRX_GTX_N[0..15] PEX_RX1_N GPIO2 VGA_BL_PWM <34> PCH_THRMTRIP#_R <19,32>

1
PCIE_CTX_GRX_P5 AP14 P5 VGA_ENVDD
PCIE_CRX_GTX_P[0..15] PEX_RX2 GPIO3 VGA_ENVDD <34>

RV65
PCIE_CTX_GRX_N5 AP15 P7 VGA_ENBKL RV208
<32,5> PCIE_CRX_GTX_P[0..15] PEX_RX2_N GPIO4 VGA_ENBKL <34>

3
PCIE_CTX_GRX_P4 AN15 L7 10K_0402_5%
PCIE_CTX_GRX_N4 AM15 PEX_RX3 GPIO5 M7 FB_CLAMP_TOGGLE_REQ# QV7B
PEX_RX3_N GPIO6 @
PCIE_CTX_GRX_P3 AN17 N8 DMN66D0LDW-7 2N_SOT363-6

2
PCIE_CTX_GRX_N3 AM17 PEX_RX4 GPIO7 M1 OVERT# 5
PCIE_CTX_GRX_P2 AP17 PEX_RX4_N GPIO8 M2 VGA_ALERT#
Under GPU(below 150mils) PEX_RX5 GPIO9

6
D
150mA PCIE_CTX_GRX_N2 AP18 L1 D
MEM_VREF <28,29,30,31>

4
LV1 BLM18PG181SN1D_2P PCIE_CTX_GRX_P1 AN18 PEX_RX5_N GPIO10 M5 NVVDD PWM_VID QV7A

GPIO
1 2 +SP_PLLVDD PCIE_CTX_GRX_N1 AM18 PEX_RX6 GPIO11 N3 NVVDD PWM_VID <58>
VGA_AC_DET_R
+1.05VS_VGA PEX_RX6_N GPIO12 VGA_AC_DET_R <32> DMN66D0LDW-7 2N_SOT363-6

10K_0402_5%
22U_0805_6.3V6M

4.7U_0402_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K
PCIE_CTX_GRX_P0 AN20 M4 DPRSLPVR_VGA OVERT# 2
PEX_RX7 GPIO13 DPRSLPVR_VGA <58>

1
CV112

CV113

CV4

CV5
180ohms (ESR=0.2) Bead 1 1 1 1 PCIE_CTX_GRX_N0 AM20 N4
PEX_RX7_N GPIO14

RV223
AP20 P2

1
AP21 PEX_RX8 GPIO15 R8
AN21 PEX_RX8_N GPIO16 M6
2 2 2 2 AM21 PEX_RX9 GPIO17 R1 DGPU_HDMI_HPD
180ohms (ESR=0.2) Bead DGPU_HDMI_HPD <36>

2
AN23 PEX_RX9_N GPIO18 P3
AM23 PEX_RX10 GPIO19 P4
PEX_RX10_N GPIO20

1
AP23 P1 DV2 D
AP24 PEX_RX11 GPIO21 RB751V-40_SOD323-2 PLT_RST_VGA# 2
+3VS_VGA AN24 PEX_RX11_N VGA_AC_DET_R 2 1 G QV5
AM24 PEX_RX12 VGA_AC_DET <45>
S 2N7002KW_SOT323-3

3
+3VS_VGA AN26 PEX_RX12_N
AM26 PEX_RX13 Vendor recommand reserve PU/PD resistor 2012-0418 --> Stuff QV7, RV208
2

AP26 PEX_RX13_N 2012-0429 --> Add QV5, C38 has abnormal shutdown issue
RV24 RV25 AP27 PEX_RX14
2.2K_0402_5% 2.2K_0402_5% AN27 PEX_RX14_N AK9 VGA_CRT_R +3VS_VGA
AM27 PEX_RX15 DACA_RED AL10 VGA_CRT_G VGA_CRT_R <35>
PLT_RST_VGA#
5

PEX_RX15_N DACA_GREEN AL9 VGA_CRT_B VGA_CRT_G <35>

1

QV1B DACA_BLUE VGA_CRT_B <35> +3VALW

DACs

2
VGA_SMB_CK2 4 3 PCIE_CRX_GTX_P7 CV24 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P7 AK14
EC_SMB_CK2 <15,32,40,45> PEX_TX0
PCIE_CRX_GTX_N7 CV26 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N7 AJ14 AM9 VGA_CRT_HSYNC RV52

2
2N7002DW-T/R7_SOT363-6 PCIE_CRX_GTX_P6 1 2 PCIE_CRX_C_GTX_P6 AH14 PEX_TX0_N DACA_HSYNC AN9 VGA_CRT_VSYNC VGA_CRT_HSYNC <35> GC6@
CV21 0.22U_0402_10V6K 10K_0402_5%
PCIE_CRX_GTX_N6 1 2 PCIE_CRX_C_GTX_N6 AG14 PEX_TX1 DACA_VSYNC VGA_CRT_VSYNC <35> RV53
CV23 0.22U_0402_10V6K
PCIE_CRX_GTX_P5 CV25 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P5 AK15 PEX_TX1_N 10K_0402_5%

1
PEX_TX2

2
PCIE_CRX_GTX_N5 CV27 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N5 AJ15 AG10 +DACA_VDD

G
PEX_TX2_N DACA_VDD QV6

PCI EXPRESS
PCIE_CRX_GTX_P4 CV29 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P4 AL16 AP9 +DACA_VREF

1
2

PCIE_CRX_GTX_N4 CV31 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N4 AK16 PEX_TX3 DACA_VREF AP8 DACA_RSET FB_CLAMP_TOGGLE_REQ# 3 1
QV1A PEX_TX3_N DACA_RSET GC6_EVENT# <19,32,45>

0.1U_0402_10V7K
PCIE_CRX_GTX_P3 CV33 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P3 AK17

D
PEX_TX4

1
VGA_SMB_DA2 1 6

CV130
C PCIE_CRX_GTX_N3 CV28 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N3 AJ17 C
EC_SMB_DA2 <15,32,40,45> PEX_TX4_N 1
PCIE_CRX_GTX_P2 CV30 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P2 AH17 RV107 2N7002KW_SOT323-3
2N7002DW-T/R7_SOT363-6 PCIE_CRX_GTX_N2 CV32 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N2 AG17 PEX_TX5 124_0402_1%
PCIE_CRX_GTX_P1 CV36 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P1 AK18 PEX_TX5_N
PEX_TX6 SLI@ 2 SLI@
PCIE_CRX_GTX_N1 CV41 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N1 AJ18

2
PCIE_CRX_GTX_P0 CV34 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P0 AL19 PEX_TX6_N +3VS_VGA
PU AT EC SIDE, +3VS AND 4.7K PCIE_CRX_GTX_N0 CV35 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N0 AK19 PEX_TX7 R4 VGA_CRT_CLK
GPIO 14 of GPU connect to PCH GPIO 0
PEX_TX7_N I2CA_SCL VGA_CRT_CLK <35>
AK20 R5 VGA_CRT_DATA
VGA_CRT_DATA <35>
AJ20 PEX_TX8
PEX_TX8_N
I2CA_SDA CRT VGA_ALERT# 1 2
AH20 R7 I2CB_SCL RV15 2.2K_0402_5%
AG20 PEX_TX9 I2CB_SCL R6 I2CB_SDA VGA_EDID_CLK 1 2
AK21 PEX_TX9_N I2CB_SDA RV4 2.2K_0402_5%

I2C
AJ21 PEX_TX10 R2 VGA_EDID_CLK VGA_EDID_DATA 1 2
VGA_EDID_CLK <34> SLI@
AL22 PEX_TX10_N
PEX_TX11
I2CC_SCL
I2CC_SDA
R3 VGA_EDID_DATA
VGA_EDID_DATA <34>
LVDS VGA_BL_PWM 2 1 RV7 2.2K_0402_5%
AK22 RV16 10K_0402_5% VGA_CRT_DATA 1 2
+3VS PEX_TX11_N
AK23 T4 VGA_SMB_CK2 RV10 2.2K_0402_5%
AJ23 PEX_TX12 I2CS_SCL T3 VGA_SMB_DA2 VGA_CRT_CLK 1 2
AH23 PEX_TX12_N I2CS_SDA RV11 2.2K_0402_5%
1 PEX_TX13
C1061 AG23 I2CB_SCL 1 2
0.1U_0402_16V4Z AK24 PEX_TX13_N RV12 2.2K_0402_5%
AJ24 PEX_TX14 I2CB_SDA 1 2
2 AL25 PEX_TX14_N RV13 2.2K_0402_5%
PEX_TX15 60mA Close to GPU OVERT# 1 2
AK25 +PLLVDD
PEX_TX15_N RV1 10K_0402_5%
5

UV2 AD8 1 2 VGA_CRT_R 1 SLI@ 2 VGA_AC_DET_R 1 2

PLT_RST# 2 PLLVDD RV2 10K_0402_5%
P

<18,32,37,38,44,45,6> PLT_RST# B AJ11 45mA RV112 @ 0_0402_5% RV106 150_0402_1%

4 PLT_RST_VGA# PEX_WAKE_N AE8 VGA_CRT_G 1 SLI@ 2
DGPU_HOLD_RST# 1 Y SP_PLLVDD
<18> DGPU_HOLD_RST# A CLK_PCIE_VGA AL13 45mA RV108 150_0402_1%
G

<15> CLK_PCIE_VGA PEX_REFCLK SLI@ 2

2

CLK_PCIE_VGA# AK13 AD7 +SP_PLLVDD VGA_CRT_B 1

<15> CLK_PCIE_VGA# PEX_REFCLK_N VID_PLLVDD
CLK_REQ_GPU# AK12 RV109 150_0402_1%

CLK
3

RV111 PEX_CLKREQ_N
NC7SZ08P5X_NL_SC70-5 10K_0402_5%
1 @ 2 PEX_TSTCLK_OUT AJ26 H3 XTAL_IN
B Differential signal RV20 200_0402_1% PEX_TSTCLK_OUT# AK26 PEX_TSTCLK_OUT XTAL_IN H2 XTAL_OUT B
PEX_TSTCLK_OUT_N XTAL_OUT
1

PLT_RST_VGA# AJ12 J4 XTALOUT 220 ohms @100MHz (ESR=0.05)

AP29 PEX_RST_N XTAL_OUTBUFF H1 XTALSSIN 1 2
PEX_TERMP XTAL_SSIN 120mA

1
1 2 PEX_TERMP 10K_0402_5% RV26 LV5 SLI@
RV22 2.49K_0402_1% RV27 +DACA_VDD
Under GPU Near GPU 2 1
R1495 @ 0_0402_5% +3VS_VGA

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

4.7U_0603_6.3V6K
10K_0402_5% BLM18PG181SN1D_0603

@ CV125

@ CV126

SLI@ CV139

SLI@ CV122

SLI@ CV127

SLI@ CV128
1U_0402_6.3V6K
1 2 1 1 1 1 1 1

2
N14P_FCBGA908 GT@ Internal Thermal Sensor
FB_CLAMP_MON 2 2 2 2 2 2
CV126
2

+3VS_VGA
+3VS RV238 1 2
0_0402_5% RV23 10M_0402_5%
GC6@
2

10K_0402_5%
1
1

RV230 YV1 OPT@

RV235 10K_0402_5% 4 3 XTAL_OUT
10K_0402_5% @ NC OSC
GC6@ RV231
XTAL_IN 1 2 LV7
1

2 1 +3VS_VGA OSC NC +PLLVDD 1 2

2

<18,23,51> DGPU_PWR_EN +1.05VS_VGA

22U_0805_6.3V6M
0.1U_0402_10V7K
QV2 27MHZ 16PF +-30PPM X3G027000FG1H-HX
1

CV131
1 1 1 1 R_short 0_0402_5%
1

AO3413_SOT23-3 D RV236 10K_0402_5%

CV40
2

2 10K_0402_5% CV37 CV38

G GC6@ RV32 27P_0402_50V8J 27P_0402_50V8J
GC6@ S 10K_0402_5% 2 2 2 2
3

2
G
0.1U_0402_10V7K

QV16
GC6@ CV148

A 1 For GC6 1 3 CLK_REQ_GPU# A

<15> CLK_REQ_GPU#_R 20120816 --> CV37, CV38 change to 27pf
1

D
Under GPU Near GPU
D

2
<18,23,51> DGPU_PWR_EN
2

G 2 2N7002H 1N_SOT23-3
FB_CLAMP <23,27,45>
QV3 S @ RV232
3

2N7002KW_SOT323-3 10K_0402_5%
GC6@ @
1

1 2 Title
Security
Security Classification
Classification LC Future Center Secret Data
1

RV237 RV233 0_0402_5%

10K_0402_5%
@ Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-PCIE/DAC/GPIO
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 23 of 65
5 4 3 2 1
 5 4 3 2 1

UV1D

Part 4 of 7
<34> VGA_TXCLK+ VGA_TXCLK+ AM6
VGA_TXCLK- AN6 IFPA_TXC P8
<34> VGA_TXCLK- IFPA_TXC_N NC
<34> VGA_TXOUT0+ VGA_TXOUT0+ AP3 AC6
VGA_TXOUT0- AN3 IFPA_TXD0 NC AJ28
<34> VGA_TXOUT0- IFPA_TXD0_N NC
<34> VGA_TXOUT1+ VGA_TXOUT1+ AN5 AJ4
VGA_TXOUT1- AM5 IFPA_TXD1 NC AJ5
<34> VGA_TXOUT1- IFPA_TXD1_N NC
<34> VGA_TXOUT2+ VGA_TXOUT2+ AL6 AL11
VGA_TXOUT2- AK6 IFPA_TXD2 NC C15
<34> VGA_TXOUT2- IFPA_TXD2_N NC

NC
AJ6 D19
AH6 IFPA_TXD3 NC D20
D IFPA_TXD3_N NC D23 D
NC D26
AJ9 NC H31
AH9 IFPB_TXC NC T8
AP6 IFPB_TXC_N NC V32
AP5 IFPB_TXD4 NC
AM7 IFPB_TXD4_N
AL7 IFPB_TXD5
for 15" dual channel IFPB_TXD5_N
AN8
AM8 IFPB_TXD6
AK8 IFPB_TXD6_N
AL8 IFPB_TXD7
IFPB_TXD7_N L4 VCCSENSE_VGA
VDD_SENSE VCCSENSE_VGA <58>
AK1
AJ1 IFPC_L0
AJ3 IFPC_L0_N L5 VSSSENSE_VGA
IFPC_L1 GND_SENSE VSSSENSE_VGA <58>
AJ2
AH3 IFPC_L1_N
IFPC_L2 trace width: 16mils
AH4
AG5 IFPC_L2_N differential voltage sensing.
AG4 IFPC_L3 differential signal routing.
IFPC_L3_N
TEST
AM1 AK11 TESTMODE
AM2 IFPD_L0 TESTMODE
AM3 IFPD_L0_N AM10
IFPD_L1 JTAG_TCK TV2

1
AM4 AM11
IFPD_L1_N JTAG_TDI TV3
AL3 AP12
IFPD_L2 JTAG_TDO TV4 10K_0402_5%
C AL4 AP11 C
IFPD_L2_N JTAG_TMS TV5
AK4 AN11 1 2 RV33
AK5 IFPD_L3 JTAG_TRST_N RV34 10K_0402_5%

2
IFPD_L3_N

LVDS/TMDS
<36> VGA_HDMI_TX2+ VGA_HDMI_TX2+ AD2
VGA_HDMI_TX2- AD3 IFPE_L0
<36> VGA_HDMI_TX2- IFPE_L0_N
VGA_HDMI_TX1+ AD1
<36>
<36>
VGA_HDMI_TX1+
VGA_HDMI_TX1- VGA_HDMI_TX1- AC1 IFPE_L1 SERIAL
VGA_HDMI_TX0+ AC2 IFPE_L1_N H6 ROM_CS#
<36> VGA_HDMI_TX0+ IFPE_L2 ROM_CS_N
<36> VGA_HDMI_TX0- VGA_HDMI_TX0- AC3 H4 ROM_SCLK
IFPE_L2_N ROM_SCLK ROM_SCLK <33>
<36> VGA_HDMI_CLK+ VGA_HDMI_CLK+ AC4 H5 ROM_SI ROM_SI <33>
VGA_HDMI_CLK- AC5 IFPE_L3 ROM_SI H7 ROM_SO
<36> VGA_HDMI_CLK- IFPE_L3_N ROM_SO ROM_SO <33>

AE3
AE4 IFPF_L0
AF4 IFPF_L0_N
AF5 IFPF_L1
AD4 IFPF_L1_N GENERAL RV35 10K_0402_5%
AD5 IFPF_L2 L2 2 1
AG1 IFPF_L2_N BUFRST_N
AF1 IFPF_L3 L3
IFPF_L3_N CEC
J1 1 2
MULTI_STRAP_REF0_GND RV38 40.2K_0402_1%
AG3
AG2 IFPC_AUX_I2CW _SCL
IFPC_AUX_I2CW _SDA_N J2 STRAP0
STRAP0 STRAP0 <33>
J7 STRAP1
B STRAP1 STRAP1 <33> B
AK3 J6 STRAP2 STRAP2 <33>
+3VS_VGA AK2 IFPD_AUX_I2CX_SCL STRAP2 J5 STRAP3
IFPD_AUX_I2CX_SDA_N STRAP3 STRAP3 <33>
J3 STRAP4 STRAP4 <33>
STRAP4
SLI@
1 2 VGA_HDMI_CLK VGA_HDMI_CLK AB3
RV113 4.7K_0402_5% HDMI <36> VGA_HDMI_CLK
VGA_HDMI_DATA AB4 IFPE_AUX_I2CY_SCL
<36> VGA_HDMI_DATA IFPE_AUX_I2CY_SDA_N K3
SLI@ THERMDP
1 2 VGA_HDMI_DATA K4
RV114 4.7K_0402_5% AF3 THERMDN
AF2 IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N

1MB SPI ROM FOR VBIOS ROM (SLI)

N14P_FCBGA908
+3VS_VGA
CV295
2 1 20mils

1
@
0.1U_0402_16V4Z @ @
RV229 RV225
10K_0402_5% 10K_0402_5%
@
UV15 @

2
RV224 0_0402_5%
ROM_CS#1 2 ROM_CS#_R 1 8
ROM_SO 1 2 ROM_SO_R 2 CS# VCC 7 ROM_HOLD#
RV226 0_0402_5% 3 DO HOLD# 6 @
A W P# CLK A
@ 4 5 RV228 0_0402_5%
GND DIO ROM_SCLK_R1 2 ROM_SCLK
MX25L1005AMC-12G SOP ROM_SI_R 1 2 ROM_SI
RV227 0_0402_5%
@
Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-LVDS/HDMI/DP/THM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 24 of 65
5 4 3 2 1
 5 4 3 2 1

UV1E
Near GPU
+1.5VS_VGA
For GDDR5 setting. Near GPU Part 5 of 7 2000mA +1.05VS_VGA
3.5A
AA27 AG19
FBVDDQ_0 PEX_IOVDD_0

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
CV273

CV274

CV275

CV276

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AA30 AG21
FBVDDQ_1 PEX_IOVDD_1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CV263

CV264

CV265

CV266

CV267

CV268

CV269

CV270

CV271

CV272

CV43

CV44

CV45

CV46

CV47

CV48

CV49

CV50

CV51

CV52
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 1 1 2 2 2 2 1 1 1 1 AB27 AG22 1 1 1 1 1 1 2 2 2 2
AB33 FBVDDQ_2 PEX_IOVDD_2 AG24
AC27 FBVDDQ_3 PEX_IOVDD_3 AH21
AD27 FBVDDQ_4 PEX_IOVDD_4 AH25
2 2 2 2 2 2 1 1 1 1 2 2 2 2 AE27 FBVDDQ_5 PEX_IOVDD_5 2 2 2 2 2 2 1 1 1 1
AF27 FBVDDQ_6
AG27 FBVDDQ_7 AG13
B13 FBVDDQ_8 PEX_IOVDDQ_0 AG15
FBVDDQ_9 PEX_IOVDDQ_1 Under GPU(below 150mils) +1.05VS_VGA
D B16 AG16 D
FBVDDQ_10 PEX_IOVDDQ_2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
Under GPU(below 150mils) B19 AG18
+1.5VS_VGA FBVDDQ_11 PEX_IOVDDQ_3

CV54

CV53

CV56

CV55
E13 AG25 1 1 1 1
E16 FBVDDQ_12 PEX_IOVDDQ_4 AH15
FBVDDQ_13 PEX_IOVDDQ_5

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
E19 AH18
FBVDDQ_14 PEX_IOVDDQ_6
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CV277

CV281

CV282

CV278

CV279

CV280

CV292

CV287

CV294

CV284

CV285

CV286
1 1 1 1 1 1 1 1 1 1 1 1 H10 AH26
H11 FBVDDQ_15 PEX_IOVDDQ_7 AH27 2 2 2 2
H12 FBVDDQ_16 PEX_IOVDDQ_8 AJ27
H13 FBVDDQ_17 PEX_IOVDDQ_9 AK27
2 2 2 2 2 2 2 2 2 2 2 2 H14 FBVDDQ_18 PEX_IOVDDQ_10 AL27
FBVDDQ_19 PEX_IOVDDQ_11

POWER
H15 AM28
H16 FBVDDQ_20 PEX_IOVDDQ_12 AN28 +3VS_VGA
H18 FBVDDQ_21 PEX_IOVDDQ_13
H19 FBVDDQ_22
H20 FBVDDQ_23
H21 FBVDDQ_24 AH12
FBVDDQ_25 PEX_PLL_HVDD

0.1U_0402_10V7K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
H22
FBVDDQ_26

CV70

CV74

CV73
H23 1 1 1
H24 FBVDDQ_27
H8 FBVDDQ_28 AG12
H9 FBVDDQ_29 PEX_SVDD_3V3
L27 FBVDDQ_30 2 2 2
M27 FBVDDQ_31
N27 FBVDDQ_32 AG26 +PEX_PLLVDD
FBVDDQ_33 PEX_PLLVDD Under GPU(below 150mils)
P27
R27 FBVDDQ_34
T27 FBVDDQ_35
T30 FBVDDQ_36 J8
T33 FBVDDQ_37 VDD33_0 K8
S3 off --> +3VS, +3VS_VGA, +VDD33MISC +3VS_VGA
FBVDDQ_38 VDD33_1 Place near GPU
V27 L8
FBVDDQ_39 VDD33_2 RV5
W27 M8 +VDD33 2 1
FBVDDQ_40 VDD33_3

0.1U_0402_10V7K

0.1U_0402_10V7K

4.7U_0603_6.3V6K
W30
FBVDDQ_41 R_short 0_0603_5%

1U_0402_6.3V6K
CV109

CV111

CV293

CV75
W33 1 1 1 1
Y27 FBVDDQ_42
FBVDDQ_43 NV Check
AH8 +IFPAB_PLLVDD
C IFPAB_PLLVDD AJ8 2 1 C
RV141 IFPAB_RSET 2 2 2 2
1 2 FB_VDDQ_SENSE 1K_0402_1% RV40
<55> VDDQ_SENSE
AG8 +IFPAB_IOVDD @
R_short 0_0402_5% IFPA_IOVDD AG9
RV142 IFPB_IOVDD
1 2 FB_VSS_SENSE F1 Place near balls
FB_VDDQ_SENSE
R_short 0_0402_5% @
AF7 +IFPC_PLLVDD 1 2
+1.5VS_VGA F2 IFPC_PLLVDD AF8 10K_0402_5% RV42 2 1
FB_GND_SENSE IFPC_RSET 1K_0402_1% RV43
AF6 +IFPC_IOVDD 1 @ 2 @
1 2 J27 IFPC_IOVDD 10K_0402_5% RV44
RV6 40.2_0402_1% FB_CAL_PD_VDDQ IFPAB & IFPEF have to use
CALIBRATION PIN GDDR5 AG7 +IFPD_PLLVDD 1 2
1 2 H27 IFPD_PLLVDD AN2 10K_0402_5% RV45 2 1
RV8 40.2_0402_1% FB_CAL_PU_GND IFPD_RSET
FB_CAL_x_PD_VDDQ 40.2Ohm @ 1K_0402_1% RV46
AG6 +IFPD_IOVDD 1 2 @
1 2 H25 IFPD_IOVDD 10K_0402_5% RV47
RV9 60.4_0402_1% FB_CAL_TERM_GND
FB_CAL_x_PU_GND 40.2Ohm AB8 +IFPEF_PLLVDD
@
IFPEF_PLVDD AD6 2 1
IFPEF_RSET 1K_0402_1% RV50
FB_CAL_xTERM_GND 60.4Ohm AC7 +IFPE_IOVDD
IFPE_IOVDD AC8
Place near balls IFPF_IOVDD

+1.05VS_VGA
120mA
LV2
+PEX_PLLVDD 2 1

1U_0603_10V6K

4.7U_0805_25V6-K
0.1U_0402_10V7K
N14P_FCBGA908
R_short 0_0603_5%

CV65

CV66
CV3
1 1 1

2 2 2
B 300ohms @100MHz (ESR=0.25) B
P/N: SM010031680
+3VS_VGA
120ohms @100MHz (ESR=0.18)
LV9 220mA +1.05VS_VGA P/N:SM01000BZ00
2 1 +IFPEF_PLLVDD LV6 200mA Place near balls
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

BLM18PG181SN1D_0603 2 1 +IFPAB_PLLVDD
1U_0402_6.3V6K
CV149

CV147

CV171

CV173

CV150
4.7U_0603_6.3V6K

SLI@ 1 1 1 1 1 BLM18PG181SN1D_0603
0.1U_0402_10V7K

SLI@
1U_0402_6.3V6K
CV146

CV140

CV141

1 1 1
CV140
CV147 2 2 2 2 2
4.7U_0603_6.3V6K

2 2 2
SLI@ SLI@ SLI@ SLI@
SLI@
SLI@ SLI@
Place near balls 10K_0402_5% SLI@
10K_0402_5% OPT@
OPT@
Place near balls
180ohms @100MHz (ESR=0.2)
P/N: SM010030710
+1.05VS_VGA
220ohms @100MHz (ESR=0.05) +3VS_VGA
LV10 570mA LV4
0.1U_0402_10V7K

0.1U_0402_10V7K

2 1 +IFPE_IOVDD 2 1 +IFPAB_IOVDD
0.1U_0402_10V7K

0.1U_0402_10V7K
1U_0402_6.3V6K
CV152

CV172

CV153

CV158

BLM18PG181SN1D_0603 1 1 1 1 BLM18PG181SN1D_0603 IFPA_IOVDD and

1U_0402_6.3V6K
CV156

CV176

CV216

CV197

SLI@ SLI@ 1 1 1 1 IFPB_IOVDD combined

4.7U_0603_6.3V6K

2 2 2 2
4.7U_0603_6.3V6K

CV172 CV176 2 2 2 2

SLI@ SLI@ SLI@

SLI@ SLI@
SLI@ SLI@ SLI@
A A
Place near balls
10K_0402_5% 10K_0402_5%
OPT@ OPT@
Place near balls

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400-LA8691P
Date: Monday, January 14, 2013 Sheet 25 of 65
5 4 3 2 1
 5 4 3 2 1

UV1F

Part 6 of 7
A2 D2
AA17 GND_0 GND_100 D31
AA18 GND_1 GND_101 D33
UV1G +VGA_CORE AA20 GND_2 GND_102 E10
+VGA_CORE AA22 GND_3 GND_103 E22
AB12 GND_4 GND_104 E25
Part 7 of 7 V17 AB14 GND_5 GND_105 E5
AA12 VDD_56 V18 AB16 GND_6 GND_106 E7
AA14 VDD_0 VDD_57 V20 AB19 GND_7 GND_107 F28
D
AA16 VDD_1 VDD_58 V22 AB2 GND_8 GND_108 F7 D

AA19 VDD_2 VDD_59 W12 AB21 GND_9 GND_109 G10

AA21 VDD_3 VDD_60 W14 A33 GND_10 GND_110 G13
AA23 VDD_4 VDD_61 W16 AB23 GND_11 GND_111 G16
AB13 VDD_5 VDD_62 W19 AB28 GND_12 GND_112 G19
AB15 VDD_6 VDD_63 W21 AB30 GND_13 GND_113 G2
AB17 VDD_7 VDD_64 W23 AB32 GND_14 GND_114 G22
AB18 VDD_8 VDD_65 Y13 AB5 GND_15 GND_115 G25
AB20 VDD_9 VDD_66 Y15 AB7 GND_16 GND_116 G28
AB22 VDD_10 VDD_67 Y17 AC13 GND_17 GND_117 G3
AC12 VDD_11 VDD_68 Y18 AC15 GND_18 GND_118 G30
AC14 VDD_12 VDD_69 Y20 AC17 GND_19 GND_119 G32
AC16 VDD_13 VDD_70 Y22 AC18 GND_20 GND_120 G33
AC19 VDD_14 VDD_71 AA13 GND_21 GND_121 G5
AC21 VDD_15 AC20 GND_22 GND_122 G7
AC23 VDD_16 U1 AC22 GND_23 GND_123 K2
M12 VDD_17 XVDD_1 U2 AE2 GND_24 GND_124 K28
M14 VDD_18 XVDD_2 U3 AE28 GND_25 GND_125 K30
VDD_19 XVDD_3 GND_26 GND_126
POWER
M16 U4 AE30 K32
M19 VDD_20 XVDD_4 U5 AE32 GND_27 GND_127 K33
M21 VDD_21 XVDD_5 U6 AE33 GND_28 GND_128 K5
M23 VDD_22 XVDD_6 U7 AE5 GND_29 GND_129 K7
N13 VDD_23 XVDD_7 U8 AE7 GND_30 GND_130 M13
N15 VDD_24 XVDD_8 AH10 GND_31 GND_131 M15
N17 VDD_25 AA15 GND_32 GND_132 M17
N18 VDD_26 V1 AH13 GND_33 GND_133 M18
N20 VDD_27 XVDD_9 V2 AH16 GND_34 GND_134 M20
N22 VDD_28 XVDD_10 V3 AH19 GND_35 GND_135 M22
P12 VDD_29 XVDD_11 V4 AH2 GND_36 GND_136 N12
C P14 VDD_30 XVDD_12 V5 AH22 GND_37 GND_137 N14 C
P16 VDD_31 XVDD_13 V6 AH24 GND_38 GND_138 N16
P19 VDD_32 XVDD_14 V7 AH28 GND_39 GND_139 N19
P21 VDD_33 XVDD_15 V8 AH29 GND_40 GND_140 N2
P23 VDD_34 XVDD_16 AH30 GND_41 GND_141 N21
R13 VDD_35 AH32 GND_42 GND_142 N23

GND
R15 VDD_36 W2 AH33 GND_43 GND_143 N28
R17 VDD_37 XVDD_17 W3 AH5 GND_44 GND_144 N30
R18 VDD_38 XVDD_18 W4 AH7 GND_45 GND_145 N32
R20 VDD_39 XVDD_19 W5 AJ7 GND_46 GND_146 N33
R22 VDD_40 XVDD_20 W7 AK10 GND_47 GND_147 N5
T12 VDD_41 XVDD_21 W8 AK7 GND_48 GND_148 N7
T14 VDD_42 XVDD_22 AL12 GND_49 GND_149 P13
T16 VDD_43 AL14 GND_50 GND_150 P15
T19 VDD_44 Y1 AL15 GND_51 GND_151 P17
T21 VDD_45 XVDD_23 Y2 AL17 GND_52 GND_152 P18
T23 VDD_46 XVDD_24 Y3 AL18 GND_53 GND_153 P20
U13 VDD_47 XVDD_25 Y4 AL2 GND_54 GND_154 P22
U15 VDD_48 XVDD_26 Y5 AL20 GND_55 GND_155 R12
U17 VDD_49 XVDD_27 Y6 AL21 GND_56 GND_156 R14
U18 VDD_50 XVDD_28 Y7 AL23 GND_57 GND_157 R16
U20 VDD_51 XVDD_29 Y8 AL24 GND_58 GND_158 R19
U22 VDD_52 XVDD_30 AL26 GND_59 GND_159 R21
V13 VDD_53 AL28 GND_60 GND_160 R23
V15 VDD_54 AA1 AL30 GND_61 GND_161 T13
VDD_55 XVDD_31 AA2 AL32 GND_62 GND_162 T15
XVDD_32 AA3 AL33 GND_63 GND_163 T17
XVDD_33 AA4 AL5 GND_64 GND_164 T18
XVDD_34 AA5 AM13 GND_65 GND_165 T2
XVDD_35 AA6 AM16 GND_66 GND_166 T20
B XVDD_36 AA7 AM19 GND_67 GND_167 T22 B
XVDD_37 AA8 AM22 GND_68 GND_168 AG11
XVDD_38 AM25 GND_69 GND_169 T28
AN1 GND_70 GND_170 T32
AN10 GND_71 GND_171 T5
AN13 GND_72 GND_172 T7
N14P_FCBGA908 AN16 GND_73 GND_173 U12
AN19 GND_74 GND_174 U14
AN22 GND_75 GND_175 U16
AN25 GND_76 GND_176 U19
AN30 GND_77 GND_177 U21
AN34 GND_78 GND_178 U23
AN4 GND_79 GND_179 V12
AN7 GND_80 GND_180 V14
AP2 GND_81 GND_181 V16
AP33 GND_82 GND_182 V19
B1 GND_83 GND_183 V21
B10 GND_84 GND_184 V23
B22 GND_85 GND_185 W13
B25 GND_86 GND_186 W15
B28 GND_87 GND_187 W17
B31 GND_88 GND_188 W18
B34 GND_89 GND_189 W20
B4 GND_90 GND_190 W22
B7 GND_91 GND_191 W28
C10 GND_92 GND_192 Y12
C13 GND_93 GND_193 Y14
C19 GND_94 GND_194 Y16
C22 GND_95 GND_195 Y19
A C25 GND_96 GND_196 Y21 A
C28 GND_97 GND_197 Y23
C7 GND_98 GND_198 AH11
GND_99 GND_199 C16
GND_OPT W32
GND_OPT

Security Classification LC Future Center Secret Data Title

N14P_FCBGA908
Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-VGA CORE, GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 26 of 65
5 4 3 2 1
 5 4 3 2 1

FBC_D[0..63]
FBA_D[0..63] <30,31> FBC_D[0..63]
<28,29> FBA_D[0..63]

30ohms (ESR=0.01) Bead

P/N;SM010007W00 UV1B PU for X16 mode PU for X16 mode
UV1C
Part 2 of 7
+1.05VS_VGA +FB_PLLAVDD FBA_D0 L28 U30 FBA_CS#_L Part 3 of 7
FBA_D1 M29 FBA_D0 FBA_CMD0 T31 FBA_MA3_BA3_L FBA_CS#_L <28> FBC_D0 G9 D13 FBC_CS#_L
200mA FBA_D2 L29 FBA_D1 FBA_CMD1 U29 FBA_MA2_BA0_L FBA_MA3_BA3_L <28> FBC_D1 E9 FBB_D0 FBB_CMD0 E14 FBC_MA3_BA3_L FBC_CS#_L <30>
FBMA-L11-160808300LMA25T_2P
1 2 +FB_PLLAVDD FBA_D3 M28 FBA_D2
FBA_D3
FBA_CMD2
FBA_CMD3
R34 FBA_MA4_BA2_L FBA_MA2_BA0_L <28>
FBA_MA4_BA2_L <28>
FBC_D2 G8 FBB_D1
FBB_D2
FBB_CMD1
FBB_CMD2
F14 FBC_MA2_BA0_L FBC_MA3_BA3_L <30>
FBC_MA2_BA0_L <30>
GDDR5
D FBA_D4 N31 R33 FBA_MA5_BA1_L FBC_D3 F9 A12 FBC_MA4_BA2_L D
LV3 FBA_D5 P29 FBA_D4
FBA_D5
FBA_CMD4
FBA_CMD5
U32 FBA_WE#_L FBA_MA5_BA1_L <28>+1.5VS_VGA
FBA_WE#_L <28>
FBC_D4 F11 FBB_D3
FBB_D4
FBB_CMD3
FBB_CMD4
B12 FBC_MA5_BA1_L FBC_MA4_BA2_L <30>
FBC_MA5_BA1_L <30>+1.5VS_VGA
Mode H - Mirror Mode Mapping
Place close to BGA FBA_D6 R29 U33 FBA_MA7_MA8_L FBC_D5 G11 C14 FBC_WE#_L
FBA_D7 P28 FBA_D6 FBA_CMD6 U28 FBA_MA6_MA11_L FBA_MA7_MA8_L <28> FBC_D6 F12 FBB_D5 FBB_CMD5 B14 FBC_MA7_MA8_L FBC_WE#_L <30>
FBA_D7 FBA_CMD7 FBA_MA6_MA11_L <28> FBB_D6 FBB_CMD6 FBC_MA7_MA8_L <30>

1
FBA_D8 J28 V28 FBA_ABI#_L FBC_D7 G12 G15 FBC_MA6_MA11_L DATA Bus
FBA_D8 FBA_CMD8 FBA_ABI#_L <28> FBB_D7 FBB_CMD7 FBC_MA6_MA11_L <30>

1
FBA_D9 H29 V29 FBA_MA12_RFU_L RV209 FBC_D8 G6 F15 FBC_ABI#_L
FBA_D10 J29 FBA_D9 FBA_CMD9 V30 FBA_MA0_MA10_L FBA_MA12_RFU_L <28> FBC_D9 F5 FBB_D8 FBB_CMD8 E15 FBC_MA12_RFU_L FBC_ABI#_L <30>
FBA_D10 FBA_CMD10 FBA_MA0_MA10_L <28> 10K_0402_5% FBB_D9 FBB_CMD9 FBC_MA12_RFU_L <30>
RV210 Address 0..31 32..63
FBA_D11 H28 U34 FBA_MA1_MA9_L FBC_D10 E6 D15 FBC_MA0_MA10_L 10K_0402_5%
FBA_D12 G29 FBA_D11 FBA_CMD11 U31 FBA_RAS#_L FBA_MA1_MA9_L <28> FBC_D11 F6 FBB_D10 FBB_CMD10 A14 FBC_MA1_MA9_L FBC_MA0_MA10_L <30>
FBA_RAS#_L <28> FBx_CMD0 CS#

2
FBA_D13 E31 FBA_D12 FBA_CMD12 V34 FBA_RST#_L FBC_D12 F4 FBB_D11 FBB_CMD11 D14 FBC_RAS#_L FBC_MA1_MA9_L <30>
FBA_RST#_L <28> FBC_RAS#_L <30>

2
FBA_D14 E32 FBA_D13 FBA_CMD13 V33 FBA_CKE_L FBC_D13 G4 FBB_D12 FBB_CMD12 A15 FBC_RST#_L
FBA_D14 FBA_CMD14 FBA_CKE_L <28> FBB_D13 FBB_CMD13 FBC_RST#_L <30> FBx_CMD1 A3_BA3
FBA_D15 F30 Y32 FBA_CAS#_L FBC_D14 E2 B15 FBC_CKE_L
FBA_D16 C34 FBA_D15 FBA_CMD15 AA31 FBA_CS#_H FBA_CAS#_L <28> FBC_D15 F3 FBB_D14 FBB_CMD14 C17 FBC_CAS#_L FBC_CKE_L <30>
FBA_D16 FBA_CMD16 FBA_CS#_H <29> FBB_D15 FBB_CMD15 FBC_CAS#_L <30> FBx_CMD2 A2_BA0
FBA_D17 D32 AA29 FBA_MA3_BA3_H FBC_D16 C2 D18 FBC_CS#_H
FBA_D18 B33 FBA_D17 FBA_CMD17 AA28 FBA_MA2_BA0_H FBA_MA3_BA3_H <29> FBC_D17 D4 FBB_D16 FBB_CMD16 E18 FBC_MA3_BA3_H FBC_CS#_H <31>
FBA_D18 FBA_CMD18 FBA_MA2_BA0_H <29> FBB_D17 FBB_CMD17 FBC_MA3_BA3_H <31> FBx_CMD3 A4_BA2
FBA_D19 C33 AC34 FBA_MA4_BA2_H FBC_D18 D3 F18 FBC_MA2_BA0_H
FBA_D20 F33 FBA_D19 FBA_CMD19 AC33 FBA_MA5_BA1_H FBA_MA4_BA2_H <29> FBC_D19 C1 FBB_D18 FBB_CMD18 A20 FBC_MA4_BA2_H FBC_MA2_BA0_H <31>
FBA_D20 FBA_CMD20 FBA_MA5_BA1_H <29>+1.5VS_VGA FBB_D19 FBB_CMD19 FBC_MA4_BA2_H <31> FBx_CMD4 A5_BA1
FBA_D21 F32 AA32 FBA_WE#_H FBC_D20 B3 B20 FBC_MA5_BA1_H
FBA_D22 H33 FBA_D21 FBA_CMD21 AA33 FBA_MA7_MA8_H FBA_WE#_H <29> FBC_D21 C4 FBB_D20 FBB_CMD20 C18 FBC_WE#_H FBC_MA5_BA1_H <31>+1.5VS_VGA
FBA_D22 FBA_CMD22 FBA_MA7_MA8_H <29> FBB_D21 FBB_CMD21 FBC_WE#_H <31> FBx_CMD5 WE#
FBA_D23 H32 Y28 FBA_MA6_MA11_H FBC_D22 B5 B18 FBC_MA7_MA8_H
FBA_D23 FBA_CMD23 FBA_MA6_MA11_H <29> FBB_D22 FBB_CMD22 FBC_MA7_MA8_H <31>

MEMORY INTERFACE

1
FBA_D24 P34 Y29 FBA_ABI#_H FBC_D23 C5 G18 FBC_MA6_MA11_H FBx_CMD6 A7_A8
FBA_D24 FBA_CMD24 FBA_ABI#_H <29> FBB_D23 FBB_CMD23 FBC_MA6_MA11_H <31>

1
FBA_D25 P32 W31 FBA_MA12_RFU_H RV221 FBC_D24 A11 G17 FBC_ABI#_H
FBA_D26 P31 FBA_D25 FBA_CMD25 Y30 FBA_MA0_MA10_H FBA_MA12_RFU_H <29> FBC_D25 C11 FBB_D24 FBB_CMD24 F17 FBC_MA12_RFU_H FBC_ABI#_H <31>
10K_0402_5% RV222 FBx_CMD7 A6_A11

MEMORY INTERFACE B
FBA_D27 P33 FBA_D26 FBA_CMD26 AA34 FBA_MA1_MA9_H FBA_MA0_MA10_H <29> FBC_D26 D11 FBB_D25 FBB_CMD25 D16 FBC_MA0_MA10_H FBC_MA12_RFU_H <31>
FBA_D27 FBA_CMD27 FBA_MA1_MA9_H <29> FBB_D26 FBB_CMD26 FBC_MA0_MA10_H <31> 10K_0402_5%
FBA_D28 L31 Y31 FBA_RAS#_H FBC_D27 B11 A18 FBC_MA1_MA9_H FBx_CMD8 ABI#
FBA_RAS#_H <29> FBC_MA1_MA9_H <31>

2
FBA_D29 L34 FBA_D28 FBA_CMD28 Y34 FBA_RST#_H FBC_D28 D8 FBB_D27 FBB_CMD27 D17 FBC_RAS#_H
FBA_RST#_H <29> FBC_RAS#_H <31>

2
FBA_D30 L32 FBA_D29 FBA_CMD29 Y33 FBA_CKE_H FBC_D29 A8 FBB_D28 FBB_CMD28 A17 FBC_RST#_H
FBA_D30 FBA_CMD30 FBA_CKE_H <29> FBB_D29 FBB_CMD29 FBC_RST#_H <31> FBx_CMD9 A12_RFU
FBA_D31 L33 V31 FBA_CAS#_H FBC_D30 C8 B17 FBC_CKE_H
FBA_D32 AG28 FBA_D31 FBA_CMD31 FBA_CAS#_H <29> FBC_D31 B8 FBB_D30 FBB_CMD30 E17 FBC_CAS#_H FBC_CKE_H <31>
FBA_D32 FBB_D31 FBB_CMD31 FBC_CAS#_H <31> FBx_CMD10 A0_A10
FBA_D33 AF29 FBC_D32 F24
FBA_D34 AG29 FBA_D33 FBC_D33 G23 FBB_D32
FBA_D34 FBB_D33 FBx_CMD11 A1_A9
FBA_D35 AF28 R32 FBC_D34 E24
C FBA_D36 AD30 FBA_D35 FBA_CMD_RFU0 AC32 FBC_D35 G24 FBB_D34 C12 C
FBA_D36 FBA_CMD_RFU1 FBB_D35 FBB_CMD_RFU0 FBx_CMD12 RAS#
FBA_D37 AD29 FBC_D36 D21 C20
FBA_D38 AC29 FBA_D37 FBC_D37 E21 FBB_D36 FBB_CMD_RFU1
FBA_D38 FBB_D37 FBx_CMD13 RST#
FBA_D39 AD28 @ FBC_D38 G21
FBA_D39 FBB_D38

A
FBA_D40 AJ29 R28 60.4_0402_1%
1 2RV58 FBC_D39 F21 @ FBx_CMD14 CKE#
FBA_D40 FBA_DEBUG0 +1.5VS_VGA FBB_D39
FBA_D41 AK29 AC2860.4_0402_1%
1 2RV59 FBC_D40 G27 G14 60.4_0402_1%
1 2RV60
FBA_D41 FBA_DEBUG1 FBB_D40 FBB_DEBUG0 +1.5VS_VGA
FBA_D42 AJ30 FBC_D41 D27 G20 60.4_0402_1%
1 2RV61 FBx_CMD15 CAS#
FBA_D43 AK28 FBA_D42 FBC_D42 G26 FBB_D41 FBB_DEBUG1
FBA_D43 @ FBB_D42
FBA_D44 AM29 FBC_D43 E27 @ FBx_CMD16 CS#
FBA_D45 AM31 FBA_D44 R30 FBA_CLK0 FBC_D44 E29 FBB_D43
FBA_D46 AN29 FBA_D45 FBA_CLK0 R31 FBA_CLK0# FBA_CLK0 <28> FBC_D45 F29 FBB_D44 D12 FBC_CLK0
FBA_D46 FBA_CLK0_N FBA_CLK0# <28> FBB_D45 FBB_CLK0 FBC_CLK0 <30> FBx_CMD17 A3_BA3
FBA_D47 AM30 AB31 FBA_CLK1 FBC_D46 E30 E12 FBC_CLK0#
FBA_D48 AN31 FBA_D47 FBA_CLK1 AC31 FBA_CLK1# FBA_CLK1 <29> FBC_D47 D30 FBB_D46 FBB_CLK0_N E20 FBC_CLK1 FBC_CLK0# <30>
FBA_D48 FBA_CLK1_N FBA_CLK1# <29> FBB_D47 FBB_CLK1 FBC_CLK1 <31> FBx_CMD18 A2_BA0
FBA_D49 AN32 FBC_D48 A32 F20 FBC_CLK1#
FBA_D50 AP30 FBA_D49 FBC_D49 C31 FBB_D48 FBB_CLK1_N FBC_CLK1# <31>
FBA_D50 FBB_D49 FBx_CMD19 A4_BA2
FBA_D51 AP32 FBC_D50 C32
FBA_D52 AM33 FBA_D51 K31 FBA_WCK0 FBC_D51 B32 FBB_D50
FBA_D52 FBA_WCK01 FBA_WCK0 <28> FBB_D51 FBx_CMD20 A5_BA1
FBA_D53 AL31 L30 FBA_WCK0_N FBC_D52 D29 F8 FBC_WCK0
FBA_D54 AK33 FBA_D53 FBA_WCK01_N H34 FBA_WCK1 FBA_WCK0_N <28> FBC_D53 A29 FBB_D52 FBB_WCK01 E8 FBC_WCK0_N FBC_WCK0 <30>
FBA_D54 FBA_WCK23 FBA_WCK1 <28> FBB_D53 FBB_WCK01_N FBC_WCK0_N <30> FBx_CMD21 WE#
FBA_D55 AK32 J34 FBA_WCK1_N FBC_D54 C29 A5 FBC_WCK1
FBA_D56 AD34 FBA_D55 FBA_WCK23_N AG30 FBA_WCK2 FBA_WCK1_N <28> FBC_D55 B29 FBB_D54 FBB_WCK23 A6 FBC_WCK1_N FBC_WCK1 <30>
FBA_D56 FBA_WCK45 FBA_WCK2 <29> FBB_D55 FBB_WCK23_N FBC_WCK1_N <30> FBx_CMD22 A7_A8
FBA_D57 AD32 AG31 FBA_WCK2_N FBC_D56 B21 D24 FBC_WCK2
FBA_D58 AC30 FBA_D57 FBA_WCK45_N AJ34 FBA_WCK3 FBA_WCK2_N <29> FBC_D57 C23 FBB_D56 FBB_WCK45 D25 FBC_WCK2_N FBC_WCK2 <31>
FBA_D58 FBA_WCK67 FBA_WCK3 <29> FBB_D57 FBB_WCK45_N FBC_WCK2_N <31> FBx_CMD23 A6_A11
FBA_D59 AD33 AK34 FBA_WCK3_N FBC_D58 A21 B27 FBC_WCK3
FBA_D60 AF31 FBA_D59 FBA_WCK67_N FBA_WCK3_N <29> FBC_D59 C21 FBB_D58 FBB_WCK67 C27 FBC_WCK3_N FBC_WCK3 <31>
FBA_D60 FBB_D59 FBB_WCK67_N FBC_WCK3_N <31> FBx_CMD24 ABI#
FBA_D61 AG34 FBC_D60 B24
FBA_D62 AG32 FBA_D61 FBC_D61 C24 FBB_D60
FBA_D62 FBB_D61 FBx_CMD25 A12_RFU
FBA_D63 AG33 J30 FBC_D62 B26
FBA_D63 FBA_WCKB01 J31 FBC_D63 C26 FBB_D62 D6
FBA_WCKB01_N FBB_D63 FBB_WCKB01 FBx_CMD26 A0_A10
FBA_DBI0# P30 J32 D7
<28> FBA_DBI0# FBA_DBI1# F31 FBA_DQM0 FBA_WCKB23 J33 FBC_DBI0# E11 FBB_WCKB01_N C6
<28> FBA_DBI1# FBA_DQM1 FBA_WCKB23_N GC6 support on 15" <30> FBC_DBI0# FBB_DQM0 FBB_WCKB23 FBx_CMD27 A1_A9
FBA_DBI2# F34 AH31 FBC_DBI1# E3 B6
B <28> FBA_DBI2# FBA_DBI3# M32 FBA_DQM2 FBA_WCKB45 AJ31 <30> FBC_DBI1# FBC_DBI2# A3 FBB_DQM1 FBB_WCKB23_N F26 B
<28> FBA_DBI3# FBA_DQM3 FBA_WCKB45_N FB_CLAMP <30> FBC_DBI2# FBB_DQM2 FBB_WCKB45 FBx_CMD28 RAS#
FBA_DBI4# AD31 AJ32 FBC_DBI3# C9 E26
<29> FBA_DBI4# FBA_DQM4 FBA_WCKB67 FB_CLAMP <23,45> <30> FBC_DBI3# FBB_DQM3 FBB_WCKB45_N
FBA_DBI5# AL29 AJ33 FBC_DBI4# F23 A26 FBx_CMD29 RST#
<29> FBA_DBI5# FBA_DBI6# AM32 FBA_DQM5 FBA_WCKB67_N <31> FBC_DBI4# FBC_DBI5# F27 FBB_DQM4 FBB_WCKB67 A27
<29> FBA_DBI6# FBA_DBI7# AF34 FBA_DQM6 <31> FBC_DBI5# FBC_DBI6# C30 FBB_DQM5 FBB_WCKB67_N
<29> FBA_DBI7# FBA_DQM7
BOM structure from "NOGC6@" to "Mount" <31> FBC_DBI6# FBB_DQM6 FBx_CMD30 CKE#
RV66 10K_0402_5% FBC_DBI7# A24
FBA_EDC0 M31 E1 2 NOGC6@
1 <31> FBC_DBI7# FBB_DQM7
FBA_DQS_WP0 FB_CLAMP FBx_CMD31 CAS#
FBA_EDC1 G31 FBC_EDC0 D10
<28> FBA_EDC[3..0] FBA_EDC2 E33 FBA_DQS_WP1 +FB_PLLAVDD FBC_EDC1 D5 FBB_DQS_WP0
FBA_EDC3 M33 FBA_DQS_WP2 CV106 0.1U_0402_10V7K FBC_EDC2 C3 FBB_DQS_WP1
<29> FBA_EDC[7..4] FBA_EDC4 AE31 FBA_DQS_WP3 K27 1 2 FBC_EDC3 B9 FBB_DQS_WP2
FBA_EDC5 AK30 FBA_DQS_WP4 FB_DLL_AVDD FBC_EDC4 E23 FBB_DQS_WP3 H17
FBA_DQS_WP5 FBB_DQS_WP4 FBB_PLL_AVDD +FB_PLLAVDD

0.1U_0402_10V7K
FBA_EDC6 AN33 Place close to ball FBC_EDC5 E28
FBA_DQS_WP6 FBB_DQS_WP5

CV108
FBA_EDC7 AF33 FBC_EDC6 B30 1
FBA_DQS_WP7 U27 FBC_EDC7 A23 FBB_DQS_WP6
FBA_PLL_AVDD +FB_PLLAVDD FBB_DQS_WP7

22U_0805_6.3V6M
0.1U_0402_10V7K

M30
FBA_DQS_RN0
CV107

CV110
1U_0402_6.3V6K

H30 1 1 1 D9
FBA_DQS_RN1 <30> FBC_EDC[3..0] FBB_DQS_RN0 2

CV39
E34 E4
M34 FBA_DQS_RN2 H26 B2 FBB_DQS_RN1
AF30 FBA_DQS_RN3 FB_VREF <31> FBC_EDC[7..4] A9 FBB_DQS_RN2
AK31 FBA_DQS_RN4 2 2 2 D22 FBB_DQS_RN3
AM34 FBA_DQS_RN5 D28 FBB_DQS_RN4
FBA_DQS_RN6 FBB_DQS_RN5
Place close to ball
AF32 A30
FBA_DQS_RN7 B23 FBB_DQS_RN6 FBC_RST#_L
Place close to ball FBB_DQS_RN7
Place close to BGA FBC_RST#_H

For N13P-GT GC6 support N14P_FCBGA908

1
+3VS N14P_FCBGA908 RV74 RV73
FBA_RST#_L 10K_0402_5% 10K_0402_5%
FBA_RST#_H
1

D
2 QV4 @

2
A <18> DGPU_GC6_EN A
RV169 G 2N7002_SOT23 RV172 @
1

1 2
1 @ 2 S GC6_EN <32>
3

RV71 RV72
0_0402_5%DV3 DAN202UT106_SC70-3
0_0402_5% 10K_0402_5% 10K_0402_5%
FB_CLAMP RV18
1 2 S_GC6_EN 2
GC6@ 1
2

2 0_0402_5%1 3 FBVDDQ_PWR_EN <55>

10K_0402_5% RV68 Security Classification LC Future Center Secret Data Title
1

GC6@ GC6@
RV29 GC6@
Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-MEM Interface
RV156 200K_0402_5% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
1 NOGC6@2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
<19,55,58> DGPU_PWROK
2

Custom 1.0
0_0402_5%
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 27 of 65
5 4 3 2 1
 5 4 3 2 1

Memory - Lower 32 bits UV3 UV4

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 FBA_D0 A4 FBA_D24
FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1 FBA_EDC3 C2 DQ24 DQ0 A2 FBA_D25
C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D26
R13 EDC1 EDC2 DQ26 DQ2 B2 R13 EDC1 EDC2 DQ26 DQ2 B2
<27> FBA_D[0..31]
FBA_EDC2
EDC2 EDC1 DQ27 DQ3
FBA_D3 BYTE0 FBA_EDC1
EDC2 EDC1 DQ27 DQ3
FBA_D27
R2 E4 FBA_D4 R2 E4 FBA_D28 BYTE3
EDC3 EDC0 DQ28 DQ4 E2 FBA_D5 EDC3 EDC0 DQ28 DQ4 E2 FBA_D29
DQ29 DQ5 F4 FBA_D6 DQ29 DQ5 F4 FBA_D30
<27> FBA_EDC[3..0] DQ30 DQ6 DQ30 DQ6
FBA_DBI0# D2 F2 FBA_D7 FBA_DBI3# D2 F2 FBA_D31
<27> FBA_DBI0# DBI0# DBI3# DQ31 DQ7 <27> FBA_DBI3# DBI0# DBI3# DQ31 DQ7
D13 A11 D13 A11
FBA_DBI2# P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_DBI1# P13 DBI1# DBI2# DQ16 DQ8 A13
<27> FBA_DBI2# DBI2# DBI1# DQ17 DQ9 <27> FBA_DBI1# DBI2# DBI1# DQ17 DQ9
D
P2 B11 P2 B11 D
DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13
FBA_CLK0 J12 DQ19 DQ11 E11 FBA_CLK0 J12 DQ19 DQ11 E11
<27> FBA_CLK0 CK DQ20 DQ12 CK DQ20 DQ12
FBA_CLK0# J11 E13 FBA_CLK0# J11 E13
<27> FBA_CLK0# CK# DQ21 DQ13 CK# DQ21 DQ13
FBA_CKE_L J3 F11 FBA_CKE_L J3 F11
<27> FBA_CKE_L CKE# DQ22
DQ23
DQ14
DQ15
F13 CKE# DQ22
DQ23
DQ14
DQ15
F13 GDDR5
U11 FBA_D16 U11 FBA_D8
<27> FBA_MA2_BA0_L
FBA_MA2_BA0_L H11
BA0/A2 BA2/A4
DQ8
DQ9
DQ16
DQ17
U13 FBA_D17 FBA_MA4_BA2_L H11
BA0/A2 BA2/A4
DQ8
DQ9
DQ16
DQ17
U13 FBA_D9 Mode H - Mirror Mode Mapping
FBA_MA5_BA1_L K10 T11 FBA_D18 FBA_MA3_BA3_L K10 T11 FBA_D10
<27> FBA_MA5_BA1_L BA1/A5 BA3/A3 DQ10 DQ18 BA1/A5 BA3/A3 DQ10 DQ18
FBA_MA4_BA2_L K11 T13 FBA_D19 FBA_MA2_BA0_L K11 T13 FBA_D11 BYTE1
<27> FBA_MA4_BA2_L BA2/A4 BA0/A2 DQ11 DQ19 BA2/A4 BA0/A2 DQ11 DQ19
FBA_MA3_BA3_L H10 N11 FBA_D20 BYTE2 FBA_MA5_BA1_L H10 N11 FBA_D12 DATA Bus
<27> FBA_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 BA3/A3 BA1/A5 DQ12 DQ20
N13 FBA_D21 N13 FBA_D13
DQ13 DQ21 M11 FBA_D22 DQ13 DQ21 M11 FBA_D14
DQ14 DQ22 DQ14 DQ22
Address 0..31 32..63
FBA_MA7_MA8_L K4 M13 FBA_D23 FBA_MA0_MA10_L K4 M13 FBA_D15
<27> FBA_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 A8/A7 A10/A0 DQ15 DQ23
FBA_MA1_MA9_L H5 U4 FBA_MA6_MA11_L H5 U4 FBx_CMD0 CS#
<27> FBA_MA1_MA9_L A9/A1 A11/A6 DQ0 DQ24 A9/A1 A11/A6 DQ0 DQ24
FBA_MA0_MA10_L H4 U2 FBA_MA7_MA8_L H4 U2
<27> FBA_MA0_MA10_L A10/A0 A8/A7 DQ1 DQ25 A10/A0 A8/A7 DQ1 DQ25
FBA_MA6_MA11_L K5 T4 FBA_MA1_MA9_L K5 T4 FBx_CMD1 A3_BA3
<27> FBA_MA6_MA11_L A11/A6 A9/A1 DQ2 DQ26 A11/A6 A9/A1 DQ2 DQ26
FBA_MA12_RFU_L J5 T2 FBA_MA12_RFU_L J5 T2
<27> FBA_MA12_RFU_L A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27
N4 N4 FBx_CMD2 A2_BA0
A5 DQ4 DQ28 N2 A5 DQ4 DQ28 N2
U5 VPP/NC DQ5 DQ29 M4 +1.5VS_VGA U5 VPP/NC DQ5 DQ29 M4
VPP/NC DQ6 DQ30 VPP/NC DQ6 DQ30
FBx_CMD3 A4_BA2
2 RV115 1 M2 2 RV116 1 M2
DQ7 DQ31 DQ7 DQ31
1K_0402_1%
+1.5VS_VGA
1K_0402_1%
+1.5VS_VGA
FBx_CMD4 A5_BA1
J1 J1
2 RV117 1 J10 MF 2 RV118 1 J10 MF
SEN SEN FBx_CMD5 WE#
2 RV119 1 1K_0402_1% J13 B1 2 RV120 1 1K_0402_1% J13 B1
ZQ VDDQ D1 ZQ VDDQ D1
121_0402_1%
VDDQ
121_0402_1%
VDDQ
FBx_CMD6 A7_A8
F1 F1
J4 VDDQ M1 J4 VDDQ M1
Follow DG <27> FBA_ABI#_L
FBA_ABI#_L
ABI# VDDQ
FBA_ABI#_L
ABI# VDDQ FBx_CMD7 A6_A11
FBA_RAS#_L G3 P1 FBA_CAS#_L G3 P1
<27> FBA_RAS#_L RAS# CAS# VDDQ RAS# CAS# VDDQ
FBA_CS#_L G12 T1 FBA_WE#_L G12 T1 FBx_CMD8 ABI#
<27> FBA_CS#_L CS# WE# VDDQ CS# WE# VDDQ
FBA_CLK0 1 2 FBA_CAS#_L L3 G2 FBA_RAS#_L L3 G2
<27> FBA_CAS#_L CAS# RAS# VDDQ CAS# RAS# VDDQ
RV21 40.2_0402_1% FBA_WE#_L L12 L2 FBA_CS#_L L12 L2 FBx_CMD9 A12_RFU
<27> FBA_WE#_L WE# CS# VDDQ WE# CS# VDDQ
B3 B3
2

VDDQ D3 VDDQ D3
VDDQ VDDQ FBx_CMD10 A0_A10
RV123 F3 F3
D5 VDDQ H3 D5 VDDQ H3
160_0402_1% <27> FBA_WCK0_N
FBA_WCK0_N
WCK01# WCK23# VDDQ
FBA_WCK1_N
WCK01# WCK23# VDDQ FBx_CMD11 A1_A9
C @ FBA_WCK0 D4 K3 FBA_WCK1 D4 K3 C
<27> FBA_WCK0 WCK01 WCK23 VDDQ WCK01 WCK23 VDDQ
M3 M3 FBx_CMD12 RAS#
1

FBA_CLK0# 1 2 FBA_WCK1_N P5 VDDQ P3 FBA_WCK0_N P5 VDDQ P3

<27> FBA_WCK1_N WCK23# WCK01# VDDQ WCK23# WCK01# VDDQ
RV28 40.2_0402_1% FBA_WCK1 P4 T3 FBA_WCK0 P4 T3 FBx_CMD13 RST#
<27> FBA_WCK1 WCK23 WCK01 VDDQ WCK23 WCK01 VDDQ
E5 E5
VDDQ N5 VDDQ N5
VDDQ VDDQ
FBx_CMD14 CKE#
A10 E10 A10 E10
CV155

+FBA_VREFD_L +FBA_VREFD_L
0.01U_0402_25V7K

1 VREFD VDDQ VREFD VDDQ

U10 N10 U10 N10 FBx_CMD15 CAS#
+FBA_VREFC0 J14 VREFD VDDQ B12 +FBA_VREFC0 J14 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
2 VDDQ VDDQ
FBx_CMD16 CS#
F12 F12
VDDQ H12 VDDQ H12
VDDQ VDDQ FBx_CMD17 A3_BA3
FBA_RST#_L J2 K12 FBA_RST#_L J2 K12
<27> FBA_RST#_L RESET# VDDQ RESET# VDDQ
M12 M12 FBx_CMD18 A2_BA0
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
+1.5VS_VGA VDDQ VDDQ FBx_CMD19 A4_BA2
G13 G13
H1 VDDQ L13 H1 VDDQ L13
VSS VDDQ VSS VDDQ FBx_CMD20 A5_BA1
K1 B14 K1 B14
VSS VDDQ VSS VDDQ
1

B5 D14 B5 D14 FBx_CMD21 WE#

RV127 G5 VSS VDDQ F14 G5 VSS VDDQ F14
549_0402_1% L5 VSS VDDQ M14 L5 VSS VDDQ M14
VSS VDDQ VSS VDDQ
FBx_CMD22 A7_A8
T5 P14 T5 P14
RV212 VSS VDDQ VSS VDDQ
B10 T14 B10 T14 FBx_CMD23 A6_A11
2

1 2 +FBA_VREFC0 D10 VSS VDDQ D10 VSS VDDQ

G10 VSS G10 VSS
931_0402_1% FBx_CMD24 ABI#
820P_0402_25V7

VSS VSS
1

CV42

1 16 mil L10 A1 L10 A1

P10 VSS VSSQ C1 P10 VSS VSSQ C1
RV128
VSS VSSQ VSS VSSQ FBx_CMD25 A12_RFU
1.33K_0402_1% T10 E1 T10 E1
H14 VSS VSSQ N1 H14 VSS VSSQ N1
2 VSS VSSQ VSS VSSQ
FBx_CMD26 A0_A10
K14 R1 K14 R1
2

+1.5VS_VGA VSS VSSQ U1 +1.5VS_VGA VSS VSSQ U1

VSSQ VSSQ
FBx_CMD27 A1_A9
H2 H2
G1 VSSQ K2 G1 VSSQ K2
VDD VSSQ VDD VSSQ
FBx_CMD28 RAS#
L1 A3 L1 A3
G4 VDD VSSQ C3 G4 VDD VSSQ C3
VDD VSSQ VDD VSSQ
FBx_CMD29 RST#
L4 E3 L4 E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
B
+1.5VS_VGA VDD VSSQ VDD VSSQ FBx_CMD30 CKE# B
R5 R3 R5 R3
C10 VDD VSSQ U3 C10 VDD VSSQ U3
VDD VSSQ VDD VSSQ
FBx_CMD31 CAS#
R10 C4 R10 C4
VDD VSSQ VDD VSSQ
1

D11 R4 D11 R4
RV129 G11 VDD VSSQ F5 G11 VDD VSSQ F5
549_0402_1% L11 VDD VSSQ M5 L11 VDD VSSQ M5
P11 VDD VSSQ F10 P11 VDD VSSQ F10
RV213 VDD VSSQ VDD VSSQ
G14 M10 G14 M10
2

1 2 +FBA_VREFD_L L14 VDD VSSQ C11 L14 VDD VSSQ C11

931_0402_1% VDD VSSQ R11 VDD VSSQ R11
820P_0402_25V7

VSSQ VSSQ
1

A12 A12
CV58

1 VSSQ VSSQ
RV130 C12 C12
VSSQ VSSQ
1

D 1.33K_0402_1% E12 E12

2 VSSQ N12 VSSQ N12
<23,29,30,31> MEM_VREF G 2 VSSQ R12 VSSQ R12
2

QV9 170-BALL VSSQ U12 170-BALL VSSQ U12

S
3

2N7002W-T/R7_SOT323-3 VSSQ H13 VSSQ H13

SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
X76@ X76@

H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
+1.5VS_VGA UV3 SIDE +1.5VS_VGA UV4 SIDE
1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6
10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV68

CV69

CV77

CV78

CV71

CV76

CV79

CV80
CV166

CV129

CV132

CV133

CV174

CV134

CV135

CV136
2 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1

1 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-VRAM A Lower
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400-LA8691P
Date: Monday, March 11, 2013 Sheet 28 of 65
5 4 3 2 1
 5 4 3 2 1

Memory - Upper 32 bits UV6

UV5
MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0
A4 FBA_D56
A4 FBA_D32 FBA_EDC7 C2 DQ24 DQ0 A2 FBA_D57
FBA_EDC4 C2 DQ24 DQ0 A2 FBA_D33 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D58
C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D34 FBA_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D59
FBA_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D35 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D60
<27> FBA_D[63..32] EDC2 EDC1 DQ27 DQ3 BYTE4 EDC3 EDC0 DQ28 DQ4 BYTE7
R2 E4 FBA_D36 E2 FBA_D61
EDC3 EDC0 DQ28 DQ4 E2 FBA_D37 DQ29 DQ5 F4 FBA_D62
DQ29 DQ5 F4 FBA_D38 FBA_DBI7# D2 DQ30 DQ6 F2 FBA_D63
<27> FBA_EDC[7..4] DQ30 DQ6 <27> FBA_DBI7# DBI0# DBI3# DQ31 DQ7
FBA_DBI4# D2 F2 FBA_D39 D13 A11
<27> FBA_DBI4# DBI0# DBI3# DQ31 DQ7 DBI1# DBI2# DQ16 DQ8
D13 A11 FBA_DBI5# P13 A13
DBI1# DBI2# DQ16 DQ8 <27> FBA_DBI5# DBI2# DBI1# DQ17 DQ9
D FBA_DBI6# P13 A13 P2 B11 D
<27> FBA_DBI6# DBI2# DBI1# DQ17 DQ9 DBI3# DBI0# DQ18 DQ10
P2 B11 B13
DBI3# DBI0# DQ18 DQ10 B13 FBA_CLK1 J12 DQ19 DQ11 E11
FBA_CLK1 J12 DQ19 DQ11 E11 FBA_CLK1# J11 CK DQ20 DQ12 E13
<27> FBA_CLK1 CK DQ20 DQ12 CK# DQ21 DQ13
FBA_CLK1# J11 E13 FBA_CKE_H J3 F11
<27> FBA_CLK1# CK# DQ21 DQ13 CKE# DQ22 DQ14
FBA_CKE_H J3 F11 F13
<27> FBA_CKE_H CKE# DQ22 DQ14 DQ23 DQ15
F13 U11 FBA_D40
DQ23 DQ15 U11 FBA_D48 FBA_MA4_BA2_H H11 DQ8 DQ16 U13 FBA_D41
FBA_MA2_BA0_H H11 DQ8 DQ16 U13 FBA_D49 FBA_MA3_BA3_H K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBA_D42
<27> FBA_MA2_BA0_H BA0/A2 BA2/A4 DQ9 DQ17 BA1/A5 BA3/A3 DQ10 DQ18
FBA_MA5_BA1_H K10 T11 FBA_D50 FBA_MA2_BA0_H K11 T13 FBA_D43 BYTE5
<27> FBA_MA5_BA1_H BA1/A5 BA3/A3 DQ10 DQ18 BA2/A4 BA0/A2 DQ11 DQ19
FBA_MA4_BA2_H K11 T13 FBA_D51 FBA_MA5_BA1_H H10 N11 FBA_D44
<27>
<27>
FBA_MA4_BA2_H
FBA_MA3_BA3_H
FBA_MA3_BA3_H H10 BA2/A4
BA3/A3
BA0/A2
BA1/A5
DQ11
DQ12
DQ19
DQ20
N11 FBA_D52 BYTE6 BA3/A3 BA1/A5 DQ12
DQ13
DQ20
DQ21
N13 FBA_D45 GDDR5
N13 FBA_D53 M11 FBA_D46
DQ13
DQ14
DQ21
DQ22
M11 FBA_D54 FBA_MA0_MA10_H K4
A8/A7 A10/A0
DQ14
DQ15
DQ22
DQ23
M13 FBA_D47 Mode H - Mirror Mode Mapping
FBA_MA7_MA8_H K4 M13 FBA_D55 FBA_MA6_MA11_H H5 U4
<27> FBA_MA7_MA8_H A8/A7 A10/A0 DQ15 DQ23 A9/A1 A11/A6 DQ0 DQ24
FBA_MA1_MA9_H H5 U4 FBA_MA7_MA8_H H4 U2
<27> FBA_MA1_MA9_H A9/A1 A11/A6 DQ0 DQ24 A10/A0 A8/A7 DQ1 DQ25
FBA_MA0_MA10_H H4 U2 FBA_MA1_MA9_H K5 T4 DATA Bus
<27> FBA_MA0_MA10_H A10/A0 A8/A7 DQ1 DQ25 A11/A6 A9/A1 DQ2 DQ26
FBA_MA6_MA11_H K5 T4 FBA_MA12_RFU_H J5 T2
<27> FBA_MA6_MA11_H A11/A6 A9/A1 DQ2 DQ26 A12/RFU/NC DQ3 DQ27
FBA_MA12_RFU_H J5 T2 N4 Address 0..31 32..63
<27> FBA_MA12_RFU_H A12/RFU/NC DQ3 DQ27 DQ4 DQ28
N4 A5 N2
A5 DQ4 DQ28 N2 +1.5VS_VGA U5 VPP/NC DQ5 DQ29 M4
VPP/NC DQ5 DQ29 VPP/NC DQ6 DQ30
FBx_CMD0 CS#
U5 M4 2 RV132 1 M2
2 RV131 1 VPP/NC DQ6 DQ30 M2 DQ7 DQ31
DQ7 DQ31
1K_0402_1%
+1.5VS_VGA
FBx_CMD1 A3_BA3
1K_0402_1% J1
J1 +1.5VS_VGA 2 RV134 1 J10 MF
MF SEN FBx_CMD2 A2_BA0
2 RV133 1 J10 2 RV136 1 1K_0402_1% J13 B1
2 RV135 1 J13 SEN B1 ZQ VDDQ D1
1K_0402_1%
ZQ VDDQ
121_0402_1%
VDDQ
FBx_CMD3 A4_BA2
121_0402_1% D1 F1
VDDQ F1 J4 VDDQ M1
Follow DG VDDQ
FBA_ABI#_H
ABI# VDDQ
FBx_CMD4 A5_BA1
FBA_ABI#_H J4 M1 FBA_CAS#_H G3 P1
<27> FBA_ABI#_H ABI# VDDQ RAS# CAS# VDDQ
FBA_RAS#_H G3 P1 FBA_WE#_H G12 T1 FBx_CMD5 WE#
<27> FBA_RAS#_H RAS# CAS# VDDQ CS# WE# VDDQ
FBA_CS#_H G12 T1 FBA_RAS#_H L3 G2
<27> FBA_CS#_H CS# WE# VDDQ CAS# RAS# VDDQ
FBA_CLK1 1 2 FBA_CAS#_H L3 G2 FBA_CS#_H L12 L2 FBx_CMD6 A7_A8
<27> FBA_CAS#_H CAS# RAS# VDDQ WE# CS# VDDQ
RV31 40.2_0402_1% FBA_WE#_H L12 L2 B3
<27> FBA_WE#_H WE# CS# VDDQ VDDQ
B3 D3 FBx_CMD7 A6_A11
VDDQ VDDQ
2

D3 F3
VDDQ F3 D5 VDDQ H3
RV139
VDDQ
FBA_WCK3_N
WCK01# WCK23# VDDQ
FBx_CMD8 ABI#
C 160_0402_1% FBA_WCK2_N D5 H3 FBA_WCK3 D4 K3 C
<27> FBA_WCK2_N WCK01# WCK23# VDDQ WCK01 WCK23 VDDQ
@ FBA_WCK2 D4 K3 M3 FBx_CMD9 A12_RFU
<27> FBA_WCK2 WCK01 WCK23 VDDQ VDDQ
M3 FBA_WCK2_N P5 P3
1

1 2 P5 VDDQ P3 P4 WCK23# WCK01# VDDQ T3

FBA_CLK1#
<27> FBA_WCK3_N
FBA_WCK3_N
WCK23# WCK01# VDDQ
FBA_WCK2
WCK23 WCK01 VDDQ
FBx_CMD10 A0_A10
RV36 40.2_0402_1% FBA_WCK3 P4 T3 E5
<27> FBA_WCK3 WCK23 WCK01 VDDQ VDDQ
E5 N5 FBx_CMD11 A1_A9
VDDQ N5 +FBA_VREFD_H A10 VDDQ E10
+FBA_VREFD_H A10 VDDQ E10 U10 VREFD VDDQ N10
CV175

FBx_CMD12 RAS#
0.01U_0402_25V7K

1 VREFD VDDQ VREFD VDDQ

U10 N10 +FBA_VREFC1 J14 B12
J14 VREFD VDDQ B12 VREFC VDDQ D12
+FBA_VREFC1
VREFC VDDQ VDDQ
FBx_CMD13 RST#
D12 F12
2 VDDQ F12 VDDQ H12
VDDQ VDDQ
FBx_CMD14 CKE#
H12 FBA_RST#_H J2 K12
J2 VDDQ K12 RESET# VDDQ M12
<27> FBA_RST#_H
FBA_RST#_H
RESET# VDDQ VDDQ
FBx_CMD15 CAS#
M12 P12
VDDQ P12 VDDQ T12
VDDQ VDDQ
FBx_CMD16 CS#
T12 G13
VDDQ G13 H1 VDDQ L13
VDDQ VSS VDDQ FBx_CMD17 A3_BA3
H1 L13 K1 B14
+1.5VS_VGA K1 VSS VDDQ B14 B5 VSS VDDQ D14
VSS VDDQ VSS VDDQ
FBx_CMD18 A2_BA0
B5 D14 G5 F14
G5 VSS VDDQ F14 L5 VSS VDDQ M14 FBx_CMD19 A4_BA2
1

L5 VSS VDDQ M14 T5 VSS VDDQ P14

T5 VSS VDDQ P14 B10 VSS VDDQ T14
RV143
VSS VDDQ VSS VDDQ
FBx_CMD20 A5_BA1
549_0402_1% B10 T14 D10
D10 VSS VDDQ G10 VSS
RV214 VSS VSS
FBx_CMD21 WE#
G10 L10 A1
2

1 2 +FBA_VREFC1 L10 VSS A1 P10 VSS VSSQ C1

VSS VSSQ VSS VSSQ FBx_CMD22 A7_A8
931_0402_1% 16 mil P10 C1 T10 E1
820P_0402_25V7

VSS VSSQ VSS VSSQ

1

T10 E1 H14 N1
CV59

1 VSS VSSQ VSS VSSQ

FBx_CMD23 A6_A11
RV144 H14 N1 K14 R1
K14 VSS VSSQ R1 +1.5VS_VGA VSS VSSQ U1
1.33K_0402_1%
+1.5VS_VGA VSS VSSQ VSSQ
FBx_CMD24 ABI#
U1 H2
2 VSSQ H2 G1 VSSQ K2 FBx_CMD25 A12_RFU
2

G1 VSSQ K2 L1 VDD VSSQ A3

L1 VDD VSSQ A3 G4 VDD VSSQ C3
VDD VSSQ VDD VSSQ
FBx_CMD26 A0_A10
G4 C3 L4 E3
L4 VDD VSSQ E3 C5 VDD VSSQ N3
B VDD VSSQ VDD VSSQ FBx_CMD27 A1_A9 B
C5 N3 R5 R3
R5 VDD VSSQ R3 C10 VDD VSSQ U3
VDD VSSQ VDD VSSQ
FBx_CMD28 RAS#
C10 U3 R10 C4
R10 VDD VSSQ C4 D11 VDD VSSQ R4
+1.5VS_VGA VDD VSSQ VDD VSSQ
FBx_CMD29 RST#
D11 R4 G11 F5
G11 VDD VSSQ F5 L11 VDD VSSQ M5
VDD VSSQ VDD VSSQ
FBx_CMD30 CKE#
L11 M5 P11 F10
VDD VSSQ VDD VSSQ
1

P11 F10 G14 M10 FBx_CMD31 CAS#

RV145 G14 VDD VSSQ M10 L14 VDD VSSQ C11
549_0402_1% L14 VDD VSSQ C11 VDD VSSQ R11
VDD VSSQ R11 VSSQ A12
RV215 VSSQ VSSQ
A12 C12
2

1 2 +FBA_VREFD_H VSSQ C12 VSSQ E12

931_0402_1% VSSQ E12 VSSQ N12
820P_0402_25V7

VSSQ VSSQ
1

N12 R12
CV60

1 VSSQ VSSQ
RV146 R12 170-BALL U12
VSSQ VSSQ
1

D 1.33K_0402_1% 170-BALL U12 H13

2 VSSQ H13 SGRAM GDDR5 VSSQ K13
<23,28,30,31> MEM_VREF G 2 SGRAM GDDR5 VSSQ K13 VSSQ A14
2

QV11 VSSQ A14 VSSQ C14

S
3

2N7002W-T/R7_SOT323-3 VSSQ C14 VSSQ E14

VSSQ E14 VSSQ N14
VSSQ N14 VSSQ R14
VSSQ R14 VSSQ U14
VSSQ U14 VSSQ
VSSQ X76@
X76@
+1.5VS_VGA UV5 SIDE H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
+1.5VS_VGA UV6 SIDE
1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6
10U_0603_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV84

CV81

CV82

CV83
CV179

CV138

CV142

CV137

2 1 1 1 1 1 1 1
1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6
10U_0603_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV187

CV145

CV143

CV144
CV87

CV88

CV85

CV86

2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2
A A
1 2 2 2 2 2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-VRAM A Upper
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, March 11, 2013 Sheet 29 of 65
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Lower 32 bits

UV7 UV8

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 FBC_D0 A4 FBC_D24
FBC_EDC0 C2 DQ24 DQ0 A2 FBC_D1 FBC_EDC3 C2 DQ24 DQ0 A2 FBC_D25
C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D2 C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D26
FBC_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D3 FBC_EDC1 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D27
<27> FBC_D[0..31] R2 EDC2 EDC1 DQ27 DQ3 E4
BYTE0 R2 EDC2 EDC1 DQ27 DQ3 E4
FBC_D4 FBC_D28 BYTE3
EDC3 EDC0 DQ28 DQ4 E2 FBC_D5 EDC3 EDC0 DQ28 DQ4 E2 FBC_D29
DQ29 DQ5 F4 FBC_D6 DQ29 DQ5 F4 FBC_D30
<27> FBC_EDC[3..0] FBC_DBI0# D2 DQ30 DQ6 F2 FBC_D7 FBC_DBI3# D2 DQ30 DQ6 F2 FBC_D31
D <27> FBC_DBI0# DBI0# DBI3# DQ31 DQ7 <27> FBC_DBI3# DBI0# DBI3# DQ31 DQ7 D
D13 A11 D13 A11
FBC_DBI2# P13 DBI1# DBI2# DQ16 DQ8 A13 FBC_DBI1# P13 DBI1# DBI2# DQ16 DQ8 A13
<27> FBC_DBI2# P2 DBI2# DBI1# DQ17 DQ9 B11 <27> FBC_DBI1# P2 DBI2# DBI1# DQ17 DQ9 B11
DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13
FBC_CLK0 J12 DQ19 DQ11 E11 FBC_CLK0 J12 DQ19 DQ11 E11
<27> FBC_CLK0 FBC_CLK0# J11 CK DQ20 DQ12 E13 FBC_CLK0# J11 CK DQ20 DQ12 E13
<27> FBC_CLK0#
<27> FBC_CKE_L
FBC_CKE_L J3 CK#
CKE#
DQ21
DQ22
DQ13
DQ14
F11 FBC_CKE_L J3 CK#
CKE#
DQ21
DQ22
DQ13
DQ14
F11 GDDR5
F13 F13
DQ23
DQ8
DQ15
DQ16
U11 FBC_D16 DQ23
DQ8
DQ15
DQ16
U11 FBC_D8 Mode H - Mirror Mode Mapping
FBC_MA2_BA0_L H11 U13 FBC_D17 FBC_MA4_BA2_L H11 U13 FBC_D9
<27> FBC_MA2_BA0_L FBC_MA5_BA1_L K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBC_D18 FBC_MA3_BA3_L K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBC_D10
<27> FBC_MA5_BA1_L FBC_MA4_BA2_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D19 FBC_MA2_BA0_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D11
<27> FBC_MA4_BA2_L BA2/A4 BA0/A2 DQ11 DQ19 BA2/A4 BA0/A2 DQ11 DQ19 BYTE1 DATA Bus
FBC_MA3_BA3_L H10 N11 FBC_D20 BYTE2 FBC_MA5_BA1_L H10 N11 FBC_D12
<27> FBC_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D21 BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D13 Address 0..31 32..63
DQ13 DQ21 M11 FBC_D22 DQ13 DQ21 M11 FBC_D14
FBC_MA7_MA8_L K4 DQ14 DQ22 M13 FBC_D23 FBC_MA0_MA10_L K4 DQ14 DQ22 M13 FBC_D15
<27> FBC_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 A8/A7 A10/A0 DQ15 DQ23 FBx_CMD0 CS#
FBC_MA1_MA9_L H5 U4 FBC_MA6_MA11_L H5 U4
<27> FBC_MA1_MA9_L FBC_MA0_MA10_L H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBC_MA7_MA8_L H4 A9/A1 A11/A6 DQ0 DQ24 U2
<27> FBC_MA0_MA10_L A10/A0 A8/A7 DQ1 DQ25 A10/A0 A8/A7 DQ1 DQ25 FBx_CMD1 A3_BA3
FBC_MA6_MA11_L K5 T4 FBC_MA1_MA9_L K5 T4
<27> FBC_MA6_MA11_L FBC_MA12_RFU_L J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBC_MA12_RFU_L J5 A11/A6 A9/A1 DQ2 DQ26 T2
<27> FBC_MA12_RFU_L A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27 FBx_CMD2 A2_BA0
N4 N4
A5 DQ4 DQ28 N2 A5 DQ4 DQ28 N2
VPP/NC DQ5 DQ29 +1.5VS_VGA VPP/NC DQ5 DQ29 FBx_CMD3 A4_BA2
U5 M4 U5 M4
2 RV147 1 VPP/NC DQ6 DQ30 M2 2 RV148 1 VPP/NC DQ6 DQ30 M2
DQ7 DQ31 DQ7 DQ31 FBx_CMD4 A5_BA1
1K_0402_1% 1K_0402_1%
J1 +1.5VS_VGA J1 +1.5VS_VGA FBx_CMD5 WE#
2 RV149 1 J10 MF 2 RV150 1 J10 MF
2 RV151 1 J13 SEN B1 2 RV152 1 J13 SEN B1
1K_0402_1%
ZQ VDDQ
1K_0402_1%
ZQ VDDQ FBx_CMD6 A7_A8
121_0402_1% D1 121_0402_1% D1
VDDQ F1 VDDQ F1
VDDQ VDDQ FBx_CMD7 A6_A11
Follow DG FBC_ABI#_L J4 M1 FBC_ABI#_L J4 M1
<27> FBC_ABI#_L FBC_RAS#_L G3 ABI# VDDQ P1 FBC_CAS#_L G3 ABI# VDDQ P1
<27> FBC_RAS#_L RAS# CAS# VDDQ RAS# CAS# VDDQ FBx_CMD8 ABI#
FBC_CS#_L G12 T1 FBC_WE#_L G12 T1
FBC_CLK0 1 2 <27> FBC_CS#_L FBC_CAS#_L L3 CS# WE# VDDQ G2 FBC_RAS#_L L3 CS# WE# VDDQ G2
<27> FBC_CAS#_L CAS# RAS# VDDQ CAS# RAS# VDDQ FBx_CMD9 A12_RFU
RV37 40.2_0402_1% FBC_WE#_L L12 L2 FBC_CS#_L L12 L2
<27> FBC_WE#_L WE# CS# VDDQ B3 WE# CS# VDDQ B3
VDDQ VDDQ FBx_CMD10 A0_A10
2

C
D3 D3 C
VDDQ F3 VDDQ F3
RV155
VDDQ VDDQ FBx_CMD11 A1_A9
160_0402_1% FBC_WCK0_N D5 H3 FBC_WCK1_N D5 H3
<27> FBC_WCK0_N FBC_WCK0 D4 WCK01# WCK23# VDDQ K3 FBC_WCK1 D4 WCK01# WCK23# VDDQ K3
@
<27> FBC_WCK0 WCK01 WCK23 VDDQ WCK01 WCK23 VDDQ FBx_CMD12 RAS#
M3 M3
1

FBC_CLK0# 1 2 FBC_WCK1_N P5 VDDQ P3 FBC_WCK0_N P5 VDDQ P3

<27> FBC_WCK1_N WCK23# WCK01# VDDQ WCK23# WCK01# VDDQ FBx_CMD13 RST#
RV39 40.2_0402_1% FBC_WCK1 P4 T3 FBC_WCK0 P4 T3
<27> FBC_WCK1 WCK23 WCK01 VDDQ E5 WCK23 WCK01 VDDQ E5
VDDQ VDDQ FBx_CMD14 CKE#
N5 N5
VDDQ VDDQ
CV195
0.01U_0402_25V7K

1 +FBC_VREFD_L A10 E10 +FBC_VREFD_L A10 E10 FBx_CMD15 CAS#

U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
+FBC_VREFC0 J14 VREFD VDDQ B12 +FBC_VREFC0 J14 VREFD VDDQ B12
VREFC VDDQ VREFC VDDQ FBx_CMD16 CS#
D12 D12
2 VDDQ F12 VDDQ F12
VDDQ VDDQ FBx_CMD17 A3_BA3
H12 H12
FBC_RST#_L J2 VDDQ K12 FBC_RST#_L J2 VDDQ K12
<27> FBC_RST#_L RESET# VDDQ RESET# VDDQ FBx_CMD18 A2_BA0
M12 M12
VDDQ P12 VDDQ P12
VDDQ VDDQ FBx_CMD19 A4_BA2
T12 T12
+1.5VS_VGA VDDQ G13 VDDQ G13
VDDQ VDDQ FBx_CMD20 A5_BA1
H1 L13 H1 L13
K1 VSS VDDQ B14 K1 VSS VDDQ B14
VSS VDDQ VSS VDDQ FBx_CMD21 WE#
1

B5 D14 B5 D14
G5 VSS VDDQ F14 G5 VSS VDDQ F14
RV159
VSS VDDQ VSS VDDQ FBx_CMD22 A7_A8
549_0402_1% L5 M14 L5 M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
RV216 VSS VDDQ VSS VDDQ FBx_CMD23 A6_A11
B10 T14 B10 T14
2

1 2 +FBC_VREFC0 D10 VSS VDDQ D10 VSS VDDQ

VSS VSS FBx_CMD24 ABI#
820P_0402_25V7

931_0402_1% G10 G10

VSS VSS
1

CV61

1 L10 A1 L10 A1 FBx_CMD25 A12_RFU

RV160 P10 VSS VSSQ C1 P10 VSS VSSQ C1
T10 VSS VSSQ E1 T10 VSS VSSQ E1
1.33K_0402_1%
VSS VSSQ VSS VSSQ FBx_CMD26 A0_A10
H14 N1 H14 N1
2 K14 VSS VSSQ R1 K14 VSS VSSQ R1 FBx_CMD27 A1_A9
2

+1.5VS_VGA VSS VSSQ U1 +1.5VS_VGA VSS VSSQ U1

VSSQ H2 VSSQ H2
VSSQ VSSQ FBx_CMD28 RAS#
G1 K2 G1 K2
L1 VDD VSSQ A3 L1 VDD VSSQ A3
B VDD VSSQ VDD VSSQ FBx_CMD29 RST# B
G4 C3 G4 C3
L4 VDD VSSQ E3 L4 VDD VSSQ E3
VDD VSSQ VDD VSSQ FBx_CMD30 CKE#
C5 N3 C5 N3
R5 VDD VSSQ R3 R5 VDD VSSQ R3
+1.5VS_VGA VDD VSSQ VDD VSSQ FBx_CMD31 CAS#
C10 U3 C10 U3
R10 VDD VSSQ C4 R10 VDD VSSQ C4
D11 VDD VSSQ R4 D11 VDD VSSQ R4
VDD VSSQ VDD VSSQ
1

G11 F5 G11 F5
RV161 L11 VDD VSSQ M5 L11 VDD VSSQ M5
549_0402_1% P11 VDD VSSQ F10 P11 VDD VSSQ F10
G14 VDD VSSQ M10 G14 VDD VSSQ M10
RV217 L14 VDD VSSQ C11 L14 VDD VSSQ C11
2

1 2 +FBC_VREFD_L VDD VSSQ R11 VDD VSSQ R11

VSSQ VSSQ
820P_0402_25V7

931_0402_1% A12 A12

VSSQ VSSQ
1

CV62

1 C12 C12
RV162 VSSQ E12 VSSQ E12
1.33K_0402_1% VSSQ N12 VSSQ N12
VSSQ R12 VSSQ R12
VSSQ VSSQ
1

D 2 170-BALL U12 170-BALL U12

2

2 VSSQ H13 VSSQ H13

<23,28,29,31> MEM_VREF G SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
QV13 VSSQ A14 VSSQ A14
S
3

2N7002W-T/R7_SOT323-3 VSSQ C14 VSSQ C14

VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 +1.5VS_VGA VSSQ U14
VSSQ UV8 SIDE VSSQ
X76@ X76@
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
+1.5VS_VGA UV7 SIDE
CV95

CV96

CV93

CV94
CV207

CV163

CV161

CV162
H5GQ1H24AFR-T2L_BGA170 2 1 1 1 1 1 1 1 H5GQ1H24AFR-T2L_BGA170
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV91

CV92

CV89

CV90
CV199

CV160

CV157

CV159

2 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2

A A
1 2 2 2 2 2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-VRAM C Lower
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, March 11, 2013 Sheet 30 of 65
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits

UV9

MF=0 MF=1 MF=1 MF=0 UV10

A4 FBC_D32 MF=0 MF=1 MF=1 MF=0

FBC_EDC4 C2 DQ24 DQ0 A2 FBC_D33
C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D34 A4 FBC_D56
FBC_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D35 FBC_EDC7 C2 DQ24 DQ0 A2 FBC_D57
<27> FBC_D[63..32] R2 EDC2 EDC1 DQ27 DQ3 E4
BYTE4 C13 EDC0 EDC3 DQ25 DQ1 B4
FBC_D36 FBC_D58
EDC3 EDC0 DQ28 DQ4 E2 FBC_D37 FBC_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D59
DQ29 DQ5 F4 FBC_D38 R2 EDC2 EDC1 DQ27 DQ3 E4 FBC_D60
<27> FBC_EDC[7..4] D2 DQ30 DQ6 F2 EDC3 EDC0 DQ28 DQ4 E2
BYTE7
FBC_DBI4# FBC_D39 FBC_D61
<27> FBC_DBI4# D13 DBI0# DBI3# DQ31 DQ7 A11 DQ29 DQ5 F4 FBC_D62
D DBI1# DBI2# DQ16 DQ8 DQ30 DQ6 D
FBC_DBI6# P13 A13 FBC_DBI7# D2 F2 FBC_D63
<27> FBC_DBI6# P2 DBI2#
DBI3#
DBI1#
DBI0#
DQ17
DQ18
DQ9
DQ10
B11 <27> FBC_DBI7# D13 DBI0#
DBI1#
DBI3#
DBI2#
DQ31
DQ16
DQ7
DQ8
A11 GDDR5
B13 FBC_DBI5# P13 A13
<27> FBC_CLK1
FBC_CLK1 J12
CK
DQ19
DQ20
DQ11
DQ12
E11 <27> FBC_DBI5# P2 DBI2#
DBI3#
DBI1#
DBI0#
DQ17
DQ18
DQ9
DQ10
B11 Mode H - Mirror Mode Mapping
FBC_CLK1# J11 E13 B13
<27> FBC_CLK1# FBC_CKE_H J3 CK# DQ21 DQ13 F11 FBC_CLK1 J12 DQ19 DQ11 E11
<27> FBC_CKE_H CKE# DQ22 DQ14 F13 FBC_CLK1# J11 CK DQ20 DQ12 E13
DQ23 DQ15 CK# DQ21 DQ13 DATA Bus
U11 FBC_D48 FBC_CKE_H J3 F11
FBC_MA2_BA0_H H11 DQ8 DQ16 U13 FBC_D49 CKE# DQ22 DQ14 F13 Address
<27> FBC_MA2_BA0_H BA0/A2 BA2/A4 DQ9 DQ17 DQ23 DQ15 0..31 32..63
FBC_MA5_BA1_H K10 T11 FBC_D50 U11 FBC_D40
<27> FBC_MA5_BA1_H FBC_MA4_BA2_H K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D51 FBC_MA4_BA2_H H11 DQ8 DQ16 U13 FBC_D41
<27> FBC_MA4_BA2_H BA2/A4 BA0/A2 DQ11 DQ19 BA0/A2 BA2/A4 DQ9 DQ17 FBx_CMD0 CS#
FBC_MA3_BA3_H H10 N11 FBC_D52 BYTE6 FBC_MA3_BA3_H K10 T11 FBC_D42
<27> FBC_MA3_BA3_H BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D53 FBC_MA2_BA0_H K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D43
DQ13 DQ21 BA2/A4 BA0/A2 DQ11 DQ19 BYTE5 FBx_CMD1 A3_BA3
M11 FBC_D54 FBC_MA5_BA1_H H10 N11 FBC_D44
FBC_MA7_MA8_H K4 DQ14 DQ22 M13 FBC_D55 BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D45
<27> FBC_MA7_MA8_H A8/A7 A10/A0 DQ15 DQ23 DQ13 DQ21 FBx_CMD2 A2_BA0
FBC_MA1_MA9_H H5 U4 M11 FBC_D46
<27> FBC_MA1_MA9_H FBC_MA0_MA10_H H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBC_MA0_MA10_H K4 DQ14 DQ22 M13 FBC_D47
<27> FBC_MA0_MA10_H A10/A0 A8/A7 DQ1 DQ25 A8/A7 A10/A0 DQ15 DQ23 FBx_CMD3 A4_BA2
FBC_MA6_MA11_H K5 T4 FBC_MA6_MA11_H H5 U4
<27> FBC_MA6_MA11_H FBC_MA12_RFU_H J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBC_MA7_MA8_H H4 A9/A1 A11/A6 DQ0 DQ24 U2
<27> FBC_MA12_RFU_H A12/RFU/NC DQ3 DQ27 A10/A0 A8/A7 DQ1 DQ25 FBx_CMD4 A5_BA1
N4 FBC_MA1_MA9_H K5 T4
A5 DQ4 DQ28 N2 FBC_MA12_RFU_H J5 A11/A6 A9/A1 DQ2 DQ26 T2
VPP/NC DQ5 DQ29 A12/RFU/NC DQ3 DQ27 FBx_CMD5 WE#
U5 M4 N4
2 RV163 1 VPP/NC DQ6 DQ30 M2 A5 DQ4 DQ28 N2
DQ7 DQ31 +1.5VS_VGA VPP/NC DQ5 DQ29 FBx_CMD6 A7_A8
1K_0402_1% U5 M4
J1 +1.5VS_VGA 2 RV164 1 VPP/NC DQ6 DQ30 M2
MF DQ7 DQ31 FBx_CMD7 A6_A11
2 RV165 1 J10 1K_0402_1%
2 RV167 1 J13 SEN B1 J1 +1.5VS_VGA
1K_0402_1%
ZQ VDDQ MF FBx_CMD8 ABI#
121_0402_1% D1 2 RV166 1 J10
VDDQ F1 2 RV168 1 J13 SEN B1
VDDQ
1K_0402_1%
ZQ VDDQ FBx_CMD9 A12_RFU
Follow DG FBC_ABI#_H J4 M1 121_0402_1% D1
<27> FBC_ABI#_H FBC_RAS#_H G3 ABI# VDDQ P1 VDDQ F1
<27> FBC_RAS#_H RAS# CAS# VDDQ VDDQ FBx_CMD10 A0_A10
FBC_CS#_H G12 T1 FBC_ABI#_H J4 M1
FBC_CLK1 1 2 <27> FBC_CS#_H FBC_CAS#_H L3 CS# WE# VDDQ G2 FBC_CAS#_H G3 ABI# VDDQ P1
<27> FBC_CAS#_H CAS# RAS# VDDQ RAS# CAS# VDDQ FBx_CMD11 A1_A9
RV41 40.2_0402_1% FBC_WE#_H L12 L2 FBC_WE#_H G12 T1
<27> FBC_WE#_H WE# CS# VDDQ B3 FBC_RAS#_H L3 CS# WE# VDDQ G2
VDDQ CAS# RAS# VDDQ FBx_CMD12 RAS#
2

D3 FBC_CS#_H L12 L2
VDDQ F3 WE# CS# VDDQ B3
C RV171
VDDQ VDDQ FBx_CMD13 RST# C
160_0402_1% FBC_WCK2_N D5 H3 D3
<27> FBC_WCK2_N FBC_WCK2 D4 WCK01# WCK23# VDDQ K3 VDDQ F3
@
<27> FBC_WCK2 WCK01 WCK23 VDDQ VDDQ FBx_CMD14 CKE#
M3 FBC_WCK3_N D5 H3
1

FBC_CLK1# 1 2 FBC_WCK3_N P5 VDDQ P3 FBC_WCK3 D4 WCK01# WCK23# VDDQ K3

<27> FBC_WCK3_N WCK23# WCK01# VDDQ WCK01 WCK23 VDDQ FBx_CMD15 CAS#
RV48 40.2_0402_1% FBC_WCK3 P4 T3 M3
<27> FBC_WCK3 WCK23 WCK01 VDDQ E5 FBC_WCK2_N P5 VDDQ P3
VDDQ WCK23# WCK01# VDDQ FBx_CMD16 CS#
N5 FBC_WCK2 P4 T3
VDDQ WCK23 WCK01 VDDQ
CV215
0.01U_0402_25V7K

1 +FBC_VREFD_H A10 E10 E5 FBx_CMD17 A3_BA3

U10 VREFD VDDQ N10 VDDQ N5
+FBC_VREFC1 J14 VREFD VDDQ B12 +FBC_VREFD_H A10 VDDQ E10
VREFC VDDQ VREFD VDDQ FBx_CMD18 A2_BA0
D12 U10 N10
2 VDDQ F12 +FBC_VREFC1 J14 VREFD VDDQ B12
VDDQ VREFC VDDQ FBx_CMD19 A4_BA2
H12 D12
FBC_RST#_H J2 VDDQ K12 VDDQ F12
<27> FBC_RST#_H RESET# VDDQ VDDQ FBx_CMD20 A5_BA1
M12 H12
VDDQ P12 FBC_RST#_H J2 VDDQ K12
VDDQ RESET# VDDQ FBx_CMD21 WE#
T12 M12
+1.5VS_VGA VDDQ G13 VDDQ P12
VDDQ VDDQ FBx_CMD22 A7_A8
H1 L13 T12
K1 VSS VDDQ B14 VDDQ G13
VSS VDDQ VDDQ FBx_CMD23 A6_A11
1

B5 D14 H1 L13
G5 VSS VDDQ F14 K1 VSS VDDQ B14
RV175
VSS VDDQ VSS VDDQ FBx_CMD24 ABI#
549_0402_1% L5 M14 B5 D14
T5 VSS VDDQ P14 G5 VSS VDDQ F14
RV218 VSS VDDQ VSS VDDQ FBx_CMD25 A12_RFU
B10 T14 L5 M14
2

1 2 +FBC_VREFC1 D10 VSS VDDQ T5 VSS VDDQ P14

VSS VSS VDDQ FBx_CMD26 A0_A10
820P_0402_25V7

931_0402_1% G10 B10 T14

VSS VSS VDDQ
1

CV63

1 L10 A1 D10 FBx_CMD27 A1_A9

RV176 P10 VSS VSSQ C1 G10 VSS
T10 VSS VSSQ E1 L10 VSS A1
1.33K_0402_1%
VSS VSSQ VSS VSSQ FBx_CMD28 RAS#
H14 N1 P10 C1
2 K14 VSS VSSQ R1 T10 VSS VSSQ E1 FBx_CMD29 RST#
2

+1.5VS_VGA VSS VSSQ U1 H14 VSS VSSQ N1

VSSQ H2 K14 VSS VSSQ R1
VSSQ +1.5VS_VGA VSS VSSQ FBx_CMD30 CKE#
G1 K2 U1
L1 VDD VSSQ A3 VSSQ H2
VDD VSSQ VSSQ FBx_CMD31 CAS#
B
G4 C3 G1 K2 B
L4 VDD VSSQ E3 L1 VDD VSSQ A3
C5 VDD VSSQ N3 G4 VDD VSSQ C3
+1.5VS_VGA R5 VDD VSSQ R3 L4 VDD VSSQ E3
C10 VDD VSSQ U3 C5 VDD VSSQ N3
R10 VDD VSSQ C4 R5 VDD VSSQ R3
VDD VSSQ VDD VSSQ
1

D11 R4 C10 U3
RV177 G11 VDD VSSQ F5 R10 VDD VSSQ C4
549_0402_1% L11 VDD VSSQ M5 D11 VDD VSSQ R4
P11 VDD VSSQ F10 G11 VDD VSSQ F5
RV219 G14 VDD VSSQ M10 L11 VDD VSSQ M5
2

1 2 +FBC_VREFD_H L14 VDD VSSQ C11 P11 VDD VSSQ F10

VDD VSSQ VDD VSSQ
820P_0402_25V7

931_0402_1% R11 G14 M10

VSSQ VDD VSSQ
1

CV64

1 A12 L14 C11

RV178 VSSQ C12 VDD VSSQ R11
1.33K_0402_1% VSSQ E12 VSSQ A12
VSSQ N12 VSSQ C12
VSSQ VSSQ
1

D 2 R12 E12
2

2 170-BALL VSSQ U12 VSSQ N12

<23,28,29,30> MEM_VREF G VSSQ H13 VSSQ R12
QV15 SGRAM GDDR5 VSSQ K13 170-BALL VSSQ U12
S
3

2N7002W-T/R7_SOT323-3 VSSQ A14 VSSQ H13

VSSQ C14 SGRAM GDDR5 VSSQ K13
VSSQ E14 VSSQ A14
VSSQ N14 VSSQ C14
VSSQ R14 VSSQ E14
VSSQ U14 VSSQ N14
VSSQ +1.5VS_VGA VSSQ R14
UV10 SIDE VSSQ U14
X76@
+1.5VS_VGA VSSQ
UV9 SIDE
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
H5GQ1H24AFR-T2L_BGA170 X76@
CV227

CV103

CV104

CV101

CV102

CV170

CV168

CV169
2 1 1 1 1 1 1 1
10U_0603_6.3V6M

1U_0603_25V6
1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

H5GQ1H24AFR-T2L_BGA170
CV245

CV100

CV167

CV164

CV165
CV99

CV97

CV98

2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2

1 2 2 2 2 2 2 2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 N13P-VRAM C Upper
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, March 11, 2013 Sheet 31 of 65
5 4 3 2 1
 5 4 3 2 1

PCIE_CTX_GRX_N[0..15]
<23,5> PCIE_CTX_GRX_N[0..15]
11/11 for 2nd VGA fan PCIE_CTX_GRX_P[0..15]
need to notic EC <23,5> PCIE_CTX_GRX_P[0..15]
PCIE_CRX_GTX_N[0..15]
D <23,5> PCIE_CRX_GTX_N[0..15] D
PCIE_CRX_GTX_P[0..15]
<23,5> PCIE_CRX_GTX_P[0..15] B+_SLI
follow MXM 3.0 spec

JSLI1

1 2
3 GND GND 4
5 NC GND 6
7 NC GND 8
9 NC GND 10
11 NC +19V 12
13 NC +19V 14
15 NC +19V 16
17 NC +19V 18
PCIE_CTX_GRX_N15 19 GND +19V 20
PCIE_CTX_GRX_P15 21 PEG_RX_N7 +19V 22
PEG_RX_P7 +19V
23 24
PCIE_CTX_GRX_N14 25 GND +19V 26
PCIE_CTX_GRX_P14 27 PEG_RX_N6 GND 28 +5VS_SLI
29 PEG_RX_P6 GND 30
31 GND GND 32
PCIE_CTX_GRX_N13 33 GND GND 34
PCIE_CTX_GRX_P13 35 PEG_RX_N5 GND 36
37 PEG_RX_P5 GND 38
PCIE_CTX_GRX_N12 39 GND +5V 40
PCIE_CTX_GRX_P12 41 PEG_RX_N4 +5V 42
C 43 PEG_RX_P4 +5V 44 C
PCIE_CTX_GRX_N11 45 GND +5V 46
PCIE_CTX_GRX_P11 47 PEG_RX_N3 +5V 48
49 PEG_RX_P3 GND 50
PCIE_CTX_GRX_N10 51 GND GND 52
PCIE_CTX_GRX_P10 53 PEG_RX_N2 GND
PEG_RX_P2 +3VS_SLI
55 54
PCIE_CTX_GRX_N9 57 GND NC 56
PCIE_CTX_GRX_P9 59 PEG_RX_N1 +3V 58
61 PEG_RX_P1 +3V 60 +3VS
PCIE_CTX_GRX_N8 63 GND GND 62
PCIE_CTX_GRX_P8 65 PEG_RX_N0 NC 64
67 PEG_RX_P0 NC 66 SLI_B+_ON#
GND NC SLI_B+_ON# <52>
69 68 SLI_5V_ON#
GND NC SLI_5V_ON# <52>
PCIE_CRX_GTX_N15 0.22U_0402_10V6K 2 1 SLI@ CV20 PCIE_CRX_C_GTX_N15 71 70 SUSP#
PEG_TX_N7 NC SUSP# <45,51,55,57>
PCIE_CRX_GTX_P15 0.22U_0402_10V6K 2 1 SLI@ CV22 PCIE_CRX_C_GTX_P15 73 72
75 PEG_TX_P7 NC 74 SLI_FAN_SPEED
GND TH_TACH SLI_FAN_SPEED <41,45>
PCIE_CRX_GTX_N14 0.22U_0402_10V6K 2 1 SLI@ CV16 PCIE_CRX_C_GTX_N14 77 76 SLI_FAN_PWM SLI_FAN_PWM <41,45>
PCIE_CRX_GTX_P14 0.22U_0402_10V6K 2 1 SLI@ CV18 PCIE_CRX_C_GTX_P14 79 PEG_TX_N6 TH_PWN 78
81 PEG_TX_P6 NC 80
PCIE_CRX_GTX_N13 0.22U_0402_10V6K 2 1 SLI@ CV19 PCIE_CRX_C_GTX_N13 83 GND PEX_STD_SW# 82 VGA_AC_DET_R
PEG_TX_N5 AC_DC VGA_AC_DET_R <23>
PCIE_CRX_GTX_P13 0.22U_0402_10V6K 2 1 SLI@ CV14 PCIE_CRX_C_GTX_P13 85 84 S_DGPU_PWROK
PEG_TX_P5 PWR_GOOD S_DGPU_PWROK <19>
87 86 S_DGPU_PWR_EN# S_DGPU_PWR_EN# <51>
PCIE_CRX_GTX_N12 0.22U_0402_10V6K 2 1 SLI@ CV15 PCIE_CRX_C_GTX_N12 89 GND PWR_EN 88 CLK2_REQ_GPU#_R
PEG_TX_N4 CLK_REQ# CLK2_REQ_GPU#_R <15>
PCIE_CRX_GTX_P12 0.22U_0402_10V6K 2 1 SLI@ CV17 PCIE_CRX_C_GTX_P12 91 90 S_NVDD_PWR_EN
PEG_TX_P4 RSVD S_NVDD_PWR_EN <19>
93 92 S_DGPU_RST S_DGPU_RST <15,18>
PCIE_CRX_GTX_N11 0.22U_0402_10V6K 2 1 SLI@ CV12 PCIE_CRX_C_GTX_N11 95 GND RSVD 94 SLAVE_PRESENT#
PEG_TX_N3 NC SLAVE_PRESENT# <19>
PCIE_CRX_GTX_P11 0.22U_0402_10V6K 2 1 SLI@ CV13 PCIE_CRX_C_GTX_P11 97 96 PCH_THRMTRIP#_R PCH_THRMTRIP#_R <19,23>
99 PEG_TX_P3 TH_OVERT# 98 PLT_RST#
GND NC PLT_RST# <18,23,37,38,44,45,6> 1
PCIE_CRX_GTX_N10 0.22U_0402_10V6K 2 1 SLI@ CV10 PCIE_CRX_C_GTX_N10 101 100 GC6_EVENT_SLI# RV158 1 @ 2 0_0402_5% CV177
PEG_TX_N2 RSVD GC6_EVENT# <19,23,45>
PCIE_CRX_GTX_P10 0.22U_0402_10V6K 2 1 SLI@ CV11 PCIE_CRX_C_GTX_P10 103 102 EC_SMB_DA2 0.01U_0402_25V7K
B PEG_TX_P2 SMB_DAT EC_SMB_DA2 <15,23,40,45> B
105 104 EC_SMB_CK2 Close to SLI connector
GND SMB_CLK EC_SMB_CK2 <15,23,40,45> 2
PCIE_CRX_GTX_N9 0.22U_0402_10V6K 2 1 SLI@ CV8 PCIE_CRX_C_GTX_N9 107 106
PCIE_CRX_GTX_P9 0.22U_0402_10V6K 2 1 SLI@ CV9 PCIE_CRX_C_GTX_P9 109 PEG_TX_N1 WAKE# 108 GC6_EN
111 PEG_TX_P1 RSVD 110 S_DGPU_PWR_EN
GND RSVD S_DGPU_PWR_EN <19,51>
PCIE_CRX_GTX_N8 0.22U_0402_10V6K 2 1 SLI@ CV6 PCIE_CRX_C_GTX_N8 113 112
PCIE_CRX_GTX_P8 0.22U_0402_10V6K 2 1 SLI@ CV7 PCIE_CRX_C_GTX_P8 115 PEG_TX_N0 GND 114 CLK_PCIE_2VGA#
PEG_TX_P0 CLK_PCIE_N CLK_PCIE_2VGA# <15>
117 116 CLK_PCIE_2VGA
GND CLK_PCIE_P CLK_PCIE_2VGA <15>
118
GND
119 120
121 GND GND 122 GC6_EN <27>
GND GND

TE_2199022-1_118P-T ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 2ND VGA CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, March 11, 2013 Sheet 32 of 65
5 4 3 2 1
 5 4 3 2 1

+3VS_VGA
Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE

2
RV92 RV93 RV94 RV121 RV122 STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
45.3K_0402_1% 4.99K_0402_1% 24.9K_0402_1% 4.99K_0402_1% 20K_0402_1%
D
@ @ @ STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0] D

1
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
<24> STRAP0 STRAP0
<24> STRAP1 STRAP1 STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
<24> STRAP2 STRAP2
<24> STRAP3 STRAP3 STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
<24> STRAP4 STRAP4 CHANGE_GEN3
2

2
@ Pull-up to
@ RV95 RV96 RV97 RV124 RV125 Resistor Values Pull-down to Gnd
SLOT_CLK_CFG
+3VS_VGA
45.3K_0402_1% 4.99K_0402_1% 24.9K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
5K 1000 0000 0 GPU and MCH don't share a common reference clock
1

1
10K 1001 0001
1 GPU and MCH share a common reference clock (Default)
15K 1010 0010
20K 1011 0011
25K 1100 0100 SUB_VENDOR
30K 1101 0101
0 No VBIOS ROM (Default)
35K 1110 0110
C C
+3VS_VGA 45K 1
1111 0111 BIOS ROM is present

3GIO_PADCFG XCLK_417 USER Straps

2

RV98 RV99 RV100 3GIO_PADCFG[3:0] 0 277MHz (Default) User[3:0]

4.99K_0402_1% 10K_0402_1% 4.99K_0402_1%
@ @
2012-0418 --> Set BOM 0000 Notebook Default 1 Reserved 1000-1100 Customer defined
1

structure as Stuff for ALL SKU

<24> ROM_SI ROM_SI PEX_PLL_EN_TERM PCIE_MAX_SPEED FB_0_BAR_SIZE

<24> ROM_SO ROM_SO
<24> ROM_SCLK ROM_SCLK 0 Disable (Default) 0 Limit to PCIE Gen1 0 Reserved
2

1 Enable 1 PCIE Gen 2/3 Capable 1 Reserved

2

RV101
X76 20K_0402_1% RV102 RV103
X76@ 2 256MB (Default)
30K_0402_1%
@
15K_0402_1% SMBUS_ALT_ADDR VGA_DEVICE
1

0 0x9E (Default) 0 3D Device (Class Code 302h) 3 Reserved

B B

1 0x9C (Multi-GPU usage) 1 VGA Device (Default)

X76

GPU FB Memory (GDDR5) ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 VRAM X76 VRAM P/N

K4G20325FD-FC04 2G 64Mx32 PD 30K X76409JVL01 (2G 64Mx32) SA00005B70J

Samsung Samsung
K4G10325FG-HC04 1G 32Mx32 PD 45K PU 35K X76409JVL51 (1G 32Mx16) SA00003RS0J
N13P-GT1 PU 10K (ALL SKU) PU 45K PD 5K PD 25K PU 5K PD 45K
28nm EOL
H5GQ2H24MFR-T2C 2G 64Mx32 PD 25K X76409JVL02 (2G 64Mx32) SA00004GD0J EOL

Hynix H5GQ1H24BFR-T2C 1G 32Mx32 PD 20K Hynix X76409JVL02 (2G 64Mx32) SA00004GD1J

A A

H5GQ2H24AFR-T2C 2G 64Mx32 PD 5K X76409JVL52 (1G 32Mx16) SA00003WL1J

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P_MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 33 of 65
5 4 3 2 1
 5 4 3 2 1

+LEDVDD B+
2A 80 mil 2A 80 mil
+CMOS_PW

+LCDVDD_CONN
1 R813 2 CMOS Camera
+LEDVDD
1 1 R_short 0_0805_5% Q94 AO3413_SOT23-3 R432
JLVDS1ME@ C523 W=40mils
(40 MIL) 0_0603_5%
LVDS_A0#_CONN 1 2 470P_0603_50V8J C524 3 1 1 2

D
1 2 +CMOS_PW_R
LVDS_A0_CONN 3 4 4.7U_0805_25V6-K +3VS
3 4 2 2 1 CMOS@ 1
LVDS_A1#_CONN 5 6 9/23 EMI Request

10U_0603_6.3V6M
C519
5 6 W=60mils CMOS@ CMOS@
LVDS_A1_CONN 7 8
C518

G
9 7 8 10

2
LVDS_A2#_CONN 1 1
9 10 C1051 CMOS@ C1052 CMOS@ 0.1U_0402_16V4Z
LVDS_A2_CONN 11 12 2 2 @
11 12 +3VS 0.1U_0402_16V4Z
LVDS_ACLK#_CONN 13 14
15 13 14 16 @ 0.01U_0402_16V7K
LVDS_ACLK_CONN R822 2 1 4.7K_0402_5%
+3VS 1
17 15 16 18 2 2
@
19 17 18 20 DISPOFF# R891 2 1 R_short 0_0402_5% BKOFF# 680P_0402_50V7K
D 19 20 BKOFF# <45> CMOS@ D
<45> ECR_EN 21 22 INVPWM C528 1 R435 2
23 21 22 24 EDID_DATA_CONN 2 <45> CMOS_ON#
25 23 24 26 EDID_CLK_CONN 100K_0402_5% 1
27 25 26 28 C520
27 28 @
29 30 0.1U_0402_16V4Z
29 30
2
31 32
GNDGND

<17> EDID_CLK EDID_CLK R1210 1 2 EDID_CLK_CONN

0_0402_5% OPT@

VGA_EDID_CLK R1199 1 2
<23> VGA_EDID_CLK
0_0402_5% SLI@

<17> EDID_DATA EDID_DATA R1211 1 2 EDID_DATA_CONN

0_0402_5% OPT@

<23> VGA_EDID_DATA VGA_EDID_DATA R1200 1 2

0_0402_5% SLI@

2 @ 1 R1515
EC_INVT_PWM <45>
0_0402_5%

INVPWM 2 SLI@ 1 R824

VGA_BL_PWM <23>
0_0402_5%
C C
2 OPT@ 1 R847
PCH_PWM <17>
C58 For RF request
0_0402_5% @
2 1
20120806 --> change to 0-ohm normal symbol
0.047U_0402_16V4Z
20120807 -->
1. R1515 change to "@",
2. R824 change to "SLI@", R847 change to "OPT@" W=40mils JCMOS1
+CMOS_PW 1
USB20_N0 2 1
<18>
USB20_N0 2
<18>
USB20_P0 USB20_P0 3
4 3
OPT@ 1 R1212 2 +3VS 4
<17> PCH_ENBKL <42> DMIC_CLK 5
0_0402_5% 6 5
For CMOS <42> DMIC_DATA 6
7
SLI@ 1 R1201 2 8 7
<23> VGA_ENBKL ENBKL <45> 8
0_0402_5%
2

9
R827 10 GND
100K_0402_1% GND

ME@
1

LVDS_ACLK# R1255 1 OPT@ 2 0_0402_5% LVDS_ACLK#_CONN

<17> LVDS_ACLK# 1 2
LVDS_ACLK R1257 OPT@ 0_0402_5% LVDS_ACLK_CONN
<17> LVDS_ACLK LVDS_A0# 1 2 LVDS_A0#_CONN
R1259 OPT@ 0_0402_5%
<17> LVDS_A0# LVDS_A0 1 2 LVDS_A0_CONN
R1261 OPT@ 0_0402_5%
<17> LVDS_A0 LVDS_A1# 1 2 LVDS_A1#_CONN
PCH R1262 OPT@ 0_0402_5%
<17> LVDS_A1# 1 2
LVDS_A1 R1265 OPT@ 0_0402_5% LVDS_A1_CONN
B <17> LVDS_A1 LVDS_A2# 1 2 LVDS_A2#_CONN B
R1267 OPT@ 0_0402_5%
<17> LVDS_A2# LVDS_A2 1 2 LVDS_A2_CONN
R1269 OPT@ 0_0402_5%
<17> LVDS_A2

VGA_TXCLK- R1260 1 SLI@ 2 0_0402_5% LVDS_ACLK#_CONN

<24> VGA_TXCLK- VGA_TXCLK+ 1 SLI@ 2 LVDS_ACLK_CONN
R1264 0_0402_5%
<24> VGA_TXCLK+ VGA_TXOUT0- 1 2 LVDS_A0#_CONN
R1263 SLI@ 0_0402_5%
<24> VGA_TXOUT0- VGA_TXOUT0+ 1 2 LVDS_A0_CONN
VGA R1266 SLI@ 0_0402_5%
<24> VGA_TXOUT0+ VGA_TXOUT1- 1 2 LVDS_A1#_CONN
R1268 SLI@ 0_0402_5%
<24> VGA_TXOUT1- 1 2
VGA_TXOUT1+ R1270 SLI@ 0_0402_5% LVDS_A1_CONN
<24> VGA_TXOUT1+ VGA_TXOUT2- 1 2 LVDS_A2#_CONN
R1271 SLI@ 0_0402_5%
<24> VGA_TXOUT2- VGA_TXOUT2+ 1 2 LVDS_A2_CONN
R1272 SLI@ 0_0402_5%
<24> VGA_TXOUT2+

+LCDVDD_CONN +5VALW +3VS +3VS

LCDVDD EMI request
1

W=60mils
R1467 D59 @
R816 R817 INVPWM USB20_P0 4 1 DMIC_DATA
150_0603_1% 100K_0402_5% @ 100K_0402_5% DMIC_CLK 1 @ 2 I/O3 I/O1
470P_0402_50V7K

470P_0402_50V7K
1
100P_0402_50V8J

C530 R1498 DISPOFF#

2

2
6

0.1U_0402_16V4Z 0_0402_5% 1 C525

C934

1@ 1@ 5 2
+3VS VDD GND
3

2
S
@ C527
Q67A 2 1 R820 2
G
2
LCD_ENVDD# Q68
2N7002DW-T/R7_SOT363-6 2
AO3413_SOT23-3
100K_0402_5% 2 2 6 3
1 1
D USB20_N0 DMIC_CLK
1

A I/O4 I/O2 A
0.01U_0402_16V7K
C1046

C1050
3

@ AZC099-04S.R7G_SOT23-6
0.1U_0402_16V4Z +LCDVDD_CONN
2 2
SLI@
R1197 1 2 0_0402_5% 5 W=60mils
<23> VGA_ENVDD Q67B
OPT@ 2 2N7002DW-T/R7_SOT363-6
R1195 1 0_0402_5%
<17> PCH_ENVDD
4

1 1 Security Classification LC Future Center Secret Data Title

1

C531 C532
R821 4.7U_0603_6.3V6K 0.1U_0402_16V4Z Issued Date 2011/11/01 Deciphered Date 2012/12/31 LVDS/ CMOS/ USB-REDRIVER
100K_0402_5% 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
2

Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 34 of 65
5 4 3 2 1
 A B C D E

+5VS +5VS +5VS

3 3 3

VGA_CRT_R R1276 1 2 0_0402_5% 2

1 BLUE

2
1 GREEN

2
1 RED

BAT54S-7-F_SOT23-3
+5VS
D36
+CRT_VCC

F1
CRT Connector
<23> VGA_CRT_R
@ @ @ 2 1 1 2 +CRT_VCC_CONN
SLI@ D31 D32 D33 1
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 RB491D_SC59-3 0.5A_8V_KMC3S050RY
VGA_CRT_G R1273 1 2 0_0402_5% C536
<23> VGA_CRT_G
1 SLI@
W=40mils 2
0.1U_0402_16V4Z
1

VGA_CRT_B R1275 1 2 0_0402_5%

<23> VGA_CRT_B
SLI@

JCRT1
6
T75 PAD CRT_TEST 11
DAC_RED_1 L16 1 2 NBQ100505T-800Y_0402 RED 1
7
CRT_DDC_DAT_CONN 12
DAC_GRN_1 L17 1 2 NBQ100505T-800Y_0402 GREEN 2
8
JVGA_HS 13
DAC_BLU_1 L18 1 2 NBQ100505T-800Y_0402 BLUE 3
9

1
1 1 1 1 1 1 JVGA_VS 14
4
R830 R831 R832 C537 C538 C539 C540 C542 C541 10 G 16
150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J CRT_DDC_CLK_CONN 15 G 17
2 2 2 2 2 2 5

2
1
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J10P_0402_50V8J C543 SUYIN_070546HR015M22BZR
CLOSE TO CONN
100P_0402_50V8J ME@
2
DAC_RED R1274 1 2 0_0402_5%
<17> DAC_RED
2 OPT@ 2
DAC_GRN R1181 1 2 0_0402_5% +CRT_VCC
<17> DAC_GRN R833
OPT@ 1 2
DAC_BLU R1182 1 2 0_0402_5% 1
<17> DAC_BLU
OPT@ C544 OE# 1K_0402_5%
0.1U_0402_16V4Z
2

1
5
R840 NBQ100505T-800Y_0402
OPT@

OE#
P
CRT_HSYNC R1183 1 2 0_0402_5% HSYNC_G 2 4 CRT_HSYNC_1 1 2 CRT_HSYNC_2 1 2 JVGA_HS
<17> CRT_HSYNC A Y
33_0603_5% L19

G
U24
VGA_CRT_HSYNC R1184 1 2 0_0402_5% SN74AHCT1G125DCKR_SC70-5 1
<23> VGA_CRT_HSYNC

3
@
D8
SLI@ C545 @
10P_0402_50V8J JVGA_VS 3 6 JVGA_HS
+CRT_VCC 2 I/O2 I/O4

1 2 5 +5VS
GND VDD
C546 OE#
0.1U_0402_16V4Z
CRT_VSYNC R1185 1 2 0_0402_5% 2 CRT_DDC_CLK_CONN 1 4 CRT_DDC_DAT_CONN
<17> CRT_VSYNC I/O1 I/O3
5

1
R839 NBQ100505T-800Y_0402
OPT@
OE#
P
VGA_CRT_VSYNC R1186 1 2 0_0402_5% VSYNC_G 2 4 CRT_VSYNC_1 1 2 CRT_VSYNC_2 1 2 JVGA_VS AZC099-04S.R7G_SOT23-6
3 <23> VGA_CRT_VSYNC A Y 3
33_0603_5% L20
G

SLI@ U25 1
SN74AHCT1G125DCKR_SC70-5
+3VS
3

@ C547
10P_0402_50V8J
+CRT_VCC 2
1

1
2.2K_0402_5%
5
G

R837 R838
2.2K_0402_5%
2

<17> CRT_DDC_DATA CRT_DDC_DATA R1189 1 2 0_0402_5% CRT_DDC_DATA_R 4 3 CRT_DDC_DAT_CONN

OPT@
D
S
2
G

Q73B
2N7002KDW H_SOT363-6
<17> CRT_DDC_CLK CRT_DDC_CLK R1190 1 2 0_0402_5% CRT_DDC_CLK_R 1 6 CRT_DDC_CLK_CONN
D

OPT@
S

1 1
@ @
Q73A C548 C549
<23> VGA_CRT_DATA VGA_CRT_DATA R1191 1 2 0_0402_5% 2N7002KDW H_SOT363-6 100P_0402_50V8J 68P_0402_50V8K
SLI@ 2 2

<23> VGA_CRT_CLK VGA_CRT_CLK R1192 1 2 0_0402_5%

SLI@
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 CRT CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 35 of 65
A B C D E
 5 4 3 2 1

+3VS +3VS_VGA
W CM-2012-900T_4P
HDMI_CLK+_CK 4 3 HDMI_CLK+_CONN 1 2
4 3

2
C1016 3.3P_0402_50V8C

2
@ R1468 R1469
HDMI_CLK-_CK 1 2 HDMI_CLK-_CONN 1 2
1 2 HDMIDAT_R 0_0402_5% 0_0402_5%
C1015 3.3P_0402_50V8C
L23 HDMICLK_R OPT@ SLI@

2
@

1
1
L24 D57
HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN 1 2 PJSOT24C 3P C/A SOT-23 Q152
1 2 C1018 3.3P_0402_50V8C @ BSH111_SOT23-3
D D

2
HDMI@
@ R1470 1 SLI@ 2

G
HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN 1 2 VGA_HDMI_CLK 0_0402_5%
<24> VGA_HDMI_CLK

1
4 3 C1017 3.3P_0402_50V8C
W CM-2012-900T_4P <17> HDMICLK HDMICLK R1471 1 OPT@ 2 0_0402_5% 3 1 HDMICLK_R
@

D
W CM-2012-900T_4P

G
HDMI_TX1+_CK 4 3 HDMI_TX1+_CONN 1 2 VGA_HDMI_DATA R1472 1 SLI@ 2 0_0402_5%
4 3 <24> VGA_HDMI_DATA
C1020 3.3P_0402_50V8C
@ <17> HDMIDAT HDMIDAT R1473 1 OPT@ 2 0_0402_5% 3 1 HDMIDAT_R
HDMI_TX1-_CK 1 2 HDMI_TX1-_CONN 1 2
1 2

D
C1019 3.3P_0402_50V8C
L26 Q80
@
+3VS BSH111_SOT23-3
L27 HDMI@
HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN 1 2 +5VS
1 2 C1022 3.3P_0402_50V8C

2
@
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN 1 2
4 3 C1021 3.3P_0402_50V8C R862 +5VS PMEG2010AEH
1M_0402_5%

2
W CM-2012-900T_4P @ IF=0.1A, 0.29V HDMI@
IF=1A, 0.43V D37

2
G
Q85

2
1
PMEG2010AEH_SOD123
R1486 1 OPT@ 2 3 1
<17> TMDS_B_HPD

1
0_0402_5%

D
2N7002_SOT23

2
R885 @

1
20K_0402_5% D38 F2 HDMI@
C BAT54S-7-F_SOT23-3 0.5A_8V_KMC3S050RY C
R320

1
499_0402_1%

1
SLI@

2
HDMI_CLK+_CONN 1 2
R1499 +5VS_HDMI
HDMI_CLK-_CONN SLI@ 1 2 0_0402_5%
R321 499_0402_1%
SLI@ SLI@ 1 C561
HDMI_TX0+_CONN 1 2 0.1U_0402_16V4Z
for NV recommend

2
R322 499_0402_1% HDMI@
HDMI_TX0-_CONN SLI@ 1 2 L67
R323 499_0402_1% R860 R861 2
SLI@ BLM18PG181SN1D_0603
HDMI_TX1+_CONN 1 2 R859 2 @ 1 HDMI_DET_R 2 1 2.2K_0402_5% 2.2K_0402_5%
R324 499_0402_1% <23> DGPU_HDMI_HPD @ HDMI@ HDMI@

1
HDMI_TX1-_CONN SLI@ 1 2 1K_0402_5%

1
R325 499_0402_1%

R864
100K_0402_5%
HDMI_TX2+_CONN SLI@ 1 2 1
R326 499_0402_1% @ C59
HDMI_TX2-_CONN SLI@ 1 2

@
220P_0402_25V8J JHDMI1
R327 499_0402_1% D 2 HDMI_DET 19
1

HP_DET

2
18
2 Q114 17 +5V
+3VS DDC/CEC_GND
G 2N7002H 1N_SOT23-3 HDMIDAT_R 16
S HDMI@ HDMICLK_R 15 SDA
3

1 @ 2 14 SCL
R328 100K_0402_5% 13 Reserved
VGA_HDMI_CLK- SLI@ CV254 1 2 0.1U_0402_10V6K HDMI_CLK-_CK R866 1 @ 2 0_0402_5% HDMI_CLK-_CONN 12 CEC 20
<24> VGA_HDMI_CLK- CK- GND
11 21
VGA_HDMI_CLK+ SLI@ CV253 1 2 0.1U_0402_10V6K HDMI_CLK+_CK R865 1 @ 2 0_0402_5% HDMI_CLK+_CONN 10 CK_shield GND 22
<24> VGA_HDMI_CLK+ CK+ GND
<24> VGA_HDMI_TX0- VGA_HDMI_TX0- SLI@ CV256 1 2 0.1U_0402_10V6K HDMI_TX0-_CK R868 1 @ 2 0_0402_5% HDMI_TX0-_CONN 9 23
B 8 D0- GND B
R327 R326
VGA_HDMI_TX0+ SLI@ CV255 1 2 0.1U_0402_10V6K HDMI_TX0+_CK R867 1 @ 2 0_0402_5% HDMI_TX0+_CONN 7 D0_shield
<24> VGA_HDMI_TX0+ D0+
<24> VGA_HDMI_TX1- VGA_HDMI_TX1- SLI@ CV258 1 2 0.1U_0402_10V6K HDMI_TX1-_CK R870 1 @ 2 0_0402_5% HDMI_TX1-_CONN 6
5 D1-
VGA_HDMI_TX1+ SLI@ CV257 1 2 0.1U_0402_10V6K HDMI_TX1+_CK R869 1 @ 2 0_0402_5% HDMI_TX1+_CONN 4 D1_shield
<24> VGA_HDMI_TX1+ D1+
<24> VGA_HDMI_TX2- VGA_HDMI_TX2- SLI@ CV260 1 2 0.1U_0402_10V6K HDMI_TX2-_CK R872 1 @ 2 0_0402_5% HDMI_TX2-_CONN 3
2 D2-
680_0402_1% 680_0402_1% D2_shield
OPT@ OPT@ <24> VGA_HDMI_TX2+ VGA_HDMI_TX2+ SLI@ CV259 1 2 0.1U_0402_10V6K HDMI_TX2+_CK R871 1 @ 2 0_0402_5% HDMI_TX2+_CONN 1
D2+
R324 R323 TAITW _PDVBR0-19FLBS4NN4N0
ME@

680_0402_1% 680_0402_1%
OPT@ OPT@

R321 R320

<17> TMDS_B_DATA2#_PCH TMDS_B_DATA2#_PCH OPT@ C200 1 2 0.1U_0402_10V6K HDMI_TX2-_CK

TMDS_B_DATA2_PCH OPT@ C201 1 2 0.1U_0402_10V6K HDMI_TX2+_CK @
<17> TMDS_B_DATA2_PCH
<17> TMDS_B_DATA1#_PCH TMDS_B_DATA1#_PCH OPT@ C203 1 2 0.1U_0402_10V6K HDMI_TX1-_CK
680_0402_1% 680_0402_1% <17> TMDS_B_DATA1_PCH TMDS_B_DATA1_PCH OPT@ C206 1 2 0.1U_0402_10V6K HDMI_TX1+_CK
OPT@ OPT@ TMDS_B_DATA0#_PCH OPT@ C204 1 2 0.1U_0402_10V6K HDMI_TX0-_CK 46@
<17> TMDS_B_DATA0#_PCH
<17> TMDS_B_DATA0_PCH TMDS_B_DATA0_PCH OPT@ C205 1 2 0.1U_0402_10V6K HDMI_TX0+_CK
R325 R322 TMDS_B_CLK#_PCH OPT@ C208 1 2 0.1U_0402_10V6K HDMI_CLK-_CK
<17> TMDS_B_CLK#_PCH W/LOGO
A
<17> TMDS_B_CLK_PCH TMDS_B_CLK_PCH OPT@ C207 1 2 0.1U_0402_10V6K HDMI_CLK+_CK A

HDMI W/O Logo: RO0000001HM

680_0402_1% 680_0402_1%
OPT@ OPT@ Title
Security Classification LC Future Center Secret Data
Issued Date 2011/11/01 Deciphered Date 2012/12/31 HDMI CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, March 11, 2013 Sheet 36 of 65
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX) 9/18 JP1 Pin2,24,52 contact to +3VS_WLAN for AOAC function
Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.
+3VS_WLAN LPC_FRAME#_R R873 1 @ 2 0_0402_5% LPC_FRAME#
1 2 LPC_FRAME# <14,45>
LPC_AD3_R R874 @ 0_0402_5% LPC_AD3
LPC_AD3 <14,45>
LPC_AD2_R R875 1 @ 2 0_0402_5% LPC_AD2
1 2 LPC_AD2 <14,45>
LPC_AD1_R R876 @ 0_0402_5% LPC_AD1

For RF request
+1.5VS +1.5VS LPC_AD1 <14,45>
LPC_AD0_R R878 1 @ 2 0_0402_5% LPC_AD0
LPC_AD0 <14,45>
PCI_RST#_R R879 1 @ 2 0_0402_5% PLT_RST#

0.047U_0402_16V4Z
1 CLK_PCI_DB CLK_PCI_DB <18>
1 1

C57

1
@ R400 C564 C565
1 2 1
R_short 0_0603_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
<38,45> LAN_WAKE# R1620 1 @ 2 0_0402_5%

2
JWLN1
<16,19,38> PCIE_WAKE# PCIE_WAKE# 1 2
3 WAKE# 3.3V 4
R897 NC GND
BT_CTRL COMBT@ 1 2 BT_CTRL_R 5 6 +1.5VS_WLAN
WLAN_CLKREQ1# 7 NC 1.5V 8 LPC_FRAME#_R
0_0402_5% <15> WLAN_CLKREQ1# CLKREQ# NC
9 10 LPC_AD3_R
11 GND NC 12 LPC_AD2_R
R1556 <15> CLK_PCIE_WLAN1# REFCLK- NC
COMBT@ 1 2 BT_DISABLE# 13 14 LPC_AD1_R
<15> CLK_PCIE_WLAN1 15 REFCLK+ NC 16 LPC_AD0_R
1K_0402_5% GND NC
PCI_RST#_R 17 18 R1541 2 @ 1 0_0402_5%
19 NC GND 20 1 2 EC_WL_OFF# <45>
For isolate Intel CLK_PCI_DB WL_OFF# R880 0_0402_5%
NC NC PCH_WL_OFF# <18>
21 22 PLT_RST#
Rainbow Peak and 23 GND PERST# 24 R881 1 @ 2 0_0402_5%
PLT_RST# <18,23,32,38,44,45,6>
<15> PCIE_PRX_DTX_N2 PERn0 +3.3Vaux +3VALW
Compal debug card. <15> PCIE_PRX_DTX_P2
25 26 R882 1 2 0_0402_5% +3VS_WLAN
27 PERp0 GND 28
29 GND +1.5V 30 SMB_CLK_S3_R R883 1 @ 2 0_0402_5%
GND SMB_CLK SMB_CLK_S3 <12,13,15,46>
31 32 SMB_DATA_S3_R R884 1 @ 2 0_0402_5% SMB_DATA_S3 <12,13,15,46>
<15> PCIE_PTX_C_DRX_N2 PETn0 SMB_DATA
33 34
<15> PCIE_PTX_C_DRX_P2 35 PETp0 GND 36
GND USB_D- USB20_N10 <18> +3VS +3VS_WLAN
+3VS_WLAN 37 38
39 NC USB_D+ 40 USB20_P10 <18>
J8

@
41 NC GND 42
NC LED_WWAN# 1 2
43 44 1 2
100_0402_1% 45 NC LED_WLAN# 46
R887 47 NC LED_WPAN# 48 JUMP_43X79
EC_TX 1 2 49 NC +1.5V 50
<45> EC_TX NC GND +3VALW
EC_RX 1 2 BT_DISABLE# 51 52 Q104
<45> EC_RX NC +3.3V
R888 AO3413_SOT23-3
100_0402_1% 53 54

D
GND GND 3 1 1
AOAC@
1 C533
TAITW_PFPET0-AFGLBG1ZZ4N0 AOAC@ AOAC@ 1 0.1U_0402_16V4Z

G
2
C526 2

2
For EC to detect 0.1U_0402_16V4Z C1048
ME@
2 R889 2 AOAC@0.01U_0402_25V7K 2
debug card insert. 100K_0402_5% AOAC@ 2
R436
1 2 1
<51> AOAC_ON#
@
100K_0402_5%

1
C1055
0.1U_0402_16V4Z
2

softstart (RC) will check on EVT PCB

R1557 COMBT@
<19> PCH_BT_DISABLE# 1 2 BT_CTRL
0_0402_5%
WLAN&BT Combo module circuits
BT on module BT on module
6

D D 9/18 Increase for Intel AOAC function

<19,47> PCH_BT_ON# 2 5 SUSP <10,51,55,57> Enable Disable
Q157A

Q157B
2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

G G

S S * BT_CRTL (GPIO22)
1

@ @ H L
PCH_BT_ON# L H

3 3

Mini-Express Card(SSD)
SSD Active:4.5W(1.5A)
+3VS_SSD
+3VS +3VS_SSD
0.1U_0402_16V4Z 10U_0805_10V6K
J5
1 1 1 1 1 2
@ 1 2
C566 C567 C568 C569
JUMP_43X79
2 2 2 2 @
JSSD1
0.01U_0402_25V7K 10U_0805_10V6K 1 2
3 WAKE# 3.3V 4
5 NC GND 6
7 NC 1.5V 8
9 CLKREQ# NC 10
11 GND NC 12
13 REFCLK- NC 14
15 REFCLK+ NC 16
17 GND NC 18
19 NC GND 20
0.01U_0402_16V7K 21 NC NC 22
SATA_DTX_C_IRX_P0 2 1 C572 SATA_DTX_IRX_P0 23 GND PERST# 24
<14> SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_N0 2 1 C573 SATA_DTX_IRX_N0 25 PERn0 +3.3Vaux 26
<14> SATA_DTX_C_IRX_N0 27 PERp0 GND 28
0.01U_0402_16V7K 29 GND +1.5V 30
SATA_ITX_DRX_N0 31 GND SMB_CLK 32
<14> SATA_ITX_DRX_N0 PETn0 SMB_DATA
SATA_ITX_DRX_P0 33 34
<14> SATA_ITX_DRX_P0 PETp0 GND
4 35 36 4
37 GND USB_D- 38
+3VS_SSD 39 NC USB_D+ 40
41 NC GND 42
43 NC LED_WWAN# 44
45 NC LED_WLAN# 46
47 NC LED_WPAN# 48
49 NC +1.5V 50
SATA_DET# 1 2 51 NC GND 52
<14> SATA_DET# R896 0_0402_5% NC +3.3V
For SSD use: @ 53 54 Title
GND GND Security Classification LC Future Center Secret Data
TAITW_PFPET0-AFGLBG1ZZ4N0
Issued Date 2011/11/01 Deciphered Date 2012/12/31 MINI-CARD CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
ME@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, March 11, 2013 Sheet 37 of 65
A B C D E
 5 4 3 2 1

+3VALW +3V_LAN
Atheros request can't disable LAN power +LX
LX Voltage Configure
<Pin 40>

@
J10 Close together
Layout Notice : Place as close 1 2 +1.7V
1 2 +1.7_VDDCT
chip as possible. AR8151 <VDDCT> R1356,C955
JUMP_43X79 R1356 8151@ 0_0402_5% L74
1 2 +LX_R 1 2 +LX +1.1V
Q70 LP2301ALT1G_SOT-23

1000P_0402_50V7K
AR8161 R1357,R1372,L76

10U_0805_10V4Z
4.7UH_SIA4012-4R7M_20%

0.1U_0402_16V4Z
<DVDDL,AVDDL>

@ C935

C936

C937
R1357 8161@ 0_0402_5% 1 1

D
3 1 +1.1_DVDDL 1 2
Note: Place Close to LAN chip L75 L76
1 1 L39 DCR< 0.15 ohm
C552 C1047 2 2

G
FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P

2
D Rate current > 1A D
0.1U_0402_16V4Z 0.01U_0402_25V7K +1.1_AVDDL_L 1 2 +1.1_AVDDL 1 2 +1.1_DVDDL

0.1U_0402_16V4Z

1U_0402_6.3V4Z

4.7U_0603_6.3V6K
2 2
R59 8161@
LAN_PWR_ON# 2 1 Close to

C967

C980

C278
<45> LAN_PWR_ON# 1 1 1
100K_0402_5% 1 Pin40
@ C1056
0.1U_0402_16V4Z 2 2 2
2
20120806 -->
1. Main source was EOL, P/N : SHI0000740J
2. Change L74 P/N to "SH00000GT0J" (has used on SIT by SMT Memo)
Vendor recommand reseve the Place close to Pin34
PU resistor close LAN chip

+3V_LAN R345 1 @ 2 4.7K_0402_5%

PLT_RST#
<18,23,32,37,44,45,6> PLT_RST#

H --> Overclocking mode

Place Close to Chip U63 8161@ L --> Not overclocking mode
C
<15> PCIE_PRX_DTX_N1 C946 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N1 29 38 ACTIVITY# C
TX_N LED_0 39 LAN_LINK# ACTIVITY# <39>
C947 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P1 30
Atheros LED_1 23 LAN_CLK_SEL 2 @ 1 LAN_LINK# <39>
<15> PCIE_PRX_DTX_P1 TX_P LED_2
AR8151/AR8161 R58 10K_0402_5% 2011103 for vendor comment
36
<15> PCIE_PTX_C_DRX_N1 RX_N 12 MDI0-
35 TRXN0 11 MDI0- <39>
MDI0+
<15> PCIE_PTX_C_DRX_P1 RX_P TRXP0 15 MDI1-
MDI0+ <39> Place Close to LAN chip
32 TRXN1 14 MDI1+ MDI1- <39>
<15> CLK_PCIE_LAN# REFCLK_N TRXP1 MDI1+ <39>
33 18 MDI2-
<15> CLK_PCIE_LAN REFCLK_P TRXN2 17 MDI2- <39>
MDI2+ MDI0+ R1358 1 8151@ 2 49.9_0402_1% 1 @ 2 C938 1000P_0402_50V7K
PLT_RST# 2 TRXP2 21 MDI3- MDI2+ <39>
PERST# TRXN3 MDI3- <39>
20 MDI3+ MDI0- R1359 1 8151@ 2 49.9_0402_1% 1 2 8151@ C939 0.1U_0402_16V4Z
R1369 1 2 0_0402_5% PCIE_WAKE#_R 3 TRXP3 MDI3+ <39> Place Close to PIN1
<16,19,37> PCIE_WAKE# W AKE# MDI1+ R1360 1 8151@ 2 49.9_0402_1% 1 @ 2 C940 1000P_0402_50V7K
R1370 1 @ 2 0_0402_5% 25 10 LAN_RBIAS 1 2 +3V_LAN
<37,45> LAN_WAKE# SMCLK RBIAS
26 R1371 2.37K_0402_1% MDI1- R1361 1 8151@ 2 49.9_0402_1% 1 2 8151@ C941 0.1U_0402_16V4Z
SMDATA
Place Close to PIN10
20120718 --> for LAN wakeup backlight issue 28 1 +3V_LAN MDI2+ R1362 1 8151@ 2 49.9_0402_1% 1 @ 2 C942 1000P_0402_50V7K
NC VDD33

1000P_0402_50V7K
27

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

1U_0402_6.3V4Z
1. R1369 to "Mount" TESTMODE 1 1 1 1

2
MDI2- R1363 1 8151@ 2 49.9_0402_1% 1 2 8151@ C943 0.1U_0402_16V4Z
2. R1370 ro "@"

@
40 +LX +LX @
LX

C950

C951

C952

C953

C954
LAN_XTALO 7 R1372 1 8161@ 2 30K_0402_5% MDI3+ R1364 1 8151@ 2 49.9_0402_1% 1 @ 2 C944 1000P_0402_50V7K
+3VS

1
LAN_XTALI 8 XTLO 2 2 2 2
XTLI 5 +1.7_VDDCT C955 1 2 0.1U_0402_16V4Z MDI3- R1365 1 8151@ 2 49.9_0402_1% 1 2 8151@ C945 0.1U_0402_16V4Z
VDDCT/ISOLAN 8151@
4
<15> CLKREQ_LAN# CLKREQ# 24 +1.1_DVDDL_R R1366 1 8151@ 2 0_0402_5%
+1.1_DVDDL
DVDDL/PPS 37
+1.1_AVDDL 13 DVDDL_REG/DVDDL +1.1_DVDDL
B AVDDL Note : C938, C940, C942, 944, reserved for EMI. B
+1.1_AVDDL 19
+1.1_AVDDL 31 AVDDL 16 +AVDDH_AVDD3.3
AVDDL AVDDH/AVDD33 For AR8151: Stuff 49.9K and 0.1u
+1.1_AVDDL_L 34 22 +2.7_AVDDH For AR8161: NC
+1.1_AVDDL 6 AVDDL AVDDH 9 +2.7_AVDDH
AVDDL_REG/AVDDL AVDDH_REG
1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z
C956

C957

C958

C959

C960
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z
1 1 1 1 1
C961

C962

C963
41 1 1 1
GND +3V_LAN

C964

C965

C966
1 1 2
AR8161-AL3A-R_QFN40_5X5
2 2 2 2 2 8151@ +2.7_AVDDH
2 2 2 8161@
U63 R1367 1 2 0_0402_5%
2 2 1
8151@ 2
8151@ For AR8151: Stuff C966,R1366 +AVDDH_AVDD3.3 R1368 1 0_0402_5% +2.7_AVDDH
For AR8161: NC
Near Near Near Near
Near Near Near Near SA00003LE20

1U_0402_6.3V4Z
0.1U_0402_16V4Z
Pin9 Pin22 Pin37 Pin24
Pin13 Pin19 Pin31 Pin6

C948

C949
1 1
8161@
2 2
LAN_XTALI
Y6
LAN IC X76 VRAM P/N
Place close to Pin16
1 3 LAN_XTALO
1 3
GND GND 8161 X76409JVL04 SA000050E1J
A For AR8151: Stuff R1368 for +AVDD3.3 A
1 2 4 1 For AR8161: Stuff R1367,C949 for +AVDDH
C968 25MHZ_10PF_7V25000014 C969 8151 X76409JVL03 SA00003LE2J
15P_0402_50V8J 15P_0402_50V8J No use
2 2

Security Classification LC Future Center Secret Data Title

20120816 --->
1. change P/N to 7V2500014(10pf), SJ10000E80J Issued Date 2011/11/01 Deciphered Date 2012/12/31 LAN-AR8151/8161
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, March 11, 2013 Sheet 38 of 65
5 4 3 2 1
 5 4 3 2 1

LAN Transformer
+1.7_VDDCT
T49
2 8151@ 1 1 24 2 R1374 1
+1.7_VDDCT_R MCT3
TCT1 MCT1
R1373 1 2 R_short 0_0402_5% If vendor test result is "ok", need to change as below
MDI3+ 2 1:1 23 MDO3+
0_0603_5% C976 C970 <38> MDI3+ TD1+ MX1+ 1. Change R1374,R1375,R1376,R1377 to 0 ohm
@ 8151@
1U_0402_6.3V4Z 0.1U_0402_16V4Z 2. Change R1194 to 75 ohm
D D
2 1 3. Mount F6
4. Un mount F3,F4,F5
MDI3- 3 22 MDO3- --> 2012/02/20 : already implement to Sch
<38> MDI3- TD1- MX1-
6/23 update
4 21 MCT2 2 R1375 1
TCT2 MCT2
2 R_short 0_0402_5%
MDI2+ 5 1:1 20 MDO2+
8151@ C972 <38> MDI2+ TD2+ MX2+ BOM option:
0.1U_0402_16V4Z 1. For GDTx4
1 R1374/R1375/R1376/R1377=75 ohm
R1194=0 ohm
MDI2- 6 19 MDO2- MCT0~3=Mount
<38> MDI2- TD2- MX2-
7 18 MCT1 2 R1377 1 2. For GDTx1
TCT3 MCT3
2 R_short 0_0402_5% R1374/R1375/R1376/R1377=0 ohm
C970 C972 MDI1+ 8 1:1 17 MDO1+ R1194=75 ohm
C974 <38> MDI1+ TD3+ MX3+
8151@ MCT0=Mount
0.1U_0402_16V4Z
1 MCT1~3=Mount
8161S@ 8161S@

MDI1- 9 16 MDO1-
<38> MDI1- TD3- MX3-
0.1U_0402_16V4Z 0.1U_0402_16V4Z
10 15 MCT0 2 R1376 1
TCT4 MCT4
2 R_short 0_0402_5%
MDI0+ 11 1:1 14 MDO0+
C975 <38> MDI0+ TD4+ MX4+

1
C974 C975 8151@
0.1U_0402_16V4Z
1 R1194
8161S@ 8161S@ 75_0402_5%
MDI0- 12 13 MDO0-
<38> MDI0-

2
TD4- MX4-
1
C 0.1U_0402_16V4Z 0.1U_0402_16V4Z Place close to T49(TCT) pin NS892402 1G C
C973
10P_1206_2KV7K
2

Place Close to T49 Place Close to T49

LAN Conn.
D68 8151S@
MDI2- 1 10 MCT3
2 1 10 9 MDI3+ JRJ1 ME@
MDI2+ 3 2 9 8 MCT2 LAN_LINK# 9
B 4 3 8 7 MDI3- <38> LAN_LINK# Green LED- B
GND

5 4 7 6 MCT1 2 R1378 1 10
5 6 1 +3V_LAN Green LED+
MCT0 220_0402_5% MDO0+ 1
C978 @
11

TCLAMP3302N.TCT_SLP2626P10-10 470P_0402_50V7K PR1+

LSE-200NX3216TRLF_1206-2

LSE-200NX3216TRLF_1206-2

LSE-200NX3216TRLF_1206-2

LSE-200NX3216TRLF_1206-2
R02 2 MDO0- 2
PR1-
2

2
MDO1+ 3
@ @ @ PR2+
MDO2+ 4
F6

F3

F4

F5
PR3+
MDO2- 5
PR3-
1

1
MDO1- 6
PR2-
MDO3+ 7 14
D67 8151S@ PR4+ G2
MDI0- 1 10 MDO3- 8 13
2 1 10 9 MDI1+ PR4- G1
MDI0+ 3 2 9 8 ACTIVITY# 11
4 3 8 7 <38> ACTIVITY# Yellow LED-
MDI1-
GND

5 4 7 6 2 R1442 1 12
5 6 1 +3V_LAN Yellow LED+
Reserve for EMI go rural solution 220_0402_5%
C979 @ SANTA_130456-111
11

TCLAMP3302N.TCT_SLP2626P10-10 470P_0402_50V7K
R02 2
2012-0622 -->
1. Change the BOM Structure of LAN SURGE to "@" --> F3, F4, F5
Reserve D67,D68 for EMI go rural solution 2. Del SURGE@ on Y400 BOM, and change the BOM structure of F6 to "Stuff"
20120807 -->
A 1. Change Lan Surge P/N to "SCV00001F0J" to meet DC400V Lenovo spec A

2. Only change P/N(F3,F4,F5 and F6), not used correct symbol.

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 LAN TRANSFORMER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 39 of 65
5 4 3 2 1
 5 4 3 2 1

D Close U29 SMSC thermal sensor D

REMOTE1+
1
+3VS
placed near by VRAM REMOTE1+
Under VRAM
C449 1

1
2200P_0402_50V7K U29 @ C
2 REMOTE1- C982 2 Q137
Remove +VDD netname B
100P_0402_50V8J MMST3904-7-F_SOT323-3
1 10 EC_SMB_CK2 2 E
EC_SMB_CK2 <15,23,32,45>

3
VDD SMCLK REMOTE1-
REMOTE1+ 2 9 EC_SMB_DA2
DP1 SMDATA EC_SMB_DA2 <15,23,32,45>
REMOTE2+ 2
1 REMOTE1- 3 8
DN1 ALERT# R624
C443
C658 0.1U_0402_16V4Z REMOTE2+ 4 7 2 1
2200P_0402_50V7K 1 DP2 THERM# +3VS Close to SSD side
2 REMOTE2- REMOTE2- 5 6 REMOTE2+
DN2 GND 10K_0402_5%
1

1
@ @ C
C984 2 Q138
EMC1403-2-AIZL-TR_MSOP10 100P_0402_50V8J B MMST3904-7-F_SOT323-3
FAN_PWM & TACH 2 E

3
for PWM FAN Address 1001_101xb REMOTE2-

REMOTE2+/-:
C
internal pull up 1.2K to 1.5V Trace width/space:10/10 mil C
R for initial thermal Trace length:<8"
shutdown temp

B B

FAN1 Conn
+5VS

JFAN1
1
2 1
2 1 <45> EC_FAN_SPEED 2
<45> EC_FAN_PW M 3
C986 C49 @ 4 3
10U_0805_10V6K 0.1U_0402_10V7K 5 4
1 2 6 G5
G6
ACES_85205-04001
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 EMC THERMAL SENSOR/FAN CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 40 of 65
5 4 3 2 1
 A B C D E F G H

1
SATA HDD Conn. SATA ODD Conn. 1

JHDD1 ME@ JODD2 ME@

1 1
SATA_ITX_DRX_P1 2 GND SATA_ITX_DRX_P2_CONN 2 GND
<14> SATA_ITX_DRX_P1 A+ <14> SATA_ITX_DRX_P2_CONN A+
SATA_ITX_DRX_N1 3 SATA_ITX_DRX_N2_CONN 3
<14> SATA_ITX_DRX_N1 A- <14> SATA_ITX_DRX_N2_CONN A-
4 4
SATA_DTX_C_IRX_N1 C627 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N1 5 GND SATA_DTX_C_IRX_N2 C629 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N2 5 GND
<14> SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 C628 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P1 6 B- <14> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 C630 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P2 6 B-
<14> SATA_DTX_C_IRX_P1 7 B+ <14> SATA_DTX_C_IRX_P2 7 B+
GND R1479 1 2 R_short 0_0402_5% GND
<32,45> SLI_FAN_SPEED 1 2
<19> ODD_DETECT# R1476 @ 0_0402_5%
R710 1 @ 2 0_0402_5% 8
8 9 DP
9 VCC3.3 10 +5V
10 VCC3.3 +5VS_ODD 11 +5V
11 VCC3.3 12 MD 15
12 GND R921 1 2 10K_0402_5% ODD_DA# 13 GND GND 14
GND +3VS GND GND
@ J12 13
1 2 +5VS_HDD 14 GND R1497 1 @ 2 0_0402_5%
+5VS 1 2 15 VCC5 <18> ODD_DA#_R 1 2
R1494 R_short 0_0402_5% SANTA_202404-1
JUMP_43X79 16 VCC5 <32,45> SLI_FAN_PWM
17 VCC5
18 GND
19 RESERVED
+5VS 20 GND
21 VCC12
22 VCC12
2 VCC12 2
1 1 1 1 1
23
C631 C632 C633 C634 C635 24 GND
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0603_6.3V6M 10U_0603_6.3V6M GND
2 2 2 2 2 SANTA_190302-1

ODD Power Control

@ J6
1 2
1 2
JUMP_43X79
+5VALW +5VS +5VS_ODD +5VS_ODD
Q88 AO3413_SOT23-3 AO3413
3 VGS= -4.5V, Id=-3A, Rds<97m ohm 3
S

3 1

1
1

R923 R1496 R1477 @

G

1 2 1 1
2

100K_0402_5% @ 100K_0402_5% C1049 C638 C639 C637 470_0603_5%

0.1U_0402_16V4Z 0.01U_0402_16V7K 10U_0603_6.3V6M 0.1U_0402_16V4Z

2
2

2 1 2 2
2 R1110 1 ODD_EN#
100K_0402_5%

3
D
2
C1057 ODD_EN# 5 Q89B
6

D @ 0.01U_0402_16V7K G 2N7002KDWH_SOT363-6
2
<19> ODD_EN G 1
Q89A S

4
1

2N7002KDWH_SOT363-6
S
1

R1478
100K_0402_5%
2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 HDD/ODD CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 41 of 65
A B C D E F G H
 A B C D E F G H

LA1 +5VS_AVDD +3VS +3VS_DVDD

1 2 +5VS_AVDD
+5VS RA7
FBMA-L11160808601LMA10T_2P 1 2 +3VS_DVDD

4.7U_0805_10V4Z

0.1U_0402_16V4Z
R_short 0_0603_5%

0.1U_0402_16V4Z
600ohms @100MHz 1A 1 1

CA13

CA14

1U_0603_10V4Z
P/N: SM01000BU00 1 1

CA15

CA16
1 2 2 1
2 2

Place near UA8.Pin25

Place near UA8.Pin1

+3VS_DVDD +3VS_DVDDIO
+5VS_AVDD
1 RA6 2 +3VS_DVDDIO
Place near UA8.Pin39, Pin46

10U_0603_6.3V6M

0.1U_0402_16V4Z
1 RA5 2 +5VS_PVDD +5VS_AVDD FBMA-10-100505-101T 0402
+5VS 1 1

CA17

CA18
R_short 0_0805_5% P/N: SM01000DI0J

0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0603_6.3V6K
4.7U_0603_6.3V6K

+3VS_DVDDIO
+3VS_DVDD
2 1 1 1 2 20120813 --> RA6 symbol
2 2

CA21

CA22
600ohms @100MHz 2A from R_short to Bead @ @

CA6

CA7

CA8
P/N: SM01000EE00 symbol
1 2 2 2 1 Place near UA8.Pin1

11/07 -->

39

46

25

38

9
1
UA8 Place near UA8.Pin38 Change CA17 type to 0603

DVDD-IO
PVDD1

PVDD2

AVDD1

AVDD2

DVDD1
2012-0418 --> Channge EAPD netname to EAPD# 30 mils
EAPD# 47 24 SPKOUT_R1
<43> EAPD# DAPD/COMB_JACK LINE1-R(PORT-C-R) SPKOUT_R1 <43>
2 4 23 SPKOUT_L1
External SPK (One Channel) 2
PD# LINE1-L(PORT-C-L) SPKOUT_L1 <43>
HDA_SDOUT_AUDIO 5 22 C_MIC2 CA1277 2 1 2.2U_0603_6.3V6K MIC2_R
<14> HDA_SDOUT_AUDIO SDATA-OUT MIC1-R(PORT-B-R) MIC2_R <49>
6 21
Ext. MIC
HDA_BITCLK_AUDIO C_MIC1 CA1276 2 1 2.2U_0603_6.3V6K MIC1_R
+3VS <14> HDA_BITCLK_AUDIO BIT-CLK MIC1-L(PORT-B-L) MIC1_R <49>
HDA_SDIN0 2 RA1637 1 HDA_SDIN0_R 8 17 10 mils
<14> HDA_SDIN0 SDATA-IN MIC2-R(PORT-F-R)
22_0402_5%
2

16
RA475 MIC2-L(PORT-F-L)
@ 4.7K_0402_5% HDA_SYNC_AUDIO 10 15
<14> HDA_SYNC_AUDIO SYNC LINE2-R(PORT-E-R)
HDA_RST_AUDIO# HDA_RST_AUDIO# 11 14
<14> HDA_RST_AUDIO#
1

RESET# LINE2-L(PORT-E-L)
PC_BEEP 12
PCBEEP
@ CA1368 40
100P_0402_50V8J~N 2 RA1640 1 JDREF 19 SPK-OUT-L+
MIC Sense --> RA1639 place near pin13 JDREF 41
Capless HP Sense --> RA1638 place near pin34 20K_0402_1% 20 SPK-OUT-L-
MONO-OUT(PORT-H) 44
MIC_JD RA1639 2 1 20K_0402_1% SENSEA 13 SPK-OUT-R-
<49> MIC_JD Sense A 45
PLUG_IN RA1638 2 1 39.2K_0402_1% 18 SPK-OUT-R+
<49> PLUG_IN Sense-B 10 mils
1 2 CBN 35 33 HPOUTR_R R3 2 1 75_0402_5% HP_OUTR
CBN HPOUT-R(PORT-A-R) HP_OUTR <49>
CA1288 2.2U_0603_6.3V6K HeadPhone
CBP 36 32 HPOUTL_R R4 2 1 75_0402_5% HP_OUTL
CBP HPOUT-L(PORT-A-L) HP_OUTL <49>
2 1 CPVEE 34 48 SPDIF R945 1 2 SPDIF_OUT
CA19 2.2U_0603_6.3V6K CPVEE SPDIF-OUT FBMA-10-100505-301T_2P
SPDIF_OUT <49> SPDIF
2 1 LDO_CAP 28 EMI Request
3 CA20 4.7U_0603_6.3V6K LDO-CAP 3 DMIC_CLK_R R955 1 2 DMIC_CLK 3
GPIO1/DMIC-CLK DMIC_CLK <34>
FBMA-10-100505-301T_2P Int. MIC
Del RA3, RA4 29 2 DMIC_DATA_R R954 2 1 R_short 0_0402_5% DMIC_DATA
MIC2-VREFO GPIO0/DMIC-DATA DMIC_DATA <34>
10 mils 30 10 mils
+MIC1_VREFO_R MIC1-VREFO-R
10 mils 31
+MIC1_VREFO_L MIC1-VREFO-L

For EMI 42 27 AC97_VREF 10 mils

PVSS1 VREF

1U_0603_10V4Z

0.1U_0402_16V4Z
43 26 2 1
PVSS2 AVSS1

CA1290

CA1291
HDA_SYNC_AUDIO HDA_SDOUT_AUDIO
2 2 7 37
DVSS AVSS2
CA1278 @ CA1285 49 1 2
10P_0402_50V8J 10P_0402_50V8J Thermal PAD
1 1
Close to UA8.Pin27
ALC269Q-VC2-GR_QFN48_6X6
@ 2 RA1635 1 HDA_BITCLK_AUDIO
AGND
1 0_0402_5%
@ CA1282
22P_0402_50V8J~N
2

Pin Assignment Location Function

PC Beep SPK-OUT (Pin40/41/44/45) Internal Int Speaker
4 1 2 4
<45> BEEP#
EC Beep CA4 0.1U_0402_16V4Z Capless HP-OUT (Pin32/33) External Headphone out
RA1
1 2 PC_BEEP1 1 2 PC_BEEP MIC1(Pin21/22) External Mic in
<14> HDA_SPKR
PCH Beep CA5 0.1U_0402_16V4Z 33_0402_5%
1 RA1647 2 @
1

0_0402_5% Security Classification LC Future Center Secret Data Title

@ RA2
10K_0402_5% Issued Date 2011/11/01 Deciphered Date 2012/12/31 HD AUDIO ALC269Q-VC3
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
DGND AGND AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 42 of 65
A B C D E F G H
 A B C D E F G H

B+ B+_PVDD

2 LA57

22U_1210_25V6K~D

22U_1210_25V6K~D

22U_1210_25V6K~D
1 B+_PVDD B+ = 19V

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0_0603_5%
1A, W=40 mils 2 2 2 1 1

1
CA1369

CA1370

CA1371

CA1372

CA1373

CA1374

CA1375

CA1376
@ @ @ @ @

CA1

CA2

CA3
1 C40 C41 1
1U_0603_25V6 1U_0603_25V6

2
1 1 1 2 2

22uf*3, 10uf*8 for Damage issue

Stuff --> CA1, CA2, CA3, CA1374, CA1375 and CA1376
GAIN SETTING
+5VS

C42 2012-0418 --> Add R892 for Gain setting

1 2
+5VS
R892 @
1U_0402_6.3V6K U73 1 2
B+_PVDD
4 5 GAIN1 0_0402_5%
21 VS G1 6 GAIN2
22 PVDD G2 2012-0418 --> W=40 mils GAIN1
PVDD
One channel analog input
3 SPKOUT_L1+ LA56 2 1 R_short 0_0603_5% SPK_L1 GAIN2
OUTL+
SPKOUT_L1 C43 1 2 1U_0402_6.3V6K 8 1 SPKOUT_L2- LA58 2 1 R_short 0_0603_5% SPK_L2
<42> SPKOUT_L1 INL+ OUTL-

1
2
SPKOUT_R1 C44 1 2 1U_0402_6.3V6K 12 OUTL-
+5VS <42> SPKOUT_R1 INR+ 17 SPKOUT_R2- LA61 2 1 R_short 0_0603_5% SPK_R2 R895 R890
9 OUTR- 18 0_0402_5% 0_0402_5%
1 INL- OUTR-
1

2
R899 C45 C46 1 2 11 16 SPKOUT_R1+ LA60 2 1 R_short 0_0603_5% SPK_R1
1U_0402_6.3V6K INR- OUTR+
0_0402_5%
2 2 1U_0402_6.3V6K Add JUMP for layout route 2
@
2

7
LIM_TH 10
GND GAIN1 GAIN2 GAIN SETTING (dB)
1

R960 1 @ 2 0_0402_5% 13 19
TEMPLOCK PGND 20
R898 PGND 23
@ PGND * GND GND 9 (Default)
R_short 0_0402_5% 2 1 AMP OFF# 15 24
+3VALW SHUTDOWN PGND
R1407 10K_0402_5%
2

14 25 NC GND 13
RELEASE EP
Change BOM structure to @ 1
for leakage
C47
MAX98400BETGLFT_TQFN-EP24_4X4 +5VS GND 16.7
1U_0402_6.3V6K
2
GND NC 20.1
2012-0429 --> Change C42~C47 Cap to X5R type for Vendor suggestion
NC NC 23.3

+5VS NC 26.4

2012-0418 --> Set R890 BOM structure as Stuff

3 R959 1 @ 2 0_0402_5% 3
SPK_R1 @ CA9 1 2 1000P_0402_50V7K~N
+3VS Speaker Conn.
SPK_R2 @ CA10 1 2 1000P_0402_50V7K~N
JSPK1 ME@
2 SPK_L1 @ CA11 1 2 1000P_0402_50V7K~N SPK_L1 1
C1064 SPK_L2 2 1
0.1U_0402_10V7K SPK_L2 @ CA12 1 2 1000P_0402_50V7K~N SPK_R1 3 2
SPK_R2 4 3
4
5

1 5
2009/11/02 Modify G5
EC_MUTE# 1 6
P

<45> EC_MUTE# IN1 G6

4 AMP OFF#
EAPD# 2 O ACES_85205-04001
<42> EAPD# IN2
G

U74
3

2
SN74AHC1G08DCKR_SC70-5
3

D62 @ D61 @
AZ5125-02S.R7G_SOT23-3 AZ5125-02S.R7G_SOT23-3

1 @ 2
R958 0_0402_5%
1

2012-0622 --> change these BOM structure for BOBO noise issue
1. R958, R959 --> "UnStuff"
2. U74, C1064 --> "Stuff"
Reserve for ESD request.

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 AMP-MAX98400BETG+T

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 43 of 65
A B C D E F G H
 5 4 3 2 1

2 R1458 1
+3VS +3VS_CARD
R_short 0_0603_5% close to JREAD1 pin 9 @
MDIO5_R R1459 2 @ 1 C1023 1 2

close to JREAD1 pin 17 100_0402_5% 100P_0402_50V8J

@
U71 CLK_PCIE_CARD_PCH# MDIO5_R R1460 2 @ 1 C1024 1 2
D CLK_PCIE_CARD_PCH# <15> D
CLK_PCIE_CARD_PCH
5
JMB389 CLK_PCIE_CARD_PCH <15>
100_0402_5% 100P_0402_50V8J
+1.8VS_CARD
10 APVDD close to JREAD1 pin 36 @
36 APV18 3 1 R1461 2 MDIO5_RR R1462 2 @ 1 C1025 1 2
+3VS_CARD TAV33 APCLKN
19 4 12K_0402_1%
20 DV33 APCLKP 7 APREXT 100_0402_5% 100P_0402_50V8J
DV33 APREXT

Power
44 9 PCIE_PTX_C_DRX_N4

PCIE
18 DV33 APRXN 8 PCIE_PTX_C_DRX_N4 <15>
+1.8VS_CARD PCIE_PTX_C_DRX_P4
DV18 APRXP PCIE_PTX_C_DRX_P4 <15>
37 11 PCIE_PRX_C_DTX_N4 C1026 1 2 .1U_0402_16V7K PCIE_PRX_DTX_N4 Close to connector for EMI request.
1 2 DV18 APTXN PCIE_PRX_DTX_N4 <15>
43 12 PCIE_PRX_C_DTX_P4 C1028 1 2 .1U_0402_16V7K PCIE_PRX_DTX_P4
SDDV33_18 APTXP PCIE_PRX_DTX_P4 <15>
C1027 W=20mils
2.2U_0603_6.3V6K
Please close to pin43 +CRD_POWER
48 MDIO0
MDIO0 47 MDIO1
MDIO1

System
1 46 MDIO2 (40mil)

Card Reader
45,6> PLT_RST# 2 XRSTN MDIO2 45 MDIO3 +CRD_POWER
13 XTEST MDIO3 41 MDIO4
CPPE_N MDIO4 R1463 R1464 800mA
21 42 MDIO5 1 2 MDIO5_R 1 2 MDIO5_RR
17 CR1_LEDN MDIO5 24 MDIO6
+CRD_POWER CR1_PCTLN MIDO6 R_short 0_0402_5% R_short 0_0402_5% 1 JREAD1 ME@ (40mil)
SD_CD# 16 40 MDIO7 C1029 22 11
MS_CD# 15 CR1_CD0N/WAKEN MDIO7 29 MDIO8 XD-VCC SD4-VDD 18
CR1_CD1N MDIO8 1 MS9-VCC
XD_CD# 14 28 MDIO9 10U_0805_10V6K MDIO0 30 (40mil)
33 CR2_CD2N MDIO9 27 MDIO10 C1031 2 MDIO1 29 XD10-D0 9 MDIO5_R
C
34 SPI_CSN MDIO10 26
Close to CONN. 28 XD11-D1 SD5-CLK 4
C
MDIO11 @ 22P_0402_50V8J MDIO2 MDIO0
SPI_SO MDIO11 2 XD12-D2 SD7-DAT0

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
35 25 MDIO12 1 MDIO3 27 3 MDIO1 1 1
30 SPI_SI MDIO12 23 MDIO13 MDIO8 26 XD13-D3 SD8-DAT1 21 MDIO2
SPI_SCK MDIO13 XD14-D4 SD9-DAT2

C1030

C1032

C1033
39 22 MDIO14 MDIO9 25 19 MDIO3
TXIN MDIO14 MDIO10 24 XD15-D5 SD1-DAT3 16 MDIO4
2 MDIO11 23 XD16-D6 SD2-CMD 1 SD_CD# 2 2
XD17-D7 SD-CD 2 MDIO6
MDIO4 33 SD-WP
MDIO6 32 XD07-WE 6
6 MDIO14 34 XD08-WP SD6-VSS 13
31 APGND XD_CD# 39 XD06-ALE SD3-VSS
GND XD01-CD
GND

32 MDIO13 38
38 GND MDIO12 37 XD02-R/B
GND MDIO5_RR 36 XD03-RE 17 MDIO5_R
MDIO7 35 XD04-CE MS8-SCLK 10 MDIO0
JMB389-LGAZ0C_LQFP48_7X7 XD05-CLE MS4-DATA0 8 MDIO1
31 MS3-DATA1 12 MDIO2
40 XD GND MS5-DATA2 15 MDIO3
XD GND MS7-DATA3 14 MS_CD#
MS6-INS 7 MDIO4
MS2-BS 5
41 MS1-VSS 20
+1.8VS_CARD 42 SD CD/WP GND MS10-VSS
SD CD/WP GND
B B
T-SOL_144-1313002600_40P_NR-T
+3VS_CARD
10U_0805_10V6K
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1
C1034

C1036

C1037

+1.8VS_CARD

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2 2 2
1 1 1 1

C1038

C1039

C1040

C1041
2 2 2 2
@ @ 1
Close to pin10 C1042 1
C1043
Close to pin5->1000P->0.1u->10u 0.1U_0402_16V4Z
2 10U_0805_10V6K
2
Close to pin 19,20 Close to pin 36 Close to pin 37 Close to pin 18
XD_CD#
Close to pin 44
SD_CD# +CRD_POWER
A A
1 1
C1044 C1045
MDIO6 1 R1465 2 Title
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1K_0402_5% Security Classification LC Future Center Secret Data
@ 2 @ 2
MDIO13 1 R1466 2
Issued Date 2011/11/01 Deciphered Date 2012/12/31 CARD READER JMB389
1K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 44 of 65
5 4 3 2 1
 Support DC S5 Charge

NOS5C@
R1524 1 2 0_0603_5% +3VALW

S5C@
R1525 1 2 0_0603_5%
close EC +3VL

C1082
EC_SCI#/ EC_SMI# pull up to PCH 1 2 VCOREVCC
+3VALW_R +3VALW_R +3VALW_EC
All capacitors close to EC L80 +3VS
D70 2 1 EC_SMI#_R .1U_0402_16V7K 1 2
<19> EC_SMI# +3VALW_R
RB751V-40_SOD323-2 BLM18PG181SN1D_0603 1
D71 2 1 1
1 EC_SCI#_R C1072 C1073 C1075

0.1U_0402_16V4Z
C1076

0.1U_0402_16V4Z
C1077

0.1U_0402_16V4Z
C1078

0.1U_0402_16V4Z
C1079

0.1U_0402_16V4Z
C1080

0.1U_0402_16V4Z
C1081
<19> EC_SCI# RB751V-40_SOD323-2 1 1 1 1 1 1
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z
@ +3VS +3VALW_EC L81 2
R1519 2 1 1 2 ECAGND 2 2
+RTCBATT BLM18PG181SN1D_0603
0_0402_5% 2 2 2 2 2 2
R1520
2 1
R_short 0_0402_5%

minimum trace width 12 mil Support DC S5 Charge

114
121
127
11

74
12

18
26
50
92
3
U70
+3VALW +3VL

VCC/VCC
VBAT/VCC

AVCC
VCORE/VCC

VSTBY/VCC
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC

1
NOS5C@ S5C@
R1529 R1530
KBRST# 4 24 PWR_LED# 0_0603_5% 0_0603_5%
<19> KBRST# KBRST#/GPB6 PWM0/GPA0 PWR_LED# <47>
pull up to PCH <14> SERIRQ
SERIRQ 5 25 BATT_CHG_LED#
BATT_CHG_LED# <47>

2
LPC_FRAME# 6 SERIRQ/GPM6 PWM1/GPA1 28 BATT_LOW_LED#
<14,37> LPC_FRAME# 7 LFRAME#/GPM5 PWM2/GPA2 29 BATT_LOW_LED# <47> 2 1
LPC_AD3 LED_KB_PWM EC_SMB_CK1
<14,37> LPC_AD3 LAD3/GPM3 PWM3/GPA3 LED_KB_PWM <46>
Support DC S5 Charge LPC_AD2 8 PWM PWM4/GPA4 30 SLI_FAN_PWM For 2nd fan R1417 2.2K_0402_5%
<14,37> LPC_AD2 9 LAD2/GPM2 31 SLI_FAN_PWM <32,41>
LPC_AD1 EC_FAN_PWM For fan
<14,37> LPC_AD1 LAD1/GPM1 PWM5/GPA5 EC_FAN_PWM <40>
LPC_AD0 10 32 BEEP# For EC beep EC_SMB_DA1 2 1
+3VALW <14,37> LPC_AD0 LAD0/GPM0 PWM6/SSCK/GPA6 BEEP# <42>
CLK_PCI_EC 13 LPC 34 EC_INVT_PWM R1424 2.2K_0402_5%
NOS5C@ 2 <18> CLK_PCI_EC 14 LPCCLK/GPM4 PWM7/RIG1#/GPA7 120 EC_INVT_PWM <34>
R1404 1 WRST# ACIN 2 R1430
1
WRST# TMRI0/WUI2/GPC4 ACIN <62> GC6_EVENT# <19,23,32>
100K_0402_5% 1 EC_SMI#_R 15 124 VGA_AC_DET 20120713 --> change to normal footprint
16 ECSMI#/GPD4 TMRI1/WUI3/GPC6 VGA_AC_DET <23> 0_0402_5%
C999 BATT_LEN#
+3VL <53> BATT_LEN# PWUREQ#/BBO/SMCLK2ALT/GPC7 VGA_IMON Cancel
1U_0402_6.3V6K 17 66
S5C@ NC ADC0/GPI0
R1405 1 2 PLT_RST# 22 67 SA_PGOOD SA_PGOOD <56>
2 <18,23,32,37,38,44,6> PLT_RST# 23 LPCRST#/WUI4/GPD2 ADC1/GPI1 68
100K_0402_5% EC_SCI#_R BATT_TEMP +3VS
ECSCI#/GPD3 ADC2/GPI2 BATT_TEMP <53> +3VALW
GATEA20 126 ADC 69 IMVP_IMON
<19> GATEA20 GA20/GPB5 ADC3/GPI3 70 IMVP_IMON <59> 1 2 2 1
LAN_WAKE# R1532 @ 100K_0402_5% EC_FAN_SPEED
ADC4/WUI28/GPI4 71 ADP_I R1431 10K_0402_5%
ADC5/DCD1#/WUI29/GPI5 ADP_I <53,62>
72 AD_ID AD_ID R1533 1 @ 2 100K_0402_5%
ADC6/DSR1#/WUI30/GPI6 73 AD_ID <53> 2 1
LID_SW# SLI_FAN_SPEED
KSO[0..15] ADC7/CTS1#/WUI31/GPI7 LID_SW# <46> for power adapter ID OPT,35W --> R1532
<46> KSO[0..15] KSI0 58 R1485 10K_0402_5%
KSI1 59 KSI0/STB# 78 SUSWARN# 3V--- 90W OPT,45W --> R1532, R1533
KSI1/AFD# DAC2/TACH0B/GPJ2 SUSWARN# <16> 1.5V--- 120W SLI --> R1533 +3VS
<46> KSI[0..7] KSI[0..7] KSI2 60 79 AC_PRESENT
KSI2/INIT# DAC3/TACH1B/GPJ3 AC_PRESENT <16> 0V--- 170W
KSI3 61 DAC 80 DRAMRST_CNTRL_EC
62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 DRAMRST_CNTRL_EC <7> 1 2
KSI4 EC_WL_OFF# TP_CLK
KSI4 DAC5/RIG0#/GPJ5 EC_WL_OFF# <37> 1. Change BOM structure of R1532 and R1533 to "@"
KSI5 63 R1410 4.7K_0402_5%
KSI6 64 KSI5 85 USB_CH# 2. For Adapter AD_ID function, Power team had
KSI6 PS2CLK0/TMB0/GPF0 USB_CH# <49> reserved resistance (PR396, Pr397) at power side
KSI7 65 PS2 86 PBTN_OUT# TP_DATA 1 2
KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# <16>
KSO0 36 87 PM_SLP_SUS# R1412 4.7K_0402_5%
KSO0/PD0 PS2CLK1/DTR0#/GPF2 PM_SLP_SUS# <16,51>
KSO1 37 Int. K/B 88 SUSACK#
KSO1/PD1 PS2DAT1/RTS0#/GPF3 SUSACK# <16> +3VS
KSO2 38 89 TP_CLK
Matrix TP_CLK <46>

EXTERNAL SERIAL FLASH

KSO3 39 KSO2/PD2 PS2CLK2/WUI20/GPF4 90 TP_DATA
KSO3/PD3 PS2DAT2/WUI21/GPF5 TP_DATA <46>
KSO4 40 EC_SMB_CK2 2 1
KSO5 41 KSO4/PD4 96 CAPS_LED#
KSO5/PD5 WUI19/GPH3/ID3 CAPS_LED# <47> R1423 2.2K_0402_5%
KSO6 42 97 PCH_PWR_EN
KSO6/PD6 GPH4/ID4 PCH_PWR_EN <51>
KSO7 43 98 ACOFF R1433 EC_SMB_DA2 2 1
44 KSO7/PD7 GPH5/ID5 99 ACOFF <62> 1 2
KSO8 PCH_PWROK PCH_PWROK @ R1422 2.2K_0402_5%
KSO8/ACK# GPH6/ID6 PCH_PWROK <16>
KSO9 45
KSO9/BUSY 10K_0402_5%
EC_SMB_CK1 KSO10 46 101 GPG3 +5VALW
<49,53,62> EC_SMB_CK1 51 KSO10/PE GPG3 102
EC_SMB_DA1 KSO11 GPG4
<49,53,62> EC_SMB_DA1 KSO11/ERR# GPG4
KSO12 52 SPI Flash ROM 103 GPG5 USB_CH# 1 2
EC_SMB_CK2 KSO13 53 KSO12/SLCT GPG5 105 CMOS_ON# R1482 10K_0402_5%
<15,23,32,40> EC_SMB_CK2 KSO13 GPG7 CMOS_ON# <34>
EC_SMB_DA2 KSO14 54
<15,23,32,40> EC_SMB_DA2 KSO14
KSO15 55 USB_ON# 1 2
56 KSO15 108 EC_RX 10K_0402_5%
Reserved SMBus channel 0 KSO16/SMOSI/GPC3 RXD/SIN0/GPB0 EC_RX <37>
R1409
for debugging 57 UART 109 EC_TX
KSO17/SMISO/GPC5 TXD/SOUT0/GPB1 EC_TX <37>

EC_SMB_CK2 110 82 SYSON

111 SMCLK0/GPB3 EGAD/WUI25/GPE1 83 SYSON <55> +3VS
Please place R1435 EC_SMB_DA2 SM Bus SUSP#
SMDAT0/GPB4 EGCS#/WUI26/GPE2 SUSP# <32,51,55,57>
close to EC within 790mil EC_SMB_CK1 115 84 VR_ON
116 SMCLK1/GPC1 EGCLK/WUI27/GPE3 VR_ON <59> 2 1
EC_SMB_DA1 EC_FAN_PWM @
H_PECI R1435 2 1 43_0402_1% PECI_EC 117 SMDAT1/GPC2 77 EC_MUTE# R1402
<6> H_PECI SMCLK2/PECI/WUI22/GPF6 GPJ1 EC_MUTE# <43> 10K_0402_5%
LAN_PWR_ON# 118 100 ENBKL
<38> LAN_PWR_ON# SMDAT2/PECIRQT#/WUI23/GPF7 SSCE0#/GPG2 ENBKL <34>
<16> PM_SLP_S3# PM_SLP_S3# 94 GPIO SSCE1#/GPG0 106 H_PROCHOT#_EC 2 @ 1 R1429
WUI17/CRX1/SIN1/SMCLK3/GPH1/ID1 PROCHOT <53> +3VS
<16> PM_SLP_S4# PM_SLP_S4# 95 104 ME_FLASH 0_0402_5%
WUI18/CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 ME_FLASH <14>
EC_ON
DTR1#/SBUSY/GPG1/ID7 EC_ON <50,54>
119 BKOFF#
CRX0/GPC0 BKOFF# <34>
EC_RSMRST# 112 123 AOAC_ON LPC_FRAME# 1 2
<16> EC_RSMRST# 125 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 CTX0/TMA0/GPB2 AOAC_ON <51>
<50> ON/OFF ON/OFF TouchPad_LED R1521 10K_0402_5%
PWRSW/GPE4
WAKE UP TP_LED# <47>
76 TP_LED# 1 @ 2 R1619
TACH2/GPJ0 A_DET#_R <49>
48 SLI_FAN_SPEED 0_0402_5%
TACH1A/TMA1/GPD7 SLI_FAN_SPEED <32,41>
NOVO# 19 47 EC_FAN_SPEED
<50> NOVO# 33 BAO/WUI24/GPE0 TACH0A/GPD6 EC_FAN_SPEED <40>
USB_ON#
<48,49> USB_ON# GINT/CTS0#/GPD5
DPWROK_EC 35 GPIO
<16> DPWROK_EC 93 RTS1#/WUI5/GPE5
NUM_LED# only for Y500 CLKRUN#/WUI16/GPH0/ID0 R1427
VR_HOT# 1 2 H_PROCHOT# <53,6>
<59> VR_HOT#
EC_LID_OUT# 2 R_short 0_0402_5%
<19> EC_LID_OUT# CK32KE/GPJ7

1
128 Clock D
CK32K/GPJ6
H_PROCHOT#_EC 2 1
R1539 1 2 ECR_EN_R G
<34> ECR_EN
AVSS/AGND

0_0402_5% Q141 S C1004

3
VSS/GND
VSS/GND
VSS/GND
VSS/GND
VSS/GND
VSS/GND
VSS/GND
VSS/GND

2N7002H_SOT23-3 47P_0402_50V8J
1

R1540 1 @ 2 2
<10> CPU1.5V_S3_GATE
0_0402_5% R1102
100K_0402_5%
For Deep S3
R1542 1 GC6@ 2 IT8580E-HX_LQFP128
2

1
20
21
27
49
91
113
122

75

<23,27> FB_CLAMP
0_0402_5%
ECAGND

EMC Request BATT_TEMP 1 2 SUSP# SYSON +3VALW

C1000 100P_0402_50V8J

1
1
SYSON ACIN 1 2

2
C1001 100P_0402_50V8J
100K_0402_5% 100K_0402_5%
R1434
C1007
0.1U_0402_10V6K

R1101 R1522
10K_0402_5%

2
1

2
@

1
2 LAN_WAKE#
LAN_WAKE# <37,38>
For factory EC flash

GPG5 PAD IT0

CMOS_ON# PAD IT1
GPG3 PAD IT2
GPG4 PAD IT3
H_PROCHOT#_EC PAD IT4
PAD IT5
PAD IT6 Security Classification LC Future Center Secret Data Title
PAD IT7
Issued Date 2011/11/01 Deciphered Date 2012/12/31 EC IT8580E
WRST# PAD IT8 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 45 of 65
 5 4 3 2 1

14" INT_KBD Conn.

KSI[0..7]
KSI[0..7] <45>
KB Lighting CONN.4pin
KSO[0..15]
KSO[0..15] <45>
D JKBL1 D
+VCC_KB_LED
JKB1 1
KSO2 C734 1 2 @ 100P_0402_50V8J KSO1 C735 1 2 @ 100P_0402_50V8J KSI1 1 2 1
KSI7 2 1 3 2
2 3

0.1U_0402_10V6K
KSO15 C736 1 2 @ 100P_0402_50V8J KSO7 C737 1 2 @ 100P_0402_50V8J KSI6 3 4
3 4

C905
KSO9 4 2 5
KSO6 C738 1 2 @ 100P_0402_50V8J KSI2 C739 1 2 @ 100P_0402_50V8J KSI4 5 4 6 G1
KSI5 6 5 G2
KSO8 C740 1 2 @ 100P_0402_50V8J KSO5 C741 1 2 @ 100P_0402_50V8J KSO0 7 6 @ E&T_6906-Q04N-00R
KSI2 8 7 1 ME@
KSO13 C742 1 2 @ 100P_0402_50V8J KSI3 C743 1 2 @ 100P_0402_50V8J KSI3 9 8
KSO5 10 9
KSO12 C744 1 2 @ 100P_0402_50V8J KSO14 C745 1 2 @ 100P_0402_50V8J KSO1 11 10
KSI0 12 11
KSO11 C746 1 2 @ 100P_0402_50V8J KSI7 C747 1 2 @ 100P_0402_50V8J KSO2 13 12
KSO4 14 13
KSO10 C748 1 2 @ 100P_0402_50V8J KSI6 C749 1 2 @ 100P_0402_50V8J KSO7 15 14
KSO8 16 15 +5VS
KSO3 C750 1 2 @ 100P_0402_50V8J KSI5 C751 1 2 @ 100P_0402_50V8J KSO6 17 16 AO3413
KSO3 18 17 VGS= -4.5V, Id=-3A, Rds<97m ohm
KSO4 C752 1 2 @ 100P_0402_50V8J KSI4 C753 1 2 @ 100P_0402_50V8J KSO12 19 18 +VCC_KB_LED
KSO13 20 19 Q121 AO3413_SOT23-3
20

1
KSI0 C754 1 2 @ 100P_0402_50V8J KSO9 C755 1 2 @ 100P_0402_50V8J KSO14 21 KBL@
22 21 3 1

D
KSO11
KSO0 C756 1 2 @ 100P_0402_50V8J KSI1 C757 1 2 @ 100P_0402_50V8J KSO10 23 22 R1229
KSO15 24 23 10K_0402_5%
25 24 KBL@ 1 1

G
2

0.01U_0402_25V7K
2

2
26 G1 @ @
CONN PIN define need double check G2 C1053 C1054 C908@
0.1U_0402_16V4Z
ACES_85202-24051 2 2 0.1U_0402_16V4Z
ME@ 1 2 1
R1232 0_0402_5%
C 1 C
KBL@
C907
@

1
D 0.01U_0402_16V7K
2
2 Q122
<45> LED_KB_PWM
G 2N7002_SOT23

1
S KBL@

3
R1480
100K_0402_5%
KBL@

2
To TP/B Conn.

JTP1 ME@
SMB_DATA_S3 1
<12,13,15,37> SMB_DATA_S3 SMB_CLK_S3 2 1
<12,13,15,37> SMB_CLK_S3 3 2
TP_DATA 4 3
<45> TP_DATA 5 4
TP_CLK
B <45> TP_CLK
1
@
1
@
+3VS
6 5
6 Lid Switch B

C761 C762 C760 7

100P_0402_50V8J 100P_0402_50V8J 8 GND
2 2 0.1U_0402_16V4Z GND
ACES_88514-00601-071
1 R1002 2
+3VALW +VCC_LID R1003 1 2 100K_0402_5%
R_short 0_0402_5%

2
5711ACDL-M3T1S SOT-23
D58

VDD
4 1
I/O3 I/O1 1
+3VALW 3
OUTPUT LID_SW# <45>
C758
0.1U_0402_16V4Z 2

GND
5 2 2
VDD GND
C759
U37 10P_0402_50V8J

1
1
6 3
I/O4 I/O2

AZC099-04S.R7G_SOT23-6
@
For ESD request

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 KB /SW /LPC DEBUG CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 46 of 65
5 4 3 2 1
 +3VALW +3VALW
BATT_LOW_LED#_R BATT_CHG_LED#_R
BATT CHARGE/LOW LED

1
R1562 R1558
100K_0402_5% 100K_0402_5% White

6
D Q160A D Q158A LED2
Amber

2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
2 2
2 R1012 1 3
G G BATT_LOW_LED#_R
1 1 470_0402_5%
S S White 1
C1100 C1098 +5VALW

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z R1014 1

3
D D BATT_CHG_LED#_R 2 2
5 2 5 2
<45> BATT_LOW_LED# <45> BATT_CHG_LED# 470_0402_5%
G G
Q160B Q158B 12-22-S2ST3D-C30-2C_WHI-ORG
S 2N7002KDWH_SOT363-6 S 2N7002KDWH_SOT363-6

4
R1564 1 @ 2 R1561 1 @ 2
0_0402_5% 0_0402_5% 2012-0507 --> Add MOS solution onLED3, 2 to avoid the light blinked.

PWR LED HDD LED CapsLK LED

+3VALW +5VS @
PWR_LED#_R 1 R1491 2 TP_LED#_R
+5VS
1

10K_0402_1% White

1
R1559
100K_0402_5% LED3
1 2 2 R1013 1
R1490 <50> PWR_LED#_R +5VALW
@
10K_0402_1%
300_0402_5%
2

6
D Q159A @ D Q151A 12-21SYGCS530-E1S155TR8_W

2
2 2

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6
G G
TouchPad_LED 2012-0507 --> Change LED1 to T/P LED
1 LED1
R1322 1
S <45> TP_LED# R1621 1 2 S TP_LED#_R 1 2 2
+5VS
C1099
1

1
0_0402_5%
0.1U_0402_16V4Z 300_0402_5%

3
D
3

D @ 12-21SYGCS530-E1S155TR8_W
5 2 R1622 1 @ 2 5
<45> PWR_LED# <14> HDD_LED#
G 0_0402_5% G
Q159B Q151B LED4
2N7002KDWH_SOT363-6 1 2 2 R1323 1
S 2N7002KDWH_SOT363-6 S <45> CAPS_LED# +5VS

4
4

300_0402_5%
12-21SYGCS530-E1S155TR8_W
R1560 1 @ 2 R1492 1 2 LED3 LED2 LED1 LED4
0_0402_5% 0_0402_5%

POWER BATTERY T/P CapsLK

Screw Hole
BlueTooth DC

+3VS +3VS_BT
CPU and GPU: H_3P8X 6 MIN PCIE: H_3P3 X 1
BT@ Q154 30mils
AO3413_SOT23-3
C: H_3P8X 3 B: H_3P8X 3 E: H_3P3X 1
3 1
S

H13 H10 H12 H11 H14 H15 H28

1 1 1 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
C1070 C1069 C1083
G
2

BT@ 0.1U_0402_16V4Z BT@ 0.01U_0402_25V7K BT@ 0.1U_0402_16V4Z

1
1
BT@ 2 2 2
1 R1526 2
<19,37> PCH_BT_ON#
100K_0402_5%
CPU GPU
1
C1084
@ 0.1U_0402_16V4Z
2

BT Conn.
+3VS_BT
JBT1 ME@ ME: H_8P0 X 8; H_3P3X 1; H_4P0X3P0N X 2; H_2P0X 1
1
2 1
USB20_P13 3 2 A: H_2P8X 8
<18> USB20_P13 3
<18> USB20_N13 USB20_N13 4
4 H16 H22 H24 H25 H31 H33
H30 H32
5 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
6 GND
GND
ACES_50209-0040N-001

1
1

1
1

1
E: H_3P3X 1 H_4P0X3P0NX 3 H_2P0X 2
H29 H20 H21 H23
HOLEA HOLEA HOLEA HOLEA

1
1

1
PCB Fedical Mark PAD
Security Classification LC Future Center Secret Data Title
FD1 FD2 FD3 FD4
Issued Date 2011/11/01 Deciphered Date 2012/12/31 LED/EC SPI ROM/BT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
1

Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 47 of 65
 A B C D E

LEFT SIDE USB3.0 PORT X1

+5VALW +USB_VCCA
U39
1 8
C767 0.1U_0402_16V4Z 2 GND VOUT 7
1 2 1 3 VIN VOUT 6 1
USB_ON# 4 VIN VOUT 5 USB_OC1#
<45,49> USB_ON# EN FLG USB_OC1# <18> +USB_VCCA
G547I2P81U_MSOP8 C814 220U_6.3V_M
1
C904 1 2
Low Active 2A @ 1000P_0402_50V7K

+
2 1 2
C816 470P_0402_50V7K

JUSB1
For EMI request 1
USB20_N2 R1162 1 2 0_0402_5% USB20_N2_R 2 VBUS
<18> USB20_N2 @ D-
USB2.0 choke --> SM070000I00 <18> USB20_P2
USB20_P2 R1163 1 @ 2 0_0402_5% USB20_P2_R 3
4 D+
USB3.0 Choke --> SM070001U00 USB30_RX_N3 R1154 1 2 0_0402_5% USB30_RX_R_N3 5 GND_1
<18> USB30_RX_N3 @ SSRX-
USB30_RX_P3 R1155 1 @ 2 0_0402_5% USB30_RX_R_P3 6 13
<18> USB30_RX_P3 SSRX+ GND_6
7 12
USB30_TX_N3 C300 1 2 0.1U_0402_10V6K USB30_TX_C_N3 R1156 1 2 0_0402_5% USB30_TX_R_N3 8 GND_2 GND_5 11
<18> USB30_TX_N3 @ SSTX- GND_4
USB30_TX_P3 C299 1 2 0.1U_0402_10V6K USB30_TX_C_P3 R1157 1 @ 2 0_0402_5% USB30_TX_R_P3 9 10
L68 <18> USB30_TX_P3 SSTX+ GND_3
USB30_RX_N3 2 1 USB30_RX_R_N3 SANTA_370300-1
2 1

ME@
USB30_RX_P3 3 4 USB30_RX_R_P3
3 4
2 2
WCM-2012-900T_4P

L70
USB30_TX_C_N3 2 1 USB30_TX_R_N3
2 1
For ESD request
USB30_TX_C_P3 3 4 USB30_TX_R_P3
3 4 D27 D24
@ @
WCM-2012-900T_4P USB30_RX_R_N3 9 10 1 1USB30_RX_R_N3 USB20_N2_R 3 6
I/O2 I/O4
L72 USB30_RX_R_P3 8 9 2 2 USB30_RX_R_P3
USB20_N2 2 1 USB20_N2_R
2 1 USB30_TX_R_N3 7 4 USB30_TX_R_N3 2 5
7 4 +5VALW
GND VDD
USB20_P2 3 4 USB20_P2_R USB30_TX_R_P3 6 6 5 5 USB30_TX_R_P3
3 4
WCM-2012-900T_4P 3 3 1 4 USB20_P2_R
I/O1 I/O3
8
AZC099-04S.R7G_SOT23-6

YSCLAMP0524P_SLP2510P8-10-9

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 USB3.0 PORT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 48 of 65
A B C D E
 5 4 3 2 1

Sleep & Charge

Right side USB Charger Port (USB_Port5, near JMIC1)
D D

+5VALW +5V_CHGUSB
Active Mode Selection:

0.1U_0402_16V4Z
1U_0402_6.3V6K
1 2

C1093
M1 M2 EM_EN ACTIVE MODE

C1094
2 1
0 0 1 Dedicated Charger Emulation Cycle
0 1 0 Date Pass-through
Del C1095 0 1 1 BC1.2 DCP
1 0 0 BC1.2 SDP

9
U8 1 0 1 Dedicated Charger Emulation Cycle
1 1 0 Date Pass-through

VDD
7 *1 1 1 BC1.2 CDP
+5VALW VS1
1 1 3 R1587
VBUS1
10U_0603_6.3V6M

0.01U_0402_16V7K

8 4 10K_0402_5% +3VALW
VS2 VBUS2
C1096

C1097

1 @ 2
2 2 USB20_P5 14 17 USB20_P5_C R1583
<18> USB20_P5 DPIN DPOUT ILIM SETTING SEL Pin Decode
USB20_N5 15 16 USB20_N5_C 10K_0402_5%
<18> USB20_N5 DMIN DMOUT 1 2
USB_CH# 10 18 A_DET#_R Pull Low Pull Low
<45> USB_CH# PWR_EN A_DET# 13 A_DET#_R <45>
USB_OC2# OR-500mA 0R -1010_000
EM_EN 19 ALERT# 11 EC_SMB_DA1 USB_OC2# <18> 10K-900mA
EM_EN SMDATA/LATCH EC_SMB_DA1 <45,53,62> * 10K-1010_000
12 EC_SMB_CK1 12K-1000mA 12K-1010_000
CH_M1 1 SMCLK/S0 6 CH_SEL 1 2 EC_SMB_CK1 <45,53,62> 15K-1200mA 15K-1010_000
M1 SEL

GND FLAG
CH_M2 2 5 CH_ILIM 1 2 R1553 18K-1500mA 18K-0110_000
M2 COMM_SEL/ILIM R1555 10K_0402_5% 22K-1800mA 22K-0110_000
33K_0402_5% 27K-2000mA 27K-0110_000

GND
C C
* 33K-2500mA 33K-0110_000
R1551 1 2 EM_EN R1584 2 @ 1
+5VALW
10K_0402_5% 10K_0402_5%

21

20
UCS1002-1-BP-TR_QFN20_4X4
R1585 1 2 CH_M1 R1552 2 @ 1
10K_0402_5% 10K_0402_5%

R1586 1 2 CH_M2 R1554 2 @ 1

10K_0402_5% 10K_0402_5%

2012-0429 --> Set default mode is "BC1.2 CDP" Mode (2.5A on S0)for USB Port5

USB Power (USB20_P9) AUDIO/B Conn.

JSB1 ME@
1
+5VS 1
2
+5VALW +USB_VCCB +USB_VCCB 2
3
U69 4 3
B 1 8 5 4 B
GND VOUT +5V_CHGUSB 5
2 7 6
3 VIN VOUT 6 7 6
USB_ON# 4 VIN VOUT 5 USB_OC4# 8 7
<45,48> USB_ON# EN FLG USB_OC4# <18> 8
9
G547I2P81U_MSOP8 10 9
1 1 10
Low Active 2A 11
C988 C989 USB20_P9 12 11
@
0.1U_0402_16V4Z 1000P_0402_50V7K <18> USB20_P9 USB20_N9 13 12
2 2 <18> USB20_N9 14 13
USB20_P5_C 15 14
USB20_N5_C 16 15
17 16
EXT_MIC_L 18 17
EXT_MIC_R 19 18
MIC_JD 20 19
<42> MIC_JD 20
HP_OUTR 21
<42> HP_OUTR HP_OUTL 22 21
<42> HP_OUTL SPDIF_OUT 23 22
<42> SPDIF_OUT PLUG_IN 24 23
<42> PLUG_IN 24
25
26 GND1
Ext. MIC +MIC1_VREFO_L
GND2
ACES_88514-02401-071
+MIC1_VREFO_R

Realtek Review 10.24

A A

Remove Diode (DA1, DA2)

2

RA1622 RA1623
2.2K_0402_5% 2.2K_0402_5%

Security Classification LC Future Center Secret Data Title

1

RA1634 2 1 1K_0402_5% EXT_MIC_R

<42> MIC2_R Issued Date 2011/11/01 Deciphered Date 2012/12/31 AUDIO/B, USB CHARGER
RA1633 2 1 1K_0402_5% EXT_MIC_L
<42> MIC1_R THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 49 of 65
5 4 3 2 1
ON/OFF switch Power Button/B link
Support DC S5 Charge

SW 2@ +3VALW +3VL
to Function/B Conn. 10pin
1 3
Power Button

2
TOP Side 2 4
NOS5C@ S5C@
SMT1-05_4P R1116 R1117

6
5
100K_0402_5% 100K_0402_5%

1
J7 @
S5C@
Bottom Side 1 2 R1531 1 2 0_0603_5%
+5VALW
SHORT PADS JPW R1 ME@
D72 NOS5C@
1
3 ON/OFF 2 1
ON/OFF <45>
ON/OFFBTN# 1 NOVO_BTN# 3 2
2 51_ON# 4 3
51_ON# <52> <47> PW R_LED#_R
ON/OFFBTN# 5 4
DAN202UT106_SC70-3 6 5
6
@ 1 7
C551 8 GND
D

1
GND
EC_ON 2 100P_0402_50V8J ACES_88514-00601-071
<45,54> EC_ON
G 2

2
S Q153

3
R1523 2N7002_SOT23-3 9/23 ESD Request
10K_0402_5%

1
Support DC S5 Charge

+3VALW +3VL
2

2
R1119
R1118
NOS5C@ S5C@ 100K_0402_5%
100K_0402_5%
1

D56
NOVO# 2
<45> NOVO#
1 NOVO_BTN# EMI REQUEST 1ST = SCA00000E00
51_ON# R19 1 NOS5C@ 2 0_0402_5% 3
2ST = SCA00000R00
ON/OFF R28 1 @ 2 0_0402_5% DAN202UT106_SC70-3

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 OTHER I/O CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 50 of 65
 A B C D E

+5VALW to +5VS +3VALW to +3VS +1.5V to +1.5VS

J15 @
1 2
AP4800BGM AP4800BGM
+1.5V_CPU_VDDQ 1 2 +1.5VS
VGS=10V, ID=9A, Rds=18m ohm VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V VGS=+-25V JUMP_43X79

+5VALW +5VS +3VALW +3VS

+1.5V +1.5VS
U46 U47
8 1 8 1 3 1

D
1
1 7 2 1 1 1 7 2 1 1 1 1
1 6 3 6 3 C856 Q120 1
5 5 C857 C835
C837 C838 C840 C841 10U_0805_10V6K

G
10U_0603_6.3V6M 1U_0603_10V4Z

2
C836 10U_0603_6.3V6M 1U_0603_10V4Z C839 10U_0603_6.3V6M 1U_0603_10V4Z 2 SI2301BDS-T1-E3_SOT23-3

1
2 10U_0805_10V6K AP4800BGM-HF 2 2 2 10U_0805_10V6K AP4800BGM-HF 2 2 2 2
4

4
R1474 +3VALW
R1475 @ @
470_0603_5%

1
470_0603_5%

1
2

2
R1481 @
R1087 470_0603_5%
100K_0402_5%
R1088 2 R1085 R1089 2 2 R1086

2
5VS_GATE_R 1 5VS_GATE 3VS_GATE_R 1 3VS_GATE 1
+VSB +VSB R1090 2 1.5VS_GATE

2
1
82K_0402_5% 150K_0402_5% R_short 0_0402_5% 470K_0402_5%
1 1 R_short 0_0402_5% 1
1

3
C842 D D C843 D D D D
0.01U_0402_25V7K 2 5
SUSP 0.01U_0402_25V7K 2 SUSP5 SUSP# 2 C845 1.5VS_GATE 5
R1484 G G R1483 G G G G
@ @ .1U_0402_16V7K
2 820K_0402_5% 2 820K_0402_5% 2
Q99A Q99B Q100A Q100B Q101A
S 2N7002KDWH_SOT363-6 S S 2N7002KDWH_SOT363-6 S S 2N7002KDWH_SOT363-6 Q101B S
2

4
2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6

+5VALW +3VALW to +3V_PCH +5VALW to +5V_PCH

+5VALW +0.75VS
1

+3VALW +3V_PCH +5VALW +5V_PCH

J11 @ J14 @

1
R1120 1 2 1 2
DS3@
100K_0402_5% 1 2 1 2
1 1 R1097 R1094
2 C38 @ C39 @ 100K_0402_5% 22_0603_5% 2
JUMP_43X79 JUMP_43X79
2

PCH_PWR_EN#_R R60 1 DS3@ 2 PCH_PWR_EN# 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2
100K_0402_5% SUSP
D DS3@ <10,37,55,57> SUSP
1

2 2
PCH_PWR_EN 1 R117 2 2 Q118 Q148 Q149
<45> PCH_PWR_EN

3
G 2N7002_SOT23 AO3413_SOT23 AO3413_SOT23 D D
R_short 0_0402_5% 2 5
S SUSP
3

<32,45,55,57> SUSP#
1

PM_SLP_SUS# R1448 2 1 3 1 1. C38, C39 resistance change to 0.1u_0402 3 1

D
@ G G
<16,45> PM_SLP_SUS# 2. and the BOM structure as "@" for discharge
0_0402_5% Q107B
R1121 DS3@ 1 DS3@ 1 1 DS3@ 1 Q107A S S 2N7002KDWH_SOT363-6

4
100K_0402_5% 2N7002KDWH_SOT363-6

G
C1065 C1067

2
DS3@ DS3@ C1066 DS3@ DS3@ C1068
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2

0.01U_0402_25V7K 0.01U_0402_25V7K For Intel S3 Power Reduction.

2 2 2 2

PCH_PWR_EN#_R PCH_PWR_EN#_R

+5VALW

+3VALW +3VS +3VS_VGA

+3VS to +3VS_VGA
1

R1122 Q145

1
AOAC@
100K_0402_5%
AO3413_SOT23
R6 +5VALW
@
2

100K_0402_5% 3 1

D
AOAC_ON#
<37> AOAC_ON#
1 1

2
D AOAC@
1

1
AOAC@ 2 <57> 0.75VR_EN# C1058 C1059

1
AOAC_ON R1453 1 2 Q119

G
<45> AOAC_ON R1449 2

2
0.1U_0402_16V4Z 0.01U_0402_25V7K

3
0_0402_5% G 2N7002_SOT23 D@
2 R8 @ 1 0.75VR_EN 5 47K_0402_5% 2 2
S <56,57> +V1.05S_VCCP_PWRGOOD R1450 @ C37
3
1

G 470_0603_5% 10U_0603_6.3V6M
100K_0402_5%

2
3 Q144B 1 3
1 R1451

2
6
R1123 AOAC@ D@ 2
S DGPU_PWR_EN#

4
100K_0402_5% 2
SUSP 2N7002KDWH_SOT363-6
G 10K_0402_5%
Q144A 1
2

3
D C1011 D
2N7002KDWH_SOT363-6
S 2 R1452 1 2 0.1U_0402_10V7K @ DGPU_PWR_EN# 5
<18,23> DGPU_PWR_EN
1

G G
R_short 0_0402_5% 2
Q146A Q146B

1
S 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6 S

4
R1454
100K_0402_5%
For S3 CPU Power Saving

2
+3VS +3VS_SLI
+3VS to +3VS_SLI
2012-0419 --> modify +3VS_SLI BOM structure to "SLI@" Q147 SLI@
AO3413_SOT23
+5VALW
3 1
S

1 1
1

SLI@ SLI@
C1062 C1063
1

SLI@
G

R1502 0.1U_0402_16V4Z 0.01U_0402_25V7K 2

2

47K_0402_5% 2 2 R1500 @ C48 SLI@

470_0603_5% 10U_0603_6.3V6M
2

4 SLI@ 1 4
1 R1513
2

2
<32> S_DGPU_PWR_EN#
10K_0402_5%
1
6

SLI@ D C1012 D
2 R1503 1 2 S_DGPU_PWR_EN# 5
0.1U_0402_10V7K @
<19,32> S_DGPU_PWR_EN G G
0_0402_5% 2
Security Classification LC Future Center Secret Data Title
1

S Q150A SLI@ SLI@ Q150B S

1

SLI@ R1501 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6

100K_0402_5%
Issued Date 2011/11/01 Deciphered Date 2012/12/31 DC INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
2

Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, March 11, 2013 Sheet 51 of 65
A B C D E
 5 4 3 2 1

DC030006J00 VIN B+ to SLI_B+

PF1 PL1
B+ B+_SLI
12A_65V_451012MRL SMB3025500YA_2P SLI@
4
4 APDIN 1 2 APDIN1 1 2 PQ49
AON7403L_DFN8-5
+5VS to +5VS_SLI
3 1 JUMP_43X79
3 +5VS +5VS_SLI
2 5
PJ19

1000P_0402_50V7K

1000P_0402_50V7K

@
100P_0402_50V8J

100P_0402_50V8J

0.1U_0603_25V7K
2 3
2

PC348
1 2
1 2

SLI@
D 1 D
1

0.22U_0603_25V7K

2
PQ50 AO6409L_TSOP6

2
@ 4602-Q04C-09R 4P P2.5

PC1

PC2

PC3

PC4

D
2

2
JDCIN1

PC347

SLI@
6

S
PR303 4 5
200K_0402_1% 2

0.01U_0402_16V7K
1

0.1U_0402_16V4Z
1 1

2
SLI@

G
1

SLI@
PR305 PC351

PC350
200K_0402_1% 10U_0603_6.3V6M
SLI@ 2 2

PC349
2 SLI@

SLI@
SLI@
PR304
47K_0402_1%
1 2 PR308
<32> SLI_B+_ON#
47K_0402_1%
1 2
<32> SLI_5V_ON#
SLI@

VIN

LL4148_LL34-2
2
PD1
2012/04/13
PD2 add SLI Hot-plug Load-SW solution

1
C LL4148_LL34-2 PJ1 51ON-1 C

BATT+ 2 1 @ JUMP_43X39

1
68_1206_5%

68_1206_5%
1 2
1 2

PR1

PR2
PQ1
PR3 @ TP0610K-T1-E3_SOT23-3

2
200_0402_1%
1 2 51ON-2 3 1
VS
0.22U_0603_25V7K
1

100K_0402_1%

0.1U_0603_25V7K
2

1
PR4

PC5

PC6
1

PR5 2
2

22K_0402_1%
1 2 51ON-3

+3VLP
<50> 51_ON#
- JRTC1 + PR6
560_0603_5%
PR7
560_0603_5%
PD3
2 1 1 2 1 2 2 1
+RTCBATT

RB751V-40_SOD323-2
2

0_0402_5%

@ MAXEL_ML1220T10 1 2 +CHGRTC
+CHGRTC
PR8

PD4
@ PU1 PR9 RB751V-40_SOD323-2
@ 200_0603_5%
RTC Battery
1

APL5156-33DI-TRL_SOT89-3
3.3V
2

3 2CHGRTCIN
B VOUT VIN B
1

GND PC8
PC7 1U_0805_25V6K
10U_0603_6.3V6M 1
@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 VIN DETECTOR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 52 of 65
5 4 3 2 1
 5 4 3 2 1

VMB2 VMB
PF2 PL2
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 2 1 2
1 2 BATT+
2 3 EC_SMCA
3

1
4 EC_SMDA
4 5 PC92
5

1
D 6 33P_0201_50V8J D

2
6

1
7 PC9 PC10
7

100_0402_1%

100_0402_1%
8 1000P_0402_50V7K 0.01U_0402_25V7K

2
GND 9
GND PR10

PR11
TYCO_1775789-1
2

2
@ 2012/0705
add to PC92 for EMI

For KB930 --> Keep PU1 circuit

PH1 under CPU botten side : (Vth = 0.825V)
EC_SMB_CK1 <45,49,62> CPU thermal protection at 92+-3 degree C
For KB9012 (Red square) --> Remove PU1 circuit, but keep PR206
Recovery at 56 +-3 degree C PH201, PR205,PR211,PQ201,PR208,PR212
EC_SMB_DA1 <45,49,62>

1 2
+3VALW
VL
PR12 +3VLP

0.1U_0603_25V7K
6.49K_0402_1%
<45,62> ADP_I PR15

2
4.42K:90W

4.42K_0402_1%

13.7K_0402_1%

21.5K_0402_1%
PC11

1
1 2
BATT_TEMP <45> A/D 9.1K:120W

PR15

PR16

PR17
PR14 @

2
10K_0402_5%
16.5K:170W
+3VS

1
PU2

2
1 8
VCC TMSNS1

100K_0402_1% TSM0B104F4251RZ
2

100K_0402_1%
C 2 7 OTP_N_002 2 1 C
GND RHYST1 PR19

1
PR18

PH1
3 6 Turbo_V 10K_0402_1%
<45,6> H_PROCHOT# OT1 TMSNS2

OTP_N_003
4 5 ADP_OCP_2 1 2

1
OT2 RHYST2

2
D

10K_0402_1%
G718TM1U_SOT23-8 PR20

2
PR21
PQ3 2 ADP_OCP_1 57.6K_0402_1%
2N7002KW_SOT323-3 G
2012/04/13 S
PR20

3
add power adapter ID

1
OPT,35W --> PR396 3V--- 90W
PR22 @
0_0402_5%
PR23
R_short 0_0402_5%
57.6K:90W
+3VALW OPT,45W --> PR396, PR397 1.5V--- 120W <45> PROCHOT 1 2 2 1
MAINPWON <54>
82.5K:120W
SLI --> PR397
0V--- 170W 76.8K:170W
PR396
2 1 AD_ID <45>

100K_0402_5%

2 1

PR397 100K_0402_5%
CPU3@

B B

P2
PQ4
+3VALW +3VALW
0.01U_0402_25V7K

TP0610K-T1-E3_SOT23-3
1

100K_0402_1%

100K_0402_1%
PC12

3 1
VMB2 B+ +VSBP
2

100K_0402_1%
PR24

PR25

0.22U_0603_25V7K
2

1
PR26

PC13
PR27 PR28
2

768K_0402_1% 10M_0402_5% PC14

1

1 2 0.1U_0603_25V7K
BATT_OUT <62>

2
PR29 PQ5

2
10K_0402_1% 2N7002KW_SOT323-3 PR30
8

1 2 VL 22K_0402_1%
1

3 D 1 2
P

+ 1 2
O
2

PR31 2 G
-
G
2

221K_0402_1% PU3A S PR32

3

AS393MTR-E1 SO 8P OP 100K_0402_1%
4

+3VALW PR33 PQ6

1

1K_0402_1% D PJ2
1

1 2 2 2N7002KW_SOT323-3 @ JUMP_43X39
<54> SPOK
100K_0402_1%

2 1 G 1 2
+CHGRTC +VSBP 1 2 +VSB
2

1U_0402_6.3V6K

S
3
1
PR35

PC15

PR34 @
10K_0402_1%
2

2 1
2VREF_8205
1

A PQ7 A
PR37
1

PR36 D 2N7002KW_SOT323-3
10K_0402_1% 2 1 2
<45> BATT_LEN#
G
10K_0402_1% S
3

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 53 of 65
5 4 3 2 1
 5 4 3 2 1

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205 PJ3
+3VALW P 2 1 +3VALW
2 1
@ JUMP_43X118

1U_0603_10V6K
D D

1
PJ4

PC16
+5VALW P
2 1 +5VALW

2
2 1
2012/07/05 @ JUMP_43X118

change PR38 from 13K to 13.7K

PR38 PR39
13.7K_0402_1% 30K_0402_1%
1 2 1 2

PR40 PR41
RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
1 2 1 2
PJ5 Typ: 175mA
B+ 2 1 +3VLP
0.1U_0603_25V7K

2 1

ENTRIP2

ENTRIP1
PC22

@ JUMP_43X118 PR55 PR43 PR42

2200P_0402_50V7K

2200P_0402_50V7K
0.1U_0603_25V7K

0.1U_0603_25V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

0_0402_5% 154K_0402_1% 88.7K_0402_1%

2 1 1 2 1 2
PC17

PC26
+3VL
1

1
PC18

PC19

PC20

PC21

PC23

PC25
2

1
5

2
8
7
6
5

5
6
7
8
4

3
PU4

4.7U_0805_10V6K
2

2
PQ9

ENTRIP2

ENTRIP1
FB2

FB1
TONSEL

REF
1
C PQ8 AO4406AL_SO8 C
25
AO4466L_SO8 P PAD

PC24

2
4 4
7 24
VO2 VO1 SPOK <53>
8 23 PR45 PC28
PR44 VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
1
2
3

3
2
1
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
2.2_0603_5% BOOT2 BOOT1
PL3 PC27 UG_3V 10
VFB=2.0V 21 UG_5V PL4
3.3UH +-20% PCMC063T-3R3MN 6A 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_VMPI1004AR-4R7M-Z01_10A_20% +5VALWP
1 2 LX_3V 11 20 LX_5V 1 2
+3VALWP PHASE2 PHASE1
1

8
7
6
5

1
LG_3V 12 19 LG_5V
4.7_1206_5%

4.7_1206_5%
LGATE2 LGATE1

5
6
7
8
PQ10
PR46

PR47
SKIPSEL
AO4712_SO8 PQ11

VREG5
2012/02/29

GND

150U_B2_6.3VM_R35M

150U_B2_6.3VM_R35M
VIN
RT8205LZQW _W QFN24_4X4

NC
EN
1 1
150U_B2_6.3VM_R35M

change PC29, PC32,

2

2
4

@ 1U_0603_10V6K
1

1
4 + +
PC34 from

PC31

PC32

PC34
13

14

15

16

17

18
1

1
+
PC29

PC30

PR48
680P_0603_50V7K

SGA00001E0J to 499K_0402_1%

680P_0603_50V7K

2
2 2
SGA00002N8J 1 2

PC33
2

1
2
3

2
2 AO4456_SO8
B+

3
2
1
1
100K_0402_1%

1U_0603_10V6K
VL

1
PC35

1
PR49

PC36
Typ: 175mA

4.7U_0805_10V6K
B B

2
ENTRIP1 ENTRIP2
2

2
PQ12B RT8205_B+
6

2N7002KDW -2N_SOT363-6
PR50
PQ12A 0_0402_5% RT8205

0.1U_0603_25V7K
2N7002KDW -2N_SOT363-6 2 5 2 1 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
2VREF_8205

PC37
PR52 @
(2)SMPS2=375KHZ(+3VALWP)
1

PR51 0_0402_5% TPS51125A

2
0_0402_5% 2 1 TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP)
<53> MAINPW ON 2 1 VL
(2)SMPS2=305KHZ(+3VALWP)
PR54 @
PR53 0_0402_5%
100K_0402_1% 2 1
2 1
VL
PR185
<45,50> EC_ON 0_0402_5% +3.3VALWP Imax=7.5A ; Ipeak=9A +5VALWP Imax=11.1A ; Ipeak=13.32A
2 1
@
1/2 Delta I=1.113A (F=375K Hz) 1/2 Delta I=1.33A (F=300K Hz)
Vtrip=0.169V Vtrip=0.098V
1

PQ14 Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Rds(on)=7.0m ohm(max) ; Rds(on)=5.1m ohm(typical)

PR56 2N7002KW _SOT323-3 Ilimit_min=0.169/18m=9.388A Ilimit_min=0.098/7m=14.03A
D
1

200K_0402_1%
2> ACPRN 2 1 2 1 2 2 PQ13 Ilimit_max=0.169/15=11.26A Ilimit_max=0.098/5.1m=19.21A
G VS DTC115EUA_SC70-3 Iocp=Ilimit+1/2Delta I=10.5A~12.373A Iocp=Ilimit+1/2Delta I=15.36A ~ 20.54A
S PR57
40.2K_0402_1%

2.2U_0603_10V6K

A A
3

100K_0402_1%
1

1
PR58

PC38

3
2
2

EC_ON 2 Title
PQ15 Security Classification LC Future Center Secret Data
DTC115EUA_SC70-3
Issued Date 2011/11/01 Deciphered Date 2012/12/31 3VALWP/5VALWP
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 54 of 65
5 4 3 2 1
 A B C D

PJ6
1.5V_B+ 2
2 1
1 B+
Freq= 266~314KHz , 290KHz(typ)

470P_0603_50V7K
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
5
6
7
8
@ JUMP_43X118

1
PC39

PC40

PC41

PC42

PC43
PQ16
Iocp=13.58A~23.10A AO4406AL_SO8

2
4
PR59
0_0402_5%
1 2
<45> SYSON

3
2
1
2
47K_0402_5%
PR61 PC45 PL5

.1U_0402_16V7K
1 1

PC44 @
PR60
PU5 2.2_0603_5% 0.22U_0603_16V7K S COIL 1UH +-20% VMPI0703AR-1R0M-Z01 11A
+1.5VP

1
1 10 BST_1.5V 1 2BST_1.5V-1 1 2 1 2
PGOOD VBST
2 9 DH_1.5V

2
TRIP DRVH
3 8 LX_1.5V

4.7_1206_5%

220U_B2_6.3VM_R15M
EN SW

PR62 @
1

5
6
7
8
4 7
VFB V5IN +5VALW +

PC46
PQ17

1
5 6 DL_1.5V
RF DRVL PC47

84.5K_0402_1%

2
1
11 1U_0603_10V6K 2

470K_0402_1%

2
TP

2
4

PR63

1000P_0603_50V7K
PC48 @
TPS51212DSCR_SON10_3X3 PJ7 +1.5V

1
PR64
VFB=0.7V +1.5VP 2 1
2 1

2
AO4456_SO8 @ JUMP_43X118

3
2
1

2
PR65
1 2
PD9 PJ8
RB751V-40_SOD323-2
11.5K_0402_1%
1.5VSP_VGA_B+ 2
2 1
1 B+
1

1 2

470P_0603_50V7K
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
5
@ JUMP_43X118

1
PC49

PC50

PC51

PC52

PC53
PR66 <BOM Structure>
PR67 10K_0402_1% PQ18
2
0_0402_5% 2
2

2
FBVDDQ_PWR_EN 1 2
4
PR68
@ 0_0402_5%
1 2
<32,45,51,57> SUSP# MDV1525URH_PDFN33-8-5

3
2
1
2
PR69 @
47K_0402_5%

PR70 PC55 PL6

.1U_0402_16V7K
PC54 @

PU6 2.2_0603_5% 0.22U_0603_16V7K 1UH_PCMC063T-1R0MN_11A_20%

+1.5VSP_VGA
1

1 10 1
BST_1.5VSP_VGA 2BST_1.5VSP_VGA-1
1 2 1 2
PGOOD VBST
2 9 DH_1.5VSP_VGA
1

TRIP DRVH
3 8 LX_1.5VSP_VGA

4.7_1206_5%

220U_B2_6.3VM_R15M
EN SW

PR71 @
1
4 7

0.1U_0402_10V7K
VFB V5IN +5VALW

2
+

PC56
1
5 6 DL_1.5VSP_VGA PQ19
RF DRVL

PC58
PC57
75K_0402_1%

1
1

11 1U_0603_10V6K 2
470K_0402_1%

2
TP
2
PR72

1000P_0603_50V7K
PC59 @
TPS51212DSCR_SON10_3X3 4 PJ9 +1.5VS_VGA

1
PR73

VFB=0.7V +1.5VSP_VGA 2 1
2 1
2

@ JUMP_43X118
1

2
AON6504_POW ERDFN56-8-5

3
2
1
PR75
PR74
0_0402_5%
1 2 2 1
VDDQ_SENSE <25>
3 3
1

11.5K_0402_1%
Freq= 266~314KHz , 290KHz(typ) PR76
10K_0402_1% PJ10
2 1
Iocp=12.25A~20.77A +1.05VS +1.05VS_VGA
2

2 1
@ JUMP_43X118
+1.05VS +1.05VS_VGA

8 PQ20 1

10U_0805_25V6K
+5VALW 7 2

@ 470K_0603_5%
1U_0603_10V6K
10U_0805_25V6K

2
+5VALW 6 3
1
PC60

PC61

PC62

PR77
1

2
1

PR78

1
10K_0402_1% PR79
100K_0402_1% AO4456_SO8 PR80 PQ21 @
2

1
@ 0_0402_5% D
PR81
2

1 2 2 2N7002KW _SOT323-3
PR82 1 2 <10,37,51,57> SUSP G
PQ22B

0_0402_5% S
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6

3
<19,27,58> DGPU_PWROK
1

1 2 PR84
100K_0402_1%
3

6
PQ22A

PC63 @ 0_0402_5%
PR83 PD10 0.01u_0603_10V6K 1 2
2

@ 0_0402_5% RB751V-40_SOD323-2
SUSP# 1 2 5 2 1 2
4

1
@ 1U_0603_10V6K
1
PC64

4 4
2

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 1.5VP/1.5VSP_VGA/1.05VSP_VGA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 55 of 65
A B C D
 5 4 3 2 1

+3VS PR85
1K_0402_1%
2 1
VID [0] VID[1] VCCSA Vout PJ11
0 0 0.9V +VCC_SAP

100K_0402_5%
H_VCCSA_VID1 <10> +VCCSAP 1 2 +VCCSA
TDC 4.2A

1
0 1 0.8V PAD-OPEN 4x4m

PR86
Peak Current 6A
1 0 0.725V OCP current 7.2A

2
1 1 0.675V H_VCCSA_VID0 <10>

PR87
<45> SA_PGOOD
1K_0402_1%
output voltage adjustable network 2 1
D D
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that

H_VCCSA_VID0
H_VCCSA_VID1
+5VALW VCCSA VID is 00 prior to VCCIO stability.

SA_PGOOD
1U_0603_10V6K
2

PC65
PR88 PR89
10_0402_1% 0_0402_5%

1
2 1 +VCCSA_EN 1 2
+V1.05S_VCCP_PWRGOOD <51,57>
PC66
2.2U_0603_10V7K
1 2

18

15

14
17

13
16
PU7
PR90 PC67

VID1

VID0

EN
V5DRV

V5FILT

PGOOD
2.2_0603_5% 0.22U_0603_16V7K
12 +VCCSA_BT 1 2 +VCCSA_BT_1 1 2
19 BST PL7
PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
SW
11 +VCCSA_PHASE 1 2 +VCCSAP
20
PGND

22U_0805_6.3V6M

22U_0805_6.3V6M

0.1U_0402_10V7K
10

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
2200P_0402_50V7K
1
21 SW
2200P_0402_50V7K

PC68 @ @ @ @
0.1U_0603_25V7K

PGND

2
10U_0805_6.3V6M

10U_0805_6.3V6M
1000P_0603_50V7K

PC69

PC70

PC72

PC73

PC75

PC76
9

PC71

PC74
TPS51461RGER_QFN24_4X4

1 2
22 SW
PC78

1 2 2

1
2

VIN
PC77

PC79

PC80

8 PR91
23 SW 4.7_1206_5%
1

2 1 1 VIN
PJ12 7

2
+3VALW 2
2 1
1 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 24
VIN
SW

C @ JUMP_43X118 25 C

COMP

MODE
TP

SLEW

VOUT
VREF
GND
1

6
@ PR92
2 1

33K_0402_5%
PC81 PR93
2 1 100_0402_5%
2 1
0.22U_0402_10V6K

0.01U_0402_25V7K
2
2 1 2 1
PR95

PC83
PC82 PR94 0_0402_5%

1
3300P_0402_50V7K 4.99K_0402_1% 2 1
+VCCSA_SENSE <10>

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 VCCSAP/1.05S_VCCPP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 56 of 65
5 4 3 2 1
 5 4 3 2 1

PL8 PU8 SY8033BDBC_DFN10_3X3 PL9

4
HCB1608KF-121T30_0603 1UH_PH041H-1R0MS_3.8A_20%
1 2 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
+5VALW

PG
PVIN LX +1.8VSP
9 3

68P_0402_50V8J
PVIN LX

1
680P_0603_50V7K 4.7_1206_5%
1

1
PC84 8

PC85
22U_0805_6.3VAM SVIN PR97

PR96
D D
6 20K_0402_1%

2
5 FB

22U_0805_6.3VAM

22U_0805_6.3VAM
1 2

2
EN

1
PJ13

NC

NC
TP
FB=0.6Volt 2 1

PC87

PC88
+1.8VSP +1.8VS
2 1
<32,45,51,55> SUSP# PR98

PC86
11

2
1 2 EN_1.8VSP @ JUMP_43X118

2
0_0402_5%
+1.5V

0.1U_0402_10V7K
2

PC89 @
1.8VSP_FB PJ14

1
PR99 +0.75VSP 2 1 +0.75VS
2 1

1
1M_0402_5%

1
@ JUMP_43X118

2
PJ15 PR100

1
1
JUMP_43X118 10K_0402_1%
@ PJ16

2
2
2 1
2 1

2
PU9 @ JUMP_43X118
1
VIN NC
8 +3VALW +1.05VS_VCCPP PJ17 +1.05VS
2 1
PC90 2 7 2 1
GND NC

1
4.7U_0805_6.3V6K @ JUMP_43X118

1
3 6 PC91
PR101 VREF VCNTL

2
PR102 1K_0402_1% 4 5 1U_0603_10V6K
@ 0_0402_5% VOUT NC
1 2
<51> 0.75VR_EN# 9

2
TP
C APL5336KAI-TRL_SOP8P8 C

PR103

0.1U_0402_16V4Z
D
+0.75VSP

1
47K_0402_1% PQ23

10U_0603_6.3V6M
<10,37,51,55> SUSP 1 2 2

PC95
2N7002KW _SOT323-3

1K_0402_1%

10U_0603_6.3V6M
1

1
PC93

PC94
G

PR104

2
S
0.1U_0402_10V7K

3
2012/02/29

2
1

change PR103 from 33k to 47k

PC96

PR105
0_0402_5%
SUSP# 1 2
@ 10K_0402_1%

+3VS
2

+1.05VS_VCCPP OCP(min)=22.38A
@.1U_0402_16V7K
1
PR106

PC97

100K_0402_1%
2

PJ18
100K_0402_1%
1

1.05VS_B+ 2 1
PR107

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
2 1
B+

0.1U_0402_25V6
2

@ JUMP_43X118
PR109

1
PR108

PC99

PC102
1

5
0_0402_5%

PC98
PR110 PC103

PC101
1 2 0_0603_5% 0.1U_0603_25V7K PQ24
<51,56> +V1.05S_VCCP_PWRGOOD

2
1
BST_1.05VS_VCCP 2 1 2
1

B B
13
14
17

16

15

PU10 4
10.7K_0402_1%

EN
PAD

BST
PGOOD

MODE
2

AON6428L_DFN8-5
PR111

1 12 LX_1.05VS_VCCP PL10
0.1U_0402_25V6

VREF SW

3
2
1
1UH_PCMB062D-1R0MS_9A_20%
+1.05VS_VCCPP
1

1 2
1
PC100

2 11 DH_1.05VS_VCCP
2

REFIN DH
2

1
PQ25
PR112

1000P_0603_50V7K 4.7_1206_5%
5
PC104
12K_0402_1%

AON6504 1N DFN
TPS51219RTER_QFN16_3X3

PR113
0.01U_0402_25V7K 1
1

330U_D2_2VM_R6M
3 10 DL_1.05VS_VCCP
GSNS DL +

PC105
1

2
4
4 9 2 3
VSNS V5 +5VALW
COMP

1
PGND

PC106
TRIP

GND

3
2
1

2
5

PC107
1
54.9K_0402_1%

PR114
PR115 1

1 2 PC108
<9> VCCIO_SENSE 1 2 1U_0603_10V6K
2
2
PR116 @

0.01U_0402_25V7K
0_0402_5%

A A
10_0402_1%
1000P_0402_50V7K

2
2
PC109

PR117
1

Security Classification LC Future Center Secret Data Title

1 2
Issued Date 2011/11/01 Deciphered Date 2012/12/31 1.8VSP/0.75VSP/1.05VS_VCCPP
2

10_0402_1%
PC110
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
1000P_0402_50V7K AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1

Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 57 of 65
5 4 3 2 1
 8 7 6 5 4 3 2 1

+VGA_CORE Under VGA Core GB4-128 package

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
H H

1
PC801

PC802

PC803

PC804

PC805

PC806

PC807

PC808

PC809

PC810

PC811

PC812

PC813

PC814
2

2
+VGA_B+
+3VS PL801
HCB2012KF-121T50_0805
1 2
B+

2
PL802
PR831 HCB2012KF-121T50_0805
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
10K_0402_5% 1 2

2200P_0402_50V7K
1

1
PC815

PC816

PC817

PC818
@

0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K
PD801

1
<23>
<23>
RB751V-40_SOD323-2

PC831

PC832

PC833

PC834
DPRSLPVR_VGA
NVVDD PWM_VID
2

2
2 1
NVDD_PWR_EN <18>

2
1
PR803
120K_0402_5% PR832
G 1 2 10K_0402_5% G

PC855

2
+VGA_CORE Near VGA Core .1U_0402_16V7K
1 2
S TR FDMS3664S 2N POWER56-8 S TR FDMS3664S 2N POWER56-8

+3VS_VGA PR822 PQ801 PQ802

2
0_0402_5%
2 1 UGATE1_2_VGA 1 1

10K_0402_5%
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

0_0402_5%

0_0402_5%
1
22U_0805_6.3V6M

47U_0805_6.3V6M
1

1
PL803
PC829

PC830

PC819

PC820

PC821

PC822

PC823

PC824

PC825

PC826

PC827

PC828
+VGA_CORE
0.24UH_FDUE0630J-H-R24M-P3_22A_20%

2
7 7 1 2
2

2
2
6 6

1
PR801

PR804

PR802
PC858 PR820

1
@ 10P_0402_50V8J @
2 1 4.7_1206_5% 1 1 1

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
3
4
5

3
4
5
1 1
22U_0805_6.3V6M

22U_0805_6.3V6M

1SNUB1_VGA 2
F PR824 PR823 GPU_VID + + + F
PC868

PC869

PC836

PC837

PC857
20K_0402_1% 20K_0402_1% UGATE1_VGA PR821 PC838

PSI_VGA

EN_VGA
VREF 2 1 2 1VIDBUF 0_0603_5% 0.22U_0603_10V7K
2 2 BOOT1_2_VGA 2 1 1 2 2 2 2

1
@ PC859

1
2700P_0402_50V7-K PR829
2K_0402_1% PC835

2
4
6

1
PR825 PR826 @ 680P_0402_50V7K

2
0_0402_5% 18K_0402_1%

HG1
VID

PSI

BST1
EN
VIDBUF
2

2
2 1 2 1

2 1 PC856 7 24 PHASE1_VGA
REFIN PH1
PR805 = 45.3K ==>Fsw = 450KHz PC854 2200P_0402_50V7K
1 2 PR805 VREF 8 PU801 23 LGATE1_VGA
VREF LG1

1
0.01U_0603_50V7K 36.5K_0402_1% +VGA_B+
2 1 FS 9 NCP81172MNTWG_QFN24_4X4 22 PR811 0_0402_5% PR834 @
PR806 0_0402_5% FS PGND
2.2_0402_5%
1 2 VSS_SEN 10 21 PVCC_VGA 1 2
<24> VSSSENSE_VGA FBRTN PVCC +5VS

2200P_0402_50V7K
2
E E
PC852 PR809 FB_VGA 11 20 PC839 4.7U_0603_10V6K

0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K
1

PC853 47P_0402_50V8J 51_0402_1% PC850 10P_0402_50V8J FB LG2

1
1000P_0402_50V7K 1 2FB1_VGA1 2 1 2 COMP_VGA 12 19 1 2

PC840

PC841

PC842

PC843
TALERT#
COMP PH2

PGOOD
PR808
2

TSNS
10K_0402_1%

BST2
GND

VCC

HG2

2
<24> VCCSENSE_VGA 1 2 VCC_SEN 1 2 1 2FB2_VGA1 2

PR807 0_0402_5% PC851 PR810

25

13

14

15

16

17

18
100P_0402_50V8J 82K_0402_1% S TR FDMS3664S 2N POWER56-8 S TR FDMS3664S 2N POWER56-8

BOOT2_VGA PR818 PQ803 PQ804

2
VCC_VGA
0_0402_5%
UGATE2_VGA 2 1 UGATE2_2_VGA 1 1

PL804
100K_0402_1%_NCP15WF104F03RC

DGPU_PWROK <19,27,55> +VGA_CORE

0.24UH_FDUE0630J-H-R24M-P3_22A_20%
1

PR816 10K_0402_5% 7 7 1 2
5.9K_0402_1%

PC849 2 1 +3VS
6 6
PH801

D .1U_0402_16V7K D
2

1
PR815 2.2_0402_5% @
2 1 +5VS
2

PR819
2

4.7_1206_5% 1 1
1U_0402_10V6K

330U_D2_2V_Y

330U_D2_2V_Y
3
4
5

3
4
5
PR812
2

1SNUB2_VGA 2
Thermistor near MOSFET PR817 PC847 + +
PC848

PC845

PC846
1

0_0603_5% 0.22U_0603_10V7K
trigger point 97 degree C. 2 1 BOOT2_2_VGA 1 2
2 2
VREF

PC844
680P_0402_50V7K
N14P-GT 35W N14P-GS 25W

2
PR813 10K_0402_5% PHASE2_VGA
Ipeak=50A Ipeak=36A 2 1 +3VS

C
Imax=35A Imax=25A C
Iocp=64.8A Iocp=64.8A LGATE2_VGA
Fsw=450KHz Fsw=450KHz
bulk cap 330uF 9m *5 bulk cap 330uF 9m *3 MDU1512, Rdson(max)=5mohm

B B

A A
Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 VGA_COREP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400-LA8691P
Date: Monday, January 14, 2013 Sheet 58 of 65
8 7 6 5 4 3 2 1
 5 4 3 2 1

PR190
PR192

PR186 PC174
10_0402_1% 0.033u_0402_16V7K PC175 GFX@ GFX@

1200P_0402_50V7K
1 2 FBA3 1 2 GFX@ 0_0402_1% 1 2

330P_0402_50V8J
D GFX@ SLI@ GFX@ PUT COLSE 0_0402_1% D

75K_0402_1%
.1U_0402_16V7K SLI@
TO GT

1
PR188 PR189 1 PR190 2
Inductor

PC176

PC177

PR191
TRBSTA# 1 2 FBA1 1 2 GFX@ PH4 GFX@ GFX@

0.033U_0402_16V7K
2P: 24K 24K_0402_1% PR192 PC179

1
1
8.06K_0402_1% 806_0402_1% GFX@ GFX@ 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
1P: 24.9K GFX@

PC178
GFX@ GFX@

2
GFX@ PR193 PC180 PC181 GFX@ 2 PR1941 NTC_PH203 1.65K_0402_1% 1000P_0402_50V7K

2
1 2 FBA2 1 2 1 2 165K_0402_1%

2 PR197 1
SLI@ 0_0402_5%
10_0402_1% GFX@ 2P: 1.65K
GFX@ 560P_0402_50V7K PR196 10P_0402_50V8J PC182 PR198 2P: install
1 PR1952 1 2 COMPA1 1 2 1 2 SWN2A 1P: 1K
GFX@ GFX@ 1P: @
1K_0402_1% 5.11K_0402_1% 2200P_0402_50V7K 91K_0603_1% CSREFA
GFX@ GFX@ 1 2 PC183 TSENSEA

2
0_0402_5% 1 PR2002 SWN1A 0.047U_0402_16V7K

2 GFX@
SLI@ PR199 GFX@
2P: 21.5K 91K_0603_1% GFX@ GFX@ PR201 5.49K_0402_1%

1
CSP1A 1 2
1P: 15.8K SWN1A <60>

2
21.5K_0402_1%
PC185 GFX@

CSCOMPA
1000P_0402_50V7K
<10> VCC_AXG_SENSE

2
15K_0402_1%
1PR203
1PR202 2 2 PR204 1 CSREFA

1
PC184 0_0402_5% 0_0402_5% SLI@ 2P: install PH5

PR206
1000P_0402_50V7K SLI@ CSREFA <60> 1P: @

1
2 PR205 1 PC186 100K_0402_1%_TSM0B104F4251RZ
<10> VSS_AXG_SENSE 0.047U_0402_16V7K
PR207 0_0402_5% SLI@

1
+3VS

CSP2A
CSP1A
GFX@ 1 SLI@ 2 2 PR208 1 SLI@ CSP2A 1 2
+5VS SWN2A <60>

TRBSTA#

DROOPA

CSSUMA
0_0402_5% 0_0402_5% PR209

COMPA

TSENSEA
IMONA
FBA
1 2 GFX@ GFX@ 5.49K_0402_1% GFX@

DIFFA

ILIMA
1

PC187 GFX@ @
PR210 .1U_0402_16V7K
10K_0402_1% PR212 2P: 36K
2 PR211 1 1 2 PUT COLSE
VR_RDYA 0_0402_5% 36K_0402_1% 1P: 26.1K

60

58

52

46
57

49
48
47
61

59

56

51
55
54
53

50
TO V_GT
2

+5VS 1 PR2132 PU14 SLI@

C
2_0603_5% HOT SPOT C

VSNA

DIFFA

DROOPA

TSNSA
CSREFA
FBA

CSP2A
CSP1A
VSPA

CSCOMPA
PAD

COMPA
IOUTA
ILIMA

CSSUMA
TRBSTA#
+1.05VS GFX@ 6132_PWMA <60>
PC188
1 2 6132_VCC
.1U_0402_16V7K

.1U_0402_16V7K

1 45 PR214 PC189
2.2U_0603_10V7K 2 VCC PWMA 44 BSTA1 1 2 BSTA1_12 1
VDDBP BSTA +5VS
130_0402_1%

54.9_0402_1%

PR217 VR_RDYA 3 43 2.2_0603_5% GFX@

VRDYA HGA HG1A <60>
1

PR215 2

1 2VR_ON_CPU 4 42 GFX@ 0.22U_0603_10V7K

<45> VR_ON EN SWA SW1A <60>
PR216

PC190 PC191 0_0402_5% VR_SVID_DAT1 5 41 PC192

SDIO LGA LG1A <60>
VR_SVID_ALRT# 6 40 BST2 1 PR2182 BST2_1 2 1 2Phase: @
2

PR221 PR219 VR_SVID_CLK 7 ALERT# BST2 39 4.7_0603_5%

SCLK HG2 HG2 <60> 1Phase: install

0_0402_5%
PR224 @
0_0402_5% 95.3K_0402_1% 1 2 VBOOT 8 38 0.22U_0603_10V7K Option for
SW2 <60>
1

1 PR220 2 VR_SVID_DAT1 1 2 10K_0402_1% ROSC_CPU 9 VBOOT NCP6132AMNR2G_QFN60_7X7 SW2 37

<9> VR_SVID_DAT ROSC LG2 LG2 <60> 1 phase GFX
CPU_B+ 1 2 VRMP 10 36 6132P_VCCP 1 PR2232 2 1
<9> VR_SVID_ALRT# VRMP PVCC
VR_HOT# 11 35 0_0402_5%
<9> VR_SVID_CLK VRHOT# PGND
0.01U_0402_25V7K

PR222 1K_0402_1% VGATE 12 34 PC193

LG1 <60> +5VS

2
VRDY LG1
1

13 33 2.2U_0603_10V7K CSP2A
+1.05VS VSN SW1 SW1 <60>
PC194 14 32
+3VS VSP HG1 HG1 <60>
DIFF_CPU 15 31 BST1 1 PR2252 BST1_1 2 1

CSCOMP
2

DIFF BST1

TRBST#
4.7_0603_5%

DROOP

CSSUM

DRVEN
CSREF
1

COMP
75_0402_1%

PC195 0.22U_0603_10V7K

TSNS
CSP3
CSP2
CSP1

PWM
IOUT
ILIM
1
PR226

FB
PR227 PC200 +5VS
PC196 @ 10K_0402_5% PR228

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
43P_0402_50V7K 3P: 73.2K
2

1 2 10P_0402_50V8J 1 PR2282
<45> VR_HOT# 2P: 41.2K
2

COMP_CPU

0_0402_5%
CPU2@ FB_CPU 73.2K_0402_1% 41.2K_0402_1% Option for 3Phase: @
TRBST#
<16> VGATE

PR230
CPU2@
PR229 CPU2@ 2 phase CPU 2Phase: install
DROOP
CPU3@

TSENSE
ILIM_CPU
1 2 VSN 3P: 22p
<9> VSSSENSE 6132_PWM <60>
1

0_0402_5% CPU3@
PC197 2P: 10p
DRVEN <60>

2
21K_0402_1% 21K_0402_1%
PR232 1000P_0402_50V7K CSP3 1 PR2312 CSP3
SWN3 <60>
2

1
1 2 VSP PC198 6.98K_0402_1%
<9> VCCSENSE
2
21K_0402_1%

@ PR300
0_0402_5% 1 2 PC199 3P: install
0.047U_0402_16V7K
CPU3@

.1U_0402_16V7K
2P: @

2
B B
CPU3@ PC200 CSP1 PR233 CSREF TSENSE

1
1 PR234 2 2 1 CSP2 PC208
1

1K_0402_1% CSP3 CSP2 1 PR2352

SWN2 <60>

1
PR301 @
22P_0402_50V8J 6.98K_0402_1%
PR233

PC201
PR236 PC202 PR237 PC203 3P: 21K 0.047U_0402_16V7K

2
1 2 FB_CPU1 1 2 2 1 COMP_CPU1 2 1 12.4K_0402_1%
PR238 PC204 49.9_0402_1% 6.04K_0402_1% 2P: 12.4K CPU2@ 1200P_0402_50V7K CSREF

15K_0402_1%
1 2FB_CPU3 1 2 470P_0402_50V7K 2200P_0402_50V7K CPU2@

PR240 1

2
10_0402_1%
CSREF <60>
CSCOMP

21K_0402_1%
0.033u_0402_16V7K CSP1 1 PR2392 PH6
SWN1 <60>

1
PR302 @
PR241 PR242 PC205 6.98K_0402_1%
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 3P: 1500p PC206 100K_0402_1%_TSM0B104F4251RZ
1
0.033u_0402_16V7K

0.047U_0402_16V7K
2P: 1200p

1
1

8.06K_0402_1% 806_0402_1%
PC207 CSREF

1
CSSUM
2

@
CPU3@ PC208 CPU3@
PR244 1 2 1 PR2432 SWN1
23.7K_0402_1%

1500P_0402_50V7K 130K_0603_1% PUT COLSE

2

.1U_0402_16V7K

PC969@QC TO VCORE
PC209

3P: 23.7K 1 PR2452 SWN2

HOT SPOT
PR244

1 2 PC210 130K_0603_1%
2P: 24.9K
1

330P_0402_50V7K
24.9K_0402_1% 1 PR2462 SWN3
1

CPU2@ 130K_0603_1%
CPU3@ PR247 PC212 1 2 PC211
2012/05/07
CPU3@
CSCOMP 1 2 DROOP 1 2 CSREF 330P_0402_50V7K 3P: install change PR240, PR206 from 8.25Kohm to 15Kohm
PUT COLSE 2P: @
PR247 806_0402_1% 1000P_0402_50V7K PR248 PR249
<45> IMVP_IMON TO VCORE 1 2
NTC_PH201 1 2
3P: 806 Phase 1 75K_0402_1%
2P: 1K Inductor 165K_0402_1%
A A
PH7

1K_0402_1% 2 1
CPU2@
220K_0402_5%_ERTJ0EV224J

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 59 of 65
5 4 3 2 1
 5 4 3 2 1

CPU_B+ CPU_B+

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
B+

0.1U_0402_25V6

0.1U_0402_25V6
1000P_0402_50V7K

2200P_0402_25V7K

1000P_0402_50V7K

2200P_0402_25V7K
5

5
PL14
PQ27 HCB4532KF-800T90_1812 PQ28

1
1 2

PC330

PC213

PC214

PC215

PC216

PC440

PC217

PC218

PC219

PC220
CPU_B+
1 1

470P_0603_50V7K

470P_0603_50V7K
68U_25V_M_R0.36

1000P_0603_50V7K

68U_25V_M_R0.36
2

2
4 4
<59> HG1 <59> HG2

1
+ +

PC221

PC223

PC224

PC225
+VCC_CORE +VCC_CORE
AON6428L_DFN8-5 AON6428L_DFN8-5

2
PL15 2 2

PC222
3
2
1

3
2
1
D D
0.36UH_VMPI1004AR-R36M-Z03_30A_20% PL16
<BOM Structure> 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1 4 1 4
<59> SW1 <59> SW2

1
2 3 2 3

5
PR250 PR251
4.7_1206_5% 4.7_1206_5%
PQ29 PQ30

2
AON6504 1N DFN PR252 AON6504 1N DFN
4 V1N_CPU2 1 4 V2N_CPU 2 PR253 1 CSREF
<59> LG1 CSREF <59> <59> LG2

1SNUB_CPU1

SNUB_CPU2
10_0402_1%
10_0402_1%

SWN1 <59> SWN2 <59>

3
2
1

3
2
1
PC226

1
680P_0402_50V7K PC227

2
680P_0402_50V7K

2
CPU_B+
PR254
BST3 1 2 BST3_1

10U_0805_25V6K

10U_0805_25V6K
4.7_0603_5%

0.1U_0402_25V6

2200P_0402_25V7K
5
CPU3@
2

1
PQ31

PC229

PC230

PC231

PC232
PC228
0.22U_0603_10V7K
1

2
CPU3@
4
PU15 CPU3@ CPU3@ CPU3@ CPU3@ +VCC_CORE
1 9
BST FLAG AON6428L_DFN8-5
C C
CPU3@ 2 8 HG3 PL17
<59> 6132_PWM
3
2
1

PWM DRVH CPU3@ CPU3@

2 PR255 1EN_CPU3 3 7 SW3 1 4
QC 45W CPU DC 35W CPU
<59> DRVEN
2K_0402_1% EN SW VID1=0.9V VID1=1.05V

1
+5VS 2 1VCC_CPU3 4 6 2 3 IccMax=94A IccMax=53A
5

PR256 VCC GND 0.36UH_VMPI1004AR-R36M-Z03_30A_20% Icc_Dyn=66A Icc_Dyn=43A

1

0_0402_5% CPU3@ 5 LG3 PR257

DRVL PQ32 4.7_1206_5% Icc_TDC=52A Icc_TDC=36A
PC233 NCP5911MNTBG_DFN8_2X2 CPU3@ R_LL=1.9m ohm R_LL=1.9m ohm
2

2.2U_0603_10V7K CPU3@ AON6504 1N DFN OCP~110A OCP~65A

4 V3N_CPU 2 PR258 1 CSREF
CPU3@
SNUB_CPU3

10_0402_1%
CPU3@
3
2
1

SWN3 <59>
CPU3@
1

PC234
680P_0402_50V7K
3Phase: install
2

CPU3@
2Phase:: @

CPU_B+ CPU_B+

2Phase: install
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
1Phase:: @
0.1U_0402_25V6

0.1U_0402_25V6
2200P_0402_25V7K

2200P_0402_25V7K
B B
1

1
PC235

PC236

PC237

PC238

PC241

PC239

PC242

PC243
2

2
5

5
BSTA2 1 PR259 2 BSTA2_1
PQ33 GFX@ GFX@ GFX@ GFX@ PQ34 GFX@ GFX@ GFX@ GFX@

2
2.2_0603_5%
GFX@ PC240
0.22U_0603_10V7K

1
4 4
<59> HG1A GFX@
GFX@

PU16
AON6428L_DFN8-5 1 9 AON6428L_DFN8-5
+VCC_GFXCORE_AXG BST FLAG
3
2
1

3
2
1
PL18 2 8 HG2A GFX@ PL19
<59> 6132_PWMA PWM DRVH
0.36UH 20% PDME064T-R36MS1R405 24A GFX@ 0.36UH 20% PDME064T-R36MS1R405 24A
1 2 DRVEN 2 PR260 1 EN_GFX2 3 7 SW2A 1 2 +VCC_GFXCORE_AXG
<59> SW1A EN SW
2K_0402_1% GFX@
1

GFX@

+5VS 2 1VCC_GFX2 4 6
@ 4.7_1206_5%
5

5
PR262 VCC GND GFX@
PR261

1
0_0402_5% 5 PQ36

0_0402_5%
PQ35 DRVL

PR264
GFX@

1
NCP5911MNTBG_DFN8_2X2 AON6504 1N DFN PR263 @
2

AON6504 1N DFN PC244 4.7_1206_5% PR266

0_0402_5%

GFX@
4 2.2U_0603_10V7K LG2A 4 2 1 CSREFA
PR265

2
<59> LG1A
10_0402_1%
SNUB_GFX1

SNUB_GFX2
GFX@ GFX@ GFX@
2

2 PR267 1
3
2
1

3
2
1
CSREFA <59>
@ 680P_0402_50V7K

SWN2A <59>
GFX@

10_0402_1%
GFX@

GFX@
1

1
PC246 @
PC245

SWN1A <59>
2

680P_0402_50V7K

2
A A

QC 45W GT2 DC 35W GT2

VID1=1.23V VID1=1.23V
IccMax=46A IccMax=33A
Icc_Dyn=37A Icc_Dyn=20.2A Security Classification LC Future Center Secret Data Title
Icc_TDC=38A Icc_TDC=21.5A
R_LL=3.9m ohm R_LL=3.9m ohm Issued Date 2011/11/01 Deciphered Date 2012/12/31 CPU_CORE
OCP~55A OCP~40A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 60 of 65
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

+CPU_CORE +VCC_GFXCORE_AXG
1 1 1 1 1
5 x 22 µF (0805)
PC247
Socket Bottom 5 x (0805) no-stuff
10U_0805_6.3VAM
PC248
10U_0805_6.3VAM
PC249
10U_0805_6.3VAM
PC250
10U_0805_6.3VAM
PC251
10U_0805_6.3VAM
+VCC_GFXCORE_AXG sites
2 2 2 2 2

D
7 x 22 µF (0805) D
Socket Top 2 x (0805) no-stuff

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 sites

PC258

PC259

PC260

PC261

PC262

PC263

PC264

PC265
1 1 1 1 1 1
PC252 PC253 PC254 PC255 PC256 PC257
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 2 2 2 2 2 2 2 2
2 2 2 2 2 2
GFX@ GFX@ GFX@ GFX@ GFX@ GFX@ GFX@ GFX@
+1.05VS
+VCC_CORE +1.05VS

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1

PC271

PC272

PC273

PC274

PC275

PC276

PC277

PC278

PC279

PC280

PC281
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PC266 PC267 PC268 PC269 PC270 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2

PC282

PC283

PC284

PC285

PC286

PC287

PC288

PC289
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2

2 2 2 2 2 2 2 2

GFX@ GFX@ GFX@ GFX@ GFX@ GFX@ GFX@ GFX@

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1
1 1 1 1 1

PC295

PC296

PC297

PC298

PC299

PC300

PC301

PC302
PC290 PC291 PC292 PC293 PC294
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2
2 2 2 2 2 1 1 1

330U_D2_2VM_R9M

330U_D2_2VM_R9M

330U_D2_2VM_R9M
PC303

PC304

PC305
+ + +

C C
2 3 2 3 2 3

PC59@DC 1 1

330U_D2_2VM_R6M

330U_D2_2VM_R6M
1 1 1 1 1 GFX@ GFX@ GFX@
+ +

PC311

PC312
PC306 PC307 PC308 PC309 PC310
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 3 2 3

PC38,PC39,PC40,PC41

1 1 1 1
PC313 PC314 PC315 PC316
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2
PC32,PC49,PC54,PC55,PC56
+VCC_CORE
PC8,PC21,PC22,PC63
PC38,PC39,PC40,PC41
470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

1 1 1 1 1 1
470U_D2_2VM_R4.5M

+ + + + + +
PC317

PC318

PC319

PC320

PC321

PC322

B 2 3 2 3 2 3 2 3 2 3 2 B

@
CPU3@

DC:PC73,PC74,PC75,PC76,PC77,PC78(330uF/9m)
QC:PC76,PC78(470uF/4.5m),PC73,PC74,PC75(330uF/9m)

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 CPU_CORE1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 61 of 65
5 4 3 2 1
 5 4 3 2 1

Charge Option() bit[8]=1

P3
B+
P2

PQ37 PQ38
AO4423L 1P SO8 AO4423L 1P SO8
8 1 1 8 PR268
VIN 7 2 2 7 0.01_1206_1% PL20 CHG_B+
6 3 3 6 1UH_PCMB061H-1R0MS_7A_20%
5 5 1 4 1 2 PQ39
AO4423L 1P SO8
2 3 1 8

@ 10U_0805_25V6K

@ 10U_0805_25V6K
4

4
D D
SH00000AA00 2 7

2
PC323 3 6

2200P_0402_50V7K
PQ40 2200P_0402_50V7K 5

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1 2

PC324

PC325
200K_0402_5%

1
1

2
200K_0402_1%
0.1U_0603_25V7K

PC327

4
1
PR269

PC331

PC326

PC332
DTA144EUA_SC70-3 DISCHG_G
3

PC328

PR270
1 2

1
PR271
PC329 @ 47K_0402_1%
2

2
2 0.1U_0603_25V7K 1 2

2
ACN VIN

2ACOFF-1

1SS355_SOD323-2
2
1

ACP PR272

1DISCHG_G-1
10K_0402_1%
1

2
PD5
P2-1 PR273

0.1U_0603_25V7K

1
2 200K_0402_1%
PQ41 PQ42

1
PC333 PC334 DTC115EUA_SC70-3

1
DTC115EUA_SC70-3 +3VALW P
PR274 <54> ACPRN 1 2 2 1 PD6
3

5.1K_0402_5% 1SS355_SOD323-2
0.1U_0603_25V7K 2 1 2

100K_0402_1%
6 2
6

@ 10K_0603_1%
1

1
PR276 @
PQ44A PC335

2
PR275

PR277
PQ43A 2N7002KDW -2N_SOT363-6
2 2N7002KDW -2N_SOT363-6 0.1U_0603_25V7K

6
2 PQ45A

0.1U_0603_25V7K
BATT_OUT <53> 2 1
150K_0402_1% 2N7002KDW -2N_SOT363-6
1

1
PC336
VIN PR278 @ PR279 @
1

1
C 2 1 1 2 2 PACIN C
4.7M_0603_1% P2 PQ46
390K_0603_1%

2
1

5
AON7408L_DFN8-5
P2-2

39.2K_0402_1%

1
PR280
2N7002KDW-2N_SOT363-6

1
3

2
5

4
PR282
3
PQ43B

10_1206_5%

ACOK

ACN
CMPOUT

ACP
CMPIN
PR281 PR283 <45,53> ADP_I 1 2
2

47K_0402_1% 64.9K_0603_1% 21 4
PACIN 1 2 5 1 2 6 TP
ACDET PC339
20 1 2
SH000005Y80
PC337 .1U_0603_25V7K PC338
4

2 1 1 2 7 VCC PL21

3
2
1
PR284 IOUT PR285
1U_0603_25V6
1

PQ47 0_0402_5% 100P_0603_50V8 19 4.7UH_KJ0730-4R7M_5.5A_20% 0.01_1206_1%

PHASE
DTC115EUA_SC70-3 <45,49,53> EC_SMB_DA1 1 2 8
SDA
PU17
1 2 1 4
BATT+
PR287 BQ24737RGRR_VQFN20_3P5X3P5 LX_CHG CHG
PR286 0_0402_5% 18 DH_CHG
HIDRV

5
1 2ACOFF-12 <45,49,53> EC_SMB_CK1 1 2 9 2 3
<45> ACOFF SCL

1
10K_0402_5% PR288 PC340 PQ48

4.7_1206_5%
PR290
PR289 2.2_0603_5% 0.047U_0603_16V7K AON7702L_DFN8-5
1

1 2 10 17 BST_CHG 1 2 2 1

10U_0805_25V6K

10U_0805_25V6K
+3VALW P ILIM BTST
1

16251_SN
PR291 147K_0402_1% PD7
3

2012/02/29 RB751V-40_SOD323-2 4

LODRV
0_0402_5%

1
PC341

PC342
PR292 16 2 1

GND
SRN

SRP
Add PC337 0.1uF REGN
BM
100K_0402_1%
2

2N7002KDW-2N_SOT363-6

2
680P_0603_50V7K
BQ24737_VDD
1 12

13

14

15
11

3
2
1
3

1
PQ44B

PC343
10_0603_5%
6.8_0603_5%

2
1
PR294
BM#

PR293
PC344
BATT_OUT 5 1U_0603_25V6

2
B B
2
10K_0402_5%
4

2
2
PR295 @

PC345 DL_CHG
0.1U_0603_25V7K
2 1
1

PC346
0.1U_0603_25V7K
2

+3VS
BQ24737_VDD

PR298
10K_0402_1%
1

1
1 2
ACIN <45>
PR297
PR296 10K_0402_1%
47K_0402_1%
2

2
PACIN
2N7002KDW-2N_SOT363-6

1
3
PQ45B

PR299

ACPRN 5 12K_0402_1%
2
4

A A

For disable pre-charge circuit.

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 62 of 65
5 4 3 2 1
 5 4 3 2 1

D D

PCH_PWR_EN# 2
U14,+3VALW_PCH

V
AC A1
MODE VIN
QH4,+5VALW_PCH

V V
A2 A3 B5

VV
PU2 A5 2

V
PU3

V
B+ +3VALW_PCH
+3VALW B7 2 3
+5VALW_PCH
BATT BATT V
MODE
B1
B2
B+ B4 V
V

V
EC 4 SYS_PWROK
13
PQ2 PCH_RSMRST# PM_DRAM_PWRGD

V
V
V V PCH
B3 A5 B7 5 14
PBTN_OUT# H_CPUPWRGD
CPU

V V
V
51ON# EC_ON
PM_SLP_S3#
PM_SLP_S4# PLT_RST# 15
C PM_SLP_S5# C

PM_SLP_A#
A4 B6 PM_SLP_SUS# 6

V
V
ON/OFF V
SYSON 7 SYSON# +1.5V

V
PU5
DGPU_PWR_EN 8a (DIS) VGA_ON
+3VSDGPU

V
Q6 11
8
SUSP#,SUSP U49

V
+5VS VGATE

V
+1.5VSDGPU
U40

V
U20

V
+3VS +1.8VSDGPU VGA
U37
B B

V
U13

V
V
+1.5VS +1.0VSDGPU
PU28

V
PU8

V
V
+0.75V +VGA_CORE
VCCPPWRGOOD PU998

V
V

PU9 PU7
+1.05VS_VCCP +VCCSA
VGA_PWROK 8b (DIS)

U47
CK505
VR_ON 9 PU1000
V
10
V

+CPU_CORE

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 Power sequence

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 63 of 65
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Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase

1 For NV suggest 58 Add (reserve parts ) PC859

D D

2 For TI suggest 58 Add (reserve parts ) PR834

7
8

C C
9

10

11

12

13

14

B B

15

16

17
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/10/11 Deciphered Date 2014/07/01 PIR (PWR)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
NM-A141 1.0

Date: Monday, January 14, 2013 Sheet 64 of 65

5 4 3 2 1
 5 4 3 2 1

QIWY5 HW PIR List

NO DATE PAGE MODIFICATION LIST PURPOSE
EVT TO DVT
1 P23 Change DGPU_PWR_EN to PLT_RST_VGA# For GC6 function
2 P23 Add CV148 For GC6 function
D 3 D

4
5
6
7
8
9
10
11
12
13
14
14
15
16

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/10/11 Deciphered Date 2014/07/01 PIR (HW)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
NM-A142 1.0

Date: Monday, January 14, 2013 Sheet 65 of 65

5 4 3 2 1