Rambus 112G XSR

and LR SerDes PHYs

 Table of Contents

Introduction..........................................................................02
Part 1: Designing at 112 Gbps..............................................03
Part 2: Rambus 112G XSR SerDes PHY.................................04
Part 3: Rambus 112G LR SerDes PHY...................................06
Conclusion.............................................................................08

01
Rambus 112G XSR and LR SerDes PHYs 01
Introduction
The virtuous cycle of increased computing power
enabling new applications which demand more
computing power continues unabated. Today,
applications spanning AI, autonomous vehicles, video
streaming, AR and VR all demand more bandwidth,
lower latencies and higher speeds.
With global IP traffic now measured in zettabytes (ZB)
per year, two major technology shifts are in full swing. In
the data center, hyperscalers and service providers are
moving from 100GbE to 400GbE and beyond to support
more aggregate bandwidth as well as more bandwidth
density per square foot in their data centers. Meanwhile,
mobile networks are transitioning from 4G LTE to 5G
infrastructure to support more users, higher data rates
and more data streams per base station.
Fig. 1: Data Traffic Continues to Soar
25
20
15
Zettabytes
per Year
10 11.6
9.1
6.8
5
0
2016 2017 2018
Source: Cisco Global Cloud Index, 2017-2021.
Rambus 112G XSR and LR SerDes PHYs
As an example of the relentless growth in data traffic, the
latest Cisco® Global Cloud Index (GCI) forecast predicts
that annual global data center IP traffic will reach 20.6
ZB, or 1.7 ZB per month, by the end of 2021. That’s
a tripling of traffic from the 6.8 ZB per year, or 568
exabytes (EB) per month, of 2016.
In response, the SoCs powering the terabit routers and
switches at the heart of the network must run even
faster. The upgrade to 112G SerDes represents the
latest advancement in high-speed signaling technology
enabling communication within and between network
devices. Upcoming 28.6 terabit network equipment will
require 256 112G SerDes to achieve their
target bandwidth.
25% CAGR
2016-2021
20.6
17.1
14.1
2019 2020 2021
02
Part 1: Designing at 112 Gbps

Designing at 112 Gbps is not for the faint at heart. Issues An embedded micro-processor enables firmware-
of noise, distortion and loss all scale faster than the data controlled PMA configuration, initialization and adaption
rate. But not to worry, Rambus engineers literally wrote for maximum flexibility with minimum SoC
the book on high-speed signal integrity1. Decades of integration effort.
high-speed signaling expertise have gone into the design
of Rambus’ 112G SerDes products. The 112G SerDes are available on a leading-edge 7nm
process node. Rambus supports designers through a
Rambus’ 112G SerDes use both PAM4 and NRZ (PAM2) comprehensive set of chip and system reviews including
signaling providing reliable operation across a broad floor plan, test/characterization plan, package design,
range of data rates. As such, they support legacy board design, final chip integration, and bring-up and
protocols, and provide the scalability to achieve the test plan reviews. In addition, Rambus offers engineering
highest levels of performance. They are built on a services for package design, system board layout, and
configurable architectures that enable power to be statistically-based signal and power integrity analysis.
matched to the channel loss.

1 Kyung Suk (Dan) Oh and Xing Chao (Chuck) Yuan, “High-speed signaling: Jitter modeling, analysis, and budgeting” (Prentice Hall Modern Semiconductor Design Series).

03
Rambus 112G XSR and LR SerDes PHYs
Part 2: Rambus 112G XSR SerDes PHY
The Rambus 112G extremely short reach (XSR)
SerDes PHY is compliant with CEI-112G-XSR for
die-to-die (D2D) and die-to-optical engine (D2OE)
common electrical interfaces. Fig. 2 illustrates
the 112G XSR PHY use in ASIC-to-ASIC (D2D) and
ASIC to co-packaged optics (D2OE) interfaces in a
multi-chip module.
Key features of the Rambus 112G XSR SerDes
PHY include:
• NRZ and PAM4 signaling up to
25 Gbps NRZ to 106 Gbps PAM4
• Ultra-low power per bit for D2OE and D2D modes
• Embedded analog front-end CDR with
> 40 MHz bandwidth for high jitter tolerance
• High bandwidth density of approximately
800 Gbps/mm edge

Fig. 2: The Rambus 112G XSR SerDes PHY Supports

ASIC-to-ASIC (D2D) and ASIC to Co-packaged Optics (D2OE)
XSR with Common Clock
MCM
XSR with +/-100ppm
OE OE

Fiber
D2D D2D D2OE
ASIC ASIC OE

Long Reach
Chiplet
Fiber

ASIC ASIC OE

OE OE

04
Rambus 112G XSR and LR SerDes PHYs
 The Rambus 112G XSR SerDes PHY features an ultra-low
power and area architecture, low-power equalization
and advanced clocking and noise management
techniques. Two major features are advanced self-test
and adaptable link tracking.
Advanced self-test includes onside serial loopback,
internal serializer/de-serializer loopback, analog test
bus and process/voltage monitors. As for adaptable
link tracking, the common clocking architecture allows
matching of the incoming traffic rate to ease clock and
data recovery (CDR) performance and improve
link margin.

Fig. 3: Rambus 112G XSR SerDes PHY Functional Block Diagram

CLK0
From Clock
TX Clock Path
Distribution Digital Processing Layer
CLK90 DPL
φ270

φ180

φ90

φ0
Driver
Slices
Data [63:0]

TX EQ Mux & Tap Delay & CLK32

P25
Output Pre-Drivers Data Gen

NEA

Digital Interface
Loopback Error Pattern
Injection Generation
Sampler Array Aligner
FEA
NES FF Loopback
Loopback VTOP Data [63:0]
FF
S2P Live Eye Pattern
VMID CLK32 Monitor Checker

RX Input VBOT FF BER

VEYE
FF
t
EQ
Data [63:0]
CLK32
φ180

φ270
φ90
φ0

HSCAN CDR
CDR Logic
Vectors
PI0,180 PI90,270
Termination
and ESD
CLK90 CLK0
From Clock Distribution

05
Rambus 112G XSR and LR SerDes PHYs
 Part 3: Rambus 112G LR SerDes PHY
The Rambus 112G long reach (LR) SerDes Key features of the Rambus 112G LR SerDes
PHY is compliant with 100/200/400GBASE- PHY include:
KR, 200/400GAUI-4 C2C/C2M and many other
standards with scalability to upcoming 800GbE • Handles up to eight duplex lanes and data rate of
protocols. Configurable power settings allow it 10.3 to 106 Gbps
to support very short reach (VSR), medium reach
• ADC-DSP architecture supports channels of more
(MR) and LR applications.
than 35 dB insertion loss

Given the demanding channel loss conditions
of these longer reach applications, the LR PHY
incorporates an analog-to-digital converter (ADC)
and proprietary digital signal process (DSP) with
advanced EQ capabilities. Fig. 4 shows the PHY’s
functional block diagram and ADC-DSP-
based architecture.
• Configurable power setting to match output to the
channel loss level
• Embedded microprocessor enabling firmware-
controlled PMA configuration, initialization
and adaption

Fig. 4: Rambus 112G LR SerDes PHY Architecture

PRBS Transceiver Lane

Generator Driver
& FIR TXP

TxData TX Symbol + T-Coil

Serializer
Interface Encoder - & ESD

SysClk TxClk TXN

pllclk Lane
PLL
Clk

CDR
RxClk
Logic CTLE +
PGA RXP
RxData
RX + T-Coil
Interface DFE FFE ADC & ESD
-
RXN
Automatic Gain Control

BER Bias
Monitor Generator BIST

06
Rambus 112G XSR and LR SerDes PHYs
The proprietary ADC-DSP architecture provides a better
signal-to-noise ratio (SNR) compared to traditional feed
forward equalizer (FFE) plus decision feedback equalizer
(DFE) configurations. The Rambus architecture uses
advanced EQ techniques, low-jitter clocking technology,
and high-bandwidth low-latency CDR to achieve
industry-leading performance.
Rambus 112G XSR and LR SerDes PHYs
Like all Rambus solutions, the 112G LR PHY is built from
the ground up with design flexibility and integration
ease in mind. Its flexible layout supports placement
along all edges in an ASIC. Direct register control is
available for all PMA functions. It features built-in
pseudorandom binary sequence (PRBS) generators and
checkers, bit error rate (BER) monitoring, internal serial
and parallel loopback, and in-situ real-time monitoring
to support faster system integration and test.
07
Conclusion
Each new networking speed grade introduces
greater challenges for SoC designers. The
requirements of the next generation of terabit
switches and routers will demand interfaces
running at a blazing 112 Gbps. At 112G, issues of
noise, distortion and loss are all amplified to
an extreme.
Rambus 112G XSR and LR SerDes PHYs
With decades of experience in high-speed signaling,
Rambus has the solutions that designers can count on.
Its 112G XSR and LR SerDes PHYs, available on the latest
7nm process node, offer performance that is second to
none. The 112G PHYs offer a host of advanced features
to meet next generation requirements. And they are
backed by a portfolio of Rambus design services that will
ensure your next 112G SoC design is a first-time
right success.
08
For more information, visit
rambus.com/serdes

Rambus
1050 Enterprise Way, Suite 700
Sunnyvale, CA 94089

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