Problems of SITL: Testing the Simulink model by CompactRIO

I. Vesely*. M. Sir**
D. Zmecnik***

*Faculty of Electrical Engineering and Communication, Brno University of Technology, Center for Research and Utilization
of Renewable Energy Sources, Czech republic (Tel:+42051141148; e-mail: xvesel43@stud.feec.vutbr.cz).
** Faculty of Electrical Engineering and Communication, Brno University of Technology
Czech Republic (Tel +420541141308; e-mail: xsirmi00@stud.feec.vutbr.cz).
*** Faculty of Electrical Engineering and Communication, Brno University of Technology
Czech Republic (Tel:+42051141148; e-mail: xzamec11@stud.feec.vutbr.cz).

Abstract: This article describes the testing of the Matlab model using NI CompactRIO real-time
embedded controllers. If workplace has MATLAB and LabVIEW, the realization of testing becomes
much cheaper than buying the Matlab real-time modules. The paper describes how to install all the
programs and how to connect these programs each other, so we could easily test and debug MATLAB
model using CompactRio and Labview.
Keywords: Matlab Simulink, LabView, CompactRIO, connection, SITL, simulation, DC motor, dll

Interface Toolkit (SIT) (National Instrument, 2008c)

1. INTRODUCTION
Nowadays, Matlab Simulink is used for programming many
simulations. This environment offers significant advantages
but also disadvantages. One of these disadvantages is the
problem associated with SITL (system in the loop). Because
Matlab has the relatively expensive real-time modules, we
need to find another solution. One of them is programming
dsp or other microcontroller. However this possibility is
rather lengthy. Another solution is suitable for workplace,
which have access to Matlab and LabView at the same time
e.g. university. If this program is available, SITL testing
solution becomes much cheaper. Instead of expensive real-
time modules for Matlab can use CompactRIO, which is
sufficient for most simulations. This article describes how
these two programming environments interconnect.
2. COMPACT RIO
“NI CompactRIO real-time embedded controllers offer
powerful stand-alone embedded execution for deterministic
LabVIEW Real-Time applications. These controllers are
designed for extreme ruggedness, reliability, and low power
consumption, with dual 9 to 35 VDC supply inputs that
deliver isolated power to the CompactRIO chassis/modules
and up to a -40 to 70 °C operating temperature range. The NI
cRIO-9022, the highest-powered controller, features a 533
MHz real-time processor and provides the highest level of
performance in the CompactRIO product line. NI cRIO-901x
controllers feature a 400 MHz industrial processor balancing
low-power consumption and powerful real-time floating-
point signal analysis, control, and logging.” (National
Instrument 2011b)( National Instrument 2009c)
3. INSTALATION
Before the connection of Matlab with LabView, all programs
must be installed correctly. Programs that have to be installed
are Matlab Simuling, LabView, LabVIEW Simulation
(National Instrument, 2002), Microsoft Visual studio,
vxworks63gccdist (National Instrument, 2009b), LabVIEW
Real-Time Module. In our case we use Matlab R2010b,
Microsoft Visual studio 2010 and LabVIEW SPRING 2011.
It is necessary to know that we have to convert the model
from Simulink to the dll in Windows XP, because the
vxworks63gccdist does not work under the higher versions of
Windows. Matlab, LabView, LabVIEW Simulation Interface
Toolkit (path: C:\SimulationInterfaceToolkit\) and Microsoft
Visual studio are installed by a standard way to the root
directory C:\. Vxworks63gccdist is only copied to the root
directory C:\. The next step is the interconnection of these
programs and their settings.
In Matlab the compiler is selected and Matlab is connected to
the SIT. Selecting the compiler is done by command mex –
setup
Now the correct settings must be selected from the option of
Matlab:
Would you like mex to locate installed compilers [y]/n?
Choose:y
Select a compiler:
[1] Lcc-win32 C 2.4.1 in C:\PROGRA~1\MATLAB\R2010b\sys\lcc
[2] Microsoft Visual C++ 2010 in C:\Program Files\Microsoft Visual Studio
10.0
[0] None
Choose:2
Please verify your choices:
Compiler: Microsoft Visual C++ 2010
Location: C:\Program Files\Microsoft Visual Studio 10.0
Are these correct [y]/n?
Choose:y
“If you installed the MATLAB application software files as
read-only, the Simulation Interface Toolkit does not
configure the SIT Server to start automatically and the
SignalProbe block does not appear in the Simulink Library
Browser window. To see these changes, add the following
lines to the matlabrc.m file” (National Instrument 2010c).
 (Its the usual way is
C:\ProgramFiles\MATLAB\R2010b\toolbox\local\matlabrc.m
). At the end of the file we write:
cd C:\SimulationInterfaceToolkit
NISIT_AddPaths;
NISITServer('start',6011);
If Vxworks63gccdist is not copied to the root directory C:\.
the path in file setup-gcc.bat (\gccdist\supp\setup-gcc.bat) has
to be changed. In file the command set
GCCPATH=c:\gccdist must be changed to the current path
e.g. set GCCPATH=i:\gccdist.
And the last change is in the directory of Simulation Interface
Toolkit. The file nidll_vxworks.tlc from C:\
SimulationInterfaceToolkit\2010\VxWorks\ModelInterface\tm
w\R2007b\ is copied to C:\ SimulationInterfaceToolkit\
2010\ModelInterface\tmw\R2007b\.
And in file nidll_vxworks.tmf (C:\SimulationInterfaceToolkit\
2010\ ModelInterface\ tmw\ R2007b\) the version is changed
from SIT_VERSION=5.0 to current version in our case
SIT_VERSION= 2010.
4. CREATING DLL AND FILE .OUT
Now everything is set and a Simulink model (Fig.1) of our
application can be created and then converted into a DLL. If
we can see the following text during start, the Matlab is set
correctly (National Instrument 2011a).
SIT: Added paths for Simulation Interface Toolkit Version 2010
Starting the SIT Server on port 6011
SIT Server started
Simulink model must contain SignalProbe block and the
LabView is connected via inport and outport (Fig. 1).
Unconnected inports can be used for monitoring waveforms
in the processor of CompactRIO. The DLL file and other
files, that are generated together, are need for connecting to
LabVIEW environment. This interconnection provides
Simulation interface toolbox. If we don't want to run the
model in real-time mode, we need only DLL file which is
generated by nidll.tlc. Because in our case we need to use
real-time mode, additional files must be created, mainly .out
file which is generated by nidll_vxworks.tlc. These files are
generated in Matlab Simulink. The different versions of
Matlab Simulink may have different paths to the generator. In
Matlab R2010b Simulink path is → −
ℎ → …→
− ℎ , where nidll.tlc is selected as
System target file and then we click on build. For
nidll_vxworks.tlc it is same. Now we have all files that we
need to connect with LabView.
5. THE CONNECTION OF DLLs WITH LABVIEW
The first thing we need to know is what type of connections
of dll and LabVIEW and CoppactRio we will need. We can
choose one of the two ways. In the first way, we do not need
to change the data which are sent or received from
Fig. 1. Matlab model
CompactRIO cards. This means that the Matlab model is in
the form of DLLs, directly connected to the input and output
of cards. In the second way, inputs or outputs data of the
cards are modified or other functions, which Simulink model
does not contain, are added to the program.
2.1 First way
In this case, the model of the DLLs form is directly connected
to the inputs and outputs of CopactRio cards. (National
Instrument, 2010b).
For connection of the Matlab model and the inputs and
outputs, the bitfile must be created first. Bitfile define the
analog, digital, and pulse width modulation (PWM) inputs
and outputs of the FPGA device.( National Instrument
2008a).
To create bitfile we use project that is already created in
LabVIEW examples. The file name is sitfpga cRIO IO.lvproj
and it is located in the directory
\LabVIEW2010\vi.lib\addons\SimulationInterface\_IOTypes\
Plugins\NI-FPGA\FPGA IO Source\
This project is mostly created for other chassis or c series
modules, which we do not use. Therefore, we must revamp
the project. The most important part (sit IO cRIO.vi file) has
to be copied to another folder and then the project has to be
rebuilt into our configuration. (It is a change of Compact Rio
IP address and adding of our chassis and c series modules).
After this adjustment we upload the sit IO cRIO.vi file back
into the FPGA and we rebuild it for our configuration.
During editing a file, it is important not to change the
structure in the gray boxes
In the file, all inputs and outputs do not have to be used but
only those that are needed. The modified file is compiled to
create bitfile. This bitfile, that is created in the directory
project / FPGA Bitfiles, is copied to a directory with other
bitfiles (\LabVIEW 2010\vi.lib\addons\Simulation
Interface\_IOTypes\Plugins\NI-FPGA\FPGA Bitfiles\). Since
the file has not standard name it must be renamed to SIT
connection manager could found it. In our case its name is
sitfpga cRIO-9074 IO.lvbitx.
The connecting manager
Now we can make connections. In the blank vi we create
control and indicators by which we want control Matlab
model and display a variety of waveforms. Connection is
done using the SIT Connection Manager that we can find in
the tools. In this manager we select the real-time target. At
the beginning, we set IP addresses and the type of compact
Rio (Fig.2). Next we enter the path of model dll and path to
the directory of project in the Model and Host category.
Fig. 2. SIT Connection Manager
In the category Mappings we connect the controls from
LabVIEW with variables, which we want to control in the
model, and connect the indicators with variables, which we
want to monitor. The connection of model with the inputs
and outputs of cards is done in the Hardware I / O category.
Here we select Configure HW I/O. Then we click the right
mouse button on IP address and select Add Device- NI-FPGA
and now we can see bitfile that we have created. If there is
bitfile not displayed, it may mean that we renamed it poorly
or we save it to another directory. After confirming (press
OK), we can connect the inputs and the outputs of cards with
the inport and the outport of Matlab model (Fig. 3). This
setting could be found in the video (National Instrument,
2008b)
After everything is connected and set up, SIT connect
manager creates a project ProjectName_Driver.lvproj, which
is used for communication between the model in a format
DLLs and LabVIEW. At the same time in the original file .vi
SIT creates a model for the simulation controlling of
LabVIEW mode.
2.2 Second way
As it has been said before in the second way, we change the
Fig. 3. Configure HW I/O Mappings
Fig. 4. FPGA
input signals or output signals from the cards, or we add more
functions to the program. These additional functions can be
programmed into the RT microprocessor or directly into the
FPGA of CompactRio. These changes may be different
conversion of signal from cards, evaluation of encoder
signals, and additional functions. These changes are very
time consuming and they could be programmed directly into
the FPGA e.g. PWM.
During the connecting of model with LabVIEW we proceed
as well as in the first case. We use SIT connection manager
again, where we set the IP address, path to the directory with
the DLL and the project directory and we connect each
control and indicator block with Matlab model in the
Mappings category. But unlike the first method, we do not
create bitfile, if we want to use FPGA. Connection is done in
a project which was created by Sit connect manager. Created
project contains only the RT CompactRIO Target, where
there are files vi working with dll of Matlab model. So that
we can work with signals from the card, we can add FPGA
by classical way (National Instrument, 2009b). In our case we
use the FPGA to generate PWM and evaluation of the
encoder signals (Fig 4).
Data from the cards are first processed in the FPGA and then
send to the Real Time Processor where they are connected to
the inputs of the Matlab model. For this connection we use an
already created file ProjectName_Base Rate Loop.vi, which
is saved in the directory subVIs of CompastRio RT Target.
This file contains several parts which we can change. They
are flat sequence (Fig.5)- Init Code, where initialization is
performed before running the model, Read Code, where the
data entering into the model, Write code, where data alighting
from the Matlab model and Close Code, where final
instruction are written. The file also contains blocks for
reading and writing to I / O when using bitfile. But this was
not used in our project.
Working with Data
The input and output data of the model are in the form of 1-D
array. We have to know the order of data in the array, so that
we could use these data. This order we find in the
ProjectName _portsReadme.txt file that was generated
simultaneously with the ProjectName.out file and is saved in
the ProjectName_nidll_vxworks_rtw directory. In file we can
see each input and output position in the array, name that

Fig. 5. Base Rate Loop
matches the name in the model, width, and what is the
variable type.
<portlist>
<inport> id="0" name = "In1" width = "1" datatype =
"real_T"</inport><inport> id="1" name = "In2proud" width = "1"
datatype = "real_T"</inport><inport> id="2" name = "In3otacky" width
= "1" datatype = "real_T"</inport><outport> id = "0" name =
"Out1compare" width = "1" datatype = "real_T"</outport>
<outport> id = "1" name = "Out2sinin" width = "1" datatype =
"real_T"</outport>
<outport> id = "2" name = "Out3sin" width = "1" datatype =
"real_T"</outport>
<outport> id = "3" name = "Out4dir" width = "1" datatype =
"real_T"</outport>
<outport> id = "4" name = "Out5napeti" width = "1" datatype =
"real_T"</outport>
</portlist>
We have to save data or vice we have to obtain data using the
blocks for work with array because the data that we use are
not in the form of array. Array index is used for reading data
from the model and Build Array is used for inserting data
into the model.
Now we can read data from the cards by FPGA and can
directly modify, either in FPGA or in real time processor. To
ensure the simulation will work properly, modified data must
be inserted into Build Array in the correct order. In a similar
way we can get data from the model using the Index Array
(Fig. 6).
6. RESULTS
The project aimed to control the dc motor from MATLAB. In
the Simulink model the control of this motor was designed
(Fig.1). These are two PI controllers in the current and speed
loop. Only two signals are inputs of the Matlab model. They
are real current and real speed the output of model is the
value of voltage, which to be connected to the motor. This
model was converted into DLLs and connected to LabVIEW
and CompactRIO. All other operations, which we need for
motor control, are performed in the real-time processor and
Fig. 6. Base Rate Loop with other function
Matlab Simulink
DLL PC
motor
LabView
encoder
CompactRIO
Fig. 7. Block scheme of project
FPGA. PWM, the evaluation of encoder signals and their
conversion to speed and current readout are programmed into
the FPGA In real-time processor these signals are further
converted and sent to the model (Fig. 7). Because the current
sensor does not give the true value, it has to be converted to
the correct value. Also, the speed is calculated, we must
consider computed edges, etc. Conversely, the value of
voltage is taken from the model. This value is converted into
duty and sent to the FPGA (Fig. 6). CompactRIO
communicates with a dc motor through three C series
modules. The first C Series module is the NI 9401, PWM
values are fed to this card and then are sent to the board
Pololu High-Power Motor Driver 24v23 CS, which controls
the motor. The second C series module is the NI 9215, which
reads the current value and the third module is again the NI
9401, which reads values from the encoder. The main tuning
of simulation is performed on the main page of LabVIEW
project. Matlab model is connected with the controller in the
LabVIEW project, now we can set the various constants of
the PI controllers, switch the direction of motor rotation and
enter the desired speed (Fig. 8).
7. CONCLUSIONS
As suggested in the introduction, this solution is suitable for
such workplaces, which owns both MATLAB and
LabVIEW. These are mainly schools and other educational
institutions. As the CompactRIO consists of a microprocessor
Fig. 8. Front page of LabView project
, chassis and c series module, it is more compact. For various
applications, we can buy only those cards which we need.
Another big advantage is the presence of an FPGA, which we
use in many applications. In our case it was the generating of
PWM and the work with the signals of encoder. The
connection of these two environments does not restrict the
simulation. And for easy connection of the LabView control
with Matlab model we can easily debug the application at
runtime.
8. ACKNOWLEDGEMENTS
The research has been supported by Czech Science
Foundation under the project 102/09/H081 “SYNERGY -
Mobile Sensoric Systems and Network“, “Research of
Modern Methods and Approaches in Automation“ from the
Internal Grant Agency of Brno University of Technology
(grant No. FEKT-S-11-6) and European Regional
Development Fund under project No.
CZ.1.05/2.1.00/01.0014.
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