Curriculum Vitae

Dr. Sudhakara Reddy Penubolu

Mail : psr_vlsi_dsp@rediffmail.com
penubolusudhakarareddy@gmail.com
Mobile No.:+91-7569141402

Professor in Electronics & Communication Engineering

Targeting assignments in Research & Teaching
Industry Preference: Education
Location Preference: Hyderabad/ Secunderabad, Telangana.

Objective:- Seeking responsibilities as Research-intensive, applying Science and

Engineering methodologies, critical thinking and problem solving based targets in both
Instructional & Research areas in the field of Electronics and Communication.

Profile Summary:- A result-oriented professional with nearly 20 years of instructional

(Teaching) & Research experience in the field of Electronics and Communication entailing:
a). Research in VLSI Architectures Design for Digital Signal Processing and Digital
Communications.
b). Key role in establishing Electronics Circuits Laboratory, Electronic Computer Aided
Design & Digital Signal Processing Laboratory. Developed Advanced Microprocessor
and Embedded Systems Laboratory, and ECE R&D Cell.
c). Exposure in the area of Verilog/ VHDL, ModelSim, Xilinx ISE design suite,
MATLAB and TI-DSP CCS.
d). Expertise in teaching and conducting research activities. Gained experience of
teaching and providing guidance to the students by using interactive discussions, problem
solving and analytical subjects.
e). Preparing course materials according to syllabi, homework assignments, handouts and
conducting slip tests unit wise. Responding to the queries in a spontaneous manner;
counseling students and grooming them to attain their goal.
f). Teaching subjects titled Electronic Devices and Circuits, Signals and Systems,
Probability Theory and Stochastic Processes, Digital IC Applications, Digital Signal
Processing, Digital Communications, VLSI based System design, Digital design through
Verilog, RADAR Systems, and Wireless Communications for under graduate students;
Low Power VLSI System design, Detection and Estimation of Signals and Advanced
Wireless Communications for post graduate students. Digital Arithmetic, VLSI
architectures for Signal Processing for Research scholars.
g). Assessing students’ work; maintaining records and writing reports on students; keeping
up-to-date with curriculum changes and assessment methods.
h). Contributed in introducing focused, practice oriented, way of learning towards
progress and development.
Educational Qualifications:-

Ph. D / Doctorate in Engineering (VLSI Architectures in DSP) from Sri

Venkateswara University, Tirupati, Andhra Pradesh, India in 2010.
M. Tech. (Digital Systems & Computer Electronics) from Jawaharlal Nehru
Technological University, Hyderabad, Andhra Pradesh, India in 1999.
B. Tech. (Electronics & Communication Engineering), from N.B.K.R Institute of
Science and Technology, Sri Venkateswara University, Tirupati, Andhra Pradesh,
India, in 1993.

Working Experience: Working as Associate Professor in the department of ECE since

29.05.2006 in Srikalahastheeswara Institute of Technology (SKIT), Srikalahasthi-517640,
Andhra Pradesh, INDIA. Earlier I worked as Assistant Professor in ECE from 29.10.1999 to
28.05.2006. 20 years of teaching experience which includs 7 years of Research experience.

Research Supervising on VLSI Architectures for Digital Signal Processing and Digital
Communications area at SKIT from Oct’10 – Till to date. Steering academic projects for B. Tech,
M. Tech and Research Level.

S. No Name of Research Scholar Area/Topic Registration Details Status of Work

1 SOUBACHE. I Combined Economic Emission 101112529, Dept. of EEE, Awarded
Part-Time Scholar at PRIST University, Dispatch through different PRIST University, Thanjavur, 23.01.2016
Thanjavur, Tamilnadu evolutionary techniques Tamilnadu. 2010
2 NAGARAJU.S Energy efficient variable rate 13PH0432, Dept. of ECE, Submitted Report
Regular Scholar at SKIT R&D, JNTUA, NIDS pattern matching System SKIT R&D, JNTUA, for Pre-Ph.D
Srikalahasti. design. Srikalahasti.2013 Seminar
3 ANITHA.P De-blocking filter for high 14PH0429, Dept. of ECE, Going to Submit
Regular Scholar at SKIT R&D, JNTUA, efficiency video coding using SKIT R&D, JNTUA, Report for Pre-Ph.D
Srikalahasti. In-looping Algorithm. Srikalahasti.2014 Seminar Shortly
4 SURENDRA.V Part-Time Scholar at Radar cross section 14PH0412, Dept. of ECE, Work in Progress
SKIT R&D, JNTUA, Srikalahasti. fluctuations of the Space SKIT R&D, JNTUA,
Vehicles. Srikalahasti.2014
5 VAMSI KRISHNA.S VLSI Architectures in DSP 15PH0427, Dept. of ECE, Work in Progress
Part-Time Scholar at SKIT R&D, SKIT R&D, JNTUA,
JNTUA, Srikalahasti. Srikalahasti. 2015

I Published 26 International Journals and 8 International Conferences, 1 National Journal, 6

National conferences and 1 book chapter.

Professional Affiliations:-
Membership
Life Member NO:302
Life Member NO:LM 28808
Life Member NO:M166206
Member NO:1702
Member NO:41463794
Sr. Member NO:80338705
Name of Body/ Society
Semiconductor Society of India (SSI)
Indian Society for Technical Education (ISTE)
Institute of Electronics and Telecommunication Engineering (IETE)
VLSI Society of India (VSI)
Institute of Electrical and Electronics Engineering (IEEE)
IEEE Signal Processing Society (IEEE SP)
IEEE Communication Society (IEEE COMM)
International Association of Computer Science and Information
Technology (IACSIT)
Administrative Work Experience:-
Solano Position From To

1 Principal (FAC) Apr. 2016 Jun 2018

And Chief Superintendent of Examination Cell - SKIT Oct 2018 Jul 2019
2 Head, Department of Electronics & Communication Jul. 2004 Jul. 2006
Engineering, SKIT Jan. 2008 Dec. 2008
Mar 2016 Apr 2016
Jun 2018 Oct 2018
Jun 2018 Oct 2018
3 Time Table Coordinator, SKIT Mar. 2004 Feb. 2005
4 Convener, Anti-Ragging Committee, SKIT Sept. 2005 Aug. 2006
5 Convener, Right Information Act Cell, SKIT Dec. 2006 Feb. 2008
6 Coordinator , IETE,ISTE,IEEE-SKIT Jun. 2006 Mar.2011
7 Officer-In-Charge, Examination Cell, SKIT May. 2007 Jan. 2008
8 Member, Interview/Recruitment Committee, SKIT May, 2011 July 2011
9 P.G. Coordinator in SKIT Oct.2011 July 2014
10 Warden-SKIT (Boys & Girls) Hostels Oct.2011 Jun.2012
11 Convener, AICTE & JNTU Affairs of SKIT Nov,2012 Mar 2016
12 Convener, AFRC of SKIT Mar, 2013 Mar 2016
13 Convener, R&D Cell – SKIT Jul, 2013 Mar 2016
14 Member of Student Disciplinary Committee of SKIT July. 2013 Mar 2016
15 Member Grievance Redressal Committee of SKIT Mar 2016

Personal Details:-
Date of Birth: 01st July 1971
Languages Known: English and Telugu
Address: H. No:16-649 [2], Satya Sai Street, Sri Ram Nagar Colony, Srikalahasti, Chittoor
Dist., Andhra Pradesh, India.
Nationality: Indian
Marital Status: Married
No. of Dependents: 3
Passport No.: J3444219, 07/02/2021
Yours Faithfully
Dr. P. Sudhakara Reddy
SKIT, Srikalahasti.
 Publications
International Book Chapters
1. Sudhakara Reddy. P and Ramachandra Reddy. G, "VLSI Implementation of Least Square Channel Estimation
and QPSK Modulation Technique for 2X2 MIMO System", Book Chapter -MIMO Systems, Theory and
Applications, INTECH, Apr.2011.
International Journals
1. Sudhakara Reddy. P and Ramachandra Reddy. G, "Design and Implementation of Autocorrelator and CORDIC
Algorithm for OFDM based WLAN", EJSR, ISSN: 1450-216X, Vol.25, Issue No.2, pp 200-213, Jan 2009.
2. Sudhakara Reddy. P and Ramachandra Reddy. G, "Design and Implementation of Channel Estimation Method
and Modulation Technique for MIMO System", EJSR, Vol.25, Issue No.2, pp 257-265, Jan 2009.
3. Sudhakara Reddy. P and Ramachandra Reddy. G, "ASIC Implementation of Autocorrelation and CORDIC
Algorithm for OFDM based WLAN", EJSR, Vol.27, Issue No.4, pp 588-596, 2009.
4. Ranga Teja. R, Sudhakara Reddy. P, “Sine/Cosine Generator Using Pipelined CORDIC Processor”, IACSIT
International Journal of Engineering and Technology (IJET), Vol.3, No.4, August 2011.
5. Srinivasa Sarma and Sudhakara Reddy. P, “A Smart home security system based on ARM9”, IJARCET, Vol.1,
Issue 5, pp 29-302, ISSN: 2278-1323, Jul.2012.
6. Sri Devi. M, Sudhakara Reddy.P, “ Design and Implementation of HDLC Protocol on FPGA”, International
Journal of Engineering research and Applications (IJERA), ISSN: 2248-9622, Vol No.2,Issue No. 5,pp 2217-2219,
Sept-Oct, 2012.
7. B. Deepa, Sudhakara Reddy.P, “Performance comparison of Multi-user MIMO downlink data transmission
techniques for next generation wireless applications”, Journal of Communications and Networking, 5 thjuly, 2013.
8. B. Deepa, Sudhakara Reddy.P, “Comparison of Bit error rate and Signal to Noise ratio for Multi-user MIMO
wireless applications”, International Journal of Innovative technology and exploring engineering (IJITEE), ISSN:
2278-3075, Vol.3, Issue 3,Aug. 2013.
9. Narendra, Sudhakara Reddy.P, “ PAPR reduction technique in OFDM system for 4G wireless applications
using partial transmit sequence method”, Quest International Journal of electronics and Communication Engineering
Research (JECER) Vol.1, Issue 1, pp.38-42, ISSN 2321-3795, Sept. 2013.
10. Sreekanth Peram, Sudhakara Reddy.P, “Simulation of OFDM for Software Defined Radio Applications”,
Journal of Communications and Networking.2013.
11. I.D.Soubache, Sudhakara Reddy.P, “Solution to combined heat and power economic dispatch problem by
biogeography based optimization”, Journal of Science in Electrical Engineering, JSEE, ISSN:2277-3282, Vol.3,
Issue 2, page 85-88, 2013.
12. I.D.Soubache, Sudhakara Reddy.P, “ Economic dispatch problem using shuffled frog leaping algorithm”,
IJISME, ISSN:2319-6386, Vol X, Issue X, 2013.
13. Padma.V , Sudhakara Reddy.P “CORDIC based DFT on FPGA for DSP Applications” International Journal of
Engineering Research and Technology, IJERT, ISSN: 2278-0181,vol. 3, Issue,07, July-2014, pp.1575-1579.
14. Shaik Waseem Ahmed , Sudhakara Reddy.P, “FPGA Implementation of CORDIC based DHT for Biomedical
Image Compression Applications”, ISSN 2319-8753, Vol.3, Issue 8, August 2014.
15. Monikaswini, Sudhakara Reddy.P “FPGA Implementation of CORDIC based DCT for RADAR
Applications”, IJARECE,ISSN 2278-909X, Vol.3, Issue 8, August 2014.
16. I.D.Soubache, Sudhakara Reddy.P, “ Solution for Combined economic and emission dispatch”, American
journal of Engineering Science and Research, AJESR, Vol 1, Issue 1, page 1-5, 2014.
17. Rajasekhar, Sudhakara Reddy.P, “Modelling and Design solutions for NANO-CMOS using Predictive
Technology’, International journal of Engineering and Technical research, ISSN:2321-0869, vol.3, issue-6, june .
18. C. Triveni, Sudhakara Reddy. P, “Implementation of Phase Shifter using CORDIC on FPGA for RADAR
Applications, International Journal of Advanced Research in Electronics and Communication Engineering,
IJARECE, ISSN:2278-909X, Vol. 5, Issue 6, June 2016.
19. P.Anitha, Sudhakara Reddy. P, Giri Prasad M.N, “An Approach to Parallel Transformation Technique for
High Efficiency Video Coding”, ICMEET 2017.
20. S.Nagaraju, Sudhakara Reddy.P, “ASIC implementation of High Throughput Low Power DNA Protein
Sequence Computation using FSM”, International journal of Applied Engineering Research, ISSN: 0973-4562, vol.
12 no.16, pp:5844-5848, 2017.
21. S.Nagaraju, Sudhakara Reddy.P, “performance comparision of FSM based Bit transitions for NIDS Systems
and DNA sequence alignments”, Journal of Research in Dynamical and control system, vol.9 sp-12, 2017.
22. S.Nagaraju, Sudhakara Reddy.P, “Low power DNA protein sequence alignment using FSM state transition
controller”, Int. Journal of Bio-Medical engineering and Technology, 2017 (Accepted)
23. S. Nagaraju, Sudhakara Reddy.P, “Page enabled FSM model for Multi rate- High Throughput Regex Pattern
Matching System”,IJET, 7(4.19) (2018) 329-333.
24. Perla Anitha, P. Sudhakara Reddy, M.N. Giri Prasad, “A Review on Video coding standards”, IJETAE, Vol.8,
Issue.1,Jan 2018.
25. S.Nagaraju, Sudhakara Reddy.P, “High throughput Token driven FSM based Regex Pattern Matching for
Network Intrusion Detection System”, Springer ASIC series (Accepted), 2019.
26. Perla Anitha, P. Sudhakara Reddy, M.N. Giri Prasad, “ Content Split Block Search Algorithm based HEVC”,
JSIR, ISSN:0975-1084; 0022-4456.2019 (Accepted).
International Conferences
1. Sudhakara Reddy. P and Ramachandra Reddy. G, "Performance comparison of Autocorrelation and CORDIC
Algorithm implemented on FPGA for OFDM based WLAN", IEEE ICCSN 2009, pp 575-582, 20-22 Feb. 2009,
China.
2. Sudhakara Reddy. P and Ramachandra Reddy. G, "VLSI implementation of Autocorrelation and CORDIC
Algorithm for OFDM based WLAN", IEEE ICCSN 2010, pp 525-531, 26-28 Feb. 2010, Singapore.
3. Sudhakara Reddy. P and Ramachandra Reddy. G, "VLSI implementation of Synchronizer and pipelined
CORDIC Algorithm for fourth generation OFDM based WLAN Applications", ISBN: 978-1-61284-485-5, IEEE
ICCSN 2011.pp 837-840, 27-29th May.2011, China.
4. S.Nagaraju, Sudhakara Reddy.P, “Low Power Pattern Matching Scheme through FSM State Transition for next
generation NIDS System, No. 978-1-5090-3239-6/17, Int. conference of IEEE 2017.
5. Perla Anitha, P. Sudhakara Reddy, M.N. Giri Prasad, “ A formulation approach to Hybrid wavelet transform for
HEVC “, ISBN: 978-1-386-3030-3, ICICCT,2017.
6. Perla Anitha, P. Sudhakara Reddy, M.N. Giri Prasad, “An approach to a parallel transformation technique for
HEVC”, ISBN:978-981-10-7328-1, ICMEET, 2017
7. S.Nagaraju, Sudhakara Reddy. P, “High throughput low-power variable rate network intrusion detection system
using unique SRAM controller”, Proceedings of 2 nd international conference on micro-electronics, electromagnetic
and telecommunications, DOI:10.1007/978-981-10-4280-5, 2018.
8. Perla Anitha, P. Sudhakara Reddy, M.N. Giri Prasad, “ High Efficiency Vedio Coding De-blocking filter:
Through content split block search algorithm”, ISSN: 2194-5357, 2018.
National Journals
1. Sudhakara Reddy. P and Ramachandra Reddy. G, "Low Power VLSI Architectures for DSP: A Multirate
approach", JISR, Vol. No.2, Issue No.2, pp 107 - 118, 2008.
National Conferences
1. Sudhakara Reddy. P and Ramachandra Reddy. G, "CORDIC Algorithms & Architectures: A Study", All India
Sem./Conf. on ETM & I, Vol. 24, page No.7, 29-30 Jun. 2007, S.V.University, Tirupathi, India.
2. Sudhakara Reddy. P and Ramachandra Reddy. G, "Elementary function evaluation: A Study", National Conf.
on NETCOM 2007, 19 Apr. 2007, RMD Engineering College, Thamilnadu, INDIA.
3. Sudhakara Reddy. P, “Network based distance education for developing a learning society: e_learning”, IETE
National Conference on e_Governance, 11-13 Jun. 2004, IETE Centre, Osmania Campus, Hyderabad.
4. Subba Reddy G.V and Sudhakara Reddy. P, “Emerging trends in material research - An Overview”, National
Conf., 20-21 Aug.2004, S.V.University, Tirupathi.
5. Gowri Manohar. T and Sudhakara Reddy. P, “Speed control of induction motor using closed loop constant V/F
control: A Simulation method”, National Conf., 20-21 Aug.2004, S.V.University, Tirupathi.
6. Sudhakara Reddy. P, “Policy Management made easy: E-Governance”, National Conf. on Role of Engineers in
e_Governance, Dec. 2003, Sri Venkateswara University, Tirupati.