2018 3rd International Conference on Integrated Circuits and Microsystems
A 1.25Gbps Programmable FPGA I/O Buffer with Multi-standard Support
Taotao Qian, Lei Chen, Xuewu Li, Huabo Sun, Jie Ni
Dept. FPGA
Beijing Microelectronic Technology Institute, BMTI
Beijing, China
e-mail: 3120102128@zju.edu.cn
Abstract—In this paper, a field programmable gate array
(FPGA) I/O buffer developed to support 1.25 gigabits-per-
second differential source-synchronous standards is presented.
The I/O buffer provides the compatibility of 38 high-speed I/O
standards, features wide supply voltage range, programmable
drive strength and controlled impedance driver. To enhance
the performance and drive capacity of low voltage standards,
an auxiliary supply is introduced into the I/O buffer. The
proposed I/O buffer has been fabricated and integrated in an
SRAM-based FPGA with commercial 65nm CMOS technology.
Keywords-I/O buffer; FPGA; I/O standards; programmable;
mixed-voltage I/O; high-speed; 3.3V tolerance; LVDS
I. INTRODUCTION
The past five years have witnessed the commercial
development and continuous update of the fourth generation
(4G) mobile communication technology. With the LTE
Advanced Pro Release 13 being the latest 4G release, the
development of fifth generation (5G) has been initiated [1].
To adapt the rapid evolution of the communication
technology, the requirement of configurable hardware is
more and more urgent in communication system. On account
of the increasing non-recurrent engineering (NRE) cost and
design cycle of application specific integrated circuit (ASIC)
in nano-scale CMOS technology, field programmable gate
array (FPGA) has gradually taken place of ASIC. FPGA
possesses configurability, could satisfy the constantly
updated requirement of communication technology. The
programmable feature of FPGA help designer reduce NRE
cost, minimize development cycle and risks, which makes
FPGA widely used in communication system.
Meanwhile, as FPGA move to process the complex
signal in communication system, how to design the
compatible and high-speed FPGA I/O buffer rapidly emerges
as a tough challenge. In order to meet the demands of various
system, the FPGA devices are required to support a wide
range of high-speed I/O standards. Such a requirement leads
to a large size and power consumption of FPGA I/O buffer.
Besides, the complex I/O buffer circuits will make it harder
to meet the performance specification. In addition, to support
the 3.3V I/O standards, reduce the static power consumption
and optimize the speed, thick gate-oxide devices are required,
creating the challenge of maintaining high performance at
low voltage VCCO with thick gate-oxide devices.
To address these challenges of FPGA I/O buffer design, a
978-1-5386-8311-8/18/$31.00 ©2018 IEEE 362
novel I/O buffer is proposed and verified in 65nm CMOS
process in this paper. The architecture and working principle
of design is described in Section II. The design of circuits is
presented in Section III. In Section IV, the layout and
measurement results including eye diagrams are given. A
brief conclusion is given in Section V.
II. ARCHITECTURE OF I/O BUFFER
While FPGA plays an increasing part in several types of
system, from digital to radio frequency (RF) system, FPGA
devices are required to have programmable and flexible I/O
interfaces. In this paper, upto 38 I/O standards are supported
by the proposed I/O buffer, including 3.3V Low Voltage
Transistor-Transistor Logic (LVTTL), 3.3V Low Voltage
Complementary Metal Oxide Semiconductor (LVCMOS),
3.3V Peripheral Component Interconnect (PCI), 2.5V Stub-
Series Terminated Logic (SSTL), 2.5V Low Voltage
Differential Signaling (LVDS), 1.5V High-Speed
Transceiver Logic (HSTL) and 1.2V Gunning Transceiver
Logic (GTL). Table 1 lists all of the I/O standards supported
by the proposed I/O buffer.
If such plenty I/O standards are supported by adding
corresponding transceivers in the I/O buffer, the total size
and power consumption of I/O buffer will be very large.
Consequently, it is necessary to share the transceivers among
different I/O standards which have similar electrical feature
and termination type. For this work, the supported standards
are divided into four categories: single-ended standards,
voltage-referenced standards, pseudo-differential standards
and differential-ended standards. All of single-ended I/O use
the single-ended transceiver. The voltage-referenced I/O
inputs signal with a universal voltage-referenced receiver
and outputs signal with a universal single-ended transmitter.
Both of pseudo-differential and differential-ended I/O use a
universal differential-ended receiver. The different between
these two types of standards is the transmitting end. The
pseudo-differential I/O uses a single-ended transmitter while
differential-ended I/O needs a differential-ended transmitter.
Thus, the single-ended output buffer can be shared by the
single-ended I/O, voltage-referenced I/O and pseudo-
differential I/O. The differential-ended output buffer is used
by differential-ended I/O standards, such as LVDS. As for
receiving end, three types of input buffer are required, a
universal single-ended input buffer for single-ended I/O, a
voltage-referenced input buffer for voltage-referenced I/O, a
differential-ended input buffer for both pseudo-differential
and differential-ended I/O. Based on these sharing principle, 6LQJOH
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Figure 1. Block diagram of the proposed FPGA I/O buffer architecture.
LVCMOS18 1.8V

LVCMOS15
LVCMOS12
SSTL2 Class I and II
SSTL18 Class I and II
HSTL18 Class I,II,III and IV
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LVDS
Differential-ended LVDSEXT
I/O RSDS
HT
III. CIRCUIT DESIGN
A. Mixed-Voltage I/O Buffer
Aforementioned, one of the major challenge of this work
is supporting a wide range of I/O voltage with the universal
buffer. In order to tolerate 3.3V I/O VCCO, thick gate-oxide
devices with high threshold voltage are required. With 3.3V
devices, maintaining the performance at low voltage such as
1.2V is a tough design task. To address this challenge, some
techniques are utilized in the universal single-ended output
buffer.
1.5V When a low voltage signal at 1.0V from FPGA core
drives the output buffer to transmit a signal of high voltage
1.2V
standards through the single-ended output buffer, the voltage
2.5V in I/O pad cannot be pulled down to ground. Because the
grid-voltage of the 3.3V NMOS output transistors is too
1.8V
small for the NMOS to deliver enough drive current when
1.8V driven by a 1.0V signal. Meanwhile, for the pull-up side, the
1.0V signal is not able to turn-off the PMOS completely.
1.5V
Furthermore, if the output transistors are driven by a low
1.2V voltage signal like 1.2V, the |Vgd| of pull-up PMOS will be
1.5V higher than threshold voltage when the I/O is working at
1.2V input mode with a high voltage I/O standard. In this case, the
2.5V
PMOS will conduct incorrectly and cause an undesired
leakage path through its channel [2]. To solve these issues, a
2.5V self-adaptive level shifter is added to transfer the output
2.5V
signal of pre-driver from 1.0V VCCIINT to the I/O supply
voltage, as shown in Fig. 2(a).
1.8V Although, self-adaptive level shifter insures the output
1.8V transistors can be operated correctly, it is still a challenge to
maintain the high-speed and high current drive of the low
1.5V voltage standards with 3.3V thick gate-oxide devices.
2.5V Consequently, an auxiliary supply, VCCAUX is introduced to
power the pull-down side of the buffer, which is set to 2.5V.
2.5V As can been seen from the Fig. 2(a), the whole driving path
2.5V of the NMOS output transistor is powered by the 2.5V
VCCAUX. Different from the pull-up side, the output voltage
2.5V of the level shifter in pull-down path is fixed at VCCAUX
rather than adapting with VCCO. On the one hand, by setting
the VGS of the NMOS at 2.5V, the output stage provides fast
edge rates and strong current drive when a low voltage VCCO
like 1.2V is applied, which means the size of pull-down
NMOS transistor can be reduced [3]. On the other hand, the
constant output level simplifies the level shifter in pull-down
side.
The single-ended input buffer is shown in Fig. 2(b). The
major challenge of the receiver is the degradation of the
signal. To improve the signal integrity, a Schmitt trigger is
designed as the main circuit of input buffer. Benefit from its
hysteresis feature, the noise immunity of the single-ended
input buffer is strengthen.

363
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Fig. 3(b) illustrates the schematic of the LVDS input
buffer. The LVDS input buffer is based on a differential pair
input stage with a cross-coupled load, which increases the
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(b) Input buffer.

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B. High-Speed LVDS Buffer
An LVDS interface has a low-voltage swing, from 250-
400 mV [4], which is connected point-to-point, achieves high (1 9287

data rates and reduced power dissipation. In Addition, both

Reduced Swing Differential Signaling (RSDS) and
HyperTransport Protocol (HT) are similar to LVDS. Hence,
Figure 3. Circuit Schematic of the differential-ended buffer: (a)Output
the transmitting of these differential-ended standards can be buffer; (b) Input buffer.
implemented by a high-speed LVDS output buffer with
configurable voltage swing and common-mode voltage. Output Stage
VCCO

Fig. 3(a) illustrates the schematic of the LVDS output

buffer. The 1.0V data signal and tri-state control signal are
shifted to 2.5V firstly. Then the data driver transfers the data VCCO

signal into two non-overlapping switching signals for the VCCO

output stage. The four NMOS transistors of the output stage
are used as switches and switched according to the non-
overlapping switching signals. Consequently, the polarity of Impedance -
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the current through the programmable resistors network is Control + PAD

Refer ence
switched correspondingly, which produces a differential Resi stor

output signal swing on the output terminations. The voltage

swing and common-mode voltage is adjusted by the value
and ratio of the bias current of the current mirror, and the
output impedance of the buffer is programed by the
programmable resistors network. Thus, the configurable
current mirror and programmable resistor network enables
the output buffer to support the HT, extended LVDS, LVDS, Figure 4. Block diagram of the impedance control.
and RSDS I/O standards with one circuit.

364
C. Impedance Control
As FPGAs get bigger and system clock speeds get faster,
with ever faster edge rates, maintaining signal integrity
becomes a critical issue. Printed circuit board (PCB) traces
must be properly terminated to avoid reflection or ringing. In
order to achieve better signal integrity, we introduce an
impedance control in the I/O buffer to match the impedance
of the trace, as shown in Fig. 1. The impedance control
accurately configures the on or off state of the parallel output
stage transistors by comparing VREF with the voltage of the
pad, as shown in Fig. 4. To compensate for variation of
temperature and supply voltage fluctuations, the impedance
of the I/O is continuously adjusted by actively controlling the
number of the conducting output stage transistors.
IV. MEASUREMENT RESULTS
The proposed I/O buffer was fabricated as part of an
SRAM-based FPGA test chip using commercial 65nm
CMOS technology. The layout is shown in Fig. 5. The
measurement result of single-ended output is shown in Fig. 6.
A pair of I/O pin was configured as LVCMOS standard with
1.2V and 3.3V VCCO. The output level shows good
agreement with specification of LVCMOS standard. Fig. 7
illustrates the eye diagram between two differential-ended
I/O pin. A PRBS23 pattern sequence was generated by
FPGA core and a Keysight DSA90804A digital signal
analyzer was used to measure the eye-diagram waveform.
The measured I/O pins have the farthest path in the global
clock network, which means the worst timing condition of
the FPGA test chip. The measurement result demonstrates
the proposed I/O buffer operates well at high-speed data
rates.
Figure 5. Layout of the proposed I/O buffer.
Figure 6. Measurement of LVCMOS output with 1.2V and 3.3V VCCO.
365
(a)
(b)
Figure 7. Eye diagram (a)LVDS at 1.0Gbps;(b)LVDSEXT at 1.2Gbps.
V. CONCLUSION
This paper describes the I/O buffer design for FPGA in
65nm CMOS technology. The proposed I/O buffer supports
upto 38 I/O standards. The mixed-voltage buffer with self-
adaptive level shifter is able to transmit and receive single-
ended signals with different supply voltage. The LVDS
buffer supports various differential-ended standards which
require different common-mode voltage and voltage swing.
The design has been successfully integrated in an FPGA chip.
The measurement results demonstrate the proposed I/O
buffer is able to support 1.25Gbps source-synchronous
standards.
REFERENCES
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[3] Jeffrey Tyhach et al., “A 90-nm FPGA I/O Buffer Design With 1.6-
Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock
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CDSTIC.IEL.IELDVD070:4:32231:1501981.
[4] IEEE Standard for Low-Voltage Differential Signals (LVDS) for
Scalable Coherent Interface (SCI), 1596.3 SCI-LVDS Standard, IEEE
Std1596.3-1996, 1996.