Digital Logic Homework University of Information Technology

- Computer Engineering Faculty

Homework7
(Due November 15, 2010)
1. Draw a timing diagram for the following NOR circuit for an SR
latch with the following input changes. Assume a 2.5 ns delay
for each gate. Comment on why we don’t let S=R=1 on a latch.
Show your timing diagram to at least 60 ns.

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Digital Logic Homework University of Information Technology
- Computer Engineering Faculty

2. Assume that each flip-flop has a setup time of 2 ns, a hold time
of 3 ns and a clock-to-output delay of 5 ns. Further assume that
each gate has a delay of 2 ns except each inverter has a delay of
1 ns. What is the maximum clock frequency that you can clock
the following circuits. Also discuss what constraints are placed
on the inputs.

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Digital Logic Homework University of Information Technology
- Computer Engineering Faculty

3. For the following storage device, derive the state transition

diagram and find the next-state, or characteristic, equation
(note the outputs are complements of each other).

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Digital Logic Homework University of Information Technology
- Computer Engineering Faculty

4. A sequential circuit with two D flip flops A and B and two

4.
inputs X and Y and one output Z is specified by the following
equations.

(a) Draw the logic diagram of the circuit, (b) Derive the state
table and (c) Derive the state diagram.
5. Design a counter that counts 1,2,3,5,8,13 and then repeats.
Show the equations for each flip-flop (next state equations).
You don’t have to draw the circuit. Don’t worry about reset.
6. A 4 bit twisted ring counter is a sequential circuit which
produces the following sequence of output values: 0000,
1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats.
Design a circuit for a 4 bit twisted ring counter that uses
four D flip flops. Draw a state transition diagram, a state
table and a schematic for your circuit. Design an alternate
implementation using just three flip flops and draw a state
transition diagram , state table and a schematic for your
circuit. If your designs are extended to implement an n bit
twisted ring counter, how many flip flops are required

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Digital Logic Homework University of Information Technology
- Computer Engineering Faculty

using each of the two approaches. In what situations would

you prefer the first method? In what situations would you
prefer the second?
7. Given a SRAM memory chip that is 134,217,728 x 4, answer the
following questions:
a. How many address and data pins does this part have?
b. How many bytes of memory are in this part?
c. Show how to use these chips, and any other logic necessary,
to build 256MB of RAM that is 16 bits wide. Be sure to
show the address, data, R/W’ and enable lines on each chip.

8. Given a SRAM with 4 bytes arranged as 4x8:

a. How many of these devices would you need to make 32
bytes of memory?
b. What size external decoder would you need to implement
this 32 bytes of memory assuming you want the addresses to
be referenced as addresses 0..31?
c. How large would the decoder need to be if you wanted to
make a 32 byte memory that was 16 bits wide?

9. Specify the size of a ROM (number of words and number of bits

per word) that will accommodate the truth table for the following
combinational circuit components: (a) an 8 bit adder-subtractor
with Cin and Cout; (b) A binary multiplier that multiplies two 8-bit
numbers; (c) a code converter from a 4-digit BCD number to a
binary number.

10. Show how the sequential circuit shown below can be mapped
onto a single configurable logic block. Do this by specifying the
functions that the LUTs implement and showing the paths through
the multiplexors that must be configured to provide the required
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Digital Logic Homework University of Information Technology
- Computer Engineering Faculty

connections. Also show what values must be stored in each location

of the LUTs to implement the required logic functions.

11. You have a cache memory that will be used on a computer with a
32 bit address and 32 bit words. Assuming you have 512 KB of
cache memory , how many words of memory can you cache in
each of the following cases:
a. Fully associative
b. Set associative with 16 bits of tag and eight 64 KB x 8 SRAM
chips
c. Set associative with 24 bits of tag and eight 64 KB x 8 SRAM
chips

12. A 32K×8 RAM chip uses coincident decoding by splitting the

internal decoder into row select and column select. (a) Assuming
that the RAM cell array is square, what is the size of each decoder,
and how many AND gates are required for decoding an address?
(b) Determine the row and column selection lines that are enabled
when the input address is the binary equivalent of 2100010.

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Digital Logic Homework University of Information Technology
- Computer Engineering Faculty

13. A DRAM has a refresh interval of 128 ms and has 4096 rows.
What is the interval between refreshes for distributed refresh?
What is the minimum number of address pins on the DRAM?

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