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LM5164
SNVSAU4A – SEPTEMBER 2018 – REVISED JANUARY 2019
LM5164 100-V Input, 1-A synchronous buck DC/DC converter with ultra-low IQ
1 Features 3 Description
1• Designed for reliable and rugged applications The LM5164 synchronous buck converter is designed
to regulate over a wide input voltage range,
– Wide input voltage range of 6 V to 100 V minimizing the need for external surge suppression
– Junction temperature range: –40°C to +150°C components. A minimum controllable on-time of 50 ns
– Fixed 3-ms internal soft-start timer facilitates large step-down conversion ratios, enabling
the direct step-down from a 48-V nominal input to
– Peak and valley current-limit protection
low-voltage rails for reduced system complexity and
– Input UVLO and thermal shutdown protection solution cost. The LM5164 operates during input
• Suited for scalable Industrial power supplies and voltage dips as low as 6 V, at nearly 100% duty cycle
battery packs if needed, making it an excellent choice for wide input
supply range industrial and high cell count battery
– Low minimum on- and off-times of 50 ns
pack applications.
– Adjustable switching frequency up to 1 MHz
With integrated high-side and low-side power
– Diode emulation for high light-load efficiency MOSFETs, the LM5164 delivers up to 1-A of output
– 10.5-µA no-load input quiescent current current. A constant on-time (COT) control architecture
– 3-µA shutdown quiescent current provides nearly constant switching frequency with
excellent load and line transient response. Additional
– Optimized for CISPR 32 EMI standard
features of the LM5164 include ultra-low IQ and diode
• Integration reduces solution size and cost emulation mode operation for high light-load
– COT mode control architecture efficiency, innovative peak and valley overcurrent
– Integrated 0.725-Ω NFET buck switch supports protection, integrated VCC bias supply and bootstrap
diode, precision enable and input UVLO, and thermal
wide duty-cycle range
shutdown protection with automatic recovery. An
– Integrated 0.34-Ω NFET synchronous rectifier open-drain PGOOD indicator provides sequencing,
eliminates external Schottky diode fault reporting, and output voltage monitoring.
– 1.2-V internal voltage reference The LM5164 is available in a thermally-enhanced, 8-
– No loop compensation components pin SO PowerPAD™ package. Its 1.27-mm pin pitch
– Internal VCC bias regulator and boot diode provides adequate spacing for high-voltage
applications.
– Open-drain power good indicator
– 8-Pin SOIC package with PowerPAD™ Device Information(1)
• Create a custom design using WEBENCH® power PART NUMBER PACKAGE BODY SIZE (NOM)
designer LM5164 SO PowerPAD (8) 4.89 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
2 Applications the end of the data sheet.
• Appliances, power and garden tools
• High-cell-count battery packs (E-Bike, E-Scooter)
• Motor drives, drones, telecom
Typical Application Typical Application Efficiency, VOUT = 12 V
VOUT = 12 V 100
LO
U1
VIN = 6 V...100 V 68 µH IOUT = 1 A
90
VIN SW
CBST
LM5164 80
CIN 2.2 nF RFB1
Efficiency (%)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5164
SNVSAU4A – SEPTEMBER 2018 – REVISED JANUARY 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 16
2 Applications ........................................................... 1 8.1 Application Information............................................ 16
3 Description ............................................................. 1 8.2 Typical Application .................................................. 16
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 22
5 Pin Configuration and Functions ......................... 3 10 Layout................................................................... 23
6 Specifications......................................................... 4 10.1 Layout Guidelines ................................................. 23
6.1 Absolute Maximum Ratings ...................................... 4 10.2 Layout Example .................................................... 25
6.2 ESD Ratings.............................................................. 4 11 Device and Documentation Support ................. 26
6.3 Recommended Operating Conditions....................... 4 11.1 Device Support...................................................... 26
6.4 Thermal Information .................................................. 5 11.2 Related Documentation ....................................... 26
6.5 Electrical Characteristics........................................... 5 11.3 Receiving Notification of Documentation Updates 27
6.6 Typical Characteristics ............................................. 7 11.4 Community Resources.......................................... 27
7 Detailed Description .............................................. 9 11.5 Trademarks ........................................................... 27
7.1 Overview .................................................................. 9 11.6 Electrostatic Discharge Caution ............................ 27
7.2 Functional Block Diagram ....................................... 10 11.7 Glossary ................................................................ 27
7.3 Feature Description................................................. 10 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 15 Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• First release of production-data data sheet; add top navigator icon for TI reference design................................................. 1
DDA Package
8-Pin SO PowerPAD
Top View
GND SW
VIN BST
EP
EN/UVLO PGOOD
RON FB
Pin Functions
PIN
I/O (1) DESCRIPTION
NO. NAME
1 GND G Ground connection for internal circuits.
Regulator supply input pin to high-side power MOSFET and internal bias regulator. Connect
2 VIN P/I
directly to the input supply of the buck converter with short, low impedance paths.
Precision enable and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is
below 1.1 V, the converter is in the shutdown mode with all functions disabled. If the UVLO voltage
3 EN/UVLO I is greater than 1.1 V and below 1.5 V, the converter is in standby mode with the internal VCC
regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up
sequence begins.
4 RON I On-time programming pin. A resistor between this pin and GND sets the buck switch on-time.
5 FB I Feedback input of voltage regulation comparator.
Power good indicator. This pin is an open-drain output pin. Connect to a source voltage through an
6 PGOOD O
external pullup resistor between 10 kΩ to 100 kΩ
Bootstrap gate-drive supply. Required to connect a high-quality 2.2-nF 50-V X7R ceramic capacitor
7 BST P/I
between BST and SW to bias the internal high-side gate driver.
Switching node that is internally connected to the source of the high-side NMOS buck switch and
8 SW P the drain of the low-side NMOS synchronous rectifier. Connect to the switching node of the power
inductor.
Exposed pad of the package. No internal electrical connection. Solder the EP to the GND pin and
— EP —
connect to a large copper plane to reduce thermal resistance.
6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted) (1)
MIN MAX UNIT
VIN to GND –0.3 100
EN to GND –0.3 100
Input voltage V
FB to GND –0.3 5.5
RON to GND –0.3 5.5
Bootstrap
External BST to SW capacitance 1.5 2.5 nF
capacitor
BST to GND –0.3 105.5
BST to SW –0.3 5.5
Output voltage SW to GND –1.5 100 V
SW to GND (20-ns transient) –3
PGOOD to GND –0.3 14
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
100 100
90
90
80
Efficiency (%)
Efficiency (%)
70
80
60
50
VIN = 14V 70 VIN = 14V
VIN = 24V VIN = 24V
40 VIN = 48V VIN = 48V
VIN = 72V VIN = 72V
30 60
0.001 0.01 0.1 1 0 0.2 0.4 0.6 0.8 1
Load (A) Load (A)
Figure 1. Conversion Efficiency (Log Scale) Figure 2. Conversion Efficiency (Linear Scale)
20 20
Sleep Sleep
18 Shutdown 18 Shutdown
16 16
Quiescent Current (uA)
14 14
Current (PA)
12 12
10 10
8 8
6 6
4 4
2 2
0 0
-50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 90 100
Junction Temperature (qC) D005
Input Voltage (V) D006
Figure 3. VIN Shutdown and Sleep Supply Current vs Figure 4. VIN Shutdown and Sleep Supply Current vs Input
Temperature Voltage
725 600
590
700
580
675
Active Current (PA)
570
560
650
550
625
540
600 530
520
575
510
550 500
-50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 90 100
Junction Temperature (qC) D007
Input Voltage (V) D008
Figure 5. VIN Active Current vs Temperature Figure 6. VIN Active Current vs Input Voltage
1.2
FB Regulation Threshold (V)
1.205
1
RDSON (:)
0.8
1.2
0.6
0.4
1.195
5
Current Limit (A)
1.4
ON-Time (Ps)
4
1.3
3
1.2
2
1.1 1
Peak Current
Valley Current
1 0
-50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 90 100
Junction Temperature (qC) D011
Input Voltage (V) D012
Figure 9. Peak and Valley Current Limit vs Temperature Figure 10. COT On-Time vs VIN
7 Detailed Description
7.1 Overview
The LM5164 is an easy-to-use, ultra-low IQ constant on-time (COT) synchronous step-down buck regulator. With
integrated high-side and low-side power MOSFETs, the LM5164 is a low-cost, highly efficient buck converter that
operates from a wide input voltage of 6 V to 100 V, delivering up to 1-A DC load current. The LM5164 is
available in the 8-pin SO PowerPAD package. This constant on-time (COT) converter is ideal for low-noise, high-
current, and fast load transient requirements, operating with a predictive on-time switching pulse. Over the input
voltage range, input voltage feedforward is employed to achieve a quasi-fixed switching frequency. A controllable
on-time as low as 50 ns permits high step-down ratios and a minimum forced off-time of 50 ns provides
extremely high duty cycles allowing VIN to drop close to VOUT before frequency foldback occurs. At light loads the
device transitions into an ultra-low IQ mode to maintain high efficiency and prevent draining battery cells
connected to the input when the system is in standby. The LM5164 implements a smart peak and valley current
limit detection circuit to ensure robust protection during output short circuit conditions. Control loop compensation
is not required for this regulator, reducing design time and external component count.
The LM5164 incorporates additional features for comprehensive system requirements, including an open-drain
Power Good circuit for power-rail sequencing and fault reporting, internally-fixed soft start, monotonic start-up
into prebiased loads, precision enable for programmable line undervoltage lockout (UVLO), smart cycle-by-cycle
current limit for optimal inductor sizing, and thermal shutdown with automatic recovery. These features enable a
flexible and easy-to-use platform for a wide range of applications. The LM5164 supports a wide range of end-
equipment systems requiring a regulated output from a high input supply where the transient voltage deviates
from its DC level. Examples of such end equipment systems are 48-V automotive systems, high cell-count
battery-pack systems, 24-V industrial systems, and 48-V telecom and PoE voltage ranges. The pin arrangement
is designed for a simple layout requiring only a few external components.
± SHUTDOWN BST
+
LOGIC
0.4 V
VIN
CBST
RON ON/OFF DISABLE
TIMERS
VOUT CONSTANT
LO VOUT
ON-TIME SW
CONTROL
RFB1 VCC
LOGIC
FEEDBACK
COMPARATOR SLEEP COUT
FB
± DETECT
RRON ZC
VREF +
ZX DETECT + PGOOD
±
RFB2 PEAK/VALLEY
CURRENT LIMIT
FB ±
GND +
PGOOD
0.9*VREF COMPARATOR
10
20mV CA t
RESR t FSW ˜ (RFB1 || RFB2 ) (7)
20mV ˜ VOUT 'IL(nom) (4) R C d
RESR t A A
VFB1 ˜ 'IL(nom) (2) VOUT
RESR t VIN-nom VOUT ˜ t ON @VIN-nom
VOUT 2 ˜ VIN ˜ FSW ˜ COUT (5)
RESR t 20mV (8)
2 ˜ VIN ˜ FSW ˜ COUT (3) 1
CFF t t TR-settling
2S ˜ FSW ˜ (RFB1 || RFB2 ) (6) CB t 3 ˜ R
FB1 (9)
Table 1 presents 3 different methods for generating appropriate voltage ripple at the feedback node. Type-1
ripple generation method uses a single resistor, RESR in series with the output capacitor. The generated voltage
ripple has two components, capacitive ripple caused by the inductor ripple current charging and discharging the
output capacitor and resistive ripple caused by the inductor ripple current flowing into the output capacitor and
through series resistance RESR. The capacitive ripple component is out of phase with the inductor current and
does not decrease monotonically during the off-time. The resistive ripple component is in phase with the inductor
current and decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at
VOUT for stable operation. If this condition is not satisfied, unstable switching behavior is observed in COT
converters, with multiple on-time bursts in close succession followed by a long off time. Equation 2 and
Equation 3 define the value of the series resistance RESR to ensure sufficient in-phase ripple at the feedback
node.
Type-2 ripple generation uses a CFF capacitor in addition to the series resistor. As the output voltage ripple is
directly AC-coupled by CFF to the feedback node, the RESR and ultimately the output voltage ripple are reduced
by a factor of VOUT / VFB1.
Type-3 ripple generation uses an RC network consisting of RA and CA, and the switch node voltage to generate a
triangular ramp that is in-phase with the inductor current. This triangular wave is the AC-coupled into the
feedback node with capacitor CB. Because this circuit does not use output voltage ripple, it is suited for
applications where low output voltage ripple is critical. TI application note AN-1481 Controlling Output ripple and
achieving ESR independence in constant on-time (COT) regulator designs provides additional details on this
topic.
Diode emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains highest efficiency
at light load currents by decreasing the effective switching frequency. DEM operation occurs when the
synchronous power MOSFET switches off as inductor valley current reaches zero. Here, the load current is less
than half of the peak-to-peak inductor current ripple in CCM. Turning off the low-side MOSFET at zero current
reduces switching loss, and preventing negative current conduction reduces conduction loss. Power conversion
efficiency is thus higher in a DEM converter than an equivalent forced-PWM CCM converter. With DEM
operation, the duration that both power MOSFETs remain off progressively increases as load current decreases.
When this idle duration exceeds 15 μs, the converter transitions into an ultra-low IQ mode, consuming only 10-μA
quiescent current from the input.
VREF
iL
Peak ILIM
IAVG(ILIM)
Valley ILIM
IAVG1
t
tON < tON
tSW > tSW
Current is sensed after a leading-edge blanking time following the high-side MOSFET turnon transition. The
propagation delay of the current limit comparator is 100 ns. During high step-down conditions when the on-time
is less than 100 ns, a back-up peak current limit comparator in the low-side FET also set at 1.5 A will enable the
fold-back valley current limit set at 1.2 A. This innovative current limit scheme enables ultra-low duty-cycle
operation permitting large step down voltage conversions while ensuring robust protection of the converter.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation and test results of
an LM5164-powered implementation, see TI Designs reference design library.
LO VOUT = 12 V
VIN = 15 V...100 V U1 IOUT = 1 A
68 PH
VIN SW
RA CA
CIN LM5164 CBST
2.2 nF 453 k: 3.3 nF
2.2 PF EN/UVLO BST RFB1
CB
453 k: COUT
56 pF 47 PF
RON FB
RRON
100 k: RFB2
GND PGOOD 49.9 k:
Figure 12. Typical Application VIN(nom) = 48 V, VOUT = 12 V, IOUT(max) = 1 A, FSW(nom) = 300 kHz
NOTE
This and subsequent design examples are provided herein to showcase the LM5164
converter in several different applications. Depending on the source impedance of the
input supply bus, an electrolytic capacitor may be required at the input to ensure stability,
particularly at low input voltage and high output current operating conditions. See Power
Supply Recommendations for more detail.
VOUT
VIN(max)
t ON(min) ˜ FSW
(17)
IOUT ˜ D ˜ 1 D
CIN t
FSW ˜ VIN(ripple) IOUT ˜ RESR
(23)
The recommended high-frequency input capacitance is 2.2 µF or higher. Ensure the input capacitor is a high-
quality X7S or X7R ceramic capacitor with sufficient voltage rating for CIN. Based on the voltage coefficient of
ceramic capacitors, choose a voltage rating of twice the maximum input voltage. Additionally, some bulk
capacitance is required if the LM5164 is not located within approximately 5 cm from the input voltage source.
This capacitor provides parallel damping to the resonance associated with parasitic inductance of the supply
lines and high-Q ceramics. See Power Supply Recommendations for more detail.
100 100
90
90
80
Efficiency (%)
Efficiency (%)
70
80
60
50
VIN = 14V 70 VIN = 14V
VIN = 24V VIN = 24V
40 VIN = 48V VIN = 48V
VIN = 72V VIN = 72V
30 60
0.001 0.01 0.1 1 0 0.2 0.4 0.6 0.8 1
Load (A) Load (A)
Figure 13. Conversion Efficiency (Log Scale) Figure 14. Conversion Efficiency (Linear Scale)
12.4
12.3
12.2
Output Voltage (V)
12.1
12
11.9
VIN = 15V
11.8 VIN = 24V
VIN = 36V
11.7 VIN = 48V
VIN = 60V
11.6
0 0.2 0.4 0.6 0.8 1
Output Current (A)
VIN = 24 V IOUT = 0.25 A to 1 A at 0.1 A/μs
Figure 15. Load and Line Regulation Performance Figure 16. Load Step Response
Figure 17. No-Load Start-up with VIN Figure 18. Full-Load Start-up with VIN
Figure 19. No-Load Start-up and Shutdown with EN/UVLO Figure 20. Full-Load Start-up and Shutdown with EN/UVLO
Figure 21. Pre-bias Start-up with EN/UVLO Figure 22. Short Circuit Applied
Figure 23. Short Circuit Recovery Figure 24. No Load to Short Circuit/Short Circuit Recovery
10 Layout
VIN
VIN
2 CIN
LM5164
High
BST di/dt
High-side loop
Q1
NMOS LO
gate driver
SW
8 VOUT
CO
Low-side Q2
NMOS
gate driver
GND
1 GND
Figure 27. DC/DC Buck Converter With Power Stage Circuit Switching Loop
The input capacitor provides the primary path for the high di/dt components of the high-side MOSFET's current.
Placing a ceramic capacitor as close as possible to the VIN and GND pins is the key to EMI reduction. Keep the
trace connecting SW to the inductor as short as possible and just wide enough to carry the load current without
excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path to minimize
parasitic resistance. Place the output capacitor close to the VOUT side of the inductor, and connect the capacitor's
return terminal to the GND pin and exposed PAD of the LM5164.
PGOOD
connection
Place resistor R8
close to the RON pin
11.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 19-Jan-2019
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
LM5164DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 150 LM5164
& no Sb/Br)
LM5164DDAT ACTIVE SO PowerPAD DDA 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 150 LM5164
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 19-Jan-2019
• Automotive: LM5164-Q1
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Jan-2019
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Jan-2019
Pack Materials-Page 2
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