Muhammad Awais H +92-3465316595

B muhammadawais@ciitwah.edu.pk

Education
2011–2014 PhD. Electronics Engineering, VLSI Research Group, Politecnico di
Torino, Italy.
Research Topic: Design of advanced LDPC decoders using traditional and new
implementation technologies.
2008–2010 MS. Electronics Engineering, Politecnico di Torino, Italy, .
Final Score: 101/110 (84%)
MS. Thesis Title: Scalable, High Throughput, Multi-standard LDPC Decoder
design and VLSI Implementation.
2003–2007 BS. Electronics Engineering, Dept. of Electronics, Intl. Islamic Univer-
sity, Islamabad, Pakistan., .
Final Score: CGPA 3.35/4.0 (76.58%)
PEC. Number: Electro. 9264
BS. Thesis Title: Design, Implementation and performance comparison of
SISO-OFDM and MIMO-OFDM system.

Research Interests
{ VLSI methods and architectures for { Digital communications
flexible channel decoders
{ Integrated system and computer ar- { RTL design, FPGA prototyping,
chitecture synthesis and optimization.
{ Design for “Beyond CMOS” nan- {
otechnologies

Work Experience
Mar. COMSATS Institute of Information Technology, Wah Cantt. .
2014–Present Department: Electrical Engineering dept.
Designation: Assistant Professor (TTS).
Nov. 2007–Aug. Pakistan Telecommunication Company Ltd.
2008 Department: Office of Transmission Network Region (Saddar) Rawalpindi.
Designation: Management Trainee Technical (MTT)
ROLE: Installation, commissioning and trouble shooting of digital radio
transceiver sites (SRAL and SRAL-XD modules).

Trainings/Achievements
One month (Nov. 2007-Dec. 2007) training at Telecommunication Staff
College Haripur. The training gave a basic knowledge and experience about
the various telecommunication techniques and technologies used by PTCL
ltd.
Winner of Visio Spark 2007. A mega level IT quiz competition (consisting of
various subjects from electronics and computer engineering fields) held at
CIIT Wah.
 Fully funded scholarship for MS leading to PhD. studies by Higher Education
Commision of Pakistan

Professional Skills
OS Linux, Unix, Windows Programming C/C++, VHDL
Scientific Tools Xilinx ISE, Quartus 2, Mod- Typography Latex, Lyx.
elsim, Synopsys Design Vi-
sion, Encounter, QCA De-
signer, ADMS, Matlab
Platforms Nios II Development Kit Cy-
clone II Edition, Virtex 5, Vir-
tex 6 Evaluation Boards

Conferences/Summer Schools Attended

INMIC-2011 Intl. Multitopic Conference 2011.
Venue: Sir Syed University of Engineering and Technology, Karachi.
Participation Type: Author, presented two research papers.
ICECS-2012 IEEE International Conference on Electronics, Circuits, and Sys-
tems 2012 .
Venue: Seville, Spain.
Participation Type: Author, lecture presentation of two research papers.
SIPD-2012 Summer School: Scuola Interpolitecnica di Dottorato 2012 .
Venue: Torino
Details: Attended and passed positively the exams of the SIPD summer school.
This school consisted of seven lectures about various advanced topics of Electronic
Engineering, delivered by professors of the Polytechnic Universities of Bari, Milan
and Torino.

References
Dr. Guido Masera, Confirmed Associate Professor, DET, Politecnico di
Torino.
Affiliation: PhD. Supervisor, MS. Thesis Supervisor
Contact Details: Email: guido.masera@polito.it Phone: +39-0110904102
Dr. Guido Montorsi, Professor, DET, Politecnico di Torino.
Affiliation: Co Supervisor
Contact Details: Email: guido.montorsi@polito.it Phone: +39-0110904144-
4144
Dr. Ashwani Singh, Consultant Sénior, Alten Group of Engg. France.
Affiliation: MS. Thesis Co Supervisor, Co-author
Contact Details: Email: singh.ashwani@gmail.com Phone: +33649584897
 List of Publications
Journals / 1. Awais. M, C. Condo,“Flexible LDPC Decoder Architectures”, Hindawi,
Transactions Journal of VLSI Design, Vol. 2012, pp. 1-16, doi:10.1155/2012/730835.
2. Awais. M, Vacca. M, Graziano. M, Roch. M.R., Masera. G, “Quantum
Dot Cellular Automata Check Node Implementation for LDPC Decoders“, IEEE
Transactions on Nanotechnology, Vol.12, no.3, pp.368-377, May 2013 [Impact
Factor (2013)=1.80]
3. Awais. M, Montorsi. G, Maurizio. M, Masera. G,“VLSI implementation of a
non binary LDPC decoder based on Analog Digital Belief Propagation Algorithm”,
IEEE. Transactions on Signal Processing, vol.62, no.15, pp.3965-3975, Aug.1, 2014
[Impact Factor (2014)=3.198]
4. A. Ahmed, M. Awais, M. Iqbal, M. Naeem, A. Anpalagan, “Estimation of
Distribution Algorithm with Thresholding for Multiple Lines Outage Detection
in Smart Grid”, Industrial Informatics, IEEE Transactions on [Under review,
Impact factor: 8.785]
5. M. Awais, M. Iqbal, M. Naeem, A. Ahmed, Nadia Qadri, A. Anpalagan, “Effi-
cient Line Outage Identification using Quantum Inspired Evolutionary Algorithm”,
Industrial Applications, IEEE Transactions on [Under review, Impact factor:
2.046]
6. A. Ahmed, M. Awais, M. Iqbal, M. Naeem, A. Anpalagan, “A Taxonomy of
Line Outage Detection Problems in Smart Power Systems”, Energies [Under
Review, Impact factor: 1.602]
7. A. Ahmed, M. Awais, M. Iqbal, M. Naeem, A. Anpalagan, “An Insight to Es-
timation of Distribution Algorithm for Line Outage Detection and Identification”,
Energy [Under Review, Impact factor: 4.465]
Published in 8. Awais. M, Singh. A, Boutillon. E., Masera. G,“A novel architecture
Conference for scalable, high throughput, multistandard LDPC decoder”, Proc. 14th
Proceedings Euromicro Conference on Digital System Design (DSD), 2011, pp.340-347.
9. Awais. M, Singh. A, G Masera, “Scalable, High Throughput LDPC
Decoder for WiMAX (802.16e) Applications ”. ACC 2011-INDIA, Part II,
CCIS 191, pp. 374-385. Springer, Heidelberg (2011).
10. Awais. M, Vacca. M, Graziano. M, Masera. G, “FFT implementation
using QCA”, in Proc. 19th IEEE Intl. Conf. Electronics Circuits and
Systems (ICECS),pp.741-744 dec. 2012- SPAIN.
11., G. Urgese, Graziano. M, Vacca. M, Awais. M, Frache. S, Zamboni. M,
“ Protein alignment HW/SW optimizations”, in Proc. 19th IEEE Intl. Conf.
Electronics Circuits and Systems (ICECS),pp.145-148 dec. 2012- SPAIN.
12., Ahmed. A, Awais. M, Maurizio. M, Masera. G,“VLSI implementation
of 16-point DCT for H.265/HEVC using walsh hadamard transform and
lifting scheme”, in Proc. 14th IEEE Intl. Multitopic Conf (INMIC),pp.144-
148, 22-24 Dec. 2011.
13., Ahmed. A, Awais. M, ur Rehman. A, Maurizio. M, Masera. G,“A
high throughput turbo decoder VLSI architecture for 3GPP LTE standard”,
in Proc. 14th IEEE Intl. Multitopic Conf (INMIC),pp.340-346, 22-24 Dec.
2011.
14., Ali. A, Awais. M, Maurizio. M, Masera. G,“FPGA accelerator of
Quasi Cyclic EG-LDPC Codes decoder for NAND flash memories”, in Proc.
Conf. on Design and Architectures for Signal and Image Processing (DASIP),
Cagliari, Italy, Oct. 2013..
Research Projects Funding
Higher Education Commision (HEC) of Pakistan startup research grant,
worth 0.5 million PKR

Thesis Supervision
“A flexible simulation platform for LDPC decoding”, Nida Tasneem, MS
Thesis
“FPGA based Emulator design for LDPC decoding”, Roman, BS Thesis

Professional Memebership and Achievements

Fully funded scholarship for MS leading to PhD. in Italy granted by HEC
Pakistan
HEC Pakistan approved supervisor
Membed Pakistan Engineering Council

Professional Activities
Reviewer at IEEE Transactions on Nanotechnology (TNANO)
Reviewer at IEEE Transactions on circuits and systems
Revewer at Journal of Circuits, Systems and Computers DOI: D-14-00369R1

Teaching Activities
Undergrat. Course on Electrical circuit DC analysis
Undergrat. Course on Signals and Systems
Undergrat. Course on Embedded system design
Undergrat. Course on Digital system design
Graduate course on Principles of Digital Communications