218 IEEE TRANSACTIONS

ON ELECTRON
DEVICES, VOL. ED-24, NO. 3, MARCH 1977

that AC3;’oAx < AC&fx, indicating a decrease in 10 and an foundly affect the behavior of devices fabricated in the
increase in doping. Also shown inFig. 2 is the AC( V) plot SOS. We conclude that the modified MIS capacitance
(at step 9) after annealing. Here again the effect of the method is an effective technique for characterizing the
annealing processis evidently counter tothat of the oxi- Si-sapphire interface region and for monitoring changes
dation process. The average valuesof ID, N , and N F Bare in it due to high-temperaturedevice processing steps.
shown in TableI. Since the counter-electrode positionson
ACKNOWLEDGMENT
the p-SOS sample after annealing were different from
those employed earlier (see Section 11-B),any quantitative We are indebted toJ. M. Breece, D. R.Capewell, and T.
comparison of the after-annealing data with those before Pawlicki for technical assistance in the preparation and
annealing is probably unwarranted. processing of the samples.
REFERENCES
Iv. DISCUSSIONAND CONCLUSIONS
[l]E. J. Boleky and J. E. Meyer, “High-performance, low-power CMOS
We have measured AC(V) for both n-SOS and p-SOS memories using silicon-on-sapphire technology,” IEEE J . Solid-
samples. We find that there are significant changes in- State Circuits, vol. SC-7, p. 135,1972.
troduced by 1) oxidation in HC1 steam at 900°C for one [2] F. P. Heiman, “Thin-film silicon-on-sapphire deep depletionMOS
transistors,” IEEE Trans. Electron Deuices,vol. ED-13, p. 855,
hour and 2) annealing inHZ a t 50OOC for 15 min. 1966.
Oxidation tends tomove the AC( V) plots tomore pos- [3] G. W. Cullen, “The preparation and propertiesof chemically vapor
deposited silicon on sapphire and spine1,”J. Crystal Growth, vol. 9,
itive bias;i.e., introduce negative charge at theSi-sapphire p. 107, 1971.
interface. In addition, oxidation tends to decrease the ef- [4] A. M. Goodman, “A useful modification of the technique for mea-
fective dopingin n-Si and increase the doping inp-Si ad- suring capacitance asa function of voltage,” I E E E Trans. Electron
jacent to the sapphire. Annealing, on the other hand, has [5] A.Deuices, vol. ED-21, p. 753, 1974.
M. Goodman, “An investigation of the silicon sapphire interface
the opposite effect. using the MIS capacitance method,” IEEE Trans. ElectronDeuices,
A detailed quantitative analysis requires that an as- vol. ED-22, p. 63, 1975.
sumption be made about the positional variationof the [6] W. Kern, “Cleaning solutions based on hydrogen peroxide for use-in
silicon semiconductor technology,” RCAReview,vol.31,p. 187,
doping. The simple assumptionof constant doping (used 1970.
to determineN and N F Bin Table I)is, strictly speaking, [7] W. Kern, “Radioisotopes in semiconductor science and technology,”
probably not justified. It does, however, provide a golld Semiconductor Products and Solid State Technology, vol. 6, p. 22,
1963.
semi-quantitative pictureof the changes occurringat and [8] A. S. Grove, Physics and Technology of Semiconductor Deuices.
near the Si-sapphire interface, changes that could pro- New York: Wiley, 1967, ch 9.

Very Small MOSFET’s for Low-Temperature Operation

Abstract-The improvements in the device characteristics of and predictable over this entiretemperature range. A device design
n-channel MOSFET’s that occur atlow temperatures are consid- is presented foran enhancement mode FET with a channel length
ered in this paper. The device parameters for polysilicon gate FET’s of 1 pm that is suitable for operation at liquid nitrogen tempera-
with channel lengthsof the order of 1 pm have been studiedboth ture.
experimentally and theoretically at temperatures ranging from
room temperature down to liquid nitrogen temperature. Excellent
agreement was found between the experimental dc device char- LIST OF SYMBOLS
acteristics andthosepredicted by a two-dimensional current
transport model, indicating that device behavior is wellunderstood
Junction capacitance.
Fast surface statecapacitance.
Gate oxide capacitance.
Manuscript received July 29,1976;revised October20,1976. Thispaper Silicon depletion layer capacitance.
is the expanded version of a talk given at theIEEE International Electron Electron diffusion coefficient.
Device Meeting in December 1975 entitled “Characterization of Very
Small MOSFETsfor Low Temperature Operation” (see Technical Di- Hole diffusion coefficient.
gest, pp. 43-46). Electric field.
The authors arewith the ThomasJ. Watson Research Center, IBM,
Yorktown Heights, NY 10598. Bottom of conduction band.
GAENSSLEK et ffl.: VERY SMALL MOSFET's 219

Fermi level. I. INTRODUCTION

Forbidden energygap.
Top of valence band.
Permittivity of free space.
Relative dielectric constantof silicon
L OW TEMPERATURE
operat.ion
holds
great
promise for improved performame, increased reli-
ability, and higher densityof MOSFET digital integrated
dioxide. circuits for computers. This paper concerns the improve-
Relative dielectric constantof silicon. ments in n-channelMOSFET device pwformance that can
Transconductance. be realized by operating thedevices near liquid nitrogen
Electron generation rate. temperature (Le., 77 K). In addition to experimental ver-
Hole generation rate. ification of improved device parametersa t low tempera-
Activation energy. tures and two-dimensional simulation of their dc charac-
Drain-to-source current. teristics, an objective of this work is the definition of a
Diode reverse current. devicedesign for ann-channel, po'lysilicon gate,en-
Current density. hancement mode MOSFET with a channel length of 1Mm
Flux of atoms. that is suitable for operation a t liquid nitrogen tempera-
Electron current density. ture. Bipolar transistors are generally considered to be
Hole current density. unusable a t such low temperatures as a consequence of
Boltzmann's constant. strongly reduced currentgain [l], [5], [40].
Channel length. Several authors have considered the potential advan-
Effective surface mobility. tages of operating semiconductor devices [2] and inte-
Electron mobility. grated circuits [3]-[5] a t low temperaltures. Advantages
Hole mobility. considered include higher switching speed due toincreased
Surface mobility. mobility and decreased electrical resis'tance; increased
Electron concentration. reliability due to exponential slow down of thermally ac-
Acceptor concentration. tivated processes such as diffusion, electromigration,and
Acceptor concentration notfrozen out. chemical reaction; improved noise behavior due toreduced
Donor concentration. thermal noise; and greater packing diensity due to im-
Intrinsic carrier concentration. proved heat removal. Low-temperature operation has also
Oxide charge density. been a major consideration in discussions of physical limits
Effective densityof states invalence band. to electronic circuitry [6], [7]. Furthe:rmore, it has been
Hole concentration. proposed that semiconductorsotherthan silicon and
Potential. germanium might find greater acceptance if low-temper-
Surface potentiala t threshold. ature operation becamea practical reality[2], [8]. To date,
Magnitude of elementary charge. however, relatively littleattention hasheen devotedto the
Electron recombination rate. device design considerations that woudd be required for
Hole recombination rate. low-temperatureoperation of high-density logic and
Aluminum sheet resistance. memory circuits utilizing large-scale integration of the
Silicon sheet resistance. silicon MOSFET technology. Such circluits might be used,
Slope of semilogarithmic transfer for example, inmedium- andlarge-size digitalcomputers
characteristic. of the future.
Thermal conductivity. Previous experimental studies of MOSFET character-
Time. istics at very low temperatures have been made [9]-[17],
Temperature. often forthe purpose of obtaining a better understanding
Limiting time to breakdown. of the transport propertiesof carriers in surface inversion
Oxide thickness. layers [9], [lo], or the temperature d.ependence of the
Electron velocity. threshold voltage [12], [16]. A t tempera.tu.res approaching
Built-in junctionvoltage. absolute zero, silicon FET's exhibit freezeout of mobile
Drain-to-source voltage. carriers in nondegenerate substrates [12],('141,[17],surface
Flat-band voltage. quantization [la], andvarious transient conduction effects
Gate voltage. [lo], [12]. A practical application of IWT's a t such ex-
Horizontal shift voltage. tremely low temperatures is as low-noise preamplifiers
Intercept of voltage axis. [12]-[X]. In the presentwork, however,the temperature
Threshold voltage. of primary interestis 77 K which is easily attained with a
Diode reverse voltage. convenient, relatively inert, cryogenic coolant (Le., liquid
Source-to-substrate voltage. nitrogen) and nearwhich some physicalparameters such
Vertical shift voltage. as electrical and thermal conductivities approach their
Channel width. optimum values, and others such as carrier mobility and
Source and draindiffusion depth. leakage current are substantially improved.
220
POLY Si GATE
---
0.4pm
0.5pm
P-TYPE SILICON (0.5ohm-cm)
Fig. 1. Cross section of n-channel MOSFET with self-aligned polysilicon
gate.
In this study, polysilicon gate, n-channel, enhancement
mode MOSFET’s are used to demonstrate some of the
performance advantages at temperatures ranging froln
room temperature (296 K) to liquid nitrogentemperatu~e
(77 K). A two-dimensional numerical device model [19],
[20] isused for devicesimulation at low temperatures. This
model previously demonstrated excellent agreement be-
tween measured and simulated characteristics of such
devices over a wide range of channel lengths at rooin
temperature [21]. In contrast, the present study explores
the degree of agreement over a wide range of lower tenl-
peratures.
Earlier work [22] considered the coordinated changcs
in physical dimensions,voltage levels, and impuritycon-
centrations necessary to scale down MOSFET source i~
drain spacings to the orderof 1pm for a given 0peratir.g
temperature. These scaling rules are based on the con-
stancy of the power density and of the electric field acrow
the gate insulator [23].Unfortunately, in this context,
temperature is not alinear scaling parameter to be changed
in concert with the dimensions, voltages, and impurity
concentrations of the device. At room temperature, limi-
tations to scaling arise as evidenced in the subthreshold
transfer characteristic and interconnection line resistances.
Lower operating temperature offers a means for oves-
coming these limitations.
11. DEVICESTRUCTURE
The device structure used in this studywas an n-channe!
enhancement mode MOSFET with a self-alignedpolysi-
licon gate (see Fig. 1). A four-mask process was used 1;o
fabricate a test chip containing FET’s with channel lengths
ranging from 0.8 to 10 pm using optical contact printing.
Fig. 2 shows a scanning electron micrographof a typical
FET (taken at 720X magnification), and anexpanded view
of the channel region (taken at 1440X magnification). The
testchip also contained MOS capacitors,four-point
probes, and diodes. The starting substrate was borcm
doped, p-type, (100) -oriented silicon with a0.5 ohm cm
resistivity (i.e., 4 X 1016 cm-3 impurity concentration).
The fabrication process was as follows. First, a field
oxide of 2500-A thickness was thermally grown. Then the
device areas were delineated anda 200-A thick Si02 gate
insulator was grown by dry thermal oxidation. Next, a
3250-A thick polysilicon layer was deposited, doped n
and thegate oxide removed over the subsequently formcd
IEEE TRANSACTIONS Oh‘ ELECTRON DEVICES, MARCH 1977
Fig. 2. Scanning electron micrograph of typical device on the right and
expanded view of channel region on the left.
source and drainregions. The source and drainwere dif-
fused from a depositedPOCls layer to a depth of about 0.5
pm. The entire structurewas then reoxidized to yield an
insulation layerof about 4000 A of Si02 (see Fig. 1).Con-
tact holes to source, gate,and drainregions were opened
where required and the aluminummetallization pattern
was delineated. A metallic layer was used between the
aluminum and theshallow p-n junctions to prevent failure
of the junctions duringthe final annealing step.An ohmic
substrate contact was provided by a backside aluminum
evaporation.
After fabrication, the chips were diced and mountedon
TO-5 headers or in 24 pin DIP’S. The chips were attached
to headers with Epo-Tex 410 epoxy which provided an
electricalconnection tothesubstrateand areliable
physical bond between the chip and theheader throughout
repeated thermal cycling. Aluminum wires of 0.7-mil di-
ameter were ultrasonically bonded to the aluminum pads.
Electrical measurements were made with the samples
immersed directly in liquid nitrogen, or in a Statham
model SD30 low-temperature testchamber which uses cold
nitrogen gas. The devices werenot passivated nor were the
chip packages sealed.
111. TWO-DIMENSIONAL NUMERICAL
DEVICE
SIMULATIONS
A two-dimensional simulationmodel [19], [20] wasused
to calculate the dc device characteristics for this study.
This model has previously demonstrated excellent agree-
ment between measured and simulated device character-
istics over a wide range of channel lengths at room tem-
perature [21]. The model uses a finite difference method
to solve the following set of nonlinear differential equations
under appropriate boundary conditions over the device
cross section:
.
J , = qpnn grad y5 + qDn grad n (3)
div Jp = q(Gp- R P ) (4)
tl
GAENSSLEN e t a l . : VERY SMALL MOSFET’? 22 1

1 1o3 1o4

E(Vlcm)
13

Fig. 3. The velocity-electric Weld characteristics of electrons on the (100) Fig. 4. Semilogarithmicplots of transfercharacteristics fora long
surface of silicon, measured by a pulse method from[26]. channel device ( L = 9 pm) with temperature aasparameter. Discrete
points (+) re resent results of two-dimensional simulations for 296
K, 200 K, ana77 K.

Equation (1)is Poisson’s equation,(2) and (3) are thehole

and electron current densities,respectively, (4) and (5) are logarithmic plot.The slope is important because the cur-
the current continuity equations for holes and electrons, rent at zero-gate voltage is a critical design parameter,
respectively, and(6) gives the total current density.
Briefly, particularly for dynamic switching circuits[27].The slope
the operation of the program is as follows: a rectangular S is mainly an inversefunction of temperature [28],
grid is set up over a desired portion of the device cross [29]:
section using doping profiles calculated previously from
a profile prediction model [24]. A subroutine assigns an
appropriate impurity concentration each to grid point. The
model can accommodate diffusedor implanted source and
drain regions as well as nonuniformly doped channel re- The slope canbe increased substantiallyonly by lowering
gions. Using Gummel’s algorithm[25], the program then the operating temperature T.Fig. 4 sh.ows the effect of
iteratively solves (1)-(6) under thefollowing assumptions: decreasing temperatures on the subthreshold transfer
complete ionization of impurity atoms in the semicon-
characteristic of a long channel device( L = 9 ym). From
ductor, Boltzmann statistics apply, and hole current and
room temperature to liquid nitrogen temperaturethe slope
generation-recombination currents are neglected. Because increases monotonically.Over this temperaturerange, for
the program simulatesonly static device characteristics, a decade of subthreshold drain current variation, the re-
freezeout inthe bulk does not affect the predicted results. quired gatevoltage change decreases from 80.0 to 21.5 mV,
All charges in the oxide (Nox< 5 X 1O1O cm-2) are reflected thus the resultant factor of slope improvementa t 77 K is
by the flatband voltage. Velocitysaturation is taken into
about 3.7.
account by using a simple,piecewise approximation to the
The cross marksgiven in Fig. 4 indicate some points of
velocity-field relationship for electrons reproducedFig. in the calculated device characteristics for 296, 200, and 77
3 from [26]. Avalanche breakdown, gate insulator break- K. These discrete points were obtained from the numerical,
down, and hot-electron injection into the gate dielectric, two-dimensional device simulations and are in excellent
however, are not included in the model. The computer agreement with the experimental curves. In calculating
program requires250 000 bytes of storage and takes about these points, the oxide charge and the :substrate doping
three minutesof CPU time on an IBMModel 91 computer
near the surfacewere determined from the experimental
for each calculationof drain current at given
a set of ap-
substrate sensitivity curve for small valuesof Vsx. Then
plied voltages. Because the carrier densities used by the the value of VFBused in the computer si.mulationwas de-
program are normalized by the intrinsic carrier concen-
termined by using (14b) below. Thus the fit obtainedin
tration, some difficulty was encountered with overflow Fig. 4 involves no adjustable parameters. The input pa-
errors during the low-temperature calculations. At low
rameters, such as junction depth and channel doping for
temperatures, themaximum applied voltageswhich could
these simulations, were derived from the! actual device
be investigated were constrained by these overflow errors
tested and from test structures on the same chip. The
and by convergence problems associated withthe extreme
substrate doping profile is modified by boron depletion
nonlinearity of the preceding equations. during field and gate oxide growth, and was determined
by spreading resistance measurements 1:21].The source/
IV. SUBTHRESHOLD
CONDUCTION drain diffusion depth xj was determined by angle lapping
One of the limitationsto miniaturization of MOSFET’s and staining. Increasesin the threshold voltage and carrier
by downward scaling is the slope of the subthreshold mobility at lower temperatures can be readily identified
transfer characteristic [22], [23] determined from a semi- in Fig. 4 andwill be discussed insubsequent sections.
222 IEEETRAKSACTIONS ON ELECTRONDEVICES,MARCH 1977

0.6

0.5
0'
o.6; SLOPE =-1.13mV/"K

0.4
V+V)

i
o.21
0.3

0.2
0.1I 1I

Ob 50 IO0 I50 2b0 2kO 360

T PK)
0.1
Fig. 6. Threshold voltage versus temperature for a long channel FET.

0
0
L(prn)
Fig. 5. Threshold voltage VT versus channel length L with temperature ni = 3.34 X 1019(T/300)3/2exp(-&/2kT) [~m-~]
as parameter.
(10)
and
V. THRESHOLD
VOLTAGE
For low drain voltages ( VOS = 0.1 V) the gate threshold
EG= 1.16 - 7.02 X 10-4T2/(T 1108) +
[eV]. (11)
voltage VTwaS obtained from the linear portion of the The thresholdvalues predicted by (8)-(11) are shown as
transfer characteristic. The threshold voltage is defined encircled dots on theright-handside of Fig. 5 . The
as the interceptof the extrapolated tangent through the threshold voltage increase at lower temperatures is mainly
point of inflection of the linear device characteristic minus due to anincrease in the band bending term$s which in
V ~ s / 2 .For high drain voltages (VOS = 4.0 V) the pr'e- turn is caused primarilyby the temperature dependence
viously determined thresholdvoltage was diminished hy of the intrinsic carrier concentration ni. The effective ac-
the measured shift inthe subthreshold characteristic due ceptorconcentrationusedintheone-dimensional
to short channel effects [23]. Under these definitions, the threshold equationwas derived from subgtrate sensitivity
threshold voltage dependence on temperature and on measurements. Carrier freezeout does nbt influence the
channel length is shown in Fig. 5 . For seven devices of ionized acceptor density within the depletion layer as
various channel lengthsthe thresholdvoltages are plotttd discussed below.
for temperaturesof 296,150, and 77 K and for drain volt- Fig. 6 shows the measured temperature dependence of
ages of 0.1 and 4.0 V. For channel lengths of less than a]?- the threshold voltage for a long device operating in the
proximately 2 pm, short channel effects become increas- linear region. The temperaturecoefficient of the threshold
ingly important asis apparent inFig. 5 . With decreasing voltage is -1.13 mV/K which is in good agreement with
channel length, a pronounced threshold dependence on values reported in the literature[30].
drain voltage is caused by merging of the depletion layers
surrounding source and drain.To first order,the threshold VI. CARRIERFREEZEOUT
voltage decrease due to short channel effects is not a At and above room temperature essentiallyall impuri-
function of the operating temperature, but rather is pre,- ties are thermally ionized becauseof their shallow energy
dominantly dependent on the device geometry and the levels. Thus for p-type silicon a t room temperature, the
electric field configuration. concentration of mobile holes in the bulk is very nearly
Over the range of temperatures studied the long channel equal to the concentration of shallow boron acceptors.As
threshold is very well described by the one-dimensional temperature decreases, the Fermi level approaches the
equation for polysilicon gate MOSFET's with n+-dopcd valence band and themobile carriers begin to "freeze out"
gate electrodes: on the acceptor impurities and a corresponding decrease
in the electrical conductivity of the bulk material is ob-
served.
The thermally generatedmobile hole concentrationp
and theposition of the Fermilevel relative to thevalence
band edge, EF - E", for boron-doped silicon may be de-
where termined from
2kT
= -In ( N ~ / n i ) [VI
4
GAENSSLEN et al.: VERYSMALL MOSFET's 223

IO

05
251 --MEASURED
CALCULATED
296 O K (Ne,
02
+ 77'K ( N A )
77 O K (N,
0 IO

.
*
z
a.
005
'Ot

002
v, (V)
Fig.9. Measured andcalculated low-frequency capacitance versus
voltage characteristics of the gate ca acitorof a MOSFET a t 77 and
296 K. Gate electrode area is 78.4 milB. Values calculated a t 77 K using
40 80 120 160 200 240 280
T (OK1 an assumed freezeout value of Na(F.0.) (+) do not agree with the
Fig. 7. Relative mobile hole concentration in the bulk pilVA versus measurements.
temperature with the acceptor concentrationN A as parameter.
The electric field within the depletion region sweeps out
any mobile holesand maintainscomplet,e ionization even
a t low temperatures. Approaching77 K, holes in the bulk
begin to freeze out, but there is essentially ]noeffect onthe
ionized impurity concentration in the depletion region. In
addition, mobile electrons injected into thesurface channel
from the degenerately doped source do notexperience any
significant freezeout effects as long tlhere
as is no sizable
donorconcentrationpresentinthedepletionregion.
Furthermore, the degenerately doped slource and drain
regions themselves will not experience freezeout to any
Y N~ = 1 0 ~ ~ ~ ~ - ~
serious degree [Ell].This means that the chargeconcen-
Fig. 8. Schematic energy band diagrams of the silicon substrate beneath tration to be used in ( 8 ) and (9) is the total acceptor im-
the gate electrode a t 296 and 77 K.
purity concentration NA.
Fig. 9 shows measurements and cal.culations of the
and "low-frequency" capacitance-voltage characteristic for the
NA gate capacitor of a MOSFET with a large gate electrode
P= (13) area of 78.4 mil2. In making thisMOS rneasurement the
1+4exp(-- 0.045eV EF - EV
source and drain were electrically connected to the sub-
kT kT strate to providemobilecarriers. The calculated and
where N v is the effective density of states in thevalence measured values of capacitance agreevery well a t both 77
band. Equations (12) and (13) assumean uncompensated and 296 K except for a slight discrepancy in the strong
nondegenerate silicon substrate witha single shallow ac- inversion region, which isrelated to the g,ateoverlap of the
ceptor level of degeneracy 4 located 0.045 eV above the source and drain regions. Also shown in Fig. 9 for com-
valence band edge. Fig. 7 shows the relative mobile hole parison is a calculated capacitance-voltage curve, delib-
concentration in the bulk ~ / N as A a function of tempera- erately generated using the freezeout valueN A(F.O.) as
ture. For thecase of 77 K and N A = 4 X 10l6~ m - ~~ /, N A the ionized acceptor concentrationin the depletion region,
= 0.09, i.e., about 91 percentof the potentially available which understandably does not agreewith the actual
carriers in the bulk are frozen out onto the boron acceptor measurements. Fig. 10 shows the substrate sensitivity
impurities. characteristic for the samelong channel length andlarge
The carrier freezeout situation at the semiconductor area F E T of Fig. 9, again a t room andl liquid nitrogen
surface under the gate electrode is different than that in temperatures. Using (8)-(11),good agreement between the
the bulk due to the band bending. Fig.8 schematically il- measured and calculated substrate sensitivity curves was
lustrates the energy band diagrams for room and liquid obtained. As also illustrated in Fig. 10, the improperuse
nitrogen temperatures. At room temperature, nearly all of NA(F.O.)in place of N A in ( 8 ) and (9) results ina cal-
of the shallow acceptors are thermally ionized in the bulk. culated substrate sensitivitya t 77 K which is clearly not
The acceptorsinthesurfacedepletion region areall in agreement with the measurements.
thermally ionized and remain ionized due to the band The 77 K-substrate sensitivity curve Fig. in 10 appears
bending that results from built-in and applied potentials.to be aparallel upward shiftof the room temperature curve
224 IEEE
OK TRANSACTIONS ELECTRON DEVICES, MARCH 1977

CALCULATED
2 .o

-
>
>+
I .o-
e

Fig. 10. Measured and calculated substrate sensitivity curves for a long
channel FET at 296 and 77 K. Values calculated at 77 K using an 21s-
sumed freezeout valuefor the substrate doping (+) do notagree with Fig. 11. Drain current ZDS versus Vc: - VT in the linear or below-
the measurements. pinchoff regime ( VIJS< VC- V T )for a long channel device (L= 9 pm)
with temperature as parameter. Right-hand scale lists surface mobility
values calculated a t a gate voltage of 0.5 V above threshold.
unchanged in shape.This is not exactly true as can be ob-
served at low substrate potentials. If (8) is rewritten asthe
usual normal form for a parabola one gets: and

From (17),
where

where p s is the surface mobility. The experimental data

of Fig. 11show the increase in transconductance from room
The shift coordinatesof the vertex are readily obtained to liquid nitrogen temperature for a long channel device
from (14a) and (14b). The vertical and horizontal shif'ts ( L = 9 pm). In order to eliminate the temperature depen-
are: dence of the device threshold, the drain current been has
Av, = V m ( T )4- #,(TI (15) plotted versus VG - VT. With a drain
voltage of 0.1 V, the
electric field isessentially uniform from source to drain and
and has a magnitudeof approximately 100 V/cm. Taking into
AVh = - A ( T ) (16) account the series resistance of the source and drain re-
gions, the transconductance was calculated fromthe IDS
respectively.
Since Avh also includes a temperature dependence,the versus VG relationship and the mobility deduced using
(18).On the right-hand side of Fig. 11are listed the surface
vertex as well as allthe other points on this curve are not
only shifted upward, butalso to theleft as the operating mobility values determined a t VG- VT = 0.5 V. As tem-
temperature is lowered. This explains why the low-tem- perature decreases from 296 to 77 K, the transconductance
and theassociated surface mobility increase by a factorof
perature curve in Fig. 10 is slightly flatter for low substrate
four.
potentials, yielding a somewhat reducedsubstrate sensi-
For relatively large drain voltages, i.e., for VDS> VG-
tivity, when compared to theroom temperature curve.
VT,the FEToperates in the square law or above-pinchoff
regime and
VII. DEVICETRANSCONDUCTANCE
The device transconductance g,, is proportional to the
carriermobilitynear the semiconductorsurface. T.9e
surface mobility inturn is a functionof the electric field, From (19),
the temperature, and the impurity concentration in t:ne
substrate beneath the gate insulator. As temperature de- gm -I dIDS
d VG vDS= Const.
coxto w
= keff __ - ( VG -
L to,
V T ) (20)
creases, the mobility and the transconductance increase
[9], another important benefitof low-temperature opera- where peff is the effective surface mobility. Fig. 12(a) shows
t.ion. the temperature dependenceof the transconductance for
For small drain voltages, i.e., for VDS< VG - V T ,the a short channel device ( L = 0.8 pm) with a large drain
FET operatesin the linear or below-pinchoff regime voltage of 4.0 V. In thechannel beneath the gate insulator,
GAENSSLEN et al.: VERY SMALL MOSFE'T's 225

Fig. 13. Diode reverse current IR versus bias VRof an nf-pjunction with
temperature as parameter.

The maximum operating voltage for lnicron sized de-

vices was determined tobe about 4V due to scaling con-
siderations [22], [23]. Relative to room temperature, the
actual circuit performance improvement obtainableat 77
K depends strongly upon the type of ci:rcuits used. The
improvement in circuit speedwill be between 4.0 and 1.7
because the switching device operates O V ~ Ithe
C whole range
from below to above pinchoff. If compal:ed to 85°C (i.e.,
358 K) operation, the improvement factor a t liquid ni-
trogen temperature would be even larger.
VIII. JUNCTION
BEHAVIORAT LOWTEMPERATURE
Since n+-p junctions are an integralplart of n-channel
MOSFET devices and circuits, changes in junction pa-
rameters due tolower operating temperatures mustalso
be considered. For an n+-p step junction with a p-type
substrate doping concentration of 4 X 10l6 ~ r n - ~the ,
junction breakdown voltage decreases by about 15 percent
in going from room to liquid nitrogen temperature as
(b) shown in Fig. 13. This change is primarily due to an in-
Fig. 12. (a) Drain current IDS versus VC - V r in the square law or crease in the electron mean free path [:32]and is small
above-pinchoff regime (VDS> VC - V r )for a short channel device
( L = 0.8 pm) with temperature as parameter.The right-hand scale lists enough that it can be neglected inview of the muchwider
calculated effective surface mobilityvalues calculated a t a gatevoltage tolerances in junction breakdown voltage .th,at are normally
of 0.5 V above threshold. (b) Surface mobility improvement factor
peff(T)/(pe&96 plotted versus Vc - V T with temperature as param- encountered. Operating voltages are usually maintained
eter. well belowthe junction breakdown voltage.
As is apparent from Fig. 13, the junction 1.eakagecurrent
a highly nonuniform electric field exists which has a peak undergoes a dramatic reduction as temperaturedecreases.
value near the drainof about IO5Vlcm as determined from The reduction is so extreme that an indirect method of
the two-dimensional simulation model. measurement must be used to determine the relative
Because the velocity of electrons is limited to a satura- leakage current change. The n+ sideof the junction was
tion value of about 8 X lo6 cmls [26] and because of the connected through a reed contact to avoltage source of 7.5
nonuniformity of the electric field,the carrier mobilityin V, as illustrated by the insertof Fig. 14. ,4fter the contact
the semiconductor beneath the gate insulatoris difficult was opened, the time decay of the potential across the
to define. Nevertheless, one can deducean effective surface junction was monitored by an FET sourcle fbllower circuit.
mobility using (19) and (20). Taking intoaccount,the series Resulting plots for three temperatures are shown in Fig.
resistances of the source and drain, the peffvalues were 14. Assuming the slope of the current a t t = 0 to be pro-
determined a t VG- VT = 0.5 V, and thevalues are listed portional to theleakage current, the reductionin leakage
on the right-hand side of Fig. 12(a). From296 to 77 K the current is.approximately 1000 times ingoing from room
increasein transconductanceandinrelated effective to liquid nitrogen temperature.The anti'cipated degreeof
surface mobility was a factorof 2.5. improvement for an ideal p-n junction is proportional to
Fig. 12(b) shows the surfacemobilityimprovement the change in the intrinsic carrier densityni, a change of
factor peff(T)/(peff)296 plotted versus VG- V T UP to 3.5 V about 30 orders of magnitude. In a practical situation,
with temperature as parameter. At 77 K, the improvement however, junction curvature, local defects, and otheref-
in effective surface mobilityand in the rela.ted transcon- fects greatly increase the leakage current over its ideal
ductance is 1.7 a t VG- VT = 3.5 V. value.
226 IEEE TRANSACTIOSS ON ELECTRON DEVICES. MARCH 1977

EG - (EF - Ev)where EG is the band-gap energy. The

shift in the voltage intercept with temperature AVi is
proportional to theshifts in the energy gap and Fermilevel
and is estimated tobe
qAvi AEG - A(EF - EV) I for 7 1 and 296 K
2 - -
l - - = (1.157 - 1.116) - (0.036 - 0.180) (21)
296 O K
0 " 1 1 1 " ' 1
0 100 200 300 400 500 600 700 800 900
= 0.185 [eV]
Vsecl
which is in good agreement with the experimentalvalue
Fig. 14. Time decay of reverse bias across an n+-pjunction at 77 K, 496
K, and an intermediate temperature. of 0.937 - 0.715 = 0.222 eV. These results simply verify
that thejunction capacitance behaves as expected a t liquid
nitrogen temperature.

Ix. ONE-MICROMETERDEVICE DESIGNFOR

OPERATION A T LIQUIDNITROGENTEMPERATURE
One of the objectives of this studywas to define a device
design for an n-channel, polysilicon gate, enhancement
mode MOSFET with a channel length of 1 pm that is
suitable for operationa t liquid nitrogen temperature. At
room temperature, a 1-pm design has been proposed[23]
that uses a boron channel implantationwith a lower doped
substrate tocombine a sufficiently high threshold voltage
with as low a substrate sensitivity aspossible [27]. Since
"-10 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 a t liquid nitrogen temperature the threshold voltage is
v, (VI increased by about 250 mV, the need for a channel im-
Fig. 15. Capacitance versus reverse bias characteristics of n+-p junctim plantation to raise the thresholdis less compelling. Cou-
a t 77 and 296 K.
pled with asteeper subthreshold slopea t liquid nitrogen
temperature this offers the possibility of using a design
The decay time foran MOS capacitor driven into deepwith a somewhat more highly, but uniformly doped sub-
depletion was also measured as a function of temperature, strate. Furthermore, in order tominimize short channel
and the results were similar to those obtained for junction effects, it was decided to use asubstrate potentialof zero
leakage. As temperature decreases, adramatic increase .in volts. The nominal thresholdvoltage forthis design then
the decay timeoccurs. The time constant to returnill-.to was chosen to be about 250 mV. Ofthis total, 175 mV are
version is of the orderof seconds a t 296 K, minutes a t 200 meant to provide for eight orders of magnitude of sub-
K, and hours a t 77 K. These results are encouraging for threshold drain current change (see (7)) as mightbe re-
dynamic memory circuits in which, a t present, abouthalf quired for the F E T switch of a dynamic one-device mem-
of the power dissipated goes into refreshing all of the ory cell. The remaining 75 mVserve as a safety margin for
memory cells every few milliseconds. short channel effects, processing tolerances, and noise
Fig. 15 shows the capacitanceC versus reverse bias'ti immunity. With a gate oxide thickness of 200 A this design
relationship of a large area n+-p junction diode a t 296 and requires a uniformly doped substrateof 1 X 1OI6~ m - ~ .
77 K plotted asC 2 and C-3 versus VR.At liquid nitrogen Fig. 16 shows the resultsof the two-dimensional simu-
temperature, the junction capacitanceis slightly smaller lations using a channel length of 1pm, channel width of 10
than its room temperature value due to changes in the pm, and diffusion depth of 0.2 pm for small and large drain
built-in voltage across the junction. For large reverse bias, voltages of 0.1 and 3.0 V, respectively. The amount of
the depletion region surrounding the n+region extends f l u threshold voltage degradation caused by short channel
into the p-type substrate. In this case the C-2 versus 'ti effects is an acceptable 30 mV, whichcan be determined
plot is linear and an ionized acceptor concentration of from the separationbetween the two curves shown in Fig.
approximately 4 X 10l6 is obtained a t both room ar d 16.
liquid nitrogen temperatures. Note that the ionized a#:- The pointof this exercise is to show that one can obtain
ceptor concentrationin the depletion region is not affecte'd a satisfactory1-pm device design for liquid nitrogen tem-
by the freezeout of mobile carriers which occurs in thebu:.k perature with the simplest possible configuration, i.e.,
of the semiconductor substrate. uniform substrate doping andzero substrate bias. When
At small valuesof VR,the diode acts as an n+ graded to a channel implantation, and/or substrate bias is used, one
p-type junction due to the tailof the acceptor impuri1.y can obtain reduced substrate sensitivityand lower junction
profile. The intercept a t zero capacitance of the versus capacitance at the expense of somewhat greater short
VRplot is proportional tovbi, the built-involtage; q vbi 5: channel effects [22], [23].
GAENSSLEN et Ul.: VERY SMALL MOSFET's 227

lot

-200 -150 -100 -50 0 !

T PC)
Fig. 18. Thermal conductivity of 0.5 0 . cm p-type silicon from [35].
VG ( V )

Fig. 16. Drain current versus gate voltage characteristic a t 77 K as h; deep [23]. Such shallow ion implanted junctions are
predicted by two-dimensional simulation for a device with a channel
length of 1 pm. desired for very high density FET's.Ai3 shown inFig. 17,
all three types of interconnection lines exhibitan advan-
TPK)
tageous decrease insheet resistance with decreasing tem-
60, I70 170 2yO 2:O 3r)O ,o,06 perature, but the degenerately doped s8iliconand polysil-
icon lines show a much less pronounced decrease, pre-
0.05 sumably due to strong impurity scattering [31]. The ex-
pected large decrease of about a factor OF six for the alu-
- 0.04 minumsheetresistancesuggests that higher currents
-P should occur in aluminum interconnection lines as the
-0.03 9 operating temperaturedecreases.
k Mass transport due to direct current, flow, i.e., electro-

20[
IO //+
+
- 0.02

- 0.01
migration, is a serious failure mechanism in metallic in-
terconnection lines for integrated circuits operating at and
above room temperature [7]. Electromigration is similar
to diffusion and may be described by an activation energy
0 - 0
equation of the form
-200 -150 -100 -50 0 50
TPC)

Fig. 17. Measured sheet resistance versus temperature for aluminum,

n+ polysilicon, and n+ion implanted (VI) lines with thicknesses of 1.0
ym, 0.35 ym, and 0.2 ym, respectively.
x. MATERIALSPROPERTIES AT LOW
TEMPERATURES
In addition to thepreviously described improvements
in FET performance and in p-n junction behavior, low-
temperature operation also offers improvements in ma-
terials properties that relate to signal transmission and
heat removal such as electrical conductivity, electromi-
gration, and thermal conductivity. Fig. 17 plots the ex-
perimental sheet resistanceof aluminum, polysilicon, and
n+ silicon interconnection lines as a functionof tempera-
ture. Aluminum lines 10 000 h; thick were deposited by
evaporation from a resistance heated source.Polysilicon
lines 3500 h; thick were chemically vapor deposited and
degenerately doped n-typefrom a deposited POC13 source.
The degenerately doped n+ silicon lines were fabricated
by ion implantinga 4 X 1015cm-2 dose of As75ions at 100
keV into thesilicon substrate toform a junction about2000
where J, is the flux of atoms along the wire, J the current
density, andAH the activation energy [33]. The addition
of copper to an aluminum film decreases the migration rate
of aluminum atoms, but does not change the activation
energy of the electromigration process [33]. Because of its
logarithmic decrease with decreasing temperature, elec-
tromigration is notexpected to be ti primaryfailure
mechanism at low temperatures, and t1hu.s one shouldbe
able to use pure aluminum lines. As the interconnection
line thickness is scaled down, however, dimensional con-
straints such asthe dc and anomalous skineffects must be
considered [6], [34].
Fig. 18 shows the experimental thermalconductivity of
-
' cm p-type silicon ( N A = 4 X 1OI6
0.5 d as given in
the literature [35]. A t liquid nitrogen temperature, the
thermal conductivity is, advantageously, aboutsix times
larger than atroom temperature. These data indicate that
much higherpower densities canbe tolerated in FET cir-
cuits at low temperatures providing thle heat can be re-
moved from the chip.
228 DEVICES, ELECTRON ON TRANSACTIONS IEEE MARCH 1977

An area of concern for low-temperature operation is associated with the vaporization of liquids (about 10 to 100
circuit failure due to thermal expansion. This concern irl W/cm2)when compared to thatof forced-air cooling (about
not so much directed towardthe silicon chips themselves, 1 W/cm2) [3]. Evaporation cooling offers the added ad-
but rather toward the relative thermal expansion differ I vantage of temperature stabilizationbecause liquid boiling
ences betweenthe processed silicon chip and the electrical occurs a t a constant temperature, but the peak nucleate
connections to and the physical supports for that chip. In boiling heat flux must notbe exceeded or a significant drop
our work, ultrasonic bonds were satisfactory for making in the heat removal rate will occur leading to thermal
electrical measurements and it was found that Epo-Teli runaway. Obviously, integrated circuits immersed directly
410 conductive epoxy provides a reliable joint between thc in a liquidcoolant might be subject to avariety of potential
chip and the header. A reliable chip packaging technique contamination problems.
is critical to low-temperature operation of integrated cir . If low-temperature operation is ever to become a com-
cuits. mercial reality for medium and large size digitalcomput-
The dielectric breakdown strengthof insulating films, ers, some form of closed-cycle refrigeration systemwill be
particularly silicon dioxide gate insulators, presents ye: required because, with the possible exception of liquid
another concern a t low temperatures. When biased a; nitrogen, cryogenic fluidsare too costly to be constantly
higher temperatures, the limiting time to breakdown 7ma:C expended inan open-pool cooling mode. Furthermore, the
of a 200 to 1000-A thick silicon dioxide film exhibits an inconvenience associated with continual liquid storage and
activation energy relationshipof the form replenishment make open-poolcooling commercially un-
attractive. On the other hand, in situations of refrigeration
maintenance or failure, cryogenic fluids do offer a unique
means for storing up refrigeration capacity until it is
where to, is the film thickness, E the electric field strength needed. Outside of the computer industry, considerable
in MV/cm, and the activation energy AH equals 0.4 e\r progress has been made inthe development of high-reli-
[36]. Presumably this equationis applicable tolow tern . ability closed-cycle refrigerators [39] for parametric am-
peratures as well. Equation (23) indicates that thedecrease plifiers in satellite receivingground stationsand for
in reliability for thinner insulating films can be cornpen.. cryopumps in vacuum evaporators. Suchexpansion engine
sated for by lower temperature operation assuming thal; refrigerators might eventually be adapted tocool digital
the electricfield strength across the insulatoris held con.. computers aswell.
stant.
In MOSFET’s used as signal amplifiers in physics ex-
periments [12]-[E], noise mechanisms are an important XII. CONCLUSIONS
consideration. The eventual application of the FET’s de-
scribed in this paper, however, is in digital switching cir- This work hasdemonstratedtheimprovements in
cuits, anddevice noisedoes not present a difficulty because MOSFET device characteristics attainable by operation
at thesignal levels usedthe limitation is internally gen- a t liquid nitrogen temperature. Bipolar transistors are
erated circuit noise ratherthan thermal noise. considered to be unusable a t such low temperatures as a
consequence of strongly reducedcurrent gain [l], [5], [40].
Liquid nitrogen is a convenient relatively inert coolant
XI. LOW-TEMPERATURE ENVIRONMENT
with a boiling point of 77.3 K near which temperature
In this study, FET’s were cooled by nitrogen gas in a manyphysical parameters experiencesignificantim-
Statham test chamber, or by direct immersion in anope;;l provements. Relative to room temperature, at liquid ni-
pool of liquid nitrogen. Liquid nitrogen is a convenient trogen temperature desirable improvements in FET device
coolant which is nontoxic, relatively noncorrosive, and has performance include: 4 times steeper device turn-on, 1.7
a boiling point of 77.3 K a t a pressure of 1atm. The va- to 4 times higher transconductance, and an increasing
porization of one liter of liquid nitrogen produces45 W s threshold voltage. These improvements allow a device
of cooling at 77.3 K. Coolants otherthan nitrogen are ab2 design for a 1-pm channel length FET with a 250-mV
of interest; for example: neon (27.1 K), argon (87.2 K:’, threshold,zero-substratebias,anduniformsubstrate
krypton (119.7 K), xenon (165.0 K), freon 22-CHC1F2 doping of 1 X 1OI6 cmV3 which exhibitsapredicted
(232.3 K), or freon 12-CClzF2 (242.6 K). threshold voltageshift of only 30 mV due to short channel
Recirculating freon or watercooling is presently used effects. Other advantages at 77 K include a decrease of
in large digital computers, although in these practical ex- 1000 times or more in junctionand inversion layer leakage
amples the semiconductor components are not in direct currents, 6 times higher silicon thermal conductivity, and
contact with the fluid but rather are indirectly cooled via 6 times lower aluminum line resistance. Reliability im-
conductive finsor plates. Severalauthors [3], [4], [37] h a w provements arealso expected becauseof the anticipated
considered the advantagesof direct immersion cooling of strong reduction in thermally activated wearout phe-
integrated circuits, and presently high power transmittin;g nomena at low temperatures. A combination of these
tubes are often cooled by evaporation of dielectric oil in ,I low-temperature advantagesmay be essential to maximize
sealed container [38]. The primary attraction of liquid the performance of very high density MOSFET digital
immersion cooling is the considerably greater heat flux integrated circuits.
GAENSSLEN etal.: VERY SMALL MOSFET’s
ACKNOWLEDGMENT
The authorswish to acknowledge the processing support
of the silicon technology group at the T. J. Watson Re- [22] R. H. Dennard, F. H. Gaensslen, L. Kuhn, a.nd.H. N. Yu, “Design
search Center, and helpful discussions with R. H.Dennard.
A careful reading of the manuscriptby F. Stern is grate-
fully appreciated.
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