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M29F200BB
2 Mbit (256Kb x8 or 128Kb x16, Boot Block)
Single Supply Flash Memory
PRELIMINARY DATA
A15 1 48 A16
A14 BYTE NC 1 44 RP
A13 VSS RB 2 43 W
A12 DQ15A–1 NC 3 42 A8
A11 DQ7 A7 4 41 A9
A10 DQ14 A6 5 40 A10
A9 DQ6 A5 6 39 A11
A8 DQ13 A4 7 38 A12
NC DQ5 A3 8 37 A13
NC DQ12 A2 9 36 A14
W DQ4 A1 10 35 A15
RP 12 37 VCC A0 11 M29F200BT 34 A16
M29F200BT
NC 13 M29F200BB 36 DQ11 E 12 M29F200BB 33 BYTE
NC DQ3 VSS 13 32 VSS
RB DQ10 G 14 31 DQ15A–1
NC DQ2 DQ0 15 30 DQ7
NC DQ9 DQ8 16 29 DQ14
A7 DQ1 DQ1 17 28 DQ6
A6 DQ8 DQ9 18 27 DQ13
A5 DQ0 DQ2 19 26 DQ5
A4 G DQ10 20 25 DQ12
A3 VSS DQ3 21 24 DQ4
A2 E DQ11 22 23 VCC
AI02914
A1 24 25 A0
AI02913
2/22
M29F200BT, M29F200BB
The blocks in the memory are asymmetrically ar- sent to the Command Interface of the internal state
ranged, see Tables 3A and 3B, Block Addresses. machine.
The first or last 64 Kbytes have been divided into Data Inputs/Outputs (DQ8-DQ14). The Data In-
four additional blocks. The 16 Kbyte Boot Block puts/Outputs output the data stored at the selected
can be used for small initialization code to start the address during a Bus Read operation when BYTE
microprocessor, the two 8 Kbyte Parameter is High, VIH. When BYTE is Low, VIL, these pins
Blocks can be used for parameter storage and the are not used and are high impedance. During Bus
remaining 32K is a small Main Block where the ap- Write operations the Command Register does not
plication may be stored. use these bits. When reading the Status Register
Chip Enable, Output Enable and Write Enable sig- these bits should be ignored.
nals control the bus operation of the memory. Data Input/Output or Address Input (DQ15A-1).
They allow simple connection to most micropro-
When BYTE is High, V IH, this pin behaves as a
cessors, often without additional logic.
Data Input/Output pin (as DQ8-DQ14). When
The memory is offered in TSOP48 (12 x 20mm) BYTE is Low, VIL, this pin behaves as an address
and SO44 packages. Access times of 45ns, 55ns, pin; DQ15A–1 Low will select the LSB of the Word
70ns and 90ns are available. The memory is sup- on the other addresses, DQ15A–1 High will select
plied with all the bits erased (set to ’1’). the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
SIGNAL DESCRIPTIONS BYTE is High and references to the Address In-
See Figure 1, Logic Diagram, and Table 1, Signal puts to include this pin when BYTE is Low except
Names, for a brief overview of the signals connect- when stated explicitly otherwise.
ed to this device. Chip Enable (E). The Chip Enable, E, activates
Address Inputs (A0-A16). The Address Inputs the memory, allowing Bus Read and Bus Write op-
select the cells in the memory array to access dur- erations to be performed. When Chip Enable is
ing Bus Read operations. During Bus Write opera- High, VIH, all other pins are ignored.
tions they control the commands sent to the Output Enable (G). The Output Enable, G, con-
Command Interface of the internal state machine. trols the Bus Read operation of the memory.
Data Inputs/Outputs (DQ0-DQ7). The Data In- Write Enable (W). The Write Enable, W, controls
puts/Outputs output the data stored at the selected the Bus Write operation of the memory’s Com-
address during a Bus Read operation. During Bus mand Interface.
Write operations they represent the commands
3/22
M29F200BT, M29F200BB
Table 3A. M29F200BT Block Addresses Table 3B. M29F200BB Block Addresses
Size Address Range Address Range Size Address Range Address Range
(Kbytes) (x8) (x16) (Kbytes) (x8) (x16)
16 3C000h-3FFFFh 1E000h-1FFFFh 64 30000h-3FFFFh 18000h-1FFFFh
8 3A000h-3BFFFh 1D000h-1DFFFh 64 20000h-2FFFFh 10000h-17FFFh
8 38000h-39FFFh 1C000h-1CFFFh 64 10000h-1FFFFh 08000h-0FFFFh
32 30000h-37FFFh 18000h-1BFFFh 32 08000h-0FFFFh 04000h-07FFFh
64 20000h-2FFFFh 10000h-17FFFh 8 06000h-07FFFh 03000h-03FFFh
64 10000h-1FFFFh 08000h-0FFFFh 8 04000h-05FFFh 02000h-02FFFh
64 00000h-0FFFFh 00000h-07FFFh 16 00000h-03FFFh 00000h-01FFFh
Reset/Block Temporary Unprotect (RP). The Re- Read/Reset commands or Hardware Resets until
set/Block Temporary Unprotect pin can be used to the memory is ready to enter Read mode.
apply a Hardware Reset to the memory or to tem- The use of an open-drain output allows the Ready/
porarily unprotect all Blocks that have been pro- Busy pins from several memories to be connected
tected. to a single pull-up resistor. A Low will then indicate
A Hardware Reset is achieved by holding Reset/ that one, or more, of the memories is busy.
Block Temporary Unprotect Low, VIL, for at least Byte/Word Organization Select (BYTE). The Byte/
tPLPX. After Reset/Block temporary unprotect goes Word Organization Select pin is used to switch be-
High, VIH, the memory will be ready for Bus Read tween the 8-bit and 16-bit Bus modes of the mem-
and Bus Write operations after tPHEL or tRHEL, ory. When Byte/Word Organization Select is Low,
whichever occurs last. See the Ready/Busy Out- VIL, the memory is in 8-bit mode, when it is High,
put section, Table 14 and Figure 10, Reset/Tem- VIH, the memory is in 16-bit mode.
porary Unprotect AC Characteristics for more
details. VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Pro-
Holding RP at V ID will temporarily unprotect the gram, Erase etc.).
protected Blocks in the memory. Program and
The Command Interface is disabled when the VCC
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
tPHPHH.
cidentally damaging the data during power up,
Ready/Busy Output (RB). The Ready/Busy pin power down and power surges. If the Program/
is an open-drain output that can be used to identify Erase Controller is programming or erasing during
when the memory array can be read. Ready/Busy this time then the operation aborts and the memo-
is high-impedance during Read mode, Auto Select ry contents being altered will be invalid.
mode and Erase Suspend mode.
A 0.1µF capacitor should be connected between
After a Hardware Reset, Bus Read and Bus Write the VCC Supply Voltage pin and the VSS Ground
operations cannot begin until Ready/Busy be- pin to decouple the current surges from the power
comes high-impedance. See Table 14 and Figure supply. The PCB track widths must be sufficient to
10, Reset/Temporary Unprotect AC Characteris- carry the currents required during program and
tics. erase operations, I CC4.
During Program or Erase operations Ready/Busy Vss Ground. The VSS Ground is the reference
is Low, VOL. Ready/Busy will remain Low during for all voltage measurements.
4/22
M29F200BT, M29F200BB
Bus Write VIL VIH VIL Command Address Hi-Z Data Input
Standby V IH X X X Hi-Z
5/22
M29F200BT, M29F200BB
6/22
M29F200BT, M29F200BB
Length
Command 1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1 X F0
Read/Reset
3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
2 X A0 PA PD
Program
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
7/22
M29F200BT, M29F200BB
The Block Protection Status of each block can be Note that the Program command cannot change a
read using a Bus Read operation with A0 = VIL, bit set at ’0’ back to ’1’ and attempting to do so will
A1 = VIH, and A12-A16 specifying the address of cause an error. One of the Erase Commands must
the block. The other address bits may be set to ei- be used to set all the bits in a block or in the whole
ther VIL or VIH. If the addressed block is protect- memory from ’0’ to ’1’.
ed then 01h is output on Data Inputs/Outputs Unlock Bypass Command. The Unlock Bypass
DQ0-DQ7, otherwise 00h is output. command is used in conjunction with the Unlock
Program Command. The Program command Bypass Program command to program the memo-
can be used to program a value to one address in ry. When the access time to the device is long (as
the memory array at a time. The command re- with some EPROM programmers) considerable
quires four Bus Write operations, the final write op- time saving can be made by using these com-
eration latches the address and data in the internal mands. Three Bus Write operations are required
state machine and starts the Program/Erase Con- to issue the Unlock Bypass command.
troller. Once the Unlock Bypass command has been is-
If the address falls in a protected block then the sued the memory will only accept the Unlock By-
Program command is ignored, the data remains pass Program command and the Unlock Bypass
unchanged. The Status Register is never read and Reset command. The memory can be read as if in
no error condition is given. Read mode.
During the program operation the memory will ig- Unlock Bypass Program Command. The Un-
nore all commands. It is not possible to issue any lock Bypass Program command can be used to
command to abort or pause the operation. Typical program one address in memory at a time. The
program times are given in Table 6. Bus Read op- command requires two Bus Write operations, the
erations during the program operation will output final write operation latches the address and data
the Status Register on the Data Inputs/Outputs. in the internal state machine and starts the Pro-
See the section on the Status Register for more gram/Erase Controller.
details. The Program operation using the Unlock Bypass
After the program operation has completed the Program command behaves identically to the Pro-
memory will return to the Read mode, unless an gram operation using the Program command. A
error has occurred. When an error occurs the protected block cannot be programmed; the oper-
memory will continue to output the Status Regis- ation cannot be aborted and the Status Register is
ter. A Read/Reset command must be issued to re- read. Errors must be reset using the Read/Reset
set the error condition and return to Read mode. command, which leaves the device in Unlock By-
pass Mode. See the Program command for details
on the behavior.
8/22
M29F200BT, M29F200BB
Unlock Bypass Reset Command. The Unlock erased. If all of the selected blocks are protected
Bypass Reset command can be used to return to the Block Erase operation appears to start but will
Read/Reset mode from Unlock Bypass Mode. terminate within about 100µs, leaving the data un-
Two Bus Write operations are required to issue the changed. No error condition is given when protect-
Unlock Bypass Reset command. ed blocks are ignored.
Chip Erase Command. The Chip Erase com- During the Block Erase operation the memory will
mand can be used to erase the entire chip. Six Bus ignore all commands except the Erase Suspend
Write operations are required to issue the Chip and Read/Reset commands. Typical block erase
Erase Command and start the Program/Erase times are given in Table 6. All Bus Read opera-
Controller. tions during the Block Erase operation will output
If any blocks are protected then these are ignored the Status Register on the Data Inputs/Outputs.
and all the other blocks are erased. If all of the See the section on the Status Register for more
blocks are protected the Chip Erase operation ap- details.
pears to start but will terminate within about 100µs, After the Block Erase operation has completed the
leaving the data unchanged. No error condition is memory will return to the Read Mode, unless an
given when protected blocks are ignored. error has occurred. When an error occurs the
During the erase operation the memory will ignore memory will continue to output the Status Regis-
all commands. It is not possible to issue any com- ter. A Read/Reset command must be issued to re-
mand to abort the operation. Typical chip erase set the error condition and return to Read mode.
times are given in Table 6. All Bus Read opera- The Block Erase Command sets all of the bits in
tions during the Chip Erase operation will output the unprotected selected blocks to ’1’. All previous
the Status Register on the Data Inputs/Outputs. data in the selected blocks is lost.
See the section on the Status Register for more Erase Suspend Command. The Erase Suspend
details. Command may be used to temporarily suspend a
After the Chip Erase operation has completed the Block Erase operation and return the memory to
memory will return to the Read Mode, unless an Read mode. The command requires one Bus
error has occurred. When an error occurs the Write operation.
memory will continue to output the Status Regis- The Program/Erase Controller will suspend within
ter. A Read/Reset command must be issued to re- 15µs of the Erase Suspend Command being is-
set the error condition and return to Read Mode. sued. Once the Program/Erase Controller has
The Chip Erase Command sets all of the bits in un- stopped the memory will be set to Read mode and
protected blocks of the memory to ’1’. All previous the Erase will be suspended. If the Erase Suspend
data is lost. command is issued during the period when the
Block Erase Command. The Block Erase com- memory is waiting for an additional block (before
mand can be used to erase a list of one or more the Program/Erase Controller starts) then the
blocks. Six Bus Write operations are required to Erase is suspended immediately and will start im-
select the first block in the list. Each additional mediately when the Erase Resume Command is
block in the list can be selected by repeating the issued. It will not be possible to select any further
sixth Bus Write operation using the address of the blocks for erasure after the Erase Resume.
additional block. The Block Erase operation starts During Erase Suspend it is possible to Read and
the Program/Erase Controller about 50µs after the Program cells in blocks that are not being erased;
last Bus Write operation. Once the Program/Erase both Read and Program operations behave as
Controller starts it is not possible to select any normal on these blocks. Reading from blocks that
more blocks. Each additional block must therefore are being erased will output the Status Register. It
be selected within 50µs of the last block. The 50µs is also possible to enter the Auto Select mode: the
timer restarts when an additional block is selected. memory will behave as in the Auto Select mode on
The Status Register can be read after the sixth all blocks until a Read/Reset command returns the
Bus Write operation. See the Status Register for memory to Erase Suspend mode.
details on how to identify if the Program/Erase Erase Resume Command. The Erase Resume
Controller has started the Block Erase operation. command must be used to restart the Program/
If any selected blocks are protected then these are Erase Controller from Erase Suspend. An erase
ignored and all the other selected blocks are can be suspended and resumed more than once.
9/22
M29F200BT, M29F200BB
10/22
M29F200BT, M29F200BB
START START
NO NO DQ5
DQ5
=1 =1
YES YES
NO YES
AI01369 AI01370
Erase Timer Bit (DQ3). The Erase Timer Bit can within the blocks being erased. Once the operation
be used to identify the start of Program/Erase completes the memory returns to Read mode.
Controller operation during a Block Erase com- During Erase Suspend the Alternative Toggle Bit
mand. Once the Program/Erase Controller starts changes from ’0’ to ’1’ to ’0’, etc. with successive
erasing the Erase Timer Bit is set to ’1’. Before the Bus Read operations from addresses within the
Program/Erase Controller starts the Erase Timer blocks being erased. Bus Read operations to ad-
Bit is set to ’0’ and additional blocks to be erased dresses within blocks not being erased will output
may be written to the Command Interface. The the memory cell data as if in Read mode.
Erase Timer Bit is output on DQ3 when the Status
After an Erase operation that causes the Error Bit
Register is read.
to be set the Alternative Toggle Bit can be used to
Alternative Toggle Bit (DQ2). The Alternative identify which block or blocks have caused the er-
Toggle Bit can be used to monitor the Program/ ror. The Alternative Toggle Bit changes from ’0’ to
Erase controller during Erase operations. The Al- ’1’ to ’0’, etc. with successive Bus Read Opera-
ternative Toggle Bit is output on DQ2 when the tions from addresses within blocks that have not
Status Register is read. erased correctly. The Alternative Toggle Bit does
During Chip Erase and Block Erase operations the not change if the addressed block has erased cor-
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with rectly.
successive Bus Read operations from addresses
11/22
M29F200BT, M29F200BB
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2.0V
1.3V
High Speed
1N914
3V
1.5V
0V 3.3kΩ
DEVICE
Standard UNDER OUT
TEST
2.4V CL = 30pF or 100pF
2.0V
0.8V
0.45V
AI01275B
Table 9. Capacitance
(TA = 25 °C, f = 1 MHz)
Symbol Parameter Test Condition Min Max Unit
C IN Input Capacitance V IN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 12 pF
Note: Sampled only, not 100% tested.
12/22
M29F200BT, M29F200BB
E = VCC ± 0.2V,
ICC3 Supply Current (Standby) CMOS
RP = VCC ± 0.2V
30 100 µA
Program/Erase
ICC4 (1) Supply Current (Program/Erase)
Controller active
20 mA
13/22
M29F200BT, M29F200BB
E = VIL,
tAVQV tACC Address Valid to Output Valid Max 45 55 70 ns
G = VIL
tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 15 18 20 ns
tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 15 18 20 ns
tELBL tELFL
Chip Enable to BYTE Low or High Max 5 5 5 ns
tELBH tELFH
tAVAV
A0-A16/
VALID
A–1
tAVQV tAXQX
tELQV tEHQX
tELQX tEHQZ
tGLQX tGHQX
tGLQV tGHQZ
DQ0-DQ7/
VALID
DQ8-DQ15
tBHQV
BYTE
14/22
M29F200BT, M29F200BB
tAVAV
A0-A16/
VALID
A–1
tWLAX
tAVWL tWHEH
tELWL tWHGL
tGHWL tWLWH
tWHWL
tDVWH tWHDX
DQ0-DQ7/
VALID
DQ8-DQ15
VCC
tVCHEL
RB
tWHRL AI01991
15/22
M29F200BT, M29F200BB
tAVAV
A0-A16/
VALID
A–1
tELAX
tAVEL tEHWH
tWLEL tEHGL
tGHEL tELEH
tEHEL
tDVEH tEHDX
DQ0-DQ7/
VALID
DQ8-DQ15
VCC
tVCHWL
RB
tEHRL AI01992
16/22
M29F200BT, M29F200BB
tPHWL (1)
RP High to Write Enable Low, Chip Enable
tPHEL tRH Min 50 50 50 ns
Low, Output Enable Low
(1)
tPHGL
tRHWL (1)
RB High to Write Enable Low, Chip Enable
tRHEL (1) tRB Min 0 0 0 ns
Low, Output Enable Low
(1)
tRHGL
tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 500 ns
Note: 1. Sampled only, not 100% tested.
W, E, G
RB
tPLPX
RP
tPHPHH
tPLYH
AI02931
17/22
M29F200BT, M29F200BB
Example: M29F200BB 55 N 1 T
Device Type
M29
Operating Voltage
F = VCC = 5V ± 10%
Device Function
200B = 2 Mbit (256Kb x8 or 128Kb x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
45 = 45 ns
55 = 55 ns
70 = 70 ns
90 = 90 ns
Package
N = TSOP48: 12 x 20 mm
M = SO44
Temperature Range
1 = 0 to 70 °C
3 = –40 to 125 °C
6 = –40 to 85 °C
Optio n
T = Tape & Reel Packing
Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed
parts, otherwise devices are shipped from the factory with the memory content erased (to FFFFh).
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
18/22
M29F200BT, M29F200BB
19/22
M29F200BT, M29F200BB
Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.05 0.15 0.002 0.006
A2 0.95 1.05 0.037 0.041
B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728
E 11.90 12.10 0.469 0.476
e 0.50 – – 0.020 – –
L 0.50 0.70 0.020 0.028
α 0° 5° 0° 5°
N 48 48
CP 0.10 0.004
Figure 11. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
A2
1 N
e
B
N/2
D1 A
D CP
DIE
TSOP-a A1 α L
Drawing is not to scale.
20/22
M29F200BT, M29F200BB
Table 18. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max
e 1.27 – – 0.050 – –
H 15.90 16.10 0.626 0.634
L 0.80 – – 0.031 – –
α 3° – – 3° – –
N 44 44
CP 0.10 0.004
Figure 12. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A2 A
C
B
e CP
E H
1
A1 α L
SO-b
21/22
M29F200BT, M29F200BB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics.
22/22