CS8351-DPSD / UNIT-IV

UNIT IV- ASYNCHRONOUS SEQUENTIAL LOGIC

Analysis and Design of Asynchronous Sequential
Circuits – Reduction of State and Flow Tables – Race-free
State Assignment – Hazards

INTRODUCTION

✔ In synchronous sequential circuits, memory elements are

clocked flip flops.
✔ In asynchronous sequential circuits, the memory elements
are unclocked flip flops (Latches) or time delay elements.

Why Asynchronous circuits??

● Used when speed of operation is important, as it

respond quickly without waiting for a clock pulse
● Used in small independent systems as only a few
components are required
● Used when the input signals may change independently of internal clock
● Used in the communication between two unitsthat have their own independent clocks

From the block diagram, the asynchronus circuits consists of:

1. Inputs / Outputs
2. Delay elements:
a. Only a short term memory
Block diagram of Asynchronous sequential circuits
b. May not really exist due tooriginal gate delay
3. Secondary variable:
a. Current state (small y)
4. Excitation variable:
a. Next state (big Y)
b. Have some delay inresponse to input changes

Types of Asynchrounous sequential circuits:

There are two types of sequential circuits:
1. Fundamental mode asynchronous sequential circuits.
2. Pulse mode asynchronous sequential circuits.

Fundamental Mode:

In a fundamental mode, only one input is allowed to change at a time and the
inputs are considered to be levels, (0 or 1).

Pulse mode:

In the pulse mode, only one input is allowed to change at a time and the inputs are considered to pulse (false-true-false)
and the input pulses must be long enough to initiate a state change.

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Difference between Synchronous and Asynchronous sequential circuits:

S.No Synchronous sequential circuits Asynchronous sequential circuits

1. It does not use clcok pulses. The change of

The change of internal state occurs in response to
internal state occurs when there is a change in
the synchronized clock pulses.
the input variables.

2. The memory elements are either unclocked flip

The memory elements are clocked flip-flops
flops are time delay elements.

3. Easier to design More difficult to design.

4. Since it does not uses clock, the state of the

Here,the timing problems are eliminated by
system is allowed to change immediately after
triggering all flip-flops with the pulse edge.
the input cahnges.

Other terms and definitions used in Asynchronous circuit:

Transition Table:

1. A state table with binary assignment is called transition table.

2. It is similar to the state table used for synchronous sequential circuits.
3. It specifies the next state of the flip flop as a function of present state and inputs.

Flow Table:

1. A flow table is similar to transition table (State table) except that the internal states are symbolized with letter
symbols rather than binary numbers.
2. This includes the output values of the circuit for each state table.

Primitive flow table:

1. This is a special case of flow table.

2. It is defined as a flow table which has exactly one stable state for each row in the table.

ANALYSIS OF FUNDAMENTAL MODE ASYNCHRONOUS SEQUENTIAL CIRCUITS:

Analysis Procedure:

1. Determine all feedback loops in the circuit.

2. Designate the output of each feedback loop with variable Y1 and its corresponding inputs y1, y2,..yk wher k is the
number of feedback loops in the circuit.
3. Derive the boolean function of all Y’s as a function of the external inputs and the y’s.
4. Plot each Y function in a map, using ‘y’ variables for the rows and external inputs for the columns.
5. Combine all the maps into one table showing Y=Y1¸ Y2, inside each square.
6. Circle all stable states where Y=y. The resulting map is then the transition table.

Problem:

1. Derive the transition table and primitive flow table for the fundamental mode asnchronous sequential circuit shown in
fig :

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2. D

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ANALYSIS OF PULSE MODE ASYNCHRONOUS SEQUENTIAL CIRCUITS:(Circuit with Latches)

1. Pule mode circuits rely on input pulses rather than levels. They allow only one input variable to change at a
time.
2. This can be implemented by employing a basic flip-flop commonly referred to as an SR latch.

Operation of SR Latch with NOR gate

The SR latch is a digital circuit with two inputs S and R and two cross coupled NORgates or two cross coupled
NAND gates as shown in fig.

In order to analyze the cricuit by transition table method, redrawing the above circuit,

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Transition table: From the transition table, writing truth table ,

S R Q Q’

1 0 1 0

0 0 1 0

0 1 0 1

0 0 0 1

1 1 0 0

From the truth table we can understand that, With SR=10, the output Y=Q=1 and the latch is said to be
in set state. Changing S to 0 leaves the circuit in the set state.With SR=01, the output Y=Q=0, and latch is said
to be reset. A change of R back to 0 leaves the circuit in the reset sate. The circuit exhibits some difficulty when
both S and R are qual to 1. In normal operation, S and R inputs are not applied ‘1’ simultaneously. This
candition can be expressed by the boolean function SR=0, which the state ANDing of S and R must always
result in a 0.

When we OR the boolean expression SR’with SR, the result is S.

From this, we deduce SR’=S when SR=0. Therefore the excitiation function
or boolean function can be expressed as,

Operation of SR Latch with NAND gate

S R Q Q’

1 0 0 1
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1 1 0 1

0 1 1 0

1 1 1 0

0 0 1 1

Note:

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Race Conditions

Race condition:
● two or morebinary state variables will change value when one input variable changes
● Cannot predict state sequence if unequal delay is encountered
Non-critical race:
● The final stable state does not depend on the change order ofstate variables

Critical race:
● The change order of state variables will result in different stable states
● Should be avoided!!

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Race-Free State Assignment
- Race can be avoided by properstate assignment:
� Direct the circuit throughintermediate unstable states witha unique state-variable change
�It is said to have a cycle
-Must ensure that a cycle willterminate with a stable state. Otherwise, the circuit willkeepgoing in unstable
states

Stability Check:
● Asynchronous sequential circuits may oscillate between unstable states due to the feedback
● It is Must to check for stability, to ensure proper operations
● The stability can be easily checked from the transition table
● If any column has no stable states, then it is unstable

Ex: when x1x2=11 in Fig. (b), Y and y are never the same

Y = x’1x2 + x2y’

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Hazards:

[Hazard is an unwanted transient i.e., spike or glitch that occurs due to unequal path or unequal propagation
delays through a combinational circuit.]

● Hazards are unwanted switching transients that may appear at the output of a circuit because different paths
exhibit different propagation delays.
● Hazards occur in combinational circuits, where they may cause a temporary false-output value.
● When this condition occurs in asynchronous sequential circuits, it may result in a transition to a wrong stable
state.
● A glitch is an unwanted pulse at the output of a combinational logic circuit. A circuit with the possible for a
glitch is said to have a hazard

Types of Hazards:
1. Static Hazard:i).Static-1 hazard & ii).Static-0 hazard
2. Dynamic Hazard
3. Essential hazard

Static Hazard:
Incorrect output due to change in a single input variable, when the output is expected to remain in the same
state.
Two types of static hazard are: (i) Static-0 hazard (ii) Static-1 hazard
● Static-0 hazard: When the output is to remain at the value 0, the output momentarily changes to 1 before
settling on 0 is known as static-0 hazard.
[When the output may momentarily (temporarily) go to 1 when it should remain 0. This is
referred to as a static 0-hazard]

● Static-1 hazard: When the output is to remain at the value 1, the output momentarily changes to 0 before
settling on 1 is known as static-1 hazard.

[When the output may momentarily (temporarily) go to 0 when it should remain 1. This is
referred to as a static 1-hazard]

1 Momentary 1 output 1 time

1
0 time0 Momentary ‘0’ output
Static -0 hazard 0
Static -1 hazard

Dynamic Hazard:

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1. Dynamic hazards occur when the output of a network is to change between its two logic states, but a
momentary false output signal occurs during the transient behavior.
2. Dynamic hazards often occur in larger logic circuits where there are different routes to the output (from
the input).
3. Dynamic hazards are more complex to resolve, but note that if all static hazards have been eliminated
from a circuit, then dynamic hazards cannot occur.

1 Momentary 1 output
1 time
1
0
0 time 0
Dynamic hazard Momentary ‘0’ output

Essential Hazard:
1. Essentialhazard is a type ofhazard that exists only in asynchronous sequential circuits with two
or more feedbacks.
2. An essential hazard is caused by unequal delays along two or more paths that originate from the same
input.

Cycle: A cycle occurs when an asynchronous machine makes a transition througha series of
unstable states. A cycle may exist that eventually reaches a stable state.

Static Hazard Elimination:

Example:Design a logic hazard-free circuit to implement the following function:F(ABC)=∑m(0,1,2,6)

Example : Design a logic hazard-free circuit to implement the following function:

F(A, B, C, D) = ∑m(0, 2, 4, 5, 6, 7, 8, 10, 11, 15)

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Solution: Fig. (a) shows the K-map with minimum covering of 1's of the function. The adjacent’1’s at minterm
locations (0, 4), (2, 6), (7, 15) and (10, 11)are not covered in the same sub-cube.Adding product terms to cover
these adjacent ‘1’ s results in a logic hazard-free function asshownin Fig. (b).

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Example:

Implement the switching function f(x1, x2, x3)= x1x2+ x 2 x3by a static hazard free 2 AND-OR gate network.

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