PIC32MX Oscillator Configuration

Click on highlighted cell

tuningValue = +\- 12.5% select settings per drop
FRC
Tune

divisorFRC = OSC_FRC_DIV_2
Internal FRC 8 MHz
Fast RC Oscillator Divider FRCDIV = 4 MHz
Oscillator 8 MHz
÷ 16 FRCDIV16 = 0.5 MHz

Enter external clock COSC = FRCPLL FPLLIDIV = DIV_3

or crystal frequency
PLL Input PLL Input
Selection Divider
8

External Clock Freq = 24 MHz System PLL

External Crystal Freq = 8 MHz

OSC1/ 8 MHz
POSC
CLKI
External
Primany POSC POSC
8
Oscillator Enable
Oscillator FRC
OSC2/ POSCMOD = XT
CLKO
POSC Divider
CLK Out 8
PBCLK
Enable
OSCIOFNC = ON UPLLIDIV=

XTPLL, HSPLL,
ECPLL, FRCPLL
Low Power LPRC 31.25 KHz
RC POSC
Oscillator LPRC
Oscillator 32 KHz
FRC
External Crystal Freq = 32.77 KHz 32.768 KHz
SOSC FRC/16
 SOSC FRC/16
SOSCI
External SOSC FRCDIV
Secondary SOSC
Oscillator Enable
Oscillator LPRC
FSOSCEN = ON
SOSCO
SOSC

Device configuration settings per

highlighted selections above
(configured at program time) FRC
// Device Config Bits in DEVCFG1:
System PLL Out
#pragma config FNOSC = FRCPLL
#pragma config FSOSCEN = ON
POSC
#pragma config POSCMOD = XT
#pragma config OSCIOFNC = ON
USB PLL Out
#pragma config FPBDIV = DIV_2
LPRC
// Device Config Bits in DEVCFG2:
#pragma config FPLLIDIV = DIV_3
SOSC
#pragma config FPLLMUL = MUL_20
#pragma config FPLLODIV = DIV_2
PBCLK
#pragma config UPLLIDIV = DIV_3
#pragma config UPLLEN = ON
SYSCLK

REFCLKI

Enter external
clock frequency

Device configuration bit options:

Bit Name Setting Options

POSCMOD = EC 0 0
XT 1 8
HS 0 0
OFF 0 0
8
FPLLIDIV = DIV_1 0
DIV_2 0
DIV_3 3
DIV_4 0
DIV_5 0
DIV_6 0
DIV_10 0
DIV_12 0
3

FPLLMUL =
MUL_15 0
MUL_16 0
MUL_17 0
MUL_18 0
MUL_19 0
MUL_20 20
MUL_21 0
MUL_24 0
20

FPLLODIV = DIV_1 0
DIV_2 2
DIV_4 0
DIV_8 0
DIV_16 0
DIV_32 0
DIV_64 0
DIV_256 0
2

FNOSC = FRC 8 0
FRCPLL 26.66667 26.666667
PRI 8 0
PRIPLL 26.66667 0
SOSC 0.032768 0
LPRC 0.031250 0
FRCDIV16 0.5 0
FRCDIV 4 0
26.666667

UPLLIDIV =DIV_1 0
DIV_2 0
DIV_3 3
DIV_4 0
DIV_5 0
DIV_6 0
 DIV_10 0
DIV_12 0
3

UPLLEN = ON
OFF

FSOSCEN = ON
OFF

OSCIOFNC = ON
OFF

FPBDIV = DIV_1 0
DIV_2 2
DIV_4 0
DIV_8 0
2
Cell formatting logic to find invalid input (false = no problem):
cell #:
E31 1 Is OSC2 needed for crystal input (can't be used as clock out)?

R49 0 Is PLL output or SYSCLK >100?

M33 0 Is USB PLL input > 4?

M33 1 Is USB PLL input < 4?
 M33 1 Is there a problem?

M20 1 Is PLL input <4?

M20 0 Is PLL input >5?
M20 1 Is PLL enabled (1 = enabled)?
M20 1 Is there a problem?

E23 0 1 0 POSCMOD = XT? Is external osc < 4?

E23 0 1 0 POSCMOD = XT? Is external osc > 10?
E23 1 0 0 POSCMOD = HS? Is external osc < 10?
E23 0 0 0 POSCMOD = HS? Is external osc > 25?
E23 0 Is there a problem?

E22 0 Is external clock >40 MHz?

E46 0 Is SOSC < 32KHz?

E46 0 Is SOSC > 100KHz?
E46 0 Is tthere a problem?

Oscillator specs per MX1XX/2XX data sheet:

Param. # Symbol Minimum Maximum Units Conditions

OS10 FOSC 0 40 MHz EC

OS10 4 40 ECPLL
OS11 3 10 XT
OS12 4 10 XTPLL
OS13 10 25 HS/HSPLL
OS15 FOSC 32 100 KHz Sosc

OS50 FIN 4 5 MHz ECPLL, HSPLL, FRCPLL mod

Oscillator specs per MX3XX/4XX data sheet:

Param. # Symbol Minimum Maximum Units Conditions

OS10 FOSC 0 50 MHz EC

OS10 4 50 ECPLL
OS11 3 10 XT
OS12 4 10 XTPLL
OS13 10 25 HS/HSPLL
OS15 FOSC 32 100 KHz Sosc

OS50 FIN 4 5 MHz ECPLL, HSPLL, FRCPLL mod

Oscillator specs per MX330/350/370/430/450/470 data sheet:
Param. # Symbol Minimum Maximum Units Conditions

OS10 FOSC 0 100 MHz EC

OS10 FOSC 0 80 MHz EC
OS10 4 100 ECPLL
OS10 4 80 ECPLL
OS11 3 10 XT
OS12 4 10 XTPLL
OS13 10 25 HS/HSPLL
OS15 FOSC 32 100 KHz Sosc

OS50 FIN 4 5 MHz ECPLL, HSPLL, FRCPLL mod

Oscillator specs per MX5XX/6XX/7XX data sheet:

Param. # Symbol Minimum Maximum Units Conditions

OS10 FOSC 0 50 MHz EC

OS10 4 50 ECPLL
OS11 3 10 XT
OS12 4 10 XTPLL
OS13 10 25 HS/HSPLL
OS15 FOSC 32 100 KHz Sosc

OS50 FIN 4 5 MHz ECPLL, HSPLL, FRCPLL mod

iguration
highlighted cells and
ettings per drop-down list

Notes:
1) Settings that produce red cells are invalid.
2) See device data sheet for details.
3) Password to unprotect = "microchip"

FPLLMUL = MUL_20 FPLLODIV = DIV_2

PLL PLL Output

XTPLL 26.667
= MHz
Multiplier Divider
2.6667 53.33 HSPLL
ECPLL
Must be 4
FRCPLL
to 5 MHz

System PLL Out

USB PLL

32 MHz
USB PLL Divide 32
Divider
x 24 ÷2
2.6667 64 32
usbClock= SYS_OSC_USBCLK_PRIMARY
Must be
DIV_3 4 MHz UPLLEN= ON

USB PLL Out

L, HSPLL, 26.667 MHz

FRCPLL
8 MHz
POSC
8 MHz
FRC
FPBDIV = DIV_2
0.5 MHz Divider PBCLK = 13.33 MHz
FRC/16
 FRC/16 Divider PBCLK =

4 MHz
FRCDIV
SYSCLK =26.6667 MHz
31.25 KHz
LPRC
32.768 KHz
SOSC

FNOSC = FRCPLL

8 MHz
FRC
Enter: trimValue (0 to 511)
53.333 MHz refOscDiv (0 to 32767)
PLL Out FREFCLKO =

POSC
8 MHz
REFCLK (
2 refOscDiv +
Out
64 KHz trimValue = 255 Enable
B PLL Out
refOscDiv = 9
31.25 KHz
LPRC REFCLK REFCLKO = 0.4211
32.768 MHz 8 Divider
SOSC
13.333 MHz FREFIN
PBCLK
26.667 MHz
SYSCLK
2 MHz
REFCLKI

refOscBaseClock = OSC_REF_BASECLOCK_FRC

Harmony functions to configure clocks at run time

(for reference only...not controlled by selections above)

PLIB_OSC_FRCDivisorSelect (OSC_ID_0, divisorFRC);

PLIB_OSC_FRCTuningSelect(OSC_ID_0, tuningValue);
PLIB_OSC_PBClockDivisorSet (OSC_ID_0, OSC_PERIPHERAL_BUS_1, peripheralBusClkDiv); //default =
PLIB_OSC_SecondaryEnable(OSC_ID_0); //default value set by FSOS
PLIB_OSC_SecondaryDisable(OSC_ID_0); //default value set by FSOSC
PLIB_OSC_SysClockSelect(OSC_ID_0, newOsc); //default value set by FNOS
PLIB_OSC_PLLEnable(OSC_ID_0, selectPLL); //enables USB or System PL
PLIB_OSC_PLLDisable(OSC_ID_0, selectPLL); //disables USB or System P
PLIB_OSC_UsbClockSourceSelect(OSC_ID_0, usbClock); // selects the Primary or FRC as base for US
PLIB_OSC_SysPLLMultiplierSelect(OSC_ID_0, pll_multiplier); //default value set by FPLLM
PLIB_OSC_SysPLLOutputDivisorSet(OSC_ID_0, PLLOutDiv); //default value set by FPLLO

PLIB_OSC_ReferenceOscBaseClockSelect (OSC_ID_0, OSC_REFERENCE_1, refOscBaseClock);

PLIB_OSC_ReferenceOscDisable(OSC_ID_0, OSC_REFERENCE_1);
PLIB_OSC_ReferenceOscEnable(OSC_ID_0, OSC_REFERENCE_1);
PLIB_OSC_ReferenceOscDivisorValueSet(OSC_ID_0, OSC_REFERENCE_1, refOscDiv);
PLIB_OSC_ReferenceOscTrimSet(OSC_ID_0, OSC_REFERENCE_1, trimValue);
PLIB_OSC_ReferenceOutputDisable(OSC_ID_0, OSC_REFERENCE_1);
PLIB_OSC_ReferenceOutputEnable(OSC_ID_0, OSC_REFERENCE_1);

Harmony Function Parameters

divisorFRC (used in PLIB_OSC_FRCDivisorSelect) (controls OSCCON: FRCDIV<2:0>)

1 OSC_FRC_DIV_1 0
2 OSC_FRC_DIV_2 2
4 OSC_FRC_DIV_4 0
8 OSC_FRC_DIV_8 0
16 OSC_FRC_DIV_16 0
32 OSC_FRC_DIV_32 0
64 OSC_FRC_DIV_64 0
256 OSC_FRC_DIV_256 0
2
tuningValue
1
2
…
64

peripheralBusClkDiv
1
2
4
8

newOsc
OSC_FRC
OSC_FRC_WITH_PLL
OSC_PRIMARY
 OSC_PRIMARY_WITH_PLL
OSC_SECONDARY
OSC_LPRC
OSC_FRC_DIV_BY_16
OSC_FRC_BY_FRCDIV

selectPLL
OSC_PLL_SYSTEM
OSC_PLL_USB

usbClock
SYS_OSC_USBCLK_PRIMARY
SYS_OSC_USBCLK_FRC

PLLInClockSource
OSC_SYSPLL_IN_CLK_SOURCE_FRC
OSC_SYSPLL_IN_CLK_SOURCE_PRIMARY

PLLInDiv
OSC_SYSPLL_IN_DIV_1
OSC_SYSPLL_IN_DIV_2
OSC_SYSPLL_IN_DIV_3
OSC_SYSPLL_IN_DIV_4
OSC_SYSPLL_IN_DIV_5
OSC_SYSPLL_IN_DIV_6
OSC_SYSPLL_IN_DIV_7
OSC_SYSPLL_IN_DIV_8

pll_multiplier
15
16
17
18
19
20
21
24

PLLOutDiv
OSC_SYSPLL_OUT_DIV_1
OSC_SYSPLL_OUT_DIV_2
OSC_SYSPLL_OUT_DIV_4
OSC_SYSPLL_OUT_DIV_8
OSC_SYSPLL_OUT_DIV_16
OSC_SYSPLL_OUT_DIV_32
OSC_SYSPLL_OUT_DIV_64
OSC_SYSPLL_OUT_DIV_256
 refOscBaseClock
OSC_REF_BASECLOCK_FRC 8 8
OSC_REF_BASECLOCK_SYSPLLOUT 53.333 0
OSC_REF_BASECLOCK_PRIMARY 8 0
OSC_REF_BASECLOCK_USBCLK 64 0
OSC_REF_BASECLOCK_LPRC 0.0313 0
OSC_REF_BASECLOCK_SOSC 0.0328 0
OSC_REF_BASECLOCK_PBCLK 13.333 0
OSC_REF_BASECLOCK_SYSCLK 26.667 0
OSC_REF_BASECLOCK_EXT 2 0
8

refOscDiv (this is a 15 bit field that can hold values from 1 to 32768)
OSC_REF_DIV_1 1
OSC_REF_DIV_2 2
OSC_REF_DIV_4 4
OSC_REF_DIV_8 8
OSC_REF_DIV_16 16
OSC_REF_DIV_32 32
OSC_REF_DIV_64 64
OSC_REF_DIV_128 128
OSC_REF_DIV_256 256
OSC_REF_DIV_512 512
OSC_REF_DIV_1024 1024
OSC_REF_DIV_2048 2048
OSC_REF_DIV_4096 4096
OSC_REF_DIV_8192 8192
OSC_REF_DIV_16384 16384
OSC_REF_DIV_32768 32768

trimValue
1 refOscDiv + trimValue = 9.4980
2
…
512

used as clock out)?

al osc < 4?
al osc > 10?
al osc < 10?
al osc > 25?

Symbol Name

External CLKI Frequency

External CLKI Frequency
External CLKI Frequency
External CLKI Frequency
Oscillator Crystal Frequency
Oscillator Crystal Frequency

PLL Input Frequency Range

Symbol Name

External CLKI Frequency

External CLKI Frequency
External CLKI Frequency
External CLKI Frequency
Oscillator Crystal Frequency
Oscillator Crystal Frequency

PLL Input Frequency Range

Symbol Name

External CLKI Frequency (-40 to 85C)

External CLKI Frequency (-40 to 105C)
External CLKI Frequency (-40 to 85C)
External CLKI Frequency (-40 to 105C)
External CLKI Frequency
External CLKI Frequency
Oscillator Crystal Frequency
Oscillator Crystal Frequency

PLL Input Frequency Range

Symbol Name

External CLKI Frequency

External CLKI Frequency
External CLKI Frequency
External CLKI Frequency
Oscillator Crystal Frequency
Oscillator Crystal Frequency

PLL Input Frequency Range

USBCLK
 FREFIN

(
2 refOscDiv +
trimValue
512 )

MHz

pheralBusClkDiv); //default = FPBDIV

//default value set by FSOSCEN
//default value set by FSOSCEN
//default value set by FNOSC
 //enables USB or System PLL
//disables USB or System PLL
imary or FRC as base for USB clock
//default value set by FPLLMULT
//default value set by FPLLODIV

1, refOscBaseClock);

refOscDiv);
 PIC32MZ Oscillator Configuration
Click on highlighted cell
tuningValue = +\- 12.5% select settings per drop-
FRC
Tune

divisorFRC = OSC_FRC_DIV_2
Internal FRC 8 MHz
Fast RC FRC FRCDIV =
Oscillator 4
Oscillator Divider
8 MHz

FPLLICLK = PLL_POSC FPLLIDIV = DIV_3

Enter external clock
PLL Input PLL Input
or crystal frequency Selection Divider
24

External Clock Freq = 24 MHz

External Crystal Freq = 22 MHz System PLL

OSC1/ 24 MHz
POSC
CLKI
External
Primany POSC POSC
UPLLFSEL =
Oscillator Enable
Oscillator
OSC2/ POSCMOD = EC USB PLL
CLKO

CLK Out USB PLL

PBCLK1 ÷ 2 = 50.00 MHz
Enable Enable
OSCIOFNC = ON UPLLEN =

Backup BFRC 8 MHz

RC Oscillator BFRC
Oscillator 8 MHz
FRCDIV
Low Power LPRC 32 KHz
RC SPLL
Oscillator LPRC
Oscillator 32 KHz
POSC
External Crystal Freq = 32.77 KHz 32.768 KHz
SOSC BFRC
 SOSC BFRC
SOSCI
External SOSC LPRC
Secondary SOSC
Oscillator Enable
Oscillator SOSC
FSOSCEN = ON
SOSCO

Device configuration settings per

highlighted selections above
(configured at program time) FRC
// Device Config Bits in DEVCFG1:
SPLL
#pragma config FNOSC = SPLL
#pragma config FSOSCEN = ON
POSC
#pragma config POSCMOD = EC
#pragma config OSCIOFNC = ON
BFRC
// Device Config Bits in DEVCFG2:
LPRC
#pragma config FPLLICLK = PLL_POSC
#pragma config FPLLIDIV = DIV_3
SOSC
#pragma config FPLLMULT = MUL_50
#pragma config FPLLODIV = DIV_2
PBCLK1
#pragma config FPLLRNG = RANGE_5_10_MHZ
#pragma config UPLLEN = OFF 3 REFCLK
inputs SYSCLK
#pragma config UPLLFSEL = FREQ_12MHZ

REFCLKIx

Enter external
clock frequency

Device configuration bit options:

Bit Name Setting Options Bit Name Setting Options

FPLLMULT = POSCMOD = EC
1 MUL_1 0 HS
2 MUL_2 0 OFF
3 MUL_3 0
4 MUL_4 0 FPLLICLK = PLL_FRC
5 MUL_5 0 PLL_POSC
 6 MUL_6 0
7 MUL_7 0 FPLLIDIV = DIV_1 0
8 MUL_8 0 DIV_2 0
9 MUL_9 0 DIV_3 3
10 MUL_1 0 DIV_4 0
11 MUL_1 0 DIV_5 0
12 MUL_1 0 DIV_6 0
13 MUL_1 0 DIV_7 0
14 MUL_1 0 DIV_8 0
15 MUL_1 0 3
16 MUL_1 0
17 MUL_1 0 FPLLODIV = DIV_2 2
18 MUL_1 0 DIV_4 0
19 MUL_1 0 DIV_8 0
20 MUL_2 0 DIV_16 0
21 MUL_2 0 DIV_32 0
22 MUL_2 0 2
23 MUL_2 0
24 MUL_2 0 FNOSC = FRCDIV 4 0
25 MUL_2 0 SPLL 200 200
26 MUL_2 0 POSC 24 0
27 MUL_2 0 BFRC 8 0
28 MUL_2 0 LPRC 0.032 0
29 MUL_2 0 SOSC 0.032768 0
30 MUL_3 0 200
31 MUL_3 0
32 MUL_3 0 FPLLRNG = RANGE_34_64_MHZ 34 64
33 MUL_3 0 RANGE_21_42_MHZ 21 42
34 MUL_3 0 RANGE_13_26_MHZ 13 26
35 MUL_3 0 RANGE_8_16_MHZ 8 16
36 MUL_3 0 RANGE_5_10_MHZ 5 10
37 MUL_3 0 Bypass
38 MUL_3 0
39 MUL_3 0 UPLLEN = ON
40 MUL_4 0 OFF
41 MUL_4 0
42 MUL_4 0 UPLLFSEL = FREQ_24MHZ
43 MUL_4 0 FREQ_12MHZ
44 MUL_4 0
45 MUL_4 0 FSOSCEN = ON
46 MUL_4 0 OFF
47 MUL_4 0
48 MUL_4 0 OSCIOFNC = ON
49 MUL_4 0 OFF
50 MUL_5 50
51 MUL_5 0
52 MUL_5 0
 53 MUL_5 0
54 MUL_5 0
55 MUL_5 0
56 MUL_5 0
57 MUL_5 0
58 MUL_5 0
59 MUL_5 0
60 MUL_6 0
61 MUL_6 0
62 MUL_6 0
63 MUL_6 0
64 MUL_6 0
65 MUL_6 0
66 MUL_6 0
67 MUL_6 0
68 MUL_6 0
69 MUL_6 0
70 MUL_7 0
71 MUL_7 0
72 MUL_7 0
73 MUL_7 0
74 MUL_7 0
75 MUL_7 0
76 MUL_7 0
77 MUL_7 0
78 MUL_7 0
79 MUL_7 0
80 MUL_8 0
81 MUL_8 0
82 MUL_8 0
83 MUL_8 0
84 MUL_8 0
85 MUL_8 0
86 MUL_8 0
87 MUL_8 0
88 MUL_8 0
89 MUL_8 0
90 MUL_9 0
91 MUL_9 0
92 MUL_9 0
93 MUL_9 0
94 MUL_9 0
95 MUL_9 0
96 MUL_9 0
97 MUL_9 0
98 MUL_9 0
99 MUL_9 0
100 MUL_1 0
101 MUL_1 0
102 MUL_1 0
103 MUL_1 0
104 MUL_1 0
105 MUL_1 0
106 MUL_1 0
107 MUL_1 0
108 MUL_1 0
109 MUL_1 0
110 MUL_1 0
111 MUL_1 0
112 MUL_1 0
113 MUL_1 0
114 MUL_1 0
115 MUL_1 0
116 MUL_1 0
117 MUL_1 0
118 MUL_1 0
119 MUL_1 0
120 MUL_1 0
121 MUL_1 0
122 MUL_1 0
123 MUL_1 0
124 MUL_1 0
125 MUL_1 0
126 MUL_1 0
127 MUL_1 0
128 MUL_1 0
50
Oscillator specs per MZ data sheet:
Param. # Symbol Minimum Maximum Units Conditions

OS10 FOSC 0 64 MHz EC

OS13 FOSC 4 32 MHz HS
OS15 FOSC 32 100 KHz Sosc
OS51 FSYS 0 200 MHz
OS55a FPB 0 100 MHz For PBCLKx, ‘x’ not = 7
OS55b FPB 0 200 MHz For PBCLK7
OS56 FREF -- 50 MHz

OS50 FIN 5 64 MHz ECPLL, HSPLL, FRCPLL mod

OS54 FVCO 350 700 MHz
OS54a FPLL 10 200 MHz

Cell formatting logic to find invalid input (false = no problem):

cell #:
F25 0 Is USB being used?
F25 0 Is input freq not equal to 12 or 24 MHz?
F25 1 Is usb PLL configured for 24 MHz?
F25 0 Is usb PLL configured for 12 MHz?
F25 0 Is there a problem?

E31 0 Is OSC2 needed for crystal input (can't be used as clock out)?
Is input to PLL outside of this range:?
M19 1 0 0 RANGE_34_64_MHZ
M19 1 0 0 RANGE_21_42_MHZ
M19 1 0 0 RANGE_13_26_MHZ
M19 0 0 0 RANGE_8_16_MHZ
M19 0 1 0 RANGE_5_10_MHZ
M19 0 Bypass
M19 0 Is there a problem?

P19 0 1 0 Is PLL multiplier output not between 350 and 700 MH

U18 0 1 0 Is PLL output not between 10 and 200 MHz?

R49 0 Is SYSCLK >200?

V28 0 Is PBCLK1 >100?

V31 0 Is PBCLK2 >100?
V34 0 Is PBCLK3 >100?
V37 0 Is PBCLK4 >100?
V40 0 Is PBCLK5 >100?
V43 0 Is PBCLK7 >200?
V46 0 Is PBCLK8 >100?

E46 0 Is SOSC < 32KHz?

E46 0 Is SOSC > 100KHz?
E46 0 Is tthere a problem?
iguration
highlighted cells and
ettings per drop-down list

Notes:
1) Settings that produce red cells are invalid
2) See device data sheet for details.
MHz 3) Password to unprotect = "microchip"

FPLLMULT = MUL_50 FPLLODIV = DIV_2

PLL PLL Output

SPLL = 200 MHz
Multiplier Divider
8 400

PLL
Range
FPLLRNG = RANGE_5_10_MHZ
Each peripheral clock
(except PBCLK1) can
be disabled.
peripheralBusClkDiv = 2
FREQ_12MHZ Divider PBCLK1 = 100 MHz

USB PLL USBCLK peripheralBusClkDiv = 2

Divider PBCLK2 = 100 MHz

USB PLL peripheralBusClkDiv = 2

Enable 100 MHz
Divider PBCLK3 =
OFF
peripheralBusClkDiv = 2
Divider PBCLK4 = 100 MHz

peripheralBusClkDiv = 2
4 MHz Divider PBCLK5 = 100 MHz
FRCDIV
200 MHz peripheralBusClkDiv = 1
SPLL
Divider PBCLK7 = 200 MHz
24 MHz
POSC
peripheralBusClkDiv = 2
8 MHz Divider PBCLK8 = 100 MHz
BFRC
 BFRC Divider PBCLK8 =

32 KHz
LPRC
SYSCLK = 200 MHz
32.768 KHz
SOSC

FNOSC = SPLL

8 MHz
FRC
Enter: trimValue (0 to 511)
200 MHz refOscDiv (0 to 32767)
SPLL FREFCLKO =

POSC
24 MHz
REFCLK (
2 refOscDiv +
Out
8 MHz trimValue = 218 Enable
BFRC
refOscDiv = 5
32 KHz
LPRC REFCLK REFCLKOx = 18.4305
32.768 KHz 200 Divider
SOSC
3 REFCLK outputs
100 MHz FREFIN SPI (REFCLK1)
PBCLK1 ADC (REFCLK3)
200 MHz SQI (REFCLK2)
SYSCLK
2 MHz
EFCLKIx
x = 1, 3, 4 (REFCLK2 is internal only)

refOscBaseClock = OSC_REF_BASECLOCK_SYSPLLOUT

Harmony functions to configure clocks at run time

(for reference only...not controlled by selections above)

PLIB_OSC_FRCDivisorSelect (OSC_ID_0, divisorFRC);

PLIB_OSC_FRCTuningSelect(OSC_ID_0, tuningValue);
PLIB_OSC_PBClockDivisorSet (OSC_ID_0, OSC_PERIPHERAL_BUS_x, peripheralBusClkDiv);
PLIB_OSC_SecondaryEnable(OSC_ID_0); //default value set by FSOS
PLIB_OSC_SecondaryDisable(OSC_ID_0); //default value set by FSOSC
PLIB_OSC_SysClockSelect(OSC_ID_0, newOsc); //default value set by FNOS
PLIB_OSC_PBOutputClockEnable (OSC_ID_0, peripheralBusNumber); //controls "ON" bit in PBxDIV re
PLIB_OSC_PBOutputClockDisable (OSC_ID_0, peripheralBusNumber); //controls "ON" bit in PBxDIV re
PLIB_OSC_PLLEnable(OSC_ID_0, selectPLL); //enables USB or System PL
PLIB_OSC_PLLDisable(OSC_ID_0, selectPLL); //disables USB or System P
PLIB_OSC_SysPLLFrequencyRangeSet(OSC_ID_0, PLLFrequencyRange); //default value set by FPLLR
PLIB_OSC_SysPLLInputClockSourceSet(OSC_ID_0, PLLInClockSource); //default value set by FPLLIC
PLIB_OSC_SysPLLInputDivisorSet(OSC_ID_0, PLLInDiv); //default value set by FPLLI
PLIB_OSC_SysPLLMultiplierSelect(OSC_ID_0, pll_multiplier); //default value set by FPLLM
PLIB_OSC_SysPLLOutputDivisorSet(OSC_ID_0, PLLOutDiv); //default value set by FPLLO

PLIB_OSC_ReferenceOscBaseClockSelect (OSC_ID_0, OSC_REFERENCE_1, refOscBaseClock);

PLIB_OSC_ReferenceOscDisable(OSC_ID_0, OSC_REFERENCE_1);
PLIB_OSC_ReferenceOscEnable(OSC_ID_0, OSC_REFERENCE_1);
PLIB_OSC_ReferenceOscDivisorValueSet(OSC_ID_0, OSC_REFERENCE_1, refOscDiv);
PLIB_OSC_ReferenceOscTrimSet(OSC_ID_0, OSC_REFERENCE_1, trimValue);
PLIB_OSC_ReferenceOutputDisable(OSC_ID_0, OSC_REFERENCE_1);
PLIB_OSC_ReferenceOutputEnable(OSC_ID_0, OSC_REFERENCE_1);

Harmony Function Parameters

divisorFRC (used in PLIB_OSC_FRCDivisorSelect) (controls OSCCON: FRCDIV<2:0>)

1 OSC_FRC_DIV_1 0
2 OSC_FRC_DIV_2 2
4 OSC_FRC_DIV_4 0
8 OSC_FRC_DIV_8 0
16 OSC_FRC_DIV_16 0
32 OSC_FRC_DIV_32 0
64 OSC_FRC_DIV_64 0
256 OSC_FRC_DIV_256 0
2
tuningValue
1
2
…
64

peripheralBusClkDiv
1
2
…
128

newOsc
OSC_FRC
 OSC_FRC_WITH_PLL
OSC_PRIMARY
OSC_PRIMARY_WITH_PLL
OSC_SECONDARY
OSC_LPRC
OSC_FRC_DIV_BY_16
OSC_FRC_BY_FRCDIV

peripheralBusNumber
OSC_PERIPHERAL_BUS_1
OSC_PERIPHERAL_BUS_2
OSC_PERIPHERAL_BUS_3
OSC_PERIPHERAL_BUS_4
OSC_PERIPHERAL_BUS_5
OSC_PERIPHERAL_BUS_7
OSC_PERIPHERAL_BUS_8

selectPLL
OSC_PLL_SYSTEM
OSC_PLL_USB

PLLFrequencyRange
OSC_SYSPLL_FREQ_RANGE_BYPASS,
OSC_SYSPLL_FREQ_RANGE_5M_TO_10M
OSC_SYSPLL_FREQ_RANGE_8M_TO_16M
OSC_SYSPLL_FREQ_RANGE_13M_TO_26M
OSC_SYSPLL_FREQ_RANGE_21M_TO_42M
OSC_SYSPLL_FREQ_RANGE_34M_TO_68M

PLLInClockSource
OSC_SYSPLL_IN_CLK_SOURCE_FRC
OSC_SYSPLL_IN_CLK_SOURCE_PRIMARY

PLLInDiv
OSC_SYSPLL_IN_DIV_1
OSC_SYSPLL_IN_DIV_2
OSC_SYSPLL_IN_DIV_3
OSC_SYSPLL_IN_DIV_4
OSC_SYSPLL_IN_DIV_5
OSC_SYSPLL_IN_DIV_6
OSC_SYSPLL_IN_DIV_7
OSC_SYSPLL_IN_DIV_8

pll_multiplier
1
2
…
128
PLLOutDiv
OSC_SYSPLL_OUT_DIV_1
OSC_SYSPLL_OUT_DIV_2
OSC_SYSPLL_OUT_DIV_4
OSC_SYSPLL_OUT_DIV_8
OSC_SYSPLL_OUT_DIV_16
OSC_SYSPLL_OUT_DIV_32
OSC_SYSPLL_OUT_DIV_64
OSC_SYSPLL_OUT_DIV_256

refOscBaseClock
OSC_REF_BASECLOCK_FRC 4 0
OSC_REF_BASECLOCK_SYSPLLOUT 200 200
OSC_REF_BASECLOCK_PRIMARY 24 0
OSC_REF_BASECLOCK_BFRC 8 0
OSC_REF_BASECLOCK_LPRC 0.032 0
OSC_REF_BASECLOCK_SOSC 0.0328 0
OSC_REF_BASECLOCK_PBCLK 100 0
OSC_REF_BASECLOCK_SYSCLK 200 0
OSC_REF_BASECLOCK_EXT 2 0
200
refOscDiv (this is a 15 bit field that can hold values from 1 to 32768)
OSC_REF_DIV_1 1
OSC_REF_DIV_2 2
OSC_REF_DIV_4 4
OSC_REF_DIV_8 8
OSC_REF_DIV_16 16
OSC_REF_DIV_32 32
OSC_REF_DIV_64 64
OSC_REF_DIV_128 128
OSC_REF_DIV_256 256
OSC_REF_DIV_512 512
OSC_REF_DIV_1024 1024
OSC_REF_DIV_2048 2048
OSC_REF_DIV_4096 4096
OSC_REF_DIV_8192 8192
OSC_REF_DIV_16384 16384
OSC_REF_DIV_32768 32768

trimValue
1 refOscDiv + trimValue = 5.4258
2
…
512
 Symbol Name

External CLKI Frequency 0

Oscillator Crystal Frequency 0 0 0
Oscillator Crystal Frequency 0 0 0
System Frequency
Peripheral Bus Frequency

Reference Clock Frequency

PLL Input Frequency Range

PLL VCO Frequency Range
PLL Output Frequency Range

used as clock out)?

ween 350 and 700 MHz?

nd 200 MHz?
eripheral clock
PBCLK1) can
bled.

PBCLK7 is the
clock for the core
 FREFIN

(
2 refOscDiv +
trimValue
512 )

MHz

3 REFCLK outputs

FCLK2 is internal only)

heralBusClkDiv);
/default value set by FSOSCEN
/default value set by FSOSCEN
//default value set by FNOSC
ontrols "ON" bit in PBxDIV register
ontrols "ON" bit in PBxDIV register
/enables USB or System PLL
/disables USB or System PLL
/default value set by FPLLRNG
/default value set by FPLLICLK
//default value set by FPLLIDIV
/default value set by FPLLMULT
/default value set by FPLLODIV

, refOscBaseClock);

efOscDiv);
PIC32MX
Oscillator
Block Diagram
PIC32MZ
Default PIC32MZ Oscillator Configuration Settings:
// Device Config Bits in DEVCFG1:
#pragma config FNOSC = FRCDIV
#pragma config FSOSCEN = ON
#pragma config POSCMOD = OFF
#pragma config OSCIOFNC = OFF
// Device Config Bits in DEVCFG2:
#pragma config FPLLODIV = DIV_32
#pragma config FPLLMULT = MUL_128
#pragma config FPLLICLK = PLL_FRC
#pragma config FPLLRNG = RANGE_8_16_MHZ
#pragma config FPLLIDIV = DIV_8
Oscillator Selection Bits (Fast RC Osc w/D
Secondary Oscillator Enable (Enable SOS
Primary Oscillator Configuration (Primary o
CLKO Output Signal Active on the OSCO
System PLL Output Clock Divider (32x Div
System PLL Multiplier (PLL Multiply by 128
System PLL Input Clock Selection (FRC is
System PLL Input Range (8-16 MHz Input
System PLL Input Divider (8x Divider)
ection Bits (Fast RC Osc w/Div-by-N (FRCDIV))
scillator Enable (Enable SOSC)
ator Configuration (Primary osc disabled)
Signal Active on the OSCO Pin (Disabled)

Output Clock Divider (32x Divider)

Multiplier (PLL Multiply by 128)
nput Clock Selection (FRC is input to the System PLL)
nput Range (8-16 MHz Input)
nput Divider (8x Divider)