Lecture Outline

ESE 570: Digital Integrated Circuits and

!  Review: Symmetric CMOS Inverter Design
VLSI Fundamentals
!  Inverter Power
!  Dynamic Characteristics
Lec 10: February 14, 2017
"  Delay
MOS Inverter: Dynamic Characteristics

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Review: CMOS Inverter: Visual VTC Review: CMOS Inverter: Visual VTC

-1 Vout = Vin - VT0p -1 Vout = Vin - VT0p

Vout = Vin - VT0n Vout = Vin - VT0n

V th− V T0p V th− V T0p

V th V th
V th− V T0n V th− V T0n

-1 -1
V th V DD V th V DD
-VT0n V IH -VT0n V IH
V IL V IL
Penn ESE 570 Spring 2017 – Khanna 3 Penn ESE 570 Spring 2017 – Khanna 4

Kenneth R. Laker,
University of
Pennsylvania, updated
12Feb15
Review: CMOS Inverter: Design/Sizing Review: Noise Margin Example
1 Compute the noise margins for a symmetric CMOS inverter has been designed to
VT 0 n + (VDD + VT 0 p ) 2
Important design achieve Vth = VDD/2, where VDD = 5 V and VT0n = - VT0p = 1 V.
kR " V + VT 0 p − Vth % Eq. for CMOS
Vth = kR = $ DD '
1+
1 # Vth − VT 0 n & inverter VTC.
kR
1
If Vth is set to ideal case: Vth =
2
VDD

2 2
" V + VT 0 p −1 2VDD %
kR = $ DD
" 1 2VDD + VT 0 p %
' =$ ' ideal Vth
NMH = NML = 2.125
# 1 2VDD − VT 0 n & # 1 2VDD − VT 0 n &
RECALL (with VDD = 5 V)
If VT0n= -VT0p= -VT0 (symmetric CMOS)
1. NMH, NML > VDD/4 = 1.25 V
2 2
" V + VT 0 p −1 2VDD % " 1 2VDD + VT 0 %
kR = $ DD ' =$ ' =1
µW µ
1 = n= 1n ⇒ p = n
k R symetric
W 2. Ideal NM => NM = NM = 2.5 V > V /2
If,
# also
1 2VDD − VT 0 n & # 1 2VDD + VT 0 & µ pWp Wn µ p H L DD

Penn ESE 570 Spring 2017 – Khanna 5 Penn ESE 570 Spring 2017 – Khanna 6

Kenneth R. Laker, Kenneth R. Laker,

University of University of
Pennsylvania, updated Pennsylvania, updated
12Feb15 12Feb15 1
 Power
!  P = I×V
Inverter Power
!  Tricky part:
"  Understanding I
"  (pairing with correct V)

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Static Current Switching Currents

!  P = Istatic×VDD !  Dynamic current flow:

!  If both transistor on:

"  Current path from Vdd
to Gnd
"  Short circuit current

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Currents Summary Currents Summary

!  I changes over time
!  At least two components
"  Istatic – no switching
"  Iswitch – when switching
"  Idyn and Isc
!  I changes over time
!  At least two components
"  Istatic – no switching
"  Iswitch – when switching
"  Idyn and Isc

CLK

ramp_enable

VRAMP

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 Switching Currents
!  Itotal(t) = Istatic(t)+Iswitch(t)
Switching
!  Iswitch(t) = Isc(t) + Idyn(t)
Dynamic Power

Idyn

Istatic
Isc

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Charging Switching Energy – focus on Idyn(t)

!  Idyn(t) – why is it changing?
"  Ids = f(Vds,Vgs)
"  and Vgs, Vds changing

Idyn
% V (
IDS ≈ ν sat COX W 'VGS − VT − DSAT *
& 2 ) Istatic
" W %) V2 ,
IDS = µn COX $ '+(VGS − VT )VDS − DS . Isc
# L &* 2 -
€ Penn ESE 570 Spring 2017 - Khanna 15 Penn ESE 570 Spring 2017 - Khanna 16

Switching Energy – focus on Idyn(t) Switching Energy

!  Do we know what this is?

∫I dyn (t)dt
Idyn Idyn

E= ∫ P(t)dt E= ∫ P(t)dt
= ∫ I(t)V dt
dd = ∫ I(t)V dt dd

= V ∫ I(t)dt
dd = V ∫ I(t)dt
dd

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 Switching Energy Switching Energy
!  Do we know what this is? !  Do we know what this is?

Q= ∫I dyn (t)dt Q= ∫I dyn (t)dt

Idyn Idyn
!  What is Q?
E= ∫ P(t)dt E= ∫ P(t)dt
= ∫ I(t)V dt
dd = ∫ I(t)V dt dd

= V ∫ I(t)dt
dd = V ∫ I(t)dt
dd

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Switching Energy Switching Energy

!  Do we know what this is? !  Do we know what this is?

Q= ∫I dyn (t)dt Q= ∫I dyn (t)dt

Idyn Idyn
!  What is Q? !  What is Q?
E= ∫ P(t)dt Q = CV = ∫ I(t)dt E= ∫ P(t)dt Q = CV = ∫ I(t)dt
= ∫ I(t)V dt = ∫ I(t)V dt
dd dd
E = CVdd2
= V ∫ I(t)dt
dd = V ∫ I(t)dt
dd
Capacitor charging energy
€
Penn ESE 570 Spring 2017 - Khanna 21
€
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Switching Power
!  Every time output switches 0#1 pay:
"  E = CV2
Switching

!  Pdyn = (# 0#1 trans) × CV2 / time Short Circuit Power

!  # 0#1 trans = ½ # of transitions

!  Pdyn = (# trans) × ½CV2 / time

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 Short Circuit Power Short Circuit Power
!  Between VTN and Vdd - VTP !  Between VTN and Vdd - VTP
"  Both N and P devices conducting "  Both N and P devices conducting
!  Roughly:

Isc

Vin
Vdd
Vdd-Vthp
Vthn
time
Isc
Vdd

time
Penn ESE 570 Spring 2017 - Khanna 25 Penn ESE 570 Spring 2017 - Khanna tsc tsc 26
Vout

time

Isdp

time

Peak Current Peak Current

!  Ipeak around Vdd/2 !  Ipeak around Vdd/2
"  If |VTN|=|VTP| and sized equal rise/Spring "  If |VTN|=|VTP| and sized equal rise/Spring
% V ( % V (
IDS ≈ ν sat COX W 'VGS − VT − DSAT * IDS ≈ ν sat COX W 'VGS − VT − DSAT *
& 2 ) & 2 )
%1(
∫ I(t)dt ≈ I peak × tsc × '& 2 *)
€ €
Vin Vin
Vdd € Vdd
Vdd-Vthp Vdd-Vthp
Vthn Vthn
time time
Isc
Vdd Isc
Vdd

time time
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Vout Vout

time time

Isdp Isdp

time time

Peak Current Short Circuit Energy

!  Ipeak around Vdd/2 !  Make it look like a capacitance, CSC
"  If |VTN|=|VTP| and sized equal rise/Spring "  Q=I×t
% V ( "  Q=CV
IDS ≈ ν sat COX W 'VGS − VT − DSAT *
& 2 )
%1(
∫ I(t)dt ≈ I peak × tsc × '& 2 *) " " 1 %%
E = Vdd × $ I peak × tsc × $ ''
€ #1& # # 2 &&
E = Vdd × I peak × t sc × % (
$2'
Vin
Vdd
E = Vdd × QSC
€
Vdd-Vthp
Vthn E = Vdd × (CSCVdd ) = CSCV 2dd
€ time
Isc
Vdd

time
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Vout

time

Isdp

time

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 Short Circuit Energy
!  Every time switch (0#1 and 1#0)
"  Also dissipate short-circuit energy: E = CV2
Dynamic Characteristics
"  Different C = Csc
"  Ccs “fake” capacitance (for accounting)

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Inverter Delay Inverter Delay

!  Caused by charging and discharging the capacitive
load
"  What is the load?

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Inverter Delay Inverter Delay

Cgb = Cgbn+ Cgbp

Cload = C#dbn + C#dbp + C#gdn + C#gdp + Cint + Cgb

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 Inverter Delay Inverter Delay

n = fan-out ≥ 1

Usually
Cdb >> Cgd
Csb >> Cgs
Cload ≈ C#dbn + C#dbp + Cint + Cgb
Cload ≈ Cdbn + Cdbp + Cint + nCgb
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Propogation Delay Definitions Propogation Delay Definitions

VDD

0 t t

VDD

V50% = VDD/2 39 40
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Propogation Delay Definitions Rise/Spring Times

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 MOS Inverter Dynamic Performance  MOS Inverter Dynamic Performance 
!  ANALYSIS (OR SIMULATION): For a given MOS inverter schematic !  ANALYSIS (OR SIMULATION): For a given MOS inverter schematic
and Cload, estimate (or measure) the propagation delays  and Cload, estimate (or measure) the propagation delays 
!  DESIGN: For given specs for the propagation delays and Cload*, !  DESIGN: For given specs for the propagation delays and Cload*,
determine the MOS inverter schematic determine the MOS inverter schematic

METHODS: METHODS:
1. Average Current Model 2. Differential Equation Model

ΔVHL V −V50% dVout dVout

τ PHL ≈ Cload = Cload OH
I avg,HL I avg,HL iC = Cload
dt
⇒ ∫ dt = C ∫
load
iC
ΔVLH V −V dt ≈ τ PHL or τ PLH
τ PLH ≈ Cload = Cload 50% OL Assume Assume
I avg,LH I avg,LH
Vin ideal Vin ideal

Penn ESE 570 Spring 2017 – Khanna 43 Penn ESE 570 Spring 2017 – Khanna 44

MOS Inverter Dynamic Performance 

!  ANALYSIS (OR SIMULATION): For a given MOS inverter schematic
and Cload, estimate (or measure) the propagation delays  Method 1
!  DESIGN: For given specs for the propagation delays and Cload*,
determine the MOS inverter schematic
Average Current Model
METHODS:
3. 1st Order RC delay Model

τ PHL ≈ 0.69 ⋅ Cload ⋅ Rn

τ PLH ≈ 0.69 ⋅ Cload ⋅ Rp
Assume
Vin ideal

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Calculation of Propagation Delays Calculation of Propagation Delays

ΔVHL V −V50% ΔVHL V −V50%

τ PHL ≈ Cload = Cload OH τ PHL ≈ Cload = Cload OH
I avg,HL I avg,HL I avg,HL I avg,HL
ΔVLH V −V ΔVLH V −V
τ PLH ≈ Cload = Cload 50% OL τ PLH ≈ Cload = Cload 50% OL
I avg,LH I avg,LH I avg,LH I avg,LH

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 Calculation of Propagation Delays Calculation of Rise/Spring Times

ΔVHL V −V50% ΔV90%−10% V −V

τ PHL ≈ Cload = Cload OH τ fall ≈ Cload = Cload 90% 10%
I avg,HL I avg,HL I avg,90%−10% I avg,90%−10%
ΔVLH V −V ΔV10%−90% V −V
τ PLH ≈ Cload = Cload 50% OL τ rise ≈ Cload = Cload 90% 10%
I avg,LH I avg,LH I avg,10%−90% I avg,10%−90%

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Calculation of Rise/Spring Times Calculation of Rise/Spring Times

ΔV90%−10% V −V ΔV90%−10% V −V
τ fall ≈ Cload = Cload 90% 10% τ fall ≈ Cload = Cload 90% 10%
I avg,90%−10% I avg,90%−10% I avg,90%−10% I avg,90%−10%
ΔV10%−90% V −V ΔV10%−90% V −V
τ rise ≈ Cload = Cload 90% 10% τ rise ≈ Cload = Cload 90% 10%
I avg,10%−90% I avg,10%−90% I avg,10%−90% I avg,10%−90%

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Calculating Propagation Delays

Assume Vin is an ideal step-input
Method 2

Differential Equation Model Two Cases

1. Vin abruptly rises => Vout Springs τ PHL
=> τ PLH
2. Vin abruptly Springs => Vout rises
=>

iDP - iDn

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 Case 1: Vin Abruptly Rises - τPHL Case 1: Vin Abruptly Rises - τPHL

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Case 1: Vin Abruptly Rises - τPHL Case 1: Vin Abruptly Rises - τPHL

≈ ≈

≈ ≈

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Case 1: Vin Abruptly Rises - τPHL Recall: CMOS Inverter: Visual VTC

≈ -1 Vout = Vin - VT0p

Vout = Vin - VT0n

V th− V T0p

V th

V out = V DD− V T0n V th− V T0n

≈
-1
V th V DD
-VT0n V IH
V IL
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 Case 1: Vin Abruptly Rises - τPHL Case 1: Vin Abruptly Rises - τPHL
≈
saturation linear
t0#t1 t1#t50%
V out = V DD− V T0n
VDD −VT 0 n " −1 % VDD /2 " −1 %
τ PHL =Cload ∫ V $ 'dVout + Cload ∫ $ 'dVout
DD
# iDn & VDD −VT 0 n
# iDn &

dVout kn
Cload ≈ −iDn saturation: iDn = (Vin −VT 0n )2
dt 2
" %
−dVout VDD −VT 0 n $ −1 '
dt = Cload τ PHL,sat = Cload ∫ V $ 'dVout
iDn V out = V DD− V T0n DD k 2
$ (VDD −VT 0n ) '
n

t=t50% Vout =VDD /2 $ −1 ' #2 &

τ PHL = ∫ t=t0
dt = Cload ∫ Vout =VDD
& )dVout
% iDn (
−Cload VDD −VT 0 n
τ PHL,sat =
kn ∫ VDD dVout
VDD −VT 0 n $ −1 ' VDD /2 $ −1 ' (VDD −VT 0n )2
τ PHL =Cload ∫ VDD &% i )(dVout + Cload ∫ VDD −VT 0 n &% i )(dVout 2
Dn Dn 2CloadVT 0n
τ PHL,sat =
t0#t1 t1#t50% kn (VDD −VT 0n )2
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Case 1: Vin Abruptly Rises - τPHL Case 1: Vin Abruptly Rises - τPHL

saturation linear Vout =VDD /2

2Cload −1 # Vout &
t0#t1 t1#t50% τ PHL,lin = ⋅ ln % (
V out = V DD− V T0n kn 2(VDD −VT 0n ) %$ ( 2(VDD −VT 0n ) −Vout ) ('
Vout =VDD −VT 0 n
VDD −VT 0 n " −1 % VDD /2 " −1 %
τ PHL =Cload ∫ V $ 'dVout + Cload ∫ $ 'dVout Cload # 2(VDD −VT 0n ) −VDD 2 &
DD
# iDn & VDD −VT 0 n
# iDn & τ PHL,lin = ln % (
kn (VDD −VT 0n ) $ VDD 2 '
kn
linear: iDn = ((Vin −VT 0n )Vout −V out2 )
2 " %
VDD /2 $ −1 '
τ PHL,lin = Cload ∫ V −V $ 'dVout
DD T 0n
$ kn ( 2(VDD −VT 0n )Vout −V out
2
) '&
#2
" %
2C VDD /2 −1
τ PHL,lin = load ∫ V −V $ 'dVout
T 0 n $ 2(V '
kn DD
# ( DD −VT 0n )Vout −V 2
out ) &
Vout =VDD /2
2Cload −1 " Vout %
τ PHL,lin =
⋅ ln $ '
kn 2(VDD −VT 0n ) $# ( 2(VDD −VT 0n ) −Vout ) '&
Penn ESE 570 Spring 2017 – Khanna 63 Penn ESE 570 Spring 2017 – Khanna 64
Vout =VDD −VT 0 n

Case 1: Vin Abruptly Rises - τPHL Case 1: Vin Abruptly Rises - τPHL

saturation linear saturation linear

t0#t1 t1#t50% t0#t1 t1#t50%
V out = V DD− V T0n V out = V DD− V T0n
VDD −VT 0 n " −1 % VDD /2 " −1 % VDD −VT 0 n " −1 % VDD /2 " −1 %
τ PHL =Cload ∫ V $ 'dVout + Cload ∫ $ 'dVout τ PHL =Cload ∫ V $ 'dVout + Cload ∫ $ 'dVout
DD
# iDn & VDD −VT 0 n
# iDn & DD
# iDn & VDD −VT 0 n
# iDn &

2CloadVT 0n Cload " 2(VDD −VT 0n ) −VDD 2 % 2CloadVT 0n Cload " 2(VDD −VT 0n ) −VDD 2 %
τ PHL,sat = τ PHL,lin = ln $ ' τ PHL,sat = τ PHL,lin = ln $ '
kn (VDD −VT 0n )2 kn (VDD −VT 0n ) # VDD 2 & kn (VDD −VT 0n )2 kn (VDD −VT 0n ) # VDD 2 &

2CloadVT 0n Cload " 2(VDD −VT 0n ) −VDD 2 % 2CloadVT 0n Cload " 2(VDD −VT 0n ) −VDD 2 %
τ PHL = + ln $ ' τ PHL = + ln $ '
kn (VDD −VT 0n )2 kn (VDD −VT 0n ) # VDD 2 & kn (VDD −VT 0n )2 kn (VDD −VT 0n ) # VDD 2 & Rn
1 ) 2V # 2(VDD −VT 0n ) &,
T 0n
τ PHL =Cload ⋅ + + ln % −1(.
kn (VDD −VT 0n ) * (VDD −VT 0n ) $ VDD 2 '-
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 Case 1: Vin Abruptly Rises - τPHL Case 1: Vin Abruptly Rises - τPHL

1 ) 2V # 2(VDD −VT 0n ) &, 1 ) 2V # 2(VDD −VT 0n ) &,

T 0n T 0n
τ PHL =Cload ⋅ + + ln % −1(. τ PHL =Cload ⋅ + + ln % −1(.
kn (VDD −VT 0n ) * (VDD −VT 0n ) $ VDD 2 '- kn (VDD −VT 0n ) * (VDD −VT 0n ) $ VDD 2 '-

Recall from static CMOS Inverter: Recall from static CMOS Inverter:
1 1
VT 0 n +
kR
(VDD + VT 0 p ) " V + VT 0 p − Vth %
2 VT 0 n +
kR
(VDD + VT 0 p ) " V + VT 0 p − Vth %
2

Vth = kR = $ DD ' Vth = kR = $ DD '

1 # Vth − VT 0 n & 1 # Vth − VT 0 n &
1+ 1+
kR kR

DESIGN: (1) Vth → kR; (2) τPHL → kn; (3) kR & kn → kp DESIGN: (1) Vth → kR; (2) τPHL → kn; (3) kR & kn → kp

(1) Vth → kR; (2) τPLH → kp; (3) kR & kp → kn

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Idea Admin
!  Ptot = Pstatic + Pdyn+ Psc !  HW 4 due Thursday, 2/16
"  Can’t ignore Static Power (aka. Leakage power)
!  Propogation Delay
"  Average Current Model
"  Differential Equation Model
"  1st Order Model

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