1834 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO.

7, AUGUST 2008

Systematic Design of Supply Regulated LC-Tank

Voltage-Controlled Oscillators
Xuejin Wang and Bertan Bakkaloglu, Member, IEEE

Abstract—Systematic design of low-dropout-regulator (LDO)

regulated low-phase-noise LC-tank voltage controlled oscillators
(VCOs) is presented. Low-frequency sensitivity profile of power
supply induced phase noise of a typical cross-coupled LC-tank
VCO is investigated. The relationship between frequency pushing
and power supply-induced phase noise is derived. Systematic
codesign of VCO sensitivity to low-frequency supply noise with
respect to an LDO output noise and power supply rejection profile
is introduced. To demonstrate the design approach experimentally,
two 2.4-GHz LC-tank VCOs with pMOS and nMOS switching
devices powered by PFET LDOs are designed and fabricated on
an 0.18- m, 7-layer metal CMOS process. By using an integrated
LDO, it is shown that the VCO phase-noise sensitivity to low
frequency improves by 55 dB at 100-kHz offset.
Index Terms—DC-DC power conversion, voltage regulators, Fig. 1. Design framework for the proposed supply regulated VCO design
phase noise, power supply rejection (PSR), voltage-controlled technique.
oscillators (VCOs).

pass element, and a feedback network. The bypass capacitor

I. INTRODUCTION provides frequency compensation at the output node and
helps with high-frequency power supply rejection (PSR). The

V OLTAGE-CONTROLLED oscillator (VCO) phase-noise

performance impacts several RF system specifications
such as error-vector-magnitude (EVM), SNR, and SNR under
resistor is the equivalent-series resistance (ESR) of
The LDO pass element could be implemented with either a
bipolar transistor or a MOS transistor. The MOS transistor
.

blocking conditions. There are two major sources for VCO
phase noise: VCO circuit device noise and ambient noise such
as supply, ground, and substrate noise. The noise from supply
lines can be classified as:
1) switching noise and interference from other circuit blocks
on the same IC, such as dividers and modulators;
2) thermal and noise associated with supply regulation
circuits and power supply parasitics.
The supply noise is becoming a critical bottleneck in
deep-submicrometer low-noise VCOs due to the reduced power
supply voltage, reduced clock swings, higher order of digital
integration, and increased number of circuits on the same IC.
It has been shown that supply noise has the highest impact
on VCO phase noise in terms of deterministic noise [1]. To
reduce the effect of supply ripple, low dropout linear regulators
(LDOs) [2], [3] are usually preferred for low-noise voltage
regulation. A block-level diagram of a VCO regulated by an
LDO with an inverting pass element is shown in Fig. 1. The
LDO circuit includes a voltage reference, an error amplifier, a
Manuscript received February 4, 2007; revised August 13, 2007. First pub-
lished February 7, 2008; last published August 13, 2008 (projected). This paper
was recommended by Associate Editor P. Carbone.
X. Wang is with Cadence Design Systems, Tempe, AZ 85282 USA (e-mail:
xuwang@cadence.com).
B. Bakkaloglu is with the Department of Electrical Engineering, Ira A.
Fulton School of Engineering, Arizona State University, Tempe, AZ 85287
USA (e-mail: bertan@asu.edu).
Digital Object Identifier 10.1109/TCSI.2008.918004
1549-8328/$25.00 © 2008 IEEE
implementation gives lower quiescent current and is more
compatible with state-of-the-art CMOS processes.
It is desirable to have the voltage regulation on the same chip
with the VCO for higher level of integration and reduced inter-
ference. The VCO and associated LDO could be optimized to-
gether for lower noise and a smaller circuit area with a reduced
number of external components.
In this paper, joint optimization of LDO output-referred noise
and PSR along with an LC-tank VCO low-frequency supply
noise sensitivity is proposed. The output noise and PSR profile
of typical fully integrated LDOs are analyzed with respect to
their loop transmission, and their impact on VCO close-in phase
noise sensitivity is optimized. With the help of the proposed
loop-shaping scheme, VCO spot phase noise can be minimized
at a given frequency range for a given system specification.
Several earlier publications have analyzed VCO noise
up-conversion. In [4], a method using impulse sensitivity
function (ISF) to calculate VCO phase noise is presented.
In [5], current-limited and voltage-limited VCO operation
is discussed, and various noise sources for phase noise in
differential cross-coupled LC oscillators are analyzed. The
ISF is applied for flicker noise up-conversion minimization in
[6]. The conversion from low-frequency amplitude noise to
phase noise is described as AM–PM noise conversion due to
nonlinear capacitances in [7] and [8]. In [9] and [10], automatic
amplitude control is applied to reduce VCO amplitude variation
and AM–PM noise conversion. In [11], phase noise due to
WANG AND BAKKALOGLU: SYSTEMATIC DESIGN OF SUPPLY REGULATED LC-TANK VOLTAGE-CONTROLLED OSCILLATORS 1835

due to low-frequency power supply noise and ripple, the

VCO oscillation frequency will change around the nominal
value by due to a frequency pushing effect, i.e., the VCO
oscillates with close-in phase noise. The frequency pushing
factor is defined as rads/V.
Representing low-frequency supply noise by a single-tone
, the VCO output signal will be both AM
and PM modulated. The VCO output signal can be expressed by

(1)

where is the oscillation amplitude, is the oscillation

frequency, and is the oscillation phase.
Assuming a narrowband FM modulation, where ,
and assuming a fixed oscillation amplitude, we can approximate
Fig. 2. pMOS and nMOS switching pair cross-coupled LC VCO topologies. (1) by

low-frequency bias noise is shown to be a function of AM-PM (2)

conversion of the switching devices as well.
An analytical technique for determining the contribution of For a given power supply frequency pushing factor , the in-
wideband supply noise to overall VCO phase noise floor is pre- stantaneous frequency can be represented by
sented in [1]. Based on the perturbation projection vector (PPV)
technique, the supply and ground noise sensitivity of oscillators (3)
has been analyzed in [12]. An LC oscillator with a power supply
pushing cancellation circuit is implemented in [13]. However, a
Therefore, instantaneous phase deviation due to supply
joint analysis and design approach of a low-noise VCO along
pushing can be represented by
with its linear supply regulator for low device noise contribu-
tion and low supply noise up-conversion have not been intro-
duced before.
This paper is organized as follows. In Section II, the power
supply noise-induced VCO phase noise is investigated. In
Section III, the LDO power supply regulation and noise per-
formance are analyzed. In Section IV, the design issues of (4)
designing the VCO and LDO together are summarized. In
Section V, experimental results on codesign approach are and the power spectral density of the phase deviation can
presented. Finally, the conclusions are drawn in Section VI. be represented by

II. LOW-FREQUENCY SUPPLY-NOISE SENSITIVITY OF VCOS (5)

Two commonly used topologies of cross-coupled LC-tank
VCOs using pMOS and nMOS switching-pair transistors are Representing the amplitude power spectral density of
shown in Fig. 2. The inductors and capacitors (varactors) form by
the LC tank of the VCO. The cross-coupled transistor pair pro-
vides a positive feedback (negative resistance) in parallel with
the LC tank. The oscillation frequency is adjusted by the tuning
voltage applied on the varactors. (6)
Low-frequency power supply noise can be up-converted to
the vicinity of the VCO oscillation frequency and therefore we obtain the supply noise source-induced phase noise in
contributes to VCO phase noise. This noise conversion is dBc/Hz as
directly related to the power supply frequency pushing factor
of the VCO. The power supply pushing factor is defined by
the output frequency change corresponding to a change of the
power supply voltage while the tuning voltage is kept constant.
Due to the bypass capacitance of the local supply regulators,
the frequency of interest for phase noise is mainly within the (7)
regulator bandwidth. It is a good approximation to assume that
the low-frequency power supply noise is constant within one This equation shows that the low-frequency power supply-
oscillation period. When the power supply voltage varies by induced phase noise magnitude is directly proportional to the
1836 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 7, AUGUST 2008

Fig. 3. Transfer function of low-frequency power supply noise to VCO phase-

noise conversion.

Fig. 5. Simulated time-domain oscillation waveforms for a typical LC-tank

oscillator.

is the gate oxide capacitance per unit area, and and are
the width and length of M0. The similar expression applies to
the transistor M1 drain current .
KCL on node and results in
Fig. 4. Typical nMOS cross-coupled LC-tank VCO schematic depicting device
nonlinearities and associated small-signal currents.

(9)
supply noise amplitude and the frequency pushing factor
and inversely proportional to the noise frequency . The fre- The MOS transistor drain currents and depend on the
quency characteristics of the transfer function from low-fre- operation region of these transistors, as shown in (8).
quency power supply noise to VCO phase noise is shown in For example, we can assume an LC-tank oscillator with
Fig. 3. nH, pF, A/V V, and
V. The time-domain output voltage waveforms of the
A. LC-Tank VCO Supply Sensitivity output nodes and from a circuit simulation are shown in
Fig. 5.
As seen from this analysis, the power supply noise-induced
At time instant A, the differential output and have the
VCO phase noise can be suppressed by reducing the VCO power
same value , where is decreasing and is increasing. At
supply frequency pushing factor . The VCO phase-noise con-
time instant B, the differential output and are at the same
version and frequency pushing have been viewed as AM–PM
voltage again, where is increasing and is decreasing. The
conversion due to the capacitance nonlinearities in prior lit-
time between A and B is half of the oscillation period.
erature [7], [8]. In addition to capacitance nonlinearities, the
Zooming into the waveform around time instant A, both M0
frequency pushing effect also arises from the nonlinearity of and M1 are in saturation region. At time T1, drops to and
the switching devices. Considering the simplified cross-coupled
M1 turns to the cut-off region. At time T2, increases
LC-tank nMOS VCO (without a current source) as shown in
to , and M0 moves to the linear region. M0 remains in the
Fig. 4, the drain current of the transistor M0 is given by
linear region until time T3, which is close to time instant B. At
time T3, drops back to and M0 changes back to the
saturation region. At time T4, increases to and M1 turns
to the saturation region.
Due to the nonlinear derivative equations, it is difficult to get
a closed-form solution of the oscillation. However, the trend of
the relationship between the oscillation frequency and circuit
(8) parameters can be observed with some approximations.
where is the threshold voltage, the coefficient The time duration between T2 and T3 occupies most of the
is the mobility of charge carriers, oscillation period. Between time T2 and T3, the transistor M1
WANG AND BAKKALOGLU: SYSTEMATIC DESIGN OF SUPPLY REGULATED LC-TANK VOLTAGE-CONTROLLED OSCILLATORS
Fig. 6. Simplified half circuit of the VCO for the switching device in the linear
region.
is in the cutoff region and transistor M0 is in the linear region.
The KCL at nodes and from (9) results in
(10)
By analyzing the linear region and assuming is small, we
have
(11)
Therefore, the device M0 acts as a variable resistor, where the
conductance is given by
(12)
The resulting half circuit in this region is shown in Fig. 6.
It contains lossy LC tank and the variable resistor representing
the switching device in parallel. For a fixed conductance , the
oscillation frequency of the circuit is given by
(13)
Therefore, the change of conductance will result in a
change in oscillation frequency of the RLC tank.
The same relation applies to the variable . A larger will
result in larger equivalent . Given that cannot be too small
for starting the oscillation, the increased will result in lower
oscillation frequency. Assuming there is no amplitude control
loop, when the power supply voltage increases, the oscilla-
tion amplitude increases with it. Therefore, the voltage be-
tween points A and B increases. It results in a bigger equivalent
conductance , resulting in a longer oscillation period.
The relationship between and the oscillation frequency
is shown in Fig. 7. The data has been obtained from circuit sim-
ulation using Cadence SpectreRF simulator. For of 1.6 V, as
increases from 0.02 to 0.05 A/V , the oscillation frequency re-
duces from 2.46 to 2.33 GHz. For of 0.03 A/V , as the power
1837
Fig. 7. Oscillation frequency versus and .
Fig. 8. VCO power supply pushing factor and power supply-induced phase
noise (normalized to power supply noise of 1 V/sqrt(Hz) at a frequency of 1 Hz)
versus .
supply voltage increases from 1.5 to 2 V, the oscillation fre-
quency reduces from 2.43 to 2.34 GHz.
As a first-order approximation, if we assume that the equiv-
alent conductance is proportional to , the pushing factor
becomes
(14)
Therefore, the magnitude of the frequency pushing factor
can be reduced by decreasing the equivalent conductance ,
which can be achieved by making small.
In this example, the pushing factor and power supply-induced
phase noise (normalized to power supply noise of 1 V/ Hz at a
frequency of 1 Hz) versus from circuit simulation are shown in
Fig. 8. If is reduced from 0.03 to 0.02, the frequency pushing
factor is changed from 180.2 to 120 MHz/V, and the power
supply-induced phase noise is reduced by 3 dB. This simulation
does not have any nonlinear capacitance involved. Therefore,
the power supply frequency pushing and power supply-induced
phase noise is purely due to the nonlinearity of the switching
devices.
1838 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 7, AUGUST 2008

As discussed earlier, another frequency pushing mechanism

is the voltage dependant capacitance, mainly from the varactors.
In addition to the varactors, the parasitic capacitance of the tran-
sistors is also voltage-dependent. The pn junction depletion-re-
gion capacitance is given by

(15)

where is the bias of the junction, is the built-in potential

of the junction, is the value of for , and equals
1/2 for constant doping and 1/3 for graded doping in the -type
and -type regions.
When the power supply voltage increases, the oscillation
amplitude will also increase, which results in the change of
the equivalent varactor capacitance. Therefore, the AM–PM Fig. 9. Typical pMOS LDO schematic diagram.
conversion occurs, changing the VCO oscillation frequency.
For the nMOS switching pair VCO, the change of the power by the VCO bias device, utilizing the LDO PSR as much as
supply voltage also changes the varactor quiescent point. All of possible.
these factors will be added to the total power supply frequency
pushing factor and thus contribute to the power supply-induced III. LDO DESIGN FOR VCO SUPPLY REGULATION
phase noise.
A typical circuit diagram of a pMOS pass-element LDO is
shown in Fig. 9. The feedback network consists of two resis-
tors and . The capacitor is used as a bypass capac-
B. Device Noise Versus Supply Noise Trade-Off itor which also provides frequency compensation at the output
node and helps with high-frequency PSR. The resistor is
If the cross-coupled LC-tank VCO has a current bias device, the equivalent-series resistance (ESR) of capacitor .
as shown in Fig. 2, the trend of the oscillation frequency de- Critical specifications of an LDO from an RF VCO supply
pendency on power supply is the same as the simple VCO. regulation point are dropout voltage, line regulation, load regu-
The power supply frequency pushing can be approximated as lation, tolerance over temperature, settling time, output capac-
a two-step process. The ripple on the power supply is applied to itor, ESR range, quiescent current flow, maximum load current,
the switching devices through the voltage divider formed by the and input/output voltage range [2]. In this section, we will an-
switching devices and the bias device. alyze the PSR and noise frequency characteristics of an LDO
The attenuation provided by the bias device on VCO power with a pMOS transistor pass element, which are specifically re-
supply sensitivity depends on the operation region of the bias lated to VCO power supply noise.
device. When the tail current device operates in the saturation
region, it acts as a high impedance current source providing iso- A. AC Analysis of LDO PSR
lation from the power supply to the VCO output. However, it
makes the tank amplitude strongly correlated to the bias cur- The feedback loop is broken at node for an open-loop
rent. Therefore, the bias current noise highly impacts the VCO analysis. The open loop transfer function is
phase noise.
The bias current noise contribution can be effectively sup- (16)
pressed by making the tail transistor spend most (or even all) of
its time in the triode region. This can be achieved by decreasing where is the transconductance of the error amplifier,
the power supply voltage, increasing the bias current, or de- is the transconductance of the pass element is
creasing the size of the switching devices. This region of opera- the output resistance of the error amplifier, is the parasitic
tion is referred to as a voltage-limited regime [5]. In this region, capacitance at node due to the pass element, and is the
the tank amplitude is limited by the available voltage supply. impedance at node and is given by
Therefore, the bias current noise does not have a strong impact
on the tank amplitude and VCO phase noise. The drawback of
this operation is that the VCO phase noise becomes more sen-
sitive to the power supply noise.
As seen from this analysis, there is a tradeoff between power
supply-induced phase noise and current bias device noise. By
powering the VCO with an LDO, the power supply noise and (17)
ripple can be attenuated. With this option, the VCO could be
optimized for reducing the device-induced phase noise. In the where is the output resistance of the pMOS pass
example design, simulation shows only 1.8-dB PSR provided element.
WANG AND BAKKALOGLU: SYSTEMATIC DESIGN OF SUPPLY REGULATED LC-TANK VOLTAGE-CONTROLLED OSCILLATORS 1839

As seen above, the open-loop LDO system has two poles due
to a two-stage operation and one zero due to the capacitor ESR.
The open-loop transfer function can be expressed as
Therefore, the two poles of PSR are in the range (0,
) and , respectively. With the two zeros at and
(18) , the Bode plot of the PSR is shown in
Fig. 10(a). The open-loop gain is shown in the same plot.
2) In the case of a dominant pole-compensated LDO with a
where
nondominant pole coinciding with the zero from the ca-
pacitor, , the Bode plots of the PSR and
open-loop gain are shown in Fig. 10(b). The pole of PSR(s)
is at . Here we assume
.
3) In the case that the zero from the capacitor is larger than
the poles and the PSR have two real poles,
The pole is associated with the LDO output node . we have
The pole is associated with the error amplifier output node
, and the zero is caused by the bypass capacitor and
the series resistance . The loop is compensated for at the
output node . The size of the compensation capacitor
can be smaller when the output resistance of the error amplifier Starting from , the two poles are at and
is low. . If we assume , as increases
There are two paths for noise to couple from the power supply from to , the two real poles are always greater than .
to the LDO output node: one is through the pMOS pass device Therefore, the Bode plots of the PSR and open-loop gain
directly; the other is through the error amplifier to the gate of for this case are shown in Fig. 10(c).
the pMOS pass device [3]. Assuming the transconductance from 4) In the case that a big zero from the capacitor is larger than
the power supply to the output of the error amplifier is , the the poles and if the zero is big enough, eventually the PSR
PSR can be represented by will have two conjugate complex poles. Let

(19)

The PSR at low frequencies is given by When has no peaking. The PSR
will first increase and then flatten after the two complex poles.
(20) The Bode plot is shown in Fig. 10(d).
When has peaking at
The PSR at high frequencies is given by . The high peaking occurs at . The
peaking frequency is at .
(21) Here, is the open-loop unity gain frequency, and we as-
sume and . The Bode plots of the PSR and
The PSR has two zeros at and (1- and two open-loop gain are shown in Fig. 10(e).
poles determined by the denominator B. Output-Referred Noise of LDOs
Due to a large output pass transistor size and output current,
(22)
the pass transistor transconductance is usually large. The
pass transistor noise density referred to the transistor gate is so
The detailed PSR frequency response for different open loop small that it can be ignored in the noise analysis. In the example
zero-pole locations can be discussed as follows. LDO design, the pass transistor only contributes 0.0002% to the
1) In the case of a typical dominant pole-compensated LDO total LDO output noise. Therefore, there are four noise sources
with a finite zero from the capacitor , we for the LDO, as shown in Fig. 11: the reference voltage noise,
have input-referred error amplifier noise, resistor noise, and re-
sistor noise.
A low-noise voltage reference is required for a low-noise
LDO design. It is not trivial to filter out the flicker noise from
the reference without a low external filter pole. In addition to
1840 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 7, AUGUST 2008

Fig. 10. Bode plot of pMOS LDO open-loop gain, PSR, and output noise for different pole and zero locations.

the resistors can be reduced by using small resistors. However,

this increases the LDO’s static current consumption.
The gain from these noise sources to the output voltage is
given by

(23)

(24)

(25)

where is the open-loop transfer function.

Therefore, the overall output noise is given by
Fig. 11. Noise sources for a pMOS LDO.

the voltage reference, the design of the error amplifier is also

important for a low-noise LDO, which may require more cur-
rent consumption and chip area. The LDO output noise due to (26)
WANG AND BAKKALOGLU: SYSTEMATIC DESIGN OF SUPPLY REGULATED LC-TANK VOLTAGE-CONTROLLED OSCILLATORS
Fig. 12. Bode plot of VCO LDO power supply sensitivity and LDO PSR.
As shown in (26), the LDO output noise spectrum is shaped
by
(27)
The spectral profile of the LDO output thermal noise can
be plotted with respect to different pole and zero locations, as
shown in Fig. 10.
IV. LDO DESIGN FOR LOW-NOISE VCOS
In the proposed approach, we presume that the LDO is dedi-
cated to VCO and associated circuitry, including frequency dou-
blers and LO buffers. Therefore, the LDO is optimized around
the VCO load condition. In case the VCO is adjusted for desired
phase noise and power consumption, the LDO needs to be de-
signed to be able to handle the load change.
Assuming , the PSR of the LDO at high
frequencies can be defined as
(28)
The pass device transconductance increases with the
square root of the increasing load current. Therefore, the
high-frequency PSR gets worse when the load current in-
creases, and the same analysis applies to the LDO output noise.
As the VCO oscillates, the current drawn from the LDO con-
tains both dc and even harmonics of the oscillation frequency.
The magnitude of the even harmonic components of the cur-
rent waveform depends on the VCO oscillation waveform. In
the implemented designs, the transient currents are 1.5 mA to
1841
3.1 mA for the pMOS VCO and 1.1 and 3.4 mA for the nMOS
VCO. Due to the high oscillation frequency and low re-
sistance, a large portion of this high-order harmonic current is
provided by the capacitor . Therefore, only a small portion
of the high-order harmonic current content travels through the
pass device. This high-order harmonic current can up-convert
the low-frequency power supply noise and LDO noise to high
frequency which can be down-converted to the VCO oscillation
frequency by the VCO’s switching devices. However, this effect
is not significant because the pass device high-order harmonic
current is only a small portion of the total current.
Utilizing the ac analysis from the previous session, a high
open-loop zero may result in peaking of the PSR and output
noise; a low can avoid the peaking and provide good PSR and
output noise at low frequencies. However, the PSR and output
noise at high frequencies worsens with a low . The location
of can be adjusted by the series resistance , which is
inversely proportional to . The series resistance should
be optimized for PSR and noise specification of the VCO.
The overall phase-noise sensitivity to global power supply
noise is the combination of the LDO PSR and VCO phase noise
sensitivity. The low-frequency power supply-induced VCO
phase noise has a 20 dB/dec dependency to the offset fre-
quency . This frequency dependency can be combined with
the LDO PSR, as discussed in Section III, to form the overall
phase noise sensitivity to power supply noise. The plots of the
overall sensitivity with respect to different LDO ac responses
are shown in Fig. 12. The design choice will be made based on
the phase-noise specification of the given power supply noise
profile. Either spot noise for critical points or integrated phase
noise can be used for the desired band of rejection.
As discussed in Section II, the VCO power supply-induced
phase noise can be reduced by lowering the VCO supply fre-
quency pushing factor. However, there is a tradeoff between
1842 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 7, AUGUST 2008

Fig. 13. Die microphotograph of the LDO and VCO.

the bias device noise-induced phase noise and supply pushing

factor. The extra power supply regulation must be provided by
the LDO.
The LDO PSR frequency response is affected by the error am-
plifier, pass device, and output bypass capacitor. A high-gain
high-bandwidth error amplifier helps to improve the low and
Fig. 14. Schematic of the LDO error amplifier.
moderate frequency PSR, with the cost of high current con-
sumption. The tradeoff between high-frequency and moderate-
frequency PSR can be made by tuning the series resistance of
the bypass capacitor.
• When the ESR is very low, the VCO power supply sen-
sitivity around the unity gain frequency will be deterio-
rated by the LDO PSR frequency peaking, as shown in
Fig. 12(e).
• When the ESR is high, the VCO power supply sensitivity
is improved at moderate frequencies but worsens at high
frequencies, as shown in Fig. 12(a).
• With moderate ESR, as shown in Fig. 12(b)–(d), trade-
offs should be made for given power supply sensitivity fre-
quency specification.
The LDO output noise (including thermal and flicker) is also
a contributor to the VCO phase noise. For a given VCO phase
noise sensitivity to its power supply node, the requirement of
LDO output noise can be derived from the VCO phase-noise
specification in a similar fashion.
Fig. 15. Measured VCO phase-noise sensitivity to power supply noise.
V. EXPERIMENTAL RESULTS
In order to verify the optimum LDO PSR and noise shaping,
two VCOs (pMOS and nMOS switching devices) and two dedi- to the gate of the LDO pMOS pass transistor. The LDO has an
cated pMOS LDOs are implemented in a 7-layer metal, 0.18- m input voltage range of 2–5 V and an output voltage of 1.65 V. At
CMOS process. To avoid the frequency peaking and poor PSR VCO supply current levels, the LDO achieves an efficiency of
at high frequencies, the ac response of Fig. 10(c) is analyzed to 76%. The LDO open-loop poles are designed to be around 42 Hz
be the selection for this implementation. The die microphoto- and 4.5 kHz, and the open-loop zero is at around 21 kHz
graph of the implemented designs is shown in Fig. 13. to suppress supply noise up-conversion at the frequency range
The VCO schematics are shown in Fig. 2. The power of 100 kHz–10 MHz. Based on quiescent current requirements,
supply voltage of the VCOs is 1.65 V. Both of the pMOS and the value of the filtering capacitor is 500 nF and is
nMOS switching-pair VCOs are designed to oscillate at around 10 . The capacitance could be reduced with the expense of
2.4 GHz with a current consumption of about 2.2 mA. The wider amplifier bandwidth or higher resistance value. With an
VCOs are optimized to achieve a low phase noise by sizing open-loop gain of 114 dB, the LDO PSR has two real poles. The
the switching and bias devices as well as the varactors. The smaller pole is slightly greater than and the larger pole is at
bias device is biased in such a way that it spends majority of about 5 MHz. This ac response achieves moderate PSR at high
a sine wave cycle in triode mode to suppress the current noise frequencies with little deterioration from frequency peaking.
from the bias device, utilizing the regulated supply voltage The impact of global power supply ripple on VCO phase
conditions as much as possible. noise is captured as follows. A frequency-swept single-tone
The LDO schematic is shown in Fig. 9. The error amplifier sine wave is applied to the global power supply. The signal
of the LDO was implemented with a folded cascode amplifier, level of the power supply stimulus is around 100 mV peak
as shown in Fig. 14. The output node of the amplifier connects to peak, which is about 5% of the supply level. The power
WANG AND BAKKALOGLU: SYSTEMATIC DESIGN OF SUPPLY REGULATED LC-TANK VOLTAGE-CONTROLLED OSCILLATORS
Fig. 16. Measured LDO PSR and improvement of VCO phase-noise sensitivity
to power supply noise.
Fig. 17. Phase noise of VCO powered by 1.65-V battery or LDO with a 2-V
battery.
of the sine wave is measured in dBm and is referred to as
50- impedance. An FM spur at the same frequency can be
observed from the VCO phase noise curve. The phase noise
at that frequency is measured in dBc/Hz. The phase-noise
sensitivity to power supply is defined as the ratio of the phase
noise peak and the input sine-wave power. The measurement
result is plotted in Fig. 15. Positive supply sensitivity of the
phase noise for the pMOS and nMOS VCOs is designed to be
similar for characterization purposes. The measurement result
for the improved phase noise sensitivity to the power supply is
plotted in Fig. 16. The LDO power supply rejection function is
also potted in the same figure.
The implemented LDO has an output noise density less than
30 nV/ Hz for frequencies above 10 kHz. To evaluate the
contribution from LDO internal noise, the VCO phase noise is
measured at two conditions: 1) powered by either a low-noise
1.65-V dedicated battery and 2) powered by the LDO with a
2-V battery input and 1.65-V output voltage. The resultant VCO
1843
phase noise is shown in Fig. 17. The VCO spot phase noise from
these two cases is within 0.2-dB error margin, indicating that the
phase-noise contribution from the LDO noise is much less com-
pared with the contribution from the VCO internal noise.
VI. CONCLUSION
In this paper, the design issue of LDO-regulated low-noise
LC-tank VCO has been discussed. The power supply-noise-in-
duced VCO phase noise was analyzed from VCO power supply
frequency pushing. The frequency pushing effect arises from
both capacitance nonlinearities and switching device nonlinear
operations. The VCO power supply frequency pushing and
phase noise AM-PM conversion factor can be lowered by
decreasing the switching device width. The frequency char-
acteristics of LDO PSR and noise were analyzed in detail
regarding the zero and poles of the LDO open loop gain.
The tradeoff between high-frequency and moderate-frequency
LDO PSR and output noise can be made by tuning the series
resistance of the bypass capacitor. The LDO and VCO should
be designed together to meet the phase-noise specifications for
a given power supply noise profile.
ACKNOWLEDGMENT
The authors would like to thank Dr. T. Copani for valuable
technical discussions and suggestions.
REFERENCES
[1] R. Fetche, C. Fetche, T. Fiez, and K. Mayaram, “Analysis of the ef-
fects of supply noise coupling on phase noise in integrated LC CMOS
oscillators,” in Proc. 2000 IEEE Radio and Wireless Conf., Sep. 10–13,
2000, pp. 199–202.
[2] G. A. Rincon-Mora, “Current efficient, low voltage, low drop-out reg-
ulators,” Ph.D. dissertation, Sch. of Elect. and Comput. Eng., Georgia
Inst. of Technol., Atlanta, 1996.
[3] V. Gupta, G. A. Rincon-Mora, and P. Raha, “Analysis and design of
monolithic, high PSR, linear regulators for SoC applications,” in Proc.
IEEE Int SOC Conf., Sep. 12-15, 2004, pp. 311–315.
[4] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical
oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179–179,
Feb. 1998.
[5] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC
oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717–724,
May 1999.
[6] B. De Muer, M. Borremans, M. Steyaert, and G. Li Puma, “A 2-GHz
low-phase-noise integrated LC-VCO set with flicker-noise upconver-
sion minimization,” IEEE J. Solid-State Circuit, vol. 35, no. 7, pp.
1034–1038, Jul. 2000.
[7] E. Hegazi, H. Sjoland, and A. A. Abidi, “A filtering technique to lower
LC oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 36, no.
12, pp. 1921–1930, Dec. 2001.
[8] S. Levantino, C. Samori, A. Zanchi, and A. L. Lacaita, “AM-to-PM
conversion in varactor-tuned oscillators,” IEEE Trans. Circuits Syst. II,
Analog Digit. Signal Process., vol. 49, no. 7, pp. 509–513, Jul. 2002.
[9] A. Zanchi, C. Samori, S. Levantino, and A. L. Lacaita, “A 2-V 2.5-
GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wideband low-
noise automatic amplitude control loop,” IEEE J. Solid-State Circuits,
vol. 36, no. 4, pp. 611–619, Apr. 2001.
[10] J. W. M. Rogers, D. Rahn, and C. Plett, “A study of digital and analog
automatic-amplitude control circuitry for voltage-controlled oscilla-
tors,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 352–356, Feb.
2003.
[11] A. Jerng and C. G. Sodini, “The impact of device type and sizing on
phase noise mechanisms,” IEEE J. Solid-State Circuits, vol. 40, no. 2,
pp. 360–369, Feb. 2005.
1844 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 7, AUGUST 2008
[12] V. Kratyuk, I. Vytyaz, U.-K. Moon, and K. Mayaram, “Analysis of
supply and ground noise sensitivity in ring and LC oscillators,” in Proc.
IEEE Int. Symp. Circuits Syst., May 23–26, 2005, no. 6, pp. 5986–5989.
[13] A. Maxim, “A multi-rate 9.953-12.5-GHz 0.2- m SiGe BiCMOS LC
oscillator using a resistor-tuned varactor and a supply pushing cancel-
lation circuit,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 918–934,
Apr. 2006.
[14] D. Leeson, “A simple model of feedback oscillator noise spectrum,”
Proc. IEEE, vol. 54, no. 2, pp. 329–330, Feb. 1966.
[15] “SpectreRF User Guide, Product Version 5.0,” Cadence Design Sys-
tems, Inc., Sep. 2003.
Xuejin Wang received the B.S. and M.S. degrees
from Tsinghua University, Beijing, China, in 1999
and 2001, respectively. He is currently working
toward the Ph.D. degree at Arizona State University,
Tempe.
His research interests include low-noise VCOs and
LDOs. He was with Neolinear, Inc., from 2003 to
2004. He is now with Cadence Design Systems, Inc.,
Tempe, as a Lead Design Engineer.
Bertan Bakkaloglu (M’94) received the Ph.D.
degree from Oregon State University, Corvallis, in
1995.
He then joined the Mixes Signal Wireless Design
Group, Texas Instruments Incorporated, Dallas, TX,
where he was involved with analog, RF, and mixed-
signal front-ends for wireless and wireline commu-
nication integrated circuits. He was a Design Leader
involved with system-on-chip designs with integrated
battery management and RF, analog baseband func-
tionality. In 2001, he joined the Broadband Commu-
nications Group, where he was involved with cable modem analog front-end
designs and gigabit Ethernet front-ends. In 2004, he joined the Electrical En-
gineering Department, Arizona State University, Tempe, as an Associate Pro-
fessor. He holds three patents. His research interests include RF and power am-
plifier supply regulators, RF synthesizers, high-speed RF data converters, and
RF built-in self-diagnostic circuits for communication integrated circuits and
antennas.
Dr. Bakkaloglu has been a Technical Program chair for the International Sym-
posium on Circuits and Systems (ISCAS) and IEEE Microwave Theory and
Techniques (MTT)/RF Integrated Circuit (RFIC) Conference.