GN001 Application Guide

Design with GaN Enhancement mode HEMT

Updated on JAN-24-2018
GaN Systems Inc.
GaN Systems – 1
Agenda

 Basics

 Gate Drive Design considerations

 Design examples

 PCB Layout

 Switching Testing results

Latest update JAN-18-2018

Please visit http://www.gansystems.com/whitepapers.php for latest version of this document

GaN Systems – 2
Fundamentals of GaN HEMT
GaN Enhancement mode High Electron Mobility Transistor (E-HEMT)
 Lateral 2-dimensional electron gas (2DEG) channel formed on AlGaN/GaN hetero-
epitaxy structure provides very high charge density and mobility
 For enhancement mode operation, a gate is implemented to deplete the 2DEG
underneath at 0V or negative bias. A positive gate bias turns on the 2DEG channel
 It works just like MOSFET except better switching performance
IDS vs. VDS characteristics
VDS VDS
200
VGS = 6V
- + - +
IDS (A) 180
160 VGS = 5V
+ 140
0V
VGS = 4V
Gate Gate 120
Source P-GaN Drain Source P-GaN Drain
AlGaN Barrier Layer AlGaN Barrier Layer 100
VGS = 3V
GaN Buffer Layers
2DEG Channel
GaN Buffer Layers 2DEG Channel 80
60
Si substrate Si substrate 40
VGS = 2V
20
0
VDS (V)
0 5 10 15 20
Substrate Substrate

GaN Systems – 3
E-HEMT Gate characteristics
Common with Si MOSFET Drain
 True e-mode normally off
 Voltage driven - driver charges/discharges CISS
 Supply Gate leakage IGSS only RG,ext Gate RG,intCGD
 Easy slew rate control by RG CDS
CGS
Differences
 Much Lower QG : Lower drive loss; faster switching
CISS = CGD+CGS
 Higher gain and lower VGS : +5-6V gate bias to turn on Source
 Lower VG(th): typ. 1.5V

Versus other e-mode GaN GaN Systems

Gate Bias Level Si MOSFET IGBT SIC MOSFET
GaN E-HEMT
 More robust gate: +7/-10V DC max rating
 No DC gate holding current required Maximum rating -10/+7V +/-20V +/-20V -8/+20V
 No complicated gate diode / PN junction Typical gate bias
0 or-3/+5-6V 0/+10-12V 0 or -9/+15V -4/+15-20V
values

GaN Systems – 4
Reverse Conduction Characteristics

Gate GaN E-HEMT MOSFET Si IGBT

GaN Reverse I/V Curve

A
A ON
RDS(ON)

ON
B RDS(ON)

B
VTH+VGS(OFF)
C
C OFF

RDS(REV)

 No body diode，but 2DEG can conduct in 3rd quadrant – No need for anti-parallel diode
 When gate is OFF (during dead time)， 2DEG exhibits like a diode with VF= Vth+ VGS(off)
 Reduce dead time loss: 1) minimize dead time; 2) Use smaller or avoid negative VGS if possible
GaN Systems – 5
Reverse recovery performance
Reverse Recovery charge QRR:
 GaN has zero QRR making it suitable for half bridge hard switching – Replace IGBT
 Si MOSFET can’t be used for any half bridge hard-switch circuit due to QRR
 Excellent reverse recovery of GaN enables new topologies such as bridgeless totem pole PFC

Half bridge turn-on 400V/20A – SJ MOSFET Half bridge turn-on 400V/20A – GaN E-HEMT

GaN EON = 92µJ

Snappy recovery : VDS
1. High dIRR/dt,
Si MOSFET QRR parasitic ringing
2. Body diode
Loss = 6670uJ! Math: VDS * ΙD
ruggedness Qoss Loss only:
1. Much lower turn-on loss
2. No snappy recovery and ΙD
uncontrolled high dIrr/dt
3. Clean waveforms
VGS

GaN Systems – 6
Setting up dead time
 For hard switching: td_pwm must be > tdelay_skew + (td(off) - td(on)):
 Gate turn-on/off delay difference varies with RG: typical +/-5ns range (GS66508)
 High/low side gate driver delay skew (worst case delay mismatch) usually dominates:
 Example Silab Si8261 isolated gate driver tdelay_skew_max = 25ns. In this case the dead
time must be set > 30ns as minimum
 However in practical circuit safety margin must be considered: for GS66508 typical
50-100ns is chosen for dead time
 For soft switching dead time needs to be chosen for achieving ZVS transition
 For 100V: smaller can be used (10-20NS) as 100V driver has better delay matching
VDS td(off) td(on) tr
VGSH
VGS_Q1 VGS_Q2

VGSL
PWM signal dead time td_pwm
Actual dead time
Td_actual ~= td_pwm - tdelay_skew - td(off) + td(on)
GaN Systems – 7
Agenda

 Basics

 Gate Drive Design considerations

 Design examples

 PCB Layout

 Switching Testing results

GaN Systems – 8
Design Considerations – fast switching
GaN switches faster than Si/SiC MOSFETs with dv/dt > 100V/ns
 GaN shows 4x faster turn-on and ~2x faster off time than state of art SiC MOSFET with similar Rds(on)

GaN E-HEMT GS66508T

VDS=400V (650V/50mΩ) VDS=400V

Cree SiC C3M006509D (900V/

GaN E-HEMT SiC
65mΩ)

5.7ns
10ns
17ns (18V/ns)
4.5ns (90V/ns)

Vgs=12V/-3V (SiC) Vgs=12V/-3V (SiC)

Vgs=6V/-3V (GaN E-HEMT) Vgs=6V/-3V (GaN E-HEMT)

VGS

Double Pulse Test Hard Switch Turn-on

(VDS=400V, ID=15A, RG(ON)=10Ω)
Hard Switching Turn-off (VDS = 400V, ID = 15A, RG(OFF)=1Ω)

GaN Systems – 9
Design Considerations
Design considerations for driving high speed GaN E-HEMTs:
Controlling noise coupling from power to gate drive loop should be the first priority:
 High dv/dt and di/dt combined with low CISS and VG(th) → Need to protect gate spikes from going above
threshold or maximum rating under miller effect for safe operation
 Gate ringing or sustained oscillation may occur if the design is not done properly and may lead to
device failure. We will discuss how to mitigate that in this section
 On the other hand, the switching performance of GaN should not be compromised too much
 This is more critical for 650V hard switching half bridge application as very high dv/dt could occur at
hard turn-on.
 Single end topology has less concern with miller effect, and for resonant ZVS topology the dv/dt and
di/dt are lower so their design requirement may be relaxed.

In this section we will walk through the design tips on how to control miller effect and mitigate gate
ringing/oscillation, followed by gate driver recommendations

GaN Systems – 10
Control miller effect
Gate drive impedance (Rg and Lg) is critical for turn-off, but less at turn-on
Basic rule: the gate needs to be held down as strong as possible with minimum impedance
Miller effect is more prominent at 650V than 100V design due to the higher dv/dt
Positive dv/dt Negative dv/dt
VDS VDS
LD
LD CGD
LG RG
CGD CDS
LG RG imiller CGS
CDS ROL
imiller CGS LCS
ROL
LCS VGS+_pk LS
LS VGS
VGS VGS-_pk
 Prevent false turn-on  Occurs at turn-on of the complementary switch in half
 Strong pull-down (low RG/ROL) bridge
 Low LG to avoid ringing  Keep VGS-_pk within -10V
 Use negative gate bias, -2 to -3V  Strong pull-down (low RG/ROL) and low LG for lower ringing
is recommended  VGS may bounce back >0V (LC ringing): ensure VGS+_pk < VG(TH
to avoid false turn-on or gate oscillation GaN Systems – 11
Control miller effect
 For negative dv/dt, it is important to have a low-Z path for the reverse miller current to reduce the
negative VGS spike (and the ringing afterwards caused by LC resonance)
 Pay attention to the VGS spike around VDS <50V due to the change of non-linear CISS/CRSS ratio
 A clamping diode is recommended for gate drive with single output. For gate drive with separate
sink output the diode may not be needed depending on the RG and LG in the circuit
 For bipolar gate bias, use a TVS diode in series with the clamping diode (or two back to back)
 CGS may not help in some cases, be careful! ( induce LC resonance with Lgate and LCS)
 Negative gate bias can help to prevent false turn-on, but ensure worst case Vgs-_pk within -10V
High dv/dt when the RON=20Ω, no DCLAMP RON=20Ω with DCLAMP
VDS other switch is being
CGD
turned on 6V Gate
RGON
DriverVO
GND CGS
RGOFF D1
Dclamp
LCS
0V
<0V +6V
VGS VDD D
RGON -13V
-3V Gate VO+ -2V
RGOFF G
Driver
-7V VO- DZ1 S
VEE -3V 3V3
D2
GaN Systems – 12
Control miller effect
Select right gate resistor D
 GaN E-HEMT speed can be easily controlled by gate resistors Gate
RGON
G
 Critical to choose the right RG(ON)/RG(OFF) ratio for performance and drive Driver VO

stability GND RGOFF D1

S

 Separate RG for turn-on and off is recommended

 Recommend RG(ON)/RG(OFF) ≥ 5-10 ratio for controlling the miller effect Low Vf Schottky Diode

 GaN has extremely low Qg and drive loss: most cases 0402/0603 SMD
resistors can be used Gate driver w/ single output
 Turn on RG(ON):
 Control the turn-on dv/dt slew rate RGON D
 Too high RG(ON) slows down switching and increases loss Gate VO+
G
RGOFF
 Too small RGON: High dv/dt -> Higher switching loss due to the Driver VO-
S
miller turn-on and potential gate oscillation GND

 For GS66508: recommend to start with RG(ON) = 10-20Ω

 Turn off RG(OFF): Gate driver w/ separate outputs
 Typical starting value range is 1-2Ω
 Provide strong and fast pull-down for robust gate drive (Preferred)

GaN Systems – 13
Mitigate gate ringing/oscillations
What causes the gate ringing/oscillation?
 Gate over/undershoot and ringing caused by high LG LD
 Common Source Inductance LCS Feedback path from power to gate loop (di/dt) LG RG CGD
 Capacitive coupling via miller capacitor CGD (dv/dt) CGS
 Noise coupling via test probe LCS
LS
What to do if gate ringing/oscillation occurs?
 First improve the layout by reducing LG, LCS and external G-D coupling: FB1
RG1
 Locate driver as close to gate as possible
 Low inductance wide PCB trace and polygon
Z=10-20

 Use kelvin source connection to minimize LCS LCS

 Select right RG to tune turn-on slew rate

 Try negative gate bias (-3V) for turn-off
 At last resort try circuits below to damp the high frequency LC ringing & LG RG1

overshoot: 3.3 RS1

 Use a ferrite bead with Z=10-20Ω@100MHz in series with gate. (ferrite 100-200pF CS1 LCS
bead may increase LG but damp the high frequency gate current ringing)
 RC snubber across G-S: example R=3.3/C=200-470pF
GaN Systems – 14
High side driver considerations
High side gate drive
 GaN enables fast switching dv/dt >100kV/us:
VCM
ICM
0V
 Minimize Coupling capacitance CIO CIO

 CM current via CIO limits CMTI Isolated DC/ ICM

VCC
DC D
 Use isolator/isolated gate driver with high CMTI RG_ON
G
 Full Isolated gate drive: PWM Isolator Gate Driver RG_OFF
S
 Best performance CIO
 Isolation power supply – Minimize inter-winding 0V ICM
0VGDH
Capacitance High side floating ground VCM

 Bootstrap:
Optional common mode choke at input side
 Common for lower voltage 100V half bridge design to suppress CM noise
 Lower cost and simpler circuit ICM
 Choose the bootstrap diode with low CJ and fast
recovery time. Watch for bootstrap diode power VCC CIO

loss limit and recovery time for high-frequency Isolated DC/

operation.
DC

 Post-regulation or voltage clamping may be required

after bootstrap High side floating ground
GaN Systems – 15
 Bootstrap circuit
 Good for low cost 0-6V gate drive
 What is the problem with traditional bootstrap circuit?
 GaN E-HEMT requires good regulation of gate bias (5-6V bias, max rating 7V)
 LS free wheeling: Switch node negative voltage overcharges bootstrap capacitors (VGS>7V)
 HS free wheeling: Bootstrap diode voltage drops reduces VGS below 6V
 Post-regulation or voltage clamping to ensure high side bias is tightly regulated to 6V
Can be over-charged to 7-9V Bootstrap with post-regulation using Bootstrap for Sync Buck (only need
+6V
DBS
VDRVH +9V for regulated high side bias to clamp overcharge, example
VBUS+
Use LDO to regulate to 6V 100V sync buck)
0.6V CBOOT +9V LP2985IM5-6.1 +6V
R1
D IN OUT +6V VDRV
0VGDH RG_ON DB1
G GND C1
0V Gate Q1
PWM_H Isolator RG_OFF CB1
Driver S DB1
DZ1 C1
0V 0VGDH 5.8V
0VGDH
VOUT Use Zener diode 0V
0V 0VGDH
+9V +6V
-2 ~ -2.5V D - 1K
RG_ON G
Q2
VSD DB1 Simple Zener diode to clamp to 6V
Gate DZ1 C1
PWM_L Driver RG_OFF +
S CB1 5.8V

GND 0V 0VGDH
GaN Systems – 16
Recommended GaN driver/controller ICs
Following drivers have been verified by GS and are recommended for design with our GaN E-HEMTs：
Configurations
650V Half/Full Bridge:
1. DC/DC: LLC, PSFB,
Sync Boost/Buck
2. AC/DC: Totem pole
PFC, Active Clamp
Flyback
3. Inverter, motor drive
80-100V Half/Full bridge
1. 48V DC/DC
2. 48V POL
3. Sync. Buck/Boost
4. Class D Audio
5. Wireless Power
Transfer
Gate Driver/Controller IC
Si8271 – Single;
Si8273/4/5 – HB/Dual
-GB (0-6V) or –AB (-3/+6V)
ADuM4121ARIZ (0-6V Drive)
ADuM4121BRIZ (-3/+6V Drive)
ACPL-P346
Use -4/+6V gate drive
LM5113(NRND): 100V, max 5MHz
LMG1205: 80V/5A HB Driver
PE29101: 100V, 48V DC/DC,
33MHz
PE29102: 60V, Class D Audio,
WPT, 40MHz
UPI Semi GaN FET drivers:
uP1966A: Dual-Channel GaN
driver
Design resources
Si827x Datasheet
Si8271 demo board (GS66508T)
IMS evaluation board User Guide
ADuM4121 Datasheet
ACPL-P346 Datasheet
ACPL-P346 Evaluation Board with
GS66508T
LM5113 Datasheet
LMG1205 Datasheet
PE29100 Datasheet
PE20102 Datasheet
PE29102 Demo board (GS61004B)
uP1966A GaN Driver
Ultra High Speed 80V HB Driver for
GaN Application
GaN Systems – 17
Recommended GaN driver/controller ICs
Configurations Gate Driver/Controller IC Design resources
Low side non-isolated LM5114/UCC27511: Single LM5114 Datasheet
driver for 650V/100V GaN*: Channel, 4A, 5-6V drive UCC2751x Datasheet
1. Flyback, Push-pull UCC27611: w/ internal LDO (5V)
2. Forward
uP1964 Datasheet
3. Boost PFC uP1964: Internal LDO for 6V drive
4. Secondary SR
5. Class E P/A Other GaN IXD609SI: Single, 6V drive, high drive current (9A)
compatible FAN3122/TC4422: Single, 6V drive, high drive current (9A)
drivers FAN3223/4/5: Dual 4A, 6V drive, for push-pull or SR application
Sync Buck DC/DC (100V LTC7800: 60V, Sync. Step-Down LTC7800 Datasheet
GaN): Controller (up to 2.2MHz, w/
1. 48V-12V DC/DC integrated GaN compatible drivers)

Secondary side NCP4305A: 5V gate drive clamp, NCP4305 Datasheet

Rectification (100V GaN): 1MHz max
1. High frequency LLC
2. Flyback SRK2001: Adaptive SR controller SRK2001 Datasheet
for LLC, 5-6V drive for GaN,
500KHz max

[*] – low side non-isolated drivers can also be used on high side / half bridge configurations by combining with level-shift /
signal isolators, see page 29 for design example. GaN Systems – 18
Agenda

 Basics

 Gate Drive Design considerations

 Design examples

 PCB Layout

 Switching Testing results

GaN Systems – 19
650V Isolated Driver Design #1 – 0-6V drive
VDD: 5/9 or 12V depending on system Si8271-based isolated driver (0-6V drive) 6V LDO for tight VDRV regulation
power rail

Optional CM Choke for better noise

immunity against dv/dt

Choose isolated DC/DC PS1:

• 5/9/12V to 9V, 1W, 3kV isolation
• Low CIO preferred for dv/dt immunity Keep this loop
• Verified/Recommended P/N: routing as tight as
• RECOM R1S-xx09/HP possible
• Mornsun Fxx09XT-1WR2

PWM Input:
• 3.3V or 5V logic from controller
• Optional RC filter for noise filtering
• Consider driver w/ deglitcher (-IS1
suffix) for noisy environment

Enable: Gate resistors:

• Direct tie to VDDI if not used Isolation 1. Turn-on RGATE R2: typ. 10-20Ω
• Recommend filter cap (100nF) close 2. Turn-off RGATE R3: typ. 1-2 Ω
to EN pin to prevent false triggering Recommended for high-frequency ZVS application
GaN Systems – 20
650V Isolated Driver Design #2 – bipolar drive
Si8271-based isolated gate driver (-3/+6V drive)
• Lower risk of cross-conduction
and gate oscillation, faster
turn-off (lower switching loss)
• Higher reverse conduction
loss
• Recommended for hard-
switching or high power
applications

DZ1 and R2 divide 9V into -6V and

+3v gate bias. The mid-point is
used as a ground 0V which should
be connected to the SS of GaN
device

• Place bypass cap C7/C8 close

to U1 VDD/GND
• Keep loop between U1 and Q1
Gate/SS as tight as possible
• Higher UVLO driver can be used

GaN Systems – 21
Bootstrap Half bridge gate driver
Recommended for low cost high frequency soft switch half bridge circuit (ACF, LLC etc)
DB1 GS66504B
SI8273
Use fast recovery low CJ diode for
Bootstrap:
• C3D1P7060Q
• UFM15PL
• ES1J

LLC test waveform (400V/1.3A 600kHz)

GaN Systems – 22
Other 650V driver design reference
ADuM4121ARZ-based isolated gate driver for GaN HEMT (0-6V drive)

GaN Systems – 23
Other 650V driver design reference
Isolated gate driver based on ACPL-P346 (-4/6V)

Half Bridge Board Reference Design

GaN Systems 650V E-HEMT GS66508T (30A/50mΩ) transistor
Broadcom 2.5A gate drive optocoupler, ACPL-P346
https://docs.broadcom.com/docs/ACPL-P346-RefDesign-RM101
GaN Systems – 24
 100V half bridge GaN driver – PE29101
U1
J2 6V REG
1 9V_EXT 1 5
IN OUT VCC_6V

A98235
2
C1
1.0 µF
0603
2

3
GND
4
C2
2.2 µF
0603
R17
DNI
0603
• 80V HB driver for GaN
ON_OFF BY PASS R18

• Support 6V gate drive

C3
10 nF DNI
0603 0603 TPSMD1
5017 CON1
575-8
VCC_6V
R23
D1
BAS70LP-7
R2
VIN+
BANANA JACK

1
• 48V DC/DC application
HSB

DNI
R24
0
0603 C7
0.10 µF
0603 CR1
C17
1 µF
100V
C16
1 µF
100V
C15
1 µF
100V
C13

(DNI)
C12

(DNI)
C11

(DNI)
C10

(DNI)
+

CON2
575-8
• High frequency (>5MHz)
• Dead time adjustable
0 CZRU52C6V2 (DNI) BANANA JACK

VIN- 1
VDDsy nc

• Small low inductance Pkg

HSS
VCC_6V
JP4
TSW-103-07-G-S
HDR_1X3_0.100"_VT TPSMD2
1 C9 5017
2 0.10 µF
3

U4
15 0603
Q1
GS61008P DS
PE29101

1
PE29101
D
VDD

3
HSB
G

6 R8 4.7 OHM 2 TPSMD3

10.6mm
HSGpu HS1 5017
1
S

1 R9 CON3
HSGpd

4
575-8

3
2 BANANA JACK
8 HSS L1
IN 14 3.3uH ±20% VOUT+ 1
LSB Q2
R5 EN 7 9 R10 4.7 OHM GS61008P DS

1
PR1 DNI EN LSGpu R14
R21 20K R11 1
PROBE 0402 16 12 D

DNI
RDHL LSGpd
Vddsync

0402 R22 20K 0603 C18 C19 C20 C21 C22 C23
5 13 PR4 D2 1.0 µF 1.0 µF 22 µF 22 µF 22 µF (DNI)
GND

LSO

RDLH LSS
G

2 PROBE BAS70LP-7B (DNI) 0603 0603 1206 1206 1206

0402
CCW

CCW

HS1 C24 CON4

1

R12 DNI 575-8

11

10

500K

4
0603 BANANA JACK

3
2 2 R13
WIPER WIPER 500K VOUT- 1
VDDsy nc
R6 R7
CW

CW
3

DNI DNI
0402 0402
R1
T1 DNI TPSMD4
0603 5017
R4
DNI
0603

JP3 VCC_6V
TSW-103-07-G-S U3
HDR_1X3_0.100"_VT NC7S08P5XCT
1 1 5
2 IN A VCC

11.7mm
3 R3 2
10K IN B
0603 3 4
GND OUT Y
C28 C8
1.0 µF DNI
0603 0603

http://www.psemi.com/newsroom/new-products/666336-pe29100-gan-fet-driver
GaN Systems – 25
100V half bridge GaN driver – PE29102
PE29102 - 60V HB GaN driver optimized for high frequency applications:
• Class D Audio, DC/DC and wireless power charging

100 V GaN Full Bridge EVB optimized for

Class D Amplifiers

For more details: http://www.gansystems.com/gs61004b-evbcd.php

GaN Systems – 26
Non-isolated low side driver for GaN
• For single-ended applications (Class E, Flyback, Push-pull etc), or
• Used to adapt MOSFET gate drive bias to 5-6V drive for GaN (low or high side)
LM5114 low side driver
9-12V Aux power
uP1964 GaN Driver VIN ADJ

LDO LDO

• integrated regulator LDO5

5V
UVLO
DRV
VDRV

GND OUTH

for 6V bias PWM OUTL

• 5V LDO PWMB GND

•
+9-12V VDD_+6V
VDRV_IN
C19 R27 R26

1uF 1K 5.1K
VDD_RTN
DRAIN
U9
VAUX_+5V 1 10 1
2 VIN ADJ 9 R29 10R
LDO5 VDRV Q4
3 8 2
C20 4 GND1 OUTH 7 GS665XX
1uF PWM OUTL R30 2R

EXPAD
5 6
PWMB GND2 4
R28 3
C21 5.1K
PWM IN
1uF

11
UP1964
VDD_RTN WDFN3X3-10L
VDD_RTN
SOURCE

From controller logic signal (3.3/5V) or

MOSFET driver output (up to 14V) GaN Systems – 27
Non-isolated low side driver for GaN
Isolated GaN driver for high side / half bridge using low side driver + signal isolator or HB driver
• Overcome frequency and drive performance limit of previous isolated driver solution
• Adapt to existing controllers/half bridge driver (ensure the driver is capable of handling high dv/dt)
• Improved gate drive loop by locating LS driver close to GaN
5V for isolators

5/9/12V

Place U4 close to
Q1 and keep the
loop tight

Isolation
GaN Systems – 28
Agenda

 Basics

 Gate Drive Design considerations

 Design examples

 PCB Layout

 Switching Testing results

GaN Systems – 29
GaN Systems Innovation - GaNPx
Traditional PQFN + Wire Bond
Innovative packaging for high speed GaN device:
 Extremely low inductance: high frequency switching
 Near Chip Scale embedded Packaging
 No wire bonding: high reliabiliy
 Better CTE match to PCB：Temp cycle reliability*
 Lower thermal resistance RthJC
TO-247
500

400

GaNPx

Vds_Si / V
300

200

Ls = ~10-15nH 100

G -0
3.02 3.04 3.06 3.08 3.1 3.12 3.14 3.16 3.18 3.2
D
S Time/uSecs 20nSecs/div

 High dv/dt
 Low VDS overshoot LSource<0.2nH

Embedded GaNPxTM  Better EMI

[*] GaNPx passed 1000hr IPC9701 solder joint reliability test, condition：12-Layer 2.5mm PCB，
5oz inner copper and 2oz outer copper。 GaN Systems – 30
PCB Layout Checklist
 Design for GaNPx embedded package LP1

 GaNPx bottom cooled B/P LD1

CGD_ext1
 GaNPx Top cooled LG1 RG1
Gate Q1
 Thermal design Driver

 Optimize and minimize layout parasitics in CISO

LG2
LM1 LCS1
LLoop
following orders :
LS1
1. Common source / mutual inductance LCS
0V
CDC_LINK
2. Gate loop inductance LG LD2
CGD_ext2
3. Power Loop inductance Lloop Gate LG3 RG1 Q2
4. Drain to gate loop capacitance CGD_ext Driver
LM1 LCS2
5. Isolation coupling capacitance CISO LG4

LS2
0V LP2

GaN Systems – 31
 GaNPX™: Bottom cooled B type family
 Embedded package with extremely low inductance
 GS66508B includes dedicated kelvin source pin (SS)
 PCB cooling using thermal pad (S) and vias or metal core PCB for high power application
GS66508B (650V, 30A, 50mΩ) DRAIN
D GS66508B

S
0.5mm
SOURCE

SS G
Top side Bottom side G SS

GATE DRIVER Thermal vias

Use SS pin for gate return

GS66504B/GS66502B (650V, GS61004B (100V/45A, 15mΩ)
DRAIN

15/7A, 100/200mΩ) GS66504B

D G
D
4.4mm

S G SOURCE

S G
0.5mm
0.5mm
Gate Return Main Current Flow

Create Kelvin source on PCB

GaN Systems – 32
GaNPX™: Bottom cooled P type
 Similar to B type except substrate (thermal pad) is floating on the package
 Use SS pin for kelvin source connection
 The thermal pad must be always connected to its source pin on PCB

GS61008P (100V/90A, 7.5mΩ)

D
DRAIN
Thermal pad G
(substrate) SS

Gate Thermal Pad (connect

S
to Source)
SS

Gate Return SOURCE

GaN Systems – 33
Layout best practice – Gate Drive
1 Use/create kelvin source to separate drive Non-isolated control
return and power ground (low LCS ). ground 0V

Physically separate high current loop and

drive loop areas to minimize noise coupling DRAIN

2 Minimize pull-down loop (Gate→R3 → GS66508B

5
U1 → C2 →GS_RTN, locate U1 and C2 4
close) GD_RTN
SOURCE

3 Minimize turn-on (pull-up) loop (locate VDD_6V

Gate Kelvin

C1 close)
C1 Source
3
R2

4 Isolate and avoid overlap between gate Si8271

R3
2 R4
1 Main current flow

drive and Drain copper pour C2

GD_RTN
Mid/bottom layer VEE_-3V
5 Isolate and avoid overlap from VDD
Drain/Source to the control grounds U1
C1
GD_RTN
DRAIN1

(CMTI, dv/dt) PWM_IN R1 1 8 1uF 1

VI VDD
10 2 7 R2 GATE 2 Q1
VCC_+5V VDDI VO+
10 R3 GS66508B
3 6 3
GD_RTN C3 GNDI VO- R4

4
1uF ENA 4 5 2 10k
EN GNDA VEE
SI8271AB-IS C2 PGND
1uF
0V
GD_RTN

GaN Systems – 34
Layout best practice – Gate drive with Top-cooled package
1 GaNPx T package located at bottom side for
heatsink attachment DRAIN
(bot side)
2 Create kelvin connection to the source
for Gate drive return (bottom side)

3 Use multiple vias for lower gate inductance GD_RTN

from bottom to top side
C1
GS66508T
4 Use one gate and keep the other floating 4
Gate R2 (bot side)
Driver Gate
VDD R3 G Source G
C1 DRAIN1
U1 GD_RTN
PWM_IN R1 1
VI VDD
8 1uF 1 1
Q1 C2
42

10 2 7 R2 GATE
VCC_+5V VDDI VO+ GS66508T
3
GNDI VO-
6 10 R3
R4
3
3

C3 2 10k
1uF ENA 4 5 GD_RTN
EN GNDA VEE Main
SI8271AB-IS C2
1uF current flow
0V
GD_RTN
2

GaN Systems – 35
Layout best practice – Half bridge power stage
Design the half bridge power stage with tight loop and low inductance
Layout guidance Half bridge design 1 Half bridge design 2
• Recommend to use 4-Layer PCB Use layer 2 as ground return (4-layer PCB) Only use top layer for power loop
• Use 2nd layer as ground return GaN E-HEMTs
Decoupling
Caps GaN E-HEMTs
• Use SMD MLCC decoupling caps PGND

and locate them close to GaN

TOP LAYER
PGND VSW VIN+
LAYER 2 TOP LAYER
PGND
PGND VIN+
• Use multiple decoupling caps to LAYER 3
Layer 2
reduce ESR/ESL and create LAYER 4 VSW

balanced power loop

PGND
• Locate drivers close to the gate
VIN+
Use kelvin source for driver
Gate
• VIN+
Driver

VSW
return Gate
VSW
Driver PGND

Gate
Driver
Gate
Driver PGND

GaN Systems – 36
Agenda

 Basics

 Gate Drive Design considerations

 Design examples

 PCB Layout

 Switching Testing results

GaN Systems – 37
Switching Test – GS66508B Half bridge Eval board
Decoupling Capacitors

Si8271GB Isolated drivers

Recommended Switching node

probe position for Eon/Eoff
measurement

Isolation Barrier Optional current shunt

VGS probe
Use copper foil to short if not used
PWM Signal/+5V VCC connector VDC- VDC+ VSW
GaN Systems – 38
 GS66508B-EVBDB PCB Layout
GND
0V_GDH
GND
VDC+

VSW VSW

0V_GDL

GND

Top Layer Mid layer 1

GND GND

VSW
VSW

GND

Mid layer 2 Bottom Layer

GaN Systems – 39
Double pulse switching test
 GS66508B hard switched VDS=400V, ID=30A, RGON=10Ω, RGOFF=1 Ω
up to 400V/30A 30A
Inductor current IL
VDS 400V
VDC+

LOUT
+ Q1
IL
VDS
400V DC VSW

Q2
VGL

VGS

GaN Systems – 40
GS66508 Double pulse switching test
VDS=400V, ID=30A Hard Switching Turn-on VDS=400V, ID=30A Hard Switching Turn-off

Estimated Loop inductance = 3nH

IL = 30A IL = 30A
VDS dip due to VDS peak = 450V
VDS = 400V loop inductance:
∆V=Lp*di/dt Peak Turn-off
dv/dt>100V/ns
Peak turn-on tr = 3.9ns
dv/dt=80V/ns

VGS
Clean VGS waveforms Clean rising edge w/ low Vds
overshoot (low loop inductance)

GaN Systems – 41
Summary
 This application guide summarized the key design considerations for GaN Systems GaN E-
HEMTs. We started with the fundamental aspects of GaN E-HEMTs and then the gate
drive design considerations were discussed. A list of recommended drivers and several
gate drive reference designs were provided.
 The second part of this guide focused on the PCB layout and discussed the layout best
practice by using GaN Systems Embedded package GaNPx.
 At last a real half bridge evaluation board design following the design recommendations
in this document was built and its switching performance was tested.
 The switching test results showed fast and clean hard switching waveforms up to full
rated current 400V/30A with minimum ringing/overshoot. This concluded that with
optimum gate drive and board layout combined with low GaNPx inductance, GaN E-
HEMTs exhibit optimum switching performance

GaN Systems – 42
Design resources

 Datasheets, spice models: http://www.gansystems.com/transistors.php

 Evaluation boards: http://www.gansystems.com/eval-boards.php

 Application notes: http://www.gansystems.com/whitepapers.php

 PCB Footprint libraries: http://gansystems.com/design_library_files.php

 FAQ: http://www.gansystems.com/faq-e-mode-hemts.php

GaN Systems – 43
Tomorrow’s power today TM

www.gansystems.com • North America • Europe • Asia

GaN Systems – 44