DESIGN AND PERFORMANCE ESTIMATION

OF FIR FILTER USING NULL CONVENTION

LOGIC
A Thesis Submitted
In Partial Fulfillment of the requirements
For the Degree of

MASTER OF TECHNOLOGY
in
(Microelectronics)

by
TOUSHIBA KHAN
(Roll No. 1705267015)

Under the supervision of

DR. S.R.P. SINHA
Prof. Dept. of Electronics Engineering
in IET, Lucknow

`to the
Department of Electronics Engineering
Institute of engineering and technology, Lucknow
Dr. A.P.J. Abdul Kalam Technical University, Lucknow
June 2019
 DECLARATION

I hereby declare that the work presented in this report entitled "DESIGN AND
PERFORMANCE ESTIMATION OF FIR FILTER USING NULL
CONVENTION LOGIC" was carried out by me. I have not submitted the matter
embodied in this report for the award of any other degree or diploma of any other
university or Institute. I have given due credit to the original authors/sources for all the
words, ideas, diagrams, graphics, computer programs, experiments, results, that are not
my original contribution. I have used quotation marks to identify verbatim sentences
and given credit to the original authors/sources. I affirm that no portion of my work is
plagiarized, and the experiments and the results reported in the report are not
manipulated. In the event of a complaint a plagiarism and the manipulation of the
experiments and results, I shall be fully responsible and answerable.

Name: Toushiba Khan

Roll No.: 1705267015

Branch: Microelectronics

ii
 CERTIFICATE

This is to certify that the project entitled, “Design and Performance estimation of FIR Filter
using null convention logic" submitted by "Toushiba khan" in partial fulfillment of the
requirements for the award of "Masters in Technology" in "Microelectronics" at the
"Institute of Engineering and Technology" is an authentic work carried out by her under my
supervision and guidance.

DATE: SUPERVISOR

Dr. S.R.P. Sinha

(Professor, IET,Lucknow)

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 ABSTRACT

The design of low-power very large scale integration (VLSI) systems has been the area of
focus of many research groups for developing variety of mobile communication and
computing systems in past few decades. The sub threshold circuits are found to be suitable for
many portable devices, including medical implantable devices. In such systems, energy
efficient circuits are expected for signal processing applications. In general, the digital signal
processing (DSP) systems widely use FIR filters for implementation. This has motivated the
research to develop efficient filters to reduce the power requirement and to improve the
packing density of the chip. In the past two decades, many researchers have reported various
techniques to reduce power consumption using CMOS transistors.

In VLSI circuit design, the Null convention logic (NCL) gates are distinctive case of the
available logical gates or operators. Such an operator consists of SET and RESET conditions
and both are not satisfied at the same time. If neither condition is satisfied, the operator
preserves its current state. FIR filter is designed using NCL at 90nm CMOS technology and
simulated using HSPICE and DSCH. Using NCL CMOS model 22.4% power reduction can
be achieved at 1.2 V compared with Static CMOS logic. However, the number of transistor
doubles in NCL CMOS model and it is operated in high speed compared to Static CMOS
model.

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 ACKNOWLEDGEMENT

I would like to express my special thanks of gratitude to my supervisor (Dr S.R.P.Sinha) as

well as our head of the department (Dr. Subodh Wairya) who gave me the golden opportunity
to do this wonderful dissertation on the topic (“ Design and Performance estimation of FIR
Filter using null convention logic”), which also helped me in doing a lot of Research and i
came to know about so many new things I am really thankful to them. Secondly I would also
like to thank my parents and friends who helped me a lot in finalizing this project within the
limited time frame.

Name: Toushiba Khan

Roll No.: 1705267015

Branch: Microelectronics

v
 TABLE OF CONTENTS
Declaration.......................................................................................................................ii
Certificate........................................................................................................................ iii
Abstract........................................................................................................................... iv
Acknowledgement ...........................................................................................................v
List of Tables....................................................................................................................viii
List of Figures...................................................................................................................ix-x
List of Symbols and Abbreviations..................................................................................xi-xii
CHAPTER 1...................................................................................................................1-8
INTRODUCTION
1.1MOTIVATION FOR LOW POWER FILTER DESIGN........................................1-2
1.2 LEVEL OF MINIMIZING POWER CONSUMPTION........................................2-3
1.3 POWER DISSIPATION.........................................................................................3
1.3.1 Static Power Dissipation..................................................................................3-4
1.3.2 Dynamic Power Dissipation............................................................................4-5
1.3.3 Short Circuit Power Dissipation......................................................................5-6
1.3.4 Total Power Dissipation.................................................................................6
1.4 FINITE IMPULSE RESPONSE FILTER...............................................................6-7
1.5 SUMMARY.............................................................................................................7-8
CHAPTER-2....................................................................................................................9-14
LITERATURE REVIEW
CHAPTER-3 ...................................................................................................................15-34
DESIGN AND PERFORMANCE ESTIMATION OF FIR FILTER USING NULL
CONVENTIONAL LOGIC
3.1 INTRODUCTION.................................................................................................15-16
3.1.1 Delay Insensitivity..........................................................................................16-19
3.2 NCL LOGIC GATES.............................................................................................19-34
3.2.1 Transistor Level Implementation.....................................................................20-22
3.3.2 Static CMOS Implementation ........................................................................23-24
3.3.3 Semi-Static CMOS Implementation...............................................................25-26
3.3 BASIC GATES AND ADDERS USING NCL......................................................27-34

vi
CHAPTER-4..................................................................................................................35-46
RESULTS AND SIMULATIONS
CHAPTER -5..................................................................................................................47-48
4 CONCLUTION AND FUTURE SCOPE
4.1 CONCLUSION............................................................................................47
4.2 FUTURE SCOPE.........................................................................................48
REFERENCES
PUBLICATION

vii
 LIST OF TABLE

NO. TITLE PAGE NO

3.1 NCL 27 fundamental gates...........................................................................21-22

3.2 Truth table of AND gate using NCL.............................................................28
3.3 Truth table of half adder using NCL.............................................................29
3.4 Truth table of full adder using NCL..............................................................30-31
3.5 Design considerations...................................................................................43
3.6 Transistor utilization in static CMOS and NCL CMOS design.....................43-44
3.7 Comparision of various parameters in static CMOS and .............................46
NCL CMOS design

viii
 LIST OF FIGURES
S.N. NAME OF FIGURE PAGE NO.

1 Symbolic Incompleteness Of Boolean AND Gate 17

2. AND Gate Using NCL and Alied Waveform 19

3. THmn Threshold Gate 20

4. Weighted Threshold Gate 20

5. General Diagram Of THmn Threshold Using Static CMOS 23

Implementation

6. TH23 Gate Static CMOS Implementation 24

7. Block Diagram Of Semi-Static CMOS Implementation 25

8. TH23 Gate Semi Static CMOS Implementation 26

9. AND Gate Using NCL 27

10. Half Adder Using NCL 29

11. Full Adder Using NCL 30

12. Bit Ripple Carry Adder Using NCL 31

13. D Flip –Flop Using NCL 32

14. Structure Of 8- Bit D Flip-Flop 33

15. Structure Of 8*8 Multiplier 34

16. Schematic Of Static CMOS Using NCL 35

17. Schematic Of THmn Threshold Gate CMOS Using NCL 35

18. Schematic Component Of Static CMOS 36

19. Schematic Component of Static CMOS Implementation 36

20. Component Of Static CMOS Using NCL 37

21. 8*8 Multiplier Using NCL 38

22. Verilog File Of Multiplier 38

23. Waveform Of Multiplier 39

24. Schematic Output Of CMOS Using NCL 40

25. Output Of Schematics 40

26. Waveform Of Schematics 41

ix
27. Schematic Of Half Adder 41

28. Schematic Of Static CMOS Implementation 42

29. Verilog File Of AND Gate 42

x
 LIST OF SYMBOLS AND ABBREVIATIONS

Symbols

fclk - clock frequency

Pd - Dynamic Power Dissipation
CL - Load capacitance
Imean - Mean current

Vtp - NMOS threshold voltage

Iscn - node short circuit currents
αn - node switching activity

n - number of nodes

Vtp - PMOS threshold voltage

fp - Repetition frequency
Psc - Short circuit power
Ps - Static Power Dissipation
VDD - Supply voltage
cn - the node capacitances
P total - Total power

Abbreviations

ASIC - Application Specific Integrated Circuit

CMOS - Complementary Metal Oxide Semiconductor
CSA - Carry Select Adder
DA - Distributed Arithmetic
DPL - Double Pass Transistor Logic
DSP - Digital Signal Processing

xi
EMI - Electro Magnetic Interference
EX-NOR - Exclusive NOR
EX-OR - Exclusive OR
F/F - Flip Flop
FA - Full Adder
FIR - Finite Impulse Response
GDI - Gate Diffusion Input
HA - Half Adder
HDPL -Hybrid Double Pass Transistor Logic
HSPICE -Hybrid Simulation Program with Integrated Circuit
Emphasis
IC - Integrated Circuits
IIR - Infinite Impulse Response
LCT - Leakage Control Transistor
LTI - Linear Time Invariant
LUT - Look Up Table
MCC - Manchester Carry Chain
MOSFET -Metal Oxide Semiconductor Field Effect Transistor
NCL - Null Convention Logic
PDP - Power Delay Product
RCA - Ripple Carry Adder
SBL - Substrate Bias Logic
SOC - System on Chip
SOI - Silicon on Insulator
VLSI - Very Large Scale Integration

xii