FALLSEM2019-20 ECE2003 ETH VL2019201000896 Reference Material I 05-Sep-2019 Verilog

Outline
 Evolution of CAD Design.

 HDL - Definition
 Features of HDL
 VHDL Vs Verilog HDL
 Emergence & Features of HDL
 History Verilog HDL.
 Verilog Basics – Lexical Conventions
 Concept of Module
 Port Connection Rules
MODULE-I VLSI SYSTEM DESIGN 1

• The first Integrated Circuit (IC) or silicon chip was
fabricated in 1960s.
• IC chip evolution -> SSI, MSI, LSI, VLSI…

• Designing single chip with more than 100,000
• transistors - VLSI.
• Complicated design processes.
• Traditional / conventional design method includes manual

translation of design description into logical equations and
then to schematic.

• Verification through bread-boarding?
• CAD (back-end) tools became critical.
• Graphic packages (PSpice, Workbench, OrCAD) for
gate level / schematic representation.
–Cannot handle higher complexities.
–Poor portability.
–Poor readability for high complex designs.
• In all the above design methods the functional bugs

cannot be identified till the design is implemented in
hardware, and hence the design time is very long.

HDL?
• In electronics, a hardware description language
or HDL is any language from a class of
computer languages for formal description of
electronic circuits. It can describe the circuit's
operation, its design, and tests to verify its
operation by means of simulation
• Popular HDLs are Verilog HDL & VHDL (for

any complexity).

• Logic Simulators for verifying functionality thus
removing functional bugs at an early stage in the
design.
• High level languages such as FORTRAN,
PASCAL, C, C++, etc., are sequential in nature.
• Digital designers felt the need for a standard
language to describe digital systems / hardware.
• Hardware Description Languages (HDLs) comes
into existence and these have special constructs to
model the concurrency of processes found in
digital systems.

• Easy development, verification and debugging
through HDLs.
• HDL descriptions are easily portable, and is also

compatible to all design tools.
• HDLs can describe the digital systems at various

abstraction levels & also supports hierarchical
modeling.
• HDL descriptions can be functionally simulated

with Logic Simulators .

• Advent of Logic synthesis tools in late 1980‟s
pushes HDLs to the forefront of digital design.
• Digital circuits described at Register Transfer

Level (RTL) using HDLs, can also be synthesized
through automated logic synthesis tools.
• Logic Synthesis tools can extract gate level

details automatically from HDL (RTL)
description.

VHDL Vs Verilog HDL
 VHDL : Very High Speed Integrated Circuit Hardware Description

Language
 Verilog HDL: Verification Logic Hardware Description Language
Differences:
 VHDL was designed to support system level design and
specification.
 Verilog HDL was designed primarily for digital hardware
designers developing FPGAs and ASICs.
The differences becomes clear when one analyze the language features.

VHDL Vs Verilog HDL
 VHDL
– Provides some high level constructs not available in
Verilog (User defined types, Configurations etc.,)
 Verilog
– Provides comprehensive support for low-level digital
design
– Not available in native VHDL
• Range of type definitions and supporting
functions(called packages need to be included)

• Developed by Philip Moorby in 1984-1985.
• Gateway Design Automation introduced Verilog in

1984 as their proprietary HDL.
• Cadence took over in 1989.
• Cadence made Verilog HDL public in 1990.
• Verilog HDL becomes IEEE 1364-1995.

• Verilog HDL is modeled after „C‟ language.
• Allows different levels of abstraction to be mixed in

the same model.
• Easy to learn and easy to use.
• Almost all logic simulation & synthesis tools

support Verilog.
• Verilog HDL is an IEEE 1364 standard.

• White space
• Operators
• Comments
• Number specification
• Strings
• Identifiers and Keywords
• Escaped Identifiers

• Comprise of the white space.
• Blank spaces ---> \b
• Tabs ---> \t
• New lines ---> \n
• White space is not ignored in strings.

• Broadly classified as:
– unary operators.
• operates on a single operand. Ex: out = ~ a;
– binary operators.
• operates on two operands. Ex: out = a && b;
– ternary operators.
• operates on three operands. Ex: out = s ? a : b;

• Improve readability and helps good documentation.
• Two comment structures are available in verilog:

– single / one line comment
• z = x + y; // arithmetic operation
– multiple line / block comment
• /* this logic performs
the reversal
of bits */
• Multiple line comments cannot be nested.

– /* This is /* a wrong
comment */ structure */
• Verilog HDL is case-sensitive.
• All the keywords in Verilog must be in lower case.
• Verilog constructs may be written across multiple

lines, or on one line.

• Identifiers and keywords are used to define
language constructs.
• Identifiers refer objects to be referenced in the

design.
• Identifiers are made of alphabets (both cases),

numbers, the underscore „_‟ and the dollar sign „$‟.
• They start with an alphabetic character or

underscore.

• They cannot start with a number or with „$‟
which is reserved for system tasks.
• Identifiers are case sensitive i.e., identifiers

differing in their case are distinct.
• An identifier say count is different from

COUNT, count and cOuNT.

Count • Example:
COUNT reg sum;
_R2_D2 input data;
R56_68
FIVE$
$count Illegal
12six_b Illegal
• Sized numbers.
– <size> ‟<base format> <number>
• Unsized numbers.
– ‟<base format> <number>
• <size> in decimal
• <base format> can be b or B, d or D, o or O and h or
H.
• Numbers without <base format> are decimal by

default.
• Examples:
Sized numbers :
4'b1111 // This is a 4-bit binary number
12'habc // This is a 12-bit hexadecimal number
16'd255 // This is a 16-bit decimal number.
Unsized numbers :
23456 // This is a 32-bit decimal number by default
'hc3 // This is a 32-bit hexadecimal number
'o21 // This is a 32-bit octal number
• X or x for unknown values.
• Z or z for high impedance values.
• X or Z at the MSB has the self padding property.
Examples:
32 ‟B z // this is a 32-bit high impedance number
6 ‟h X // this is a 6-bit hex number
12 ‟H 13x // this is a 12-bit hex number

5‟037 5-bit octal
4‟D2 4-bit decimal
7‟Hx 7-bit x (x extended), i.e.… xxxxxxx
4‟hz 4-bit z (z extended), i.e… zzzz
4‟d-4 Not legal
8 „h 2A Spaces allowed between size & „ character
& between base and value
3‟ b001 Not legal: no space allowed between ‟ and
base b
10‟b10 Padded with 0 to the left, 0000000010
3‟b1001_0011 is same as 3‟b011

• A string is a sequence of characters that are
enclosed by double quotes.
• “Verilog classes are very interesting???”
• Spaces are not ignored in strings.
• Strings cannot be on multiple lines.

• A module is a basic building block in Verilog and
can specify a system of any complexity.
• The module definition is the same for a system of

any complexity.
• Provides functionality through its port interface.
• It can be an element or a collection of lower-level

design (macro or leaf cells or primitive cells) blocks.

Components of a Verilog Module

• A module in Verilog is declared using the
keyword module and a corresponding keyword
endmodule must appear at the end of the module.
• Each module must have a module name, which
acts as an identifier.
• A module can have an optional port list which
describes the input, output & inout terminals of
the module.

module ex1( );
Module name: ex1
endmodule No. of ports: 0
module ex2(y,a,b,c,d);
Module name: ex2
output y;
input a,b,c,d; No. of ports: 5
wire f1,f2;
or o1(f1,a,b)
and a1(f2,c,d);
xor x1(y,f1,f2);
endmodule
• In Verilog nesting of modules is not permitted i.e.,
one module definition cannot contain another
module definition within the module and
endmodule statements.
module counter(q, clk, reset);
output [3:0]q;
input clk, reset;
module T_FF(q, clock, reset) // Illegal

.
endmodule
endmodule
COUNTER Modules
Module / Primitive
T_FF T_FF
(tff0) (tff1)
D_FF NOT D_FF NOT

• A module provides a template from which one can
create actual objects.
• Each object has its own name, variables, parameters

and I/O interface.
• The process of creating objects from a module

template is called instantiation, and the objects are
called instances.
• Primitives and modules can be instantiated.

ex1 and ex2 as objects
Module in top module
ex1
Top module
module templates
Module Module
Module ex1 ex2
ex2
Primitive 1 Primitive 2

Ports
All ports in the list of ports must be declared in the

module. Ports can be declared as follows:
Verilog Keyword Type of Port
input input port
output output port
inout bidirectional

Port Declarations
module fulladd4(sum, c_out, a, b, c_in);

//Begin port declarations section
output [3:0] sum;
output c_cout;
input [3:0] a, b;
input c_in; //End port declarations section ...
<module internals> ...
endmodule

Port Connection Rules

Inputs
Internally, input ports must always be of the type net.
Externally, the inputs can be connected to a variable
which is a reg or a net.
Outputs
Internally, outputs ports can be of the type reg or net.
Externally, outputs must always be connected to a net.
They cannot be connected to a reg.
Inouts
Internally, inout ports must always be of the type net.
Externally, inout ports must always be connected to a
net.
Width matching
It is legal to connect internal and external items of different sizes
when making inter-module port connections. However, a warning
is typically issued that the widths do not match.
Unconnected ports
Verilog allows ports to remain unconnected. For example, certain
output ports might be simply for debugging, and you might not be
interested in connecting them to the external signals. You can let a
port remain unconnected by instantiating a module as shown
below.

Data Types

Net Data type
Registers Data type

Data Type
A variable belongs to one of two data types

Net:
 Must be continuously driven

 Used to model connection between continuous
assignments and Instantiations.
Register:
 Retains the last value assigned to it.

 Often used to represent storage element.

• Nets represent connections / physical wires between
hardware elements.
• Nets will not store / hold any value.
• Different net types supported for synthesis:

 wire , wor, wand, tri , supply0, supply1
 wire and tri are equivalent ; when there are multiple drivers,
driving them, the output of the drivers are shorted together.
 wor / wand inserts an OR/AND gate at the connection.
 supply0 / supply1 model power supply connections.
• Default Size : 1-bit / scalar
• Default Value : z

Example for wire and wand – Net data type
module wired (a,b,f); module wired_a (a,b,f);

input a,b; input a,b;
output f; output f;
wire f; wand f;
assign f= a & b; assign f= a & b;
assign f= a | b; assign f= a | b;
endmodule endmodule

Example for supply – Net data type
module supply_wire (a,b,c,f);

input a,b;
output f;
wire t1,t2;
supply0 gnd;
supply1 vdd;
nand G1(t1,vdd,a,b);
xor G2(t2,c,gnd);
and G3(f,t1,t2);
endmodule

• wire a; // signal „a‟ declared as wire
• wire out; // signal „out‟ declared as wire
Ex: assign out = a | b; or o1(out, a, b);
• wire a, b; // signals „a‟ & „b‟ declared as wires
• wire d = 1‟b0; /*net „b‟ is fixed to logic value „0‟

at declaration*/
 In Verilog registers represent data storage
elements.
 Used to model hardware memory elements /
registers.
 Registers can hold / store a value.
 Declared by the keyword reg , integer
 Default Size : 1-bit / scalar
 Default Value : x

Other Differences
In arithmetic expression,
 An integer is treated as a 2‟s complement signed
integer
 A reg is treated as an unsigned quantity
General Rule
 “reg” is used to model actual hardware registers such
as counters, accumulators etc.,
 “integer” is used for situation like loop counting
 The reg declaration explicitly specifies the size either in
scalar or vector quantity.
 For integer it takes default size, usually 32-bits

• Nets or register data types can be declared as
vectors (more no. of bits).
• If bit width is not specified then the default value
is 1-bit (scalar).
wire a; // default scalar net value

wire [7:0] bus; // 8-bit bus
wire [31:0] busA, busB, busC; //32- bit bus
reg clock; // scalar register(default)
reg [0:40] virtual_addr; //virtual address 41 bits

• reg p;
• reg w,y;
reg reset;
initial
begin
reset = 1 ‟b1; //initialize reset to 1
#100 reset = 1 ‟b0; /* after 100 times units reset
is de asserted*/
end

• wire [15:0]busA;
busA[9]; // bit # 9 or 10th bit of vector busA from LSB
• wire [0:15]busB;
busB[9]; // bit # 9 or 7th bit of vector busB from LSB
• reg [31:0]cnt_out;
cnt_out[14:7]; // group of 8 bits of a vector register
cnt_out[7:14]; // is illegal addressing

• The operators can be :
arithmetic
logical
relational
equality
bit wise
reduction
shift
concatenation
replication
conditional

Expressions constitute operators and operands.
operation symbol operand

Multiply * binary
Divide / binary
Add + binary
Subtract - binary
Modulus % binary

Eg: a * b // multiply a and b
a / b // divide a by b
a+b // add a and b
a - b // subtract b from a
a%b // modulus of a by b
a=3‟b011 b=3‟b010 d=4 e=3
c=a * b // c= 3‟b110
c= a / b // c= 1
c= a+b // c= 3‟b101
c= a-b // c=3‟b001
c=d/e // c=1
13 % 4 // evaluates to 1.
-9 % 2 // evaluates to -1, takes sign of the
first //operand
• In arithmetic operations, if any operand bit has a

value x, then the result of the entire expression is x.
• The size of the result is determined by the size of

the largest operand.

Logical operator evaluates always to a one bit value either
true(1) or false (0) or x (unambiguous) . If any operand bit
is either x or z it is equivalent to x
operation symbol operand
logical and && binary
logical or || binary
logical not ! binary

a1 = 1‟b0; // 0 is false;
a2 = 1‟b1; // 1 is true
a1 && a2 is 0 (false)
a1 || a2 is 1 (true)
!a2 is 0 (false)
• For vector operands, a non-zero vector is treated

as logical 1.

Example:
a=10 b=00
a && b // evaluates to 0 ( 1 && 0)
a=2‟b1x b=2‟b11
a || b // is unknown, evaluates to x.

• Relational operations return logical 0 or 1. If there is any x
or z bit in operand then it will return x.
Operation Symbol Operand
greater > Binary
less than < Binary
Greater than or equal to >= Binary
Less than or equal to <= Binary

a = 5 b = 6 c = 2‟1x
a >b // evaluates to 0
a <= b // evaluates to 1
b >= c // evaluates to x

Equality operators are the following
logical equality == binary
logical inequality != binary
case equality === binary
case inequality !== binary

• Equality operator can return 1 or 0.
• Logical equality operator (== !=) will return x if

any of the operand bit has x.
• Case equality operator compares both operand bit

by bit including x and z bit. If it matches then
returns 1 or else it returns 0. It doesn‟t return x.

Contd…
a=3; b=5; c=3‟b100; d=3‟b101; e=4‟b1xxx;
f=4‟b1xxx;
g=3‟b1xxz
a !=b // evaluates to 1.
e===f // evaluates to 1.
f===g // evaluates to 0. d == e // evaluates to x

Bitwise operations are performed on each bit of the
operand
Bitwise and & Binary
Bitwise or | Binary
Bitwise negation ~ Unary
Bitwise xor ^ Binary
Bitwise xnor ~^ or ^~ Binary

module fulladd_1(sum,carry,a,b,c);
input a,b,c;
output sum,carry;
wire sum,carry;
assign sum = (a^b )^ c;

assign carry = (a&b) | (b&c) | (c&a);
endmodule

a = 3‟b111; b = 3‟b101; d = 3‟b1x1;
c = ~a; // c = 3‟b000
c = a & b; // c = 3‟b101
c = a & b; // c = 3‟b111
c = a ^ b; // c = 3‟b010
c = a | d; // c = 3‟b1x1

Reduction operators are unary operators
reduction and & unary
reduction nand ~& unary
reduction or | unary
reduction nor ~| unary
reduction xor ^ unary
reduction xnor ~^ or ~^ unary

x = 4‟b01100
c = &x // c= 0 & 1&1&0&0 c=0
c = |x // c= 0|1|1|0|0 c=1
c = ^x // c=0^1^1^0^0 c=0

Shift operator can be shift left or shift right

shift right >> unary
shift left << unary
Example:
a = 4‟b1011;
y = a >> 2; // y =4‟b0010, 0‟s filled in MSB
y = a << 2; // y = 4‟b1100, 0‟s filled in LSB

• Concatenation operator is used to append
multiple operands.
• The operand must be sized.
a=3‟b101; b=3‟b111;
y = {a,b}; // y = 6‟b101111
y = {a,b,3‟b010}; // y =101111010

Replication operator is used to concatenate same
number.
a=3‟b101 b =2‟b10
y = {2{a}}; // result of y is 6‟b101101

y = {2{a},2{b} }; // result of y is 10‟b1011011010
y = { 2{a},2‟b10}; // result of y is 6‟b10110110

Conditional operator ? :
format:
conditional_expr ? true expr : false expr;
eg:
assign out = control ? I1 : l2;
control out
1 I1
0 I2

module mux_con(out,s0,s1,i);
input s0,s1;
input [3:0]i;
output out;
wire out;
assign out = s1 ? ( s0 ? i[3]:i[2]) : (s0 ? i[1]:i[0]) ;
endmodule

+-~! unary
*/% arithmetic
+- binary
<< >> shift
< <= > >= relational
& ~& reduction and , nand
^ ~^ reduction exor, exnor
| ~| reduction or , nor
&& logical and
|| logical or
?: conditional

Structural / Gate Level Modeling
The module is implemented in terms of logic gates and

interconnections between these gates. Design at this level
is similar to describing a design in terms of a gate-level
logic diagram.

• Features:
– Hardware design is described using instantiations of
both primitives as well as modules.
– Logic independent of the ordering of instantiations of
both primitives and modules.
– Concurrent execution of both primitives and
modules.
– Instance name is mandatory for modules but optional
for primitives.

Verilog primitives
and / or buf / not Tri-state
buf bufif0
and not bufif1
nand notif0
or notif1
nor
xor
xnor
VLSI SYSTEM DESIGN 78

MODULE-I
• Verilog supports basic logic gates as predefined primitives.
• These primitives are instantiated like modules except that

they are predefined in Verilog.
• No module definition is needed for using the primitives.

Features:
• 1-output, multiple inputs.
• Output transitions (0, 1, x).
• and i1 (output, input_1, input_2, …, input_n);

• nand i2 (output, input_1, input_2, …, input_n);
• or i3 (output, input_1, input_2, …, input_n);
• nor i4 (output, input_1, input_2, …, input_n);
• xor i5 (output, input_1, input_2, …, input_n);
• xnor i6 (output, input_1, input_2, …, input_n);

Features:
• 1-input, multiple outputs.
• Output transitions (0, 1, x).
• buf i1 (output_1, output_2, …, output_n, input);

• not i2 (output_1, output_2, …, output_n, input);

Features:
• Has only 3 terminals.
• Output transitions (0, 1, x, z).
• bufif0 i1 (output, data input, control input);

• bufif1 i2 (output, data input, control input);
• notif0 i3 (output, data input, control input);
• notif1 i4 (output, data input, control input);

• Gate delay: signal propagation delay from any gate input to the gate
output.
• Rise delay: refers to the transition to the „1‟ value from any other value.
• Fall delay: refers to the transition to the „0‟ value from any other value.
• Turn-off delay: refers to the transition to the high-impedance value (z),

from any other value.
• If the value changes to x, the minimum of the three delays is taken.

• One delay specification: If specified, it is used for all transitions.
and #(delay time) a1 (out, i1, i2);
and #(4) a1 (out, i1, i2);
• Two delay specification: If specified, they refer to rise and fall times.
or #(rise_del, fall_del) o1 (out, i1, i2);
or #(5, 6) o1 (out, i1, i2);
• Three delay specification: If specified, they refer to rise, fall and turn-
off times.
bufif1 #(rise_del, fall_del, turn_off_del) b1 (out, in, cnt);
bufif1 #(2, 3, 5) b1 (out, in, crtl);
 Primitive gate delays allow three values each for the rise, fall and
turn-off delays.
 The three values are minimum, typical and maximum, and the
three are separated by colons.
 Either of the three values can be selected at the start of the

simulation (run time). If no value is selected, typical value is the
default.

• One delay specification with min:typ:max values.
and #(2:4:5) a1 (out, i1, i2);
risemin,fallmin = 2, risetyp,falltyp = 4, risemax,fallmax = 5.
• Two delay specification with min:typ:max values.

or #(1:5:3, 2:6:4) o1 (out, i1, i2);
risemin=1, risetyp=5, risemax=3, fallmin=2, falltyp=6, fallmax=4.
• Three delay specification with min:typ:max values.
bufif1 #(1:2:4, 1:3:5, 3:5:6) b1 (out, i1, i2);
risemin=1, risetyp=2, risemax=4, fallmin=1, falltyp=3, fallmax=5, turn-
offmin=3, turn-offtyp=5, turn-offmax=6.

Example - Primitive Instantiation

Primitive Instantiation - Example
// Module 4-to-1 multiplexer. Port list is taken exactly from the
I/O diagram.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
wire s1n, s0n;
wire y0, y1, y2, y3;
not (s1n, s1); not (s0n, s0);
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
or (out, y0, y1, y2, y3);
endmodule
Module Instantiation - Example
module twmux (a,b,s,y); module frmux (a,b,c,d,se1, y);

input a,b,s; input a,b,c,d,se1;
output y; output y;
wire y,s1,w1,w2;
wire y,se1,w1,w2;
not n1(s1,s);
and a1(w1,a,s); twmux t1(a,b,se1,w1);
and a2 (w2,b,s1); twmux t2(c,d,se1,w2);
or o1(y,w1,w2); twmux t3(w1,w2,se1,y);
endmodule
endmodule

Connecting Ports to External Signals
• There are two methods of making connections between

signals specified in the module instantiation and the
ports in a module definition. These two methods cannot
be mixed.
– Connecting by ordered list
– Connecting ports by name

Connecting by ordered list
• Connecting by ordered list is the most intuitive method

for most beginners.
• The signals to be connected must appear in the module

instantiation in the same order as the ports in the port
list in the module definition

Connecting by ordered list-Example

output y; output y;
wire y,s1,w1,w2;
wire y,se1,w1,w2;
not n1(s1,s);
and a1(w1,a,s); twmux t1(a,b,se1,w1);
and a2 (w2,b,s1); twmux t2(c,d,se1,w2);
or o1(y,w1,w2); twmux t3(w1,w2,se1,y);
endmodule
endmodule

Connecting Ports by name
• For large designs where modules have, say, 50 ports,

remembering the order of the ports in the module
definition is impractical and error-prone.
• Verilog provides the capability to connect external

signals to ports by the port names, rather than by
position.

Connecting Ports by name -Example

output y; output y;
wire y,s1,w1,w2;
wire y,se1,w1,w2;
not n1(s1,s);
and a1(w1,a,s); twmux t1(.a(a), .b(b), .s(se1), .y(w1) );
and a2 (w2,b,s1); twmux t2(.a (c), .b(d), .s(se1), .y(w2) );
or o1(y,w1,w2); twmux 3(.a(w1), .b(w2), .s(se1), .y(y));
endmodule
endmodule

TEST BENCH
MODULE-II VLSI SYSTEM DESIGN 97

•Once a design block is completed, it must be tested
•A design block needs to be tested for its functionality by
applying stimulus and checking results.
• For testing the design block, a stimulus block or test

bench can be created in Verilog itself.
• In the test bench we provide some stimulus to the

corresponding inputs of the design module.

Stimulus Block Instantiates Design Block

Stimulus and Design Blocks Instantiated in
a Dummy Top-Level Module

TEST BENCH FLOW
Synthesis Verilog Code

Verilog Code
(Gate Level
Netlist)
Verilog Test
Bench

Example module and_test ();
reg a,b;
wire y;
module and_gate (a,b,y); and_gate a1(a,b,y);
input a,b; initial
output y; begin
a=1‟b0;b=1‟b0;
assign y= a & b;
#100;
endmodule a=1‟b0; b=1‟b0;
#100;
a=1‟b0; b=1‟b0;
#100;
a=1‟b0; b=1‟b0;
end
endmodule

MODULE-II VLSI SYSTEM DESIGN
103
• System tasks are meant for carrying out certain
routine operations like displaying signals, nets,
time, simulation control etc.
• Syntax : $<keyword>
• All the system tasks start with „$‟ .
• These system tasks are behavioral constructs.

Different Types of System Tasks
• $display
• $monitor
• $monitor on, $monitor off
• $strobe
• $write
• $finish
• $stop

• These system functions will return the integer
value of simulation time at which they are
executed.
– $time : returns time (integer) in 64 bits
– $stime : returns time (integer) in 32 bits
– $realtime : returns time (real)

• These system tasks are used for displaying and printing
information.
• These system tasks are characterized into:

– Display and write tasks
– Strobed monitoring tasks
– Continuous monitoring tasks

Syntax:
system task name (p1, p2, p3, p4, p5, …, pn);
• The arguments p1, p2, p3, …,pn can be strings,

format specifications, variables etc.
• The system task name can be one of:

– $display or $displayb or $displayh or $displayo
– $write or $writeb or $writeh or $writeo

FORMAT DISPLAY
%d or %D ------------------------------- in decimal
%h or %H ------------------------------- in hexa decimal
%b or %B ------------------------------- in binary
%o or %O ------------------------------- in octal
%s or %S ------------------------------- string
%c or %C ------------------------------- ASCII
%m or %M ------------------------------ Hierarchical name
%e ------------------------------- real in scientific
%f ------------------------------- real in decimal

• These system tasks automatically inserts a new line
at the end after printing the information.
• If no format specification exists for an argument

then:
– $display : displays argument values in decimal.
– $displayb : displays argument values in binary.
– $displayh : displays argument values in
hexadecimal.
– $displayo : displays argument values in octal.

TEST BENCH:
Example module and_test (); initial
reg a,b; $display($time. “The value of a=%b,
wire y; b=%b, y=%b”, a,b,y);
module and_gate endmodule
(a,b,y); and_gate a1(a,b,y);
initial
input a,b;
begin
output y;
a=1‟b0;b=1‟b0;
assign y= a & b; #100;
endmodule a=1‟b0; b=1‟b0;
#100;
a=1‟b0; b=1‟b0;
#100;
a=1‟b0; b=1‟b0;
end

• These system tasks prints the information without
automatically inserting a new line at the end.

then:
– $write : displays argument values in decimal.
– $writeb : displays argument values in binary.
– $writeh : displays argument values in
hexadecimal.
– $writeo : displays argument values in octal.

• These system tasks display the data at the end of
the simulation time at which they are executed.

then:
– $strobe : displays argument values in decimal.
– $strobeb : displays argument values in binary.
– $strobeh : displays argument values in
hexadecimal.
– $strobeo :: displays argument values in octal.

• These system tasks displays the data whenever there is a
change of value in an argument in the argument list and
displays at the end of the simulation time at which they
are executed.
• If no format specification exists for an argument then:

– $monitor : displays argument values in decimal.
– $monitorb : displays argument values in binary.
– $monitorh :: displays argument values in hexadecimal.
– $monitoro : displays argument values in octal.

module stimulus;
// module D_FF with synchronous
reg clk;
reset
reg reset,d;
module D_FF(q, d, clk, reset);
wire[3:0] q;
output q;
D_FF d1(q,d, clk, reset);
input d, clk, reset;
initial clk = 1'b0;
reg q;
always #5 clk = ~clk;
always @(posedge reset or negedge
initial
clk)
begin
if (reset)
reset = 1'b1;
q <= 1'b0;
d=1‟b1;
else
#15 reset = 1'b0;
q <= d;
#50 d=1‟b0;
endmodule
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish;
initial
$monitor($time, " Output q = %d", q);
MODULE-II
endmodule
VLSI SYSTEM DESIGN 115
• $stop : causes the simulation to be suspended /
places in interactive mode, and the partial results
can be analyzed.
• $finish : causes the simulation to terminate / exits

the simulator and pass the control back to the host
operating system.

116
initial initial
forever #700 $finish;
#10 clock = ~ clock;
initial
initial clock = 1‟b0;
#100 $stop;
initial
initial forever
clock = 1‟b0; #10 clock = ~ clock;
Compiler directives
Compiler directives
• These are preceded by back quote (`) character.
• When compiled these directives in effect through

the entire compilation.
• The effect of these directives can be felt across many

different files.
• The effect stays till a different compiler directive

supercedes it or the processing completes.

`define & ùndef
• `define directive is used for text macro

substitution.
• The compiler substitutes the text of the macro

for the string `macro_name in the source
description of modules.
• A previously defined text macro can be

undefined by using the ùndef directive.

`timescale
• This directive specifies the time unit and time
precision of the modules that follow it.
• The time unit is the unit of measurement for time

values such as the simulation time and delay values.
• Syntax: `timescale time unit / time precision

– Time unit: s, ms, us, ns, ps, fs.
– The magnitude can be scaled by: 1, 10 or 100.

`timescale -Example
`timescale 100 ns / 1 ns
module dummy1;
reg toggle;
//initialize toggle
initial
toggle = 1'b0;
always #5 begin
toggle = ~toggle;
$display("%d , In %m toggle = %b ", $time, toggle);
end
endmodule

ìnclude
• This compiler directive is used to insert/include the
entire contents of a source file in another file during
compilation.
• Syntax: ìnclude “file name”

– The filename is the name of the file to be included in
the source file.
• Example:
ìnclude “mem_data.txt”
module mem1KB(…….);
endmodule

Dataflow Modeling (1/2)
• Gate level Modeling approach works well for small circuits

but not for complex designs.
• Designers can design more effectively if they concentrate on
implementing the function at a level of abstraction higher
than gate level.
• Dataflow modeling provides a powerful way to implement a
design.
• Verilog allows a circuit to be designed in terms of the data
flow between registers and how a design processes data
rather than instantiation of individual gates.
Dataflow Modeling (2/2)
• With gate densities on chips increasing rapidly, dataflow

modeling has assumed great importance.
• Currently, automated tools are used to create a gate-level
circuit from a dataflow design description. This process is
called logic synthesis.
• The data flow modeling allows the designer to concentrate on
optimizing the circuit in terms of data flow.
• In the digital design community, the term RTL (Register
Transfer Level) design is commonly used for a combination of
dataflow modeling and behavioral modeling.
• This level of abstraction level resembles like that of boolean
equation representation of digital systems.
• The dataflow assignments are called “Continuous Assignments”.
• Continuous assignments are always active.
• Syntax: assign #(delay) target = expression;
• A Verilog module can contain any number of continuous

assignment statements, and all staements execute concurrently.

• LHS target -> always a net, not a register.
• RHS -> registers, nets or function calls.
• Delay values can be specified in terms of time units.
• Whenever an event (change of value) occurs on any operand

used on the RHS of an expression, the expression is
evaluated and assigned to the LHS target.

• Regular continuous assignment.
wire mux_out, a_in, b_in, sel_in;

assign mux_out = sel_in ? b_in : a_in;
• Implicit continuous assignment.
wire a_in, b_in, sel_in;

wire mux_out = sel_in ? b_in : a_in;

wire and_out;
assign and_out = i1 & i2; // regular continuous assignment
wire exor_out = i1[31:0] ^ i2[31:0] // implicit assignment

Example – Mux Inference
module generate_mux
D
(data,select,out); A MUX
OUT
input [0:7] data; T
A
input [0:2]select;
output out;
wire out;
assign out = data[select];
SELECT
endmodule
Note: Non- constant index in expression on RHS generates MUX

Example – Decoder Inference
module generate decoder

D
(data,select,out); A
DECODER
input data; T
A
input [0:1]select; OUT
output [0:3] out;
wire [0:3] out;
assign out[select]=data;
SELECT
endmodule
Note: Non- constant index in expression on LHS generates DECODER

Example
module generate_mux
a
(a,b,f,s);
input a,b;
b
MUX f
input s;
output f;
wire f; s
assign f = s? a : b;
endmodule
Note: Conditional Operator generate MUX

Example
module latch (D,Q,En);

D Q
input D,En; LATCH
output Q;
wire Q;
assign Q=En?D:Q;
En
endmodule
Note: Using “assign” to describe sequential logic using conditional

operator.
Cyclic dependency of net also infers latch.

Delay values control the time between the change in a right
hand-side operand and when the new value is assigned to
the left-hand side.
• Regular assignment delay
• Implicit continuous assignment delay
• Net declaration delay

The delay value is specified after the keyword assign.
Any change in values of in1 or in2 will result in a delay of 10 time units before
recomputation of the expression in1 & in2, and the result will be assigned to out.
Example:
module and_ex(and_out , a_in, b_in);
input a_in, b_in;
output and_out;
wire and_out;
assign #10 and_out = a_in & b_in;
endmodule

wire out;
assign #10 out = i1 & i2; // Regular assignment delay
• The inertial delay of real circuits is modeled through

regular assignment delay.
• Any event on the RHS signals which is not lasting for the
amount of inertial delay specified will not have any effect on
the LHS target.
in1
in2
out
10 20 30 60 70 80 85
time

8/4/2011 VERILOG HDL PRESENTATION 138
An equivalent method is to use an implicit continuous assignment to
specify both a delay and an assignment on the net.
Example:
input a_in, b_in;
output and_out;
wire #10 and_out = a_in & b_in;
endmodule

A delay can be specified on a net when it is declared without
putting a continuous assignment on the net.
 If a delay is specified on a net out, then any value change applied
to the net out is delayed accordingly.
Example:
input a_in, b_in;
output and_out;
wire #10 and_out;
assign and_out = a_in & b_in;
endmodule

Behavioral Modeling
Behavioral or algorithmic level:
– This is the highest level of abstraction provided by

Verilog HDL. A module can be implemented in terms of
the desired design algorithm without concern for the
hardware implementation details. Designing at this level
is very similar to C programming.

Behavioral modeling
• There are two structured procedures in Verilog:

– initial
– always
• Concurrent execution is observed in between these

procedures.
• Sequential / concurrent execution can be realized within

these procedures.
• Only registers can be assigned in these procedures.
• The assignments in these procedures are called

“procedural assignments”.

initial statement
• Starts execution at „0‟ simulation time and executes only
once during the entire simulation.
• Multiple statements in initial block can be grouped with
(begin & end) or (fork & join) keywords.
• These blocks are not synthesizable.

initial statement
• initial blocks cannot be nested.
• Each initial block represent a separate and

independent activity.
• initial blocks are used in generating test benches.

initial block structures
initial initial
begin
xor_out = in1 ^ in2; and_out = a_in & b_in;
end
initial
initial begin
begin clk = 1‟b0;
enable = 1‟b0; reset = 1‟b0;
rst = 1‟b0; initial
#100 rst = 1‟b1; begin
#20 enable = 1‟b1; #100 reset = 1‟b1;
end #20 clk = 1‟b1;
end
end
always statement
• Starts execution at „0‟ simulation time and is active all
through out the entire simulation.
• Multiple statements inside always block can be grouped

with (begin & end) or (fork & join) keywords.
• Execution of always blocks is controlled by using the timing

control.
• always blocks cannot be nested.

always statement
• An always block without any sensitivity control will

create an infinite loop and execute forever.
• Each always block represent a separate and

independent activity.
• These blocks can synthesize to different hardware

depending on their usage.
• always block with timing control are synthesizable.

always block structures
always @(a_in or b_in)
always begin
xor_out = in1 ^ in2; and_out = a_in & b_in;
end
always
always @(posedge reset)
begin
begin
cnt = 1‟b0;
if (reset == 1‟b1)
reset = 1‟b0;
q_out = 1‟b0;
always @(posedge clk)
else
begin
q_out = d_in;
#100 cnt = 1‟b1;
end
#20 enable = 1‟b1;
end
end
always block - Examples
always statement without
always statement with timing control -Example
timing control - Example
module cntr(cnt_out, module clk_gen(clk_out);
clk_in);
input clk_in;
output cnt_out; output clk_out;
reg clk_out;
reg cnt_out;
wire clk_in;
always
always @(posedge clk_in) #5 clk_out = ~clk_out;
cnt_out = cnt_out + 1‟b1;
initial
endmodule clk_out = 1‟b1;
endmodule
Block statements
• Provides a means of grouping two or more procedural
statements together.
• Types of blocks:
– sequential block / begin-end block
– parallel block / fork-join block
• These blocks can be nested.
• These blocks can be mixed.

Sequential block
Format:
begin
<statements>
end
• Statements are executed sequentially one after the other.
• If delay is specified, it is relative to the time when the

previous statement in the block is executed.
• Control leaves the block after executing the last

statement.

Parallel block
Format:
fork
<statements>
join
 Statements are executed concurrently.

 If delay is specified, it is relative to the time, when the block
has started its execution.
 Control leaves the block after executing the last time ordered
statement.

Continuous Vs. procedural assignments
Continuous assignment Procedural assignment
Occurs within a module. Occurs inside an always or

an initial statement.
Executes concurrently Execution is w.r.t. other
with other statements. statements surrounding it.
Drives nets. Drives registers.
Uses “=” assignment Uses “=” or “<=”

operator. assignment operator.
Uses assign keyword. No assign keyword
(exception).

Procedural assignments
• These are for updating reg, integer, real, time and
their bit / part selects.
• The values of the variables can get changed only by

another procedural assignment statement.
• Procedural assignments are of two types

– blocking procedural assignment
– non-blocking procedural assignment
Blocking Assignment
• Most Commonly used type
• The target of assignment gets updated before the next

sequential statement in procedural block is executed.
• A statement using blocking assignment blocks the

execution of the statements following it, until it gets
completed.
• Recommended style for modeling combinational

logic.(data dependency)

Non-Blocking Assignment
• The assignments to the target gets scheduled for the end of the
simulation cycle.
– Normally occurs at the end of the sequential block (begin …..
end)
– Statements subsequent to the instruction under the
consideration are not blocked by the assignment.
• Recommended style for modeling sequential logic
- Can be used to assign several „reg‟ type variables synchronously,
under the control of a common block

Rules to be followed
• Verilog synthesizer ignores the delays specified in a

procedural assignment statement.
– May lead to functional mismatch between the design
model and the synthesized netlist.
• A variable cannot appear as the target of both a blocking
and a non-blocking assignment.
Following is not permissible

value = value +1;
value <=init

Example- up-down counter(synchronous
clear)
module counter (clk, clr, ld,mode,d_in,count);
input clk,mode,clr,ld;
input [0:7] d_in;
output [0:7] count; d_in
reg [0:7] count;
always @(posedge clk)
if (ld) ld clk
clr COUNTER
count<=d_in;
else if (clr) mode
count<=1‟b0;
else if (mode) count
count <=count + 1;
else
count<=count-1
endmodule
Behavioral timing controls
Procedural timing controls
• Delay based timing control
• Event based timing control
• Level sensitive timing control

Delay based timing control
• Regular delay control
• Intra assignment delay control
• Zero delay control

Regular delay control
Format:
#<delay_value> <target> = RHS expression;
• It is used to delay the execution of the corresponding

procedural statement by the defined delay value.
• Regular delays defer the execution of the entire
assignment.
e.g. : #10 c = a + b;
#(2:4:6,3:5:7) or_out = a | b;

Intra-assignment delay control
Format:
<target> = #<delay_value> RHS expression;
• Intra-assignment delays compute the RHS

expression at the current time and defer the
assignment of the computed value to the LHS target
by the defined delay value.
e.g. : c = #10 a + b;

Zero delay control
• Statements with zero initial
begin
delay execute at the end a = 1‟b1;
of the current simulation b = 1‟b0;
end
time, when all other
statements in the current initial
begin
simulation time have #0 a = 1‟b0;
executed. #0 b = 1‟b1;
end

Event based timing control
• An event is the change in the value on a register or a net.
• Implicit event: The value changes on nets and registers can

be used as events to trigger the execution of a statement.
• The event can also be based on the direction of the change.
– posedge : change towards the value 1
– negedge : change towards the value 0

Types of event based timing control
• Regular event control
• Named event control
• Event or control

Regular event control
Format:
@(event) statement;
e.g.: @ (ena) q = d;
@ (posedge t_in) q = ~q;
q = @ (negedge clk) d;
@ (posedge clk_in) q_out = d_in;

Named event control
• Events can be declared with an identifier.

• The declared can be triggered conditionally or
unconditionally, & these doesn‟t hold any data.
• The triggered events can be made to execute the a block of
statements / assignments waiting for this trigger.
• Event is declared by keyword: event event_name;
• Event triggered as: -> event_name;
• Usage: @ <event_name>

Example of named event control
module ex1(out, sig);
output out; always @(shoot)
input sig; //if (shoot == 1‟b1)
reg out; out = 1‟b1;
wire sig;
event shoot;
always @(negedge sig)
begin
if (sig == 1‟b0)
-> shoot;
else
out = 1‟b0;
end

Event or control
• The logical or of any number of events can be expressed such
that the occurrence of any one of the events triggers the
execution of the procedural statement that follows it.
Format:
always @ (event1 or event2 or event3)
always @ (posedge event1 or negedge event2)

Event or control -Example
always @ (in1 or in0 or always @ (posedge clk_in or

sel_in) negedge set_in_n)
begin begin
if (sel_in == 1‟b0) if (set_in_n == 1‟b0)
mux_out = in0;
q_out = 1‟b1;
else
mux_out = in1; else
end q_out = d_in;
end

Level sensitive control
• Execution of statements will be delayed (wait) till a
condition becomes true.
• The nature of the wait statement is level-sensitive, as

opposed to basic event control (specified by the @
character), which is edge-sensitive.
Format:
wait (condition) <statement>

Level sensitive control - Example
module lat(d_in, ena_in_n, q_out);
output q_out;
input d_in, ena_in_n;
reg q_out;
wire d_in, ena_in_n;
always @(d_in or ena_in_n)

begin
wait (ena_in_n == 1‟b0)
q_out = d_in;
end
endmodule

Behavioral constructs
if-else statements
• The if construct checks a specific condition and decides execution
based on the result.
assignment 1;
if(condition) assignment2;
assignment3;
assignment4;
 After execution of assignment1, the condition specified is checked .
If it is
satisfied , assignment2 is executed; if not it is skipped.
 In either case the execution continues through assignment3,
assignment4, etc.
 Execution of assignment2 alone is dependent on the condition. The
rest of the sequence remains.

if-else and if-elseif-else statements
if (<expression 1>)
if (<expression>)
begin
begin
true_statements 1;
true_statements; end
end :
:
if (<expression>) else if (<expression n>)
begin begin
true_statements; true_statements n;
end end
else else
begin begin
false statements; default_statements;
end end
Conditional statement - Examples
if (!ena = 1‟b1)
if (in1 == 1‟b0 && in2 == 1‟b0)
begin
dec_o1 = 1‟b1;
out = in1 & in2;
end
else if (in1 == 1‟b0 && in2 == 1‟b1)
if (sel == 1‟b0) dec_o2 = 1‟b1;
begin
mux_out = in0; else if (in1 == 1‟b1 && in2 == 1‟b0)
end dec_o3 = 1‟b1;
else
begin else
mux_out = in1; dec_o4 = 1‟b1;
end

case statement
case (expression)
•This is a multiway decision alternative 1:begin
statement that tests whether
end
an expression matches one of alternative 2:begin
a number of other alternatives.
end
alternative 3:begin
•Doesn‟t treat „x‟ & „z‟ as
end
don‟t cares. default: begin
end
endcase

case statement - Example
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0); output out;
input s1, s0;
reg out;
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0})
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
2'd3 : out = i3;
default: $display("Invalid control signals");
endcase
endmodule

casez statements
• casez: same as case statement but treats „z‟ as

don‟t cares.
• All bit positions with „z‟ can also be represented

by „?‟

casez - Examples
module
casez_ex(counter,cmd);
input[0:3] counter;
output cmd;
reg cmd;
always@(counter)
casez(counter)
4'b???1:cmd=0;
4'b??10:cmd=1;
4'b?100:cmd=2;
4'b1000:cmd=3;
default : cmd=0;
endcase
endmodule

casex statement
• casex: same as case / casez statement but treats all „x‟

and „z‟ as don‟t cares.

casex - Example
module casex_ex(sel,Bitposition);
input [5:1] sel;
output [2:0] Bitposition;
reg [2:0] Bitposition;
always @ (sel)
casex(sel)
5'bxxxx1 : Bitposition=1 ;
5'bxxx1x : Bitposition=2;
5'bxx1xx : Bitposition=3;
5'bx1xxx : Bitposition=4;
5'b1xxxx : Bitposition=5;
default : Bitposition=0;
endcase
endmodule

Looping statements
• Executes the statements for zero, one or more number of

times.
• Four types of looping statements.

– while
– for
– repeat
– forever

for loop construct
The for loop in Verilog is quite similar to the for loop in C

Format:
for (initialization; expression; inr/dcr)

begin
statements
end
The sequence of execution as follows
1. Execute initialization
2. Evaluate expression
3. If the expression evaluates to the true state(1), carry out
statements. Go to step 5.
4. If the expression evaluates to false state (0), exit the loop.
5. Execute incr/dcr. Go to step 2.

for loop - Example
module addfor (s,co,a,b,cin,en);
for (i=0; i<=7; i=i+1)
output [7:0] s; begin
output co; {c[i+1],s[i]} = (a[i] + b[i] +
input [7:0] a,b; c[i]);
input en,cin; end
co=c[8]
reg [8:0] c;
end
reg co; endmodule
reg [7:0] s;
integer i;
always @ (posedge en)
begin
c[0] = cin;

repeat construct
The repeat construct is used to repeat specified block a specified

number of times.
 The format is show below , the quantity „a „ can be a number or an
expression evaluated to a number.
As soon as the repeat statement is encountered, a is evaluated, the
block will be executed „a‟ times.
If „a‟ evaluates to 0 or x or z, the block is not executed.
Format:
repeat (a)
begin
statements
end

repeat construct - Example
module clkgen (en, cnt);
input en;
output cnt;
integer cnt;
always @ (en)
Begin
if (en)
cnt=0;
repeat (105)
#10 cnt = cnt + 1‟b1;

end
endmodule

While loop
The format of while loop is shown below.
The expression is evaluated. If it is true , the statements
executed and expression evaluated and checked again.
If the expression evaluates to false, the loop is terminated and the
following statement is taken for execution. If the expression
evaluates to true, execution of statement is repeated.
The loop is terminated and broken only if the expression evaluates
to false.
Format:
while (expression)
begin
statements
end
While loop - Example
module while2 (b,n,en,clk);

@(posedge clk)
input [7:0] n; a=a-1‟b1;
input clk,en; end
output b; b=1‟b0;
reg [7:0] a; end
initial
reg b;
b=1‟b0;
always@(posedge en) endmodule
begin
a=n;
while(|a)
begin
b=1‟b1;

forever loop
Repeated execution of a block in an endless manner is best

done with the forever loop ( compare with repeat where
the repetition is for a fixed number of times)
Format:
forever
begin
statements;
end

forever LOOP - Example
module clkgen (clk);

output clk;
reg clk;
initial
begin
clk=1'b0;
forever #10 clk=~clk;
end
initial
#1000 $finish;
endmodule

Behavioral timing controls
Procedural timing controls
• Delay based timing control
• Event based timing control
• Level sensitive timing control

Delay based timing control
• Regular delay control
• Intra assignment delay control
• Zero delay control

Regular delay control
Format:
#<delay_value> <target> = RHS expression;
• It is used to delay the execution of the corresponding

procedural statement by the defined delay value.
• Regular delays defer the execution of the entire
assignment.
e.g. : #10 c = a + b;
#(2:4:6,3:5:7) or_out = a | b;

Intra-assignment delay control
Format:
<target> = #<delay_value> RHS expression;
• Intra-assignment delays compute the RHS

expression at the current time and defer the
assignment of the computed value to the LHS target
by the defined delay value.
e.g. : c = #10 a + b;

Zero delay control
• Statements with zero initial
begin
delay execute at the end a = 1‟b1;
of the current simulation b = 1‟b0;
end
time, when all other
statements in the current initial
begin
simulation time have #0 a = 1‟b0;
executed. #0 b = 1‟b1;
end

Event based timing control
• An event is the change in the value on a register or a net.
• Implicit event: The value changes on nets and registers can

be used as events to trigger the execution of a statement.
• The event can also be based on the direction of the change.
– posedge : change towards the value 1
– negedge : change towards the value 0

Types of event based timing control
• Regular event control
• Named event control
• Event or control

Regular event control
Format:
@(event) statement;
e.g.: @ (ena) q = d;
@ (posedge t_in) q = ~q;
q = @ (negedge clk) d;
@ (posedge clk_in) q_out = d_in;

Named event control
• Events can be declared with an identifier.

• The declared can be triggered conditionally or
unconditionally, & these doesn‟t hold any data.
• The triggered events can be made to execute the a block of
statements / assignments waiting for this trigger.
• Event is declared by keyword: event event_name;
• Event triggered as: -> event_name;
• Usage: @ <event_name>

Example of named event control
module ex1(out, sig);
output out; always @(shoot)
input sig; //if (shoot == 1‟b1)
reg out; out = 1‟b1;
wire sig;
event shoot;
always @(negedge sig)
begin
if (sig == 1‟b0)
-> shoot;
else
out = 1‟b0;
end

Event or control
• The logical or of any number of events can be expressed such
that the occurrence of any one of the events triggers the
execution of the procedural statement that follows it.
Format:
always @ (event1 or event2 or event3)
always @ (posedge event1 or negedge event2)

Event or control -Example
always @ (in1 or in0 or always @ (posedge clk_in or

sel_in) negedge set_in_n)
begin begin
if (sel_in == 1‟b0) if (set_in_n == 1‟b0)
mux_out = in0;
q_out = 1‟b1;
else
mux_out = in1; else
end q_out = d_in;
end

Level sensitive control
• Execution of statements will be delayed (wait) till a
condition becomes true.
• The nature of the wait statement is level-sensitive, as

opposed to basic event control (specified by the @
character), which is edge-sensitive.
Format:
wait (condition) <statement>

Level sensitive control - Example
module lat(d_in, ena_in_n, q_out);
output q_out;
input d_in, ena_in_n;
reg q_out;
wire d_in, ena_in_n;
always @(d_in or ena_in_n)

begin
wait (ena_in_n == 1‟b0)
q_out = d_in;
end
endmodule

Behavioral constructs
if-else statements
• The if construct checks a specific condition and decides execution
based on the result.
assignment 1;
if(condition) assignment2;
assignment3;
assignment4;
 After execution of assignment1, the condition specified is checked .
If it is
satisfied , assignment2 is executed; if not it is skipped.
 In either case the execution continues through assignment3,
assignment4, etc.
 Execution of assignment2 alone is dependent on the condition. The
rest of the sequence remains.

if-else and if-elseif-else statements
if (<expression 1>)
if (<expression>)
begin
begin
true_statements 1;
true_statements; end
end :
:
if (<expression>) else if (<expression n>)
begin begin
true_statements; true_statements n;
end end
else else
begin begin
false statements; default_statements;
end end
Conditional statement - Examples
if (!ena = 1‟b1)
if (in1 == 1‟b0 && in2 == 1‟b0)
begin
dec_o1 = 1‟b1;
out = in1 & in2;
end
else if (in1 == 1‟b0 && in2 == 1‟b1)
if (sel == 1‟b0) dec_o2 = 1‟b1;
begin
mux_out = in0; else if (in1 == 1‟b1 && in2 == 1‟b0)
end dec_o3 = 1‟b1;
else
begin else
mux_out = in1; dec_o4 = 1‟b1;
end

case statement
case (expression)
•This is a multiway decision alternative 1:begin
statement that tests whether
end
an expression matches one of alternative 2:begin
a number of other alternatives.
end
alternative 3:begin
•Doesn‟t treat „x‟ & „z‟ as
end
don‟t cares. default: begin
end
endcase

case statement - Example
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0); output out;
input s1, s0;
reg out;
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0})
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
2'd3 : out = i3;
default: $display("Invalid control signals");
endcase
endmodule

casez statements
• casez: same as case statement but treats „z‟ as

don‟t cares.
• All bit positions with „z‟ can also be represented

by „?‟

casez - Examples
module
casez_ex(counter,cmd);
input[0:3] counter;
output cmd;
reg cmd;
always@(counter)
casez(counter)
4'b???1:cmd=0;
4'b??10:cmd=1;
4'b?100:cmd=2;
4'b1000:cmd=3;
default : cmd=0;
endcase
endmodule

casex statement
• casex: same as case / casez statement but treats all „x‟

and „z‟ as don‟t cares.

casex - Example
module casex_ex(sel,Bitposition);
input [5:1] sel;
output [2:0] Bitposition;
reg [2:0] Bitposition;
always @ (sel)
casex(sel)
5'bxxxx1 : Bitposition=1 ;
5'bxxx1x : Bitposition=2;
5'bxx1xx : Bitposition=3;
5'bx1xxx : Bitposition=4;
5'b1xxxx : Bitposition=5;
default : Bitposition=0;
endcase
endmodule

Looping statements
• Executes the statements for zero, one or more number of

times.
• Four types of looping statements.

– while
– for
– repeat
– forever

for loop construct
The for loop in Verilog is quite similar to the for loop in C

Format:
for (initialization; expression; inr/dcr)

begin
statements
end
The sequence of execution as follows
1. Execute initialization
2. Evaluate expression
3. If the expression evaluates to the true state(1), carry out
statements. Go to step 5.
4. If the expression evaluates to false state (0), exit the loop.
5. Execute incr/dcr. Go to step 2.

for loop - Example
module addfor (s,co,a,b,cin,en);
for (i=0; i<=7; i=i+1)
output [7:0] s; begin
output co; {c[i+1],s[i]} = (a[i] + b[i] +
input [7:0] a,b; c[i]);
input en,cin; end
co=c[8]
reg [8:0] c;
end
reg co; endmodule
reg [7:0] s;
integer i;
always @ (posedge en)
begin
c[0] = cin;

repeat construct
The repeat construct is used to repeat specified block a specified

number of times.
 The format is show below , the quantity „a „ can be a number or an
expression evaluated to a number.
As soon as the repeat statement is encountered, a is evaluated, the
block will be executed „a‟ times.
If „a‟ evaluates to 0 or x or z, the block is not executed.
Format:
repeat (a)
begin
statements
end

repeat construct - Example
module clkgen (en, cnt);
input en;
output cnt;
integer cnt;
always @ (en)
Begin
if (en)
cnt=0;
repeat (105)
#10 cnt = cnt + 1‟b1;

end
endmodule

While loop
The format of while loop is shown below.
The expression is evaluated. If it is true , the statements
executed and expression evaluated and checked again.
If the expression evaluates to false, the loop is terminated and the
following statement is taken for execution. If the expression
evaluates to true, execution of statement is repeated.
The loop is terminated and broken only if the expression evaluates
to false.
Format:
while (expression)
begin
statements
end
While loop - Example
module while2 (b,n,en,clk);

@(posedge clk)
input [7:0] n; a=a-1‟b1;
input clk,en; end
output b; b=1‟b0;
reg [7:0] a; end
initial
reg b;
b=1‟b0;
always@(posedge en) endmodule
begin
a=n;
while(|a)
begin
b=1‟b1;

forever loop
Repeated execution of a block in an endless manner is best

done with the forever loop ( compare with repeat where
the repetition is for a fixed number of times)
Format:
forever
begin
statements;
end

forever LOOP - Example
module clkgen (clk);

output clk;
reg clk;
initial
begin
clk=1'b0;
forever #10 clk=~clk;
end
initial
#1000 $finish;
endmodule

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Outline

 Evolution of CAD Design.

MODULE-I VLSI SYSTEM DESIGN 1

• IC chip evolution -> SSI, MSI, LSI, VLSI…

• Complicated design processes.

• Traditional / conventional design method includes manual

MODULE-I VLSI SYSTEM DESIGN 2

• In all the above design methods the functional bugs

MODULE-I VLSI SYSTEM DESIGN 3

• Popular HDLs are Verilog HDL & VHDL (for

MODULE-I VLSI SYSTEM DESIGN 4

MODULE-I VLSI SYSTEM DESIGN 5

• HDL descriptions are easily portable, and is also

• HDLs can describe the digital systems at various

• HDL descriptions can be functionally simulated

MODULE-I VLSI SYSTEM DESIGN 6

• Digital circuits described at Register Transfer

• Logic Synthesis tools can extract gate level

MODULE-I VLSI SYSTEM DESIGN 7

 VHDL : Very High Speed Integrated Circuit Hardware Description

MODULE-I VLSI SYSTEM DESIGN 8

MODULE-I VLSI SYSTEM DESIGN 9

• Gateway Design Automation introduced Verilog in

• Cadence took over in 1989.

• Cadence made Verilog HDL public in 1990.

• Verilog HDL becomes IEEE 1364-1995.

MODULE-I VLSI SYSTEM DESIGN 10

• Allows different levels of abstraction to be mixed in

• Easy to learn and easy to use.

• Almost all logic simulation & synthesis tools

• Verilog HDL is an IEEE 1364 standard.

MODULE-I VLSI SYSTEM DESIGN 11

MODULE-I VLSI SYSTEM DESIGN 13

MODULE-I VLSI SYSTEM DESIGN 14

MODULE-I VLSI SYSTEM DESIGN 15

• Two comment structures are available in verilog:

• Multiple line comments cannot be nested.

• All the keywords in Verilog must be in lower case.

• Verilog constructs may be written across multiple

MODULE-I VLSI SYSTEM DESIGN 17

• Identifiers refer objects to be referenced in the

• Identifiers are made of alphabets (both cases),

• They start with an alphabetic character or

MODULE-I VLSI SYSTEM DESIGN 18

• Identifiers are case sensitive i.e., identifiers

• An identifier say count is different from

MODULE-I VLSI SYSTEM DESIGN 19

• Numbers without <base format> are decimal by

MODULE-I VLSI SYSTEM DESIGN 23

MODULE-I VLSI SYSTEM DESIGN 24

• “Verilog classes are very interesting???”

• Spaces are not ignored in strings.

• Strings cannot be on multiple lines.

MODULE-I VLSI SYSTEM DESIGN 25

• The module definition is the same for a system of

• Provides functionality through its port interface.

• It can be an element or a collection of lower-level

MODULE-I VLSI SYSTEM DESIGN 26

MODULE-I VLSI SYSTEM DESIGN 27

MODULE-I VLSI SYSTEM DESIGN 28

module T_FF(q, clock, reset) // Illegal

D_FF NOT D_FF NOT

MODULE-I VLSI SYSTEM DESIGN 31

• Each object has its own name, variables, parameters