9/22/2019 Lockup latch – principle, application and timing

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Lockup latch – principle, application and timing
V
What are lock-up latches: Lock-up latch is an important element in scan-based designs, especially for hold ming
closure of shi modes. Lock-up latches are necessary to avoid skew problems during shi phase of scan-based
tes ng. A lock-up latch is nothing more than a transparent latch used intelligently in the places where clock skew is Be the first o
very large and mee ng hold ming is a challenge due to large uncommon clock path. That is why, lockup latches are
used to connect two flops in scan chain having excessive clock skews/uncommon clock paths as the probability of
hold failure is high in such cases. For instances, the launching and capturing flops may belong to two different
domains (as shown in figure below). Func onally, they might not be interac ng. Hence, the clock of these two
domains will not be balanced and will have large uncommon path. But in scan-shi mode, these interact shi ing the
data in and out. Had there been no lockup latches, it would have been very difficult for STA engineer to close ming in
a scan chain across domains. Also, probability of chip failure would have been high as there a large uncommon path
between the clocks of the two flops leading to large on-chip-varia ons. That is why; lockup latches can be referred as
as the soul mate of scan-based designs.

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Duty cycle Figure 1 : Lockup latches - the soul mate of scan-based designs
variation of
inter-clock
timing paths

Duty cycle Where to use a lock-up latch: As men oned above, a lock-up latch is used where there is high probability of hold
variation failure in scan-shi modes. So, possible scenarios where lockup latches are to be inserted are:

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9/22/2019 Lockup latch – principle, application and timing
Design problem:
How do you
detect if two 8- Scan chains from different clock domains: In this case, since, the two domains do not interact
bit func onally, so both the clock skew and uncommon clock path will be large.
numbers/signal Flops within same domain, but at remote places: Flops within a scan chain which are at remote places
s are equal
are likely to have more uncommon clock path.

In both the above men oned cases, there is a great chance that the skew between the launch and capture clocks will
Single-bit
magnitude be high. There is both the probability of launch and capture clocks having greater latency. If the capture clock has
comparator greater latency than launch clock, then the hold check will be as shown in ming diagram in figure 3. If the skew
difference is large, it will be a tough task to meet the hold ming without lockup latches.

STA query : How

positive edge
trigger reg to
positive latch
path is zero
cycle. But
positive latch to
rising flop is full
cycle?
Your co
Design problem:
me write
Logic is not a
minimization
and :-)
restructuring for Figure 2: A path crossing from domain 1 to domain 2 (scope for a lock-up latch insertion)
timing critical Blog Archive
paths
►
► 2012 (1)
How many 2- ▼
▼ 2013 (26)
input muxes are ►
► Januar
needed to
►
► Februa
create an N-
input mux ►
► March
►
► May (6
Figure 3: Timing diagram showing setup and hold checks for path crossing from domain 1 to domain 2
Setup time ▼
▼ June (2
Lockup
timing
Programming
problem: Posi ve or nega ve level latch?? It depends on the path you are inser ng a lock-up latch. Since, lock-up latches are Routing
Synthsizable inserted for hold ming; these are not needed where the path starts at a posi ve edge-triggered flop and ends at a ►
► July (5
filter design in
nega ve edge-triggered flop. It is to be noted that you will never find scan paths origina ng at posi ve edge-triggered
C++ ►
► August
flop and ending at nega ve edge-triggered flop due to DFT specific reasons. Similarly, these are not needed where
►
► Septem
path starts at a nega ve edge-triggered flop and ends at a posi ve edge-triggered flop. For rest two kinds of flop-to-
STA problem: ►
► Octobe
flop paths, lockup latches are required. The polarity of the lockup latch needs to be such that it remains open during
Checking for
setup/hold the inac ve phase of the clock. Hence, ►
► 2014 (19)
violations in a ►
► 2015 (33)
timing path
For flops triggering on posi ve edge of the clock, you need to have latch transparent when clock is low ►
► 2016 (74)
(nega ve level-sensi ve lockup latch)
►
► 2017 (45)
Mice and For flops triggering on nega ve edge of the clock, you need to have latch transparent when clock is high
poisonous ►
► 2018 (7)
(posi ve level-sensi ve lockup latch)
bottles ►
► 2019 (16)
Who inserts a lock-up latch: These days, tools exist that automa cally add lockup latches where a scan chain is
Implement 3- crossing domains. However, for cases where a lockup latch is to be inserted in an intra-domain scan chain (i.e. for
Contributors
input gates flops having uncommon path), it has to be inserted during physical implementa on itself as physical informa on is
using 2:1 muxes not feasible during scan chain implementa on (scan chain implementa on is carried out at the synthesis stage itself). Unknow
VLSI U
Why higher Which clock should be connected to lock-up latch: There are two possible ways in which we can connect the clock
education pin of the lockup latch inserted. It can either have same clock as launching flop or capturing flop. Connec ng the
Popular pos
clock pin of lockup latch to clock of capturing flop will not solve the problem as discussed below.
Why This Blog ? Lock-up latch and capturing flop having the same clock (Will not solve the problem): In this case, the
setup and hold checks will be as shown in figure 5. As is apparent from the waveforms, the hold check
Myself between domain1 flop and lockup latch is s ll the same as it was between domain 1 flop and domain 2
flop before. So, this is not the correct way to insert lockup latch.
form of win
How
propagation of
‘X’ happens
through

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9/22/2019 Lockup latch – principle, application and timing
different logic
gates in an IC le
to the...

Engineering
Change Order Amazon
(ECO)

MBIST (Memory
Built-In Self
Test)

Latchup and its

prevention in Figure 4: Lock-up latch clock pin connected to clock of capturing flop
CMOS devices

Metastability

Carry Look
Ahead Adder Also read

Interesting
Design Quiz -
BCD multiply by Figure 5: Timing diagrams for figure 4
five circuit
Drain, Gate…

Lock-up latch and launching flop having the same clock: As shown in figure 7, connec ng the lockup
latch to launch flop’s clock causes the skew to reduce between the domain1 flop and lockup latch. This
hold check can be easily met as both skew and uncommon clock path is low. The hold check between
lockup latch and domain2 flop is already relaxed as it is half cycle check. So, we can say that the correct
way to insert a lockup latch is to insert it closer to launching flop and connect the launch domain clock to
its clock pin.

Figure 6: Lock-up latch clock pin connected to clock of launch flop

timing path from

positive…

selects one ou
N-input…
Figure 7: Waveforms for figure 6

Why don’t we add buffers: If the clock skew is large at places, it will take a number of buffers to meet hold
requirement. In normal scenario, the number of buffers will become so large that it will become a concern for power
and area. Also, since skew/uncommon clock path is large, the varia on due to OCV will be high. So, it is
recommended to have a bigger margin for hold while signing it off for ming. Lock-up latch provides an area and

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9/22/2019 Lockup latch – principle, application and timing
power efficient solu on for what a number of buffers together will not be able to achieve.

Advantages of inser ng lockup latches:

Inser ng lock-up latches helps in easier hold ming closure for scan-shi mode
Robust method of hold ming closure where uncommon path is high between launch and capture flops
Power efficient and area efficient
It improves yield as it enables the device to handle more varia ons.

Lockup registers: Instead of latches, registers can also be used as lockup elements; however, they
have their own advantages and disadvantages. Please refer to Lockup latches vs. lockup registers :
what to chose for a comparative study of using lockup latches vs lockup registers.

References:
1) “Why not add buffer but lockup latch” - h p://www.edaboard.com/thread82364.html

Also read:

Setup and hold checks for latch-to-flop and flop-to-latch paths

Controllability and observability - the two DFT principles
On-chip variations - the STA takeaway
Setup and hold - basics of timing analysis
Interesting problem - latches in series

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Labels: DFT, Digital system design, IQ, latch, Lockup latch, OCV, on chip variations, setup, setup and hold, setup check,
Static timing analysis, test principles, timing, timing basics, VLSI

2 comments:

Anonymous 20 July 2013 at 05:45

Do we need to insert lockup latches in case capturing clock is built at lesser latency?
Reply

Van Sal 20 July 2013 at 21:53

As mentioned above, there are two cases in which lockup latches need to be inserted - skew and
uncommon path. If we consider ideal scenario, there should not be the need. However, due to on-chip
variations, the variation in launch and capture path may be very large. So, if launch and capture path
have large uncommon path, even if the capture flop is built at lesser latency; in real silicon scenario, it
may exceed the latency of launch clock path. Hence, it is better if we have a lockup latch for better yield.
Reply

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