Digital Assignment – 2.

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Programme Name & Branch: B.Tech – CSE

Course Name & Code: Computer Architecture and Organization & CSE2001

Class Number: SJT 422 Date of Submission: 24.09.2019 Slot: C1+TC1

Faculty : Dr T Gopalakrishnan

General instruction(s):

 Missing data if any may be assumed suitably.

Assignment Questions

1. Represent the decimal number = (-35.6875)10 in IEEE 754 single precision floating
point representation.
2. Perform 13 ÷ 4 by restoring division algorithm.
3. Consider that floating point numbers are represented in a 17 bit format with a 7-bit,
excess 63 exponent. The 9-bit mantissa is normalized as in the IEEE format, with an
implied 1 to the left of the binary point. Represent floating value=(+4.25)10.
4. C20F0000H is hexadecimal equivalent of IEEE single precision floating point number. Convert
it into its decimal equivalent.
5. Consider two floating point numbers A = 32.5 and B = 4.25.
(i) Represent these numbers in 17-bit format (1 bit sign, 7 bits exponent, 9 bits mantissa)
similar to IEEE 754 format.
(ii) Perform A+B. Use 17 bit format to show the result.
(iii) Perform A×B. Use 17 bit format to show the result.

6. A computer system has a byte addressable main memory of size 4GB. It has Cache
memory of size 4MB and block size is 1KB. How many bits will be used to specify
Tag, Block and Word fields in direct- mapped cache?

7. The word length is 32 bits. A 4-way set associative cache memory unit with a capacity of
16 KB is built using a block size of 8 words. The size of the physical address space is 4
GB. The number of bits for the TAG field is _____.

8. Consider a 2-way set associative cache with total 16 cache blocks. The main memory consists
of 256 blocks and request for main memory blocks in following order:
0,255,1,72, 4, 159,3,8,133,255,216,219,63,8,45,133,3
 Find out the hit and miss ratio for the given references of Main Memory blocks if LRU block
replacement policy is used. Assume cache is empty initially.
9. A computer system has a 128 byte cache. It uses four-way set-associative mapping with 8
bytes in each block. The physical address size is 32 bits, and the smallest addressable unit is
1 byte.

(i) To what block frames of the cache can the address 000010AFH be assigned?

(ii) If the addresses 000010AFH and FFFF7AxyH can be simultaneously assigned to the same
Cache set, what values can the address digits x and y have?

10. a) How many 128 x 8 RAM chips are needed to provide a memory capacity of 4096 bytes?
b) How many lines of the address bus must be used to access 2048 bytes of memory?
c) How many of these lines will be common to all chips?
d) How many lines must be decode for chip select? e. Specify the size of the decoders.

11. A computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8. The computer system
needs 2K bytes of RAM, 4K bytes of ROM, and four interface units, each with four registers.
A memory-mapped I/O configuration is used. The two highest-order bits of the address bus
are assigned 00 for RAM and 10 for interface registers. a. How many RAM and ROM chips
are needed? b. Draw a memory-address map for the system. c. Give the address range in
hexadecimal for RAM, ROM and interface.

12.