1 2 3 4

A A

U_Connections U_Power
Connections.SchDoc Power.SchDoc

EXT_POWERED EXT_POWERED
U_FPGA U_AFE
FPGA.SchDoc AFE.SchDoc
GPIO_[55..0] GPIO_[55..0] XCVR_RESET XCVR_RESET
XCVR_ENABLE XCVR_ENABLE
FPGA_INIT_B XCVR_EN_AGC XCVR_EN_AGC
B FPGA_DONE XCVR_SYNC_IN XCVR_SYNC_IN B
PROGRAM_B XCVR_TXNRX XCVR_TXNRX
FX3_GPIO50
FPGA_INIT_B XCVR_SPI_ENB XCVR_SPI_ENB
FX3_GPIO57
FPGA_DONE XCVR_SCLK XCVR_SCLK
FX3_GPIO52
PROGRAM_B XCVR_MOSI XCVR_MOSI
XCVR_MISO XCVR_MISO
FX3_GPIO51
FX3_GPIO0
FX3_GPIO54
FPGA_SPI_SS XCVR_DATA_CLK XCVR_DATA_CLK
FX3_GPIO[57..50]

FX3_GPIO53
FPGA_SPI_CLK XCVR_CLK_OUT XCVR_CLK_OUT
FX3_GPIO56
FPGA_SPI_MOSI XCVR_FB_CLK XCVR_FB_CLK
FX3_GPIO55
FX3_I2C_SDA FPGA_SPI_MISO XCVR_TX_FRAME XCVR_TX_FRAME
FX3_I2C_SCL FPGA_SPI_DQ2 XCVR_RX_FRAME XCVR_RX_FRAME
FPGA_SPI_DQ3
U_USB
XCVR_CTRL_IN[3..0] XCVR_CTRL_IN[3..0]
USB.SchDoc
XCVR_CTRL_OUT[7..0] XCVR_CTRL_OUT[7..0]
RESET RESET
XCVR_P0_D[11..0] XCVR_P0_D[11..0]
FX3_I2C_SCL
FX3_I2C_SDA

FX3_GPIO[57..50]

C XCVR_P1_D[11..0] XCVR_P1_D[11..0] C

RX_BAND_A TX_BAND_A
IF_DQ[31..0] IF_DQ[31..0] RX_BAND_B TX_BAND_B
IF_CTL[12..0] IF_CTL[12..0] RX_BAND_C RX_BAND_A
IF_INT IF_INT TX_BAND_A RX_BAND_B
IF_PCLK IF_PCLK TX_BAND_B RX_BAND_C

Title
D D
FreeSRP
Size Number Revision
A4 1 2
Date: 29/02/2016 Sheet 1 of 7
File: C:\Users\..\FreeSRP.SchDoc Drawn By: Lukas Lao Beyer
1 2 3 4
 1 2 3 4 5 6 7 8

6V5: 6.50V, 1A 1V3_XCVR: 1.30V, 1.2A

IMPORTANT:
Check out layout & stencil recommendations in datasheet
GND
L4
GND C161 C162 C163
1uH B82472G6102M
BUS/EXTERNAL POWER SELECTION GND 6V5 C159 C160
C1210
47uF
10uF 100nF

C1210 100nF
C170 R50 C173 C174 C175 47uF 1V3_XCVR
U10

10
1
C1210 1M C1210 C1210 C1210 1 10
A External 22uF 47uF 22uF 22uF 1V8 VIN VOUT R45 A
2 9 2 11
regulated 9V V+ VIN VOUT VIN VOUT

L1

L2
3 12 16K 1%
input D3 VIN VOUT
3 8 15 13
EN FB VIN VOUT
4 16 14
EXT PS/SYNC VIN VOUT
C172
SSB43L-E3/52T Q1 6 5 R49 4 9 R46
NTMS4177P V+: 4 to 9V VAUX PG 82K C171 EN ADJ GND
GND 10K 1%
100nF 7 PP 10pF 5 7
VBUS 5, 6, 7, 8 1, 2, 3
V+ GND PGND PG SS
U12 8 17
USB NC EP C158
TPS63060 6
4.5-5.5V GND
U15 4 R53 10nF
1 5 470K R52 GND GND GND GND ADP1755ACPZ-R7
VIN GATE 0.5R
6
SENSE
GND GND
4
1V0: 1.00V, 4A
STAT
3 2 C182
1V3_SYNTH: 1.30V, 1.2A
CTL GND C1210
LTC4412ES6 22uF
1% Connect directly GND
R38 R39 between pins 35
5K62 210R and 33/34 GND C166 C167 C168
GND GND GND
C1210 10uF 100nF
U7 LMZ30604 C164 C165 47uF
35 36 C1210 100nF
EXT_POWERED 3V3 VADJ SENSE+ 47uF 1V3_SYNTH
U11
B Q2 GND R40 B
4 8 1 10
R54 BSS84 RT/CLK VOUT 1V8 VIN VOUT R47
1M2 9 2 11
22K VOUT GND VIN VOUT 16K 1%
GND 6 10 3 12
TP10 SS/TR VOUT VIN VOUT
7 11 15 13
GND STSEL VOUT C145 C44 VIN VOUT
12 16 14
VOUT C1210 T520D VIN VOUT
13
VOUT 47uF 100uF R48
30 14 4 9
V+ VIN VOUT EN ADJ GND
31 38 10K 1%
VIN VOUT 1V0
C147 32 5 7
C146 VIN PG SS
T520D 17
3V3: 3.30V, 0.8A C1210 PH
220uF 1 18 8 17
47uF AGND PH NC EP C169
5 19 6
GND AGND PH GND 10nF
29 20
AGND PH
U14 LD1117AS33TR 33 21 ADP1755ACPZ-R7
AGND PH
3 2 34 22
V+ VIN VOUT 3V3 AGND PH
4 23
VOUT PH
37 24 GND GND
C180 GND C181 PGND PH
25
100nF 10uF PH
39
PH
1

DNC
DNC
DNC
DNC
DNC
28
INH/UVLO PWRGD
27
1V2: 1.20V, 0.5A

2
3
15
16
26
Input and output GND
GND
cap ground
points must be C155 C156
close 1uF 2u2
U9A TPS73512DRBR
1V8: 1.80V, 4A
C C
8 1
5V_TX: 5.00V, 0.2A
V+ IN OUT 1V2
5 3
EN NR
U9B
Connect directly GND
U13 LT3042 2
5V_TX between pins 35 NC C157
1 10 6
6V5 IN OUT and 33/34 NC

9
2 9 7 47nF
IN OUTS C177 R42 NC
3 8
EN/UV GND 4u7 GND
4 7 U8 LMZ30604 TPS73512DRBR
GND

PG SET 1.15k 1%
C176 5 6 35 36
4u7 ILIM PGFB GND VADJ SENSE+
GND R43 4 8
RT/CLK VOUT
11

C178 R44 9
348k 1% VOUT GND
GND 1uF 49K9 1% 6 10
SS/TR VOUT
7 11
GND STSEL VOUT C150 C151
GND 12
VOUT C1210 T520D
13
VOUT 47uF 100uF
GND 30 14
V+ VIN VOUT
31 38
VIN VOUT 1V8
C149 32
C148 VIN
GND T520D 17
C1210 PH
220uF 1 18
47uF AGND PH
5 19
GND AGND PH
29 20
AGND PH
33 21
AGND PH
34 22
AGND PH
23
PH
D 37 24 D
PGND PH
25
PH
39
PH
DNC
DNC
DNC
DNC
DNC

28 27 Title
INH/UVLO PWRGD
Power
2
3
15
16
26

Size Number Revision

A3 2 2
Date: 29/02/2016 Sheet 2 of 7
File: C:\Users\..\Power.SchDoc Drawn By: Lukas Lao Beyer
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

EXPANSION HEADERS LED INDICATORS

GPIO_[55..0]
GPIO_[55..0] POWER INDICATORS

GPIO_50
GPIO_52
GPIO_42
GPIO_41
GPIO_43
GPIO_45
GPIO_44
GPIO_46
GPIO_47
GPIO_54
D4

A FPGA_INIT_B R57 A
P8
PROGRAM_B 3V3 GND
GPIO_34 GPIO_0 120R
1 32
GPIO_2 GPIO_37 RED
2 31
GPIO_5 GPIO_28

10
3 30

1
2
3
4
5
6
7
8
9
GPIO_3 GPIO_38
FX3_I2C_SDA 4 29
P7 GPIO_20 GPIO_36
5 28

1
2
3
4
5
6
7
8
9
10
TP11 GPIO_32 GPIO_39
6 27

62674-201121ALF
GPIO_35 GPIO_33
FX3_I2C_SCL 7 26
GPIO_15 GPIO_26

20
19
18
17
16
15
14
13
12
11
TP12 8 25
GPIO_17 GPIO_27 P10
9 24 D6
GPIO_9 GPIO_14 GPIO_50
10 23 GND 1 2

20
19
18
17
16
15
14
13
12
11
GPIO_12 GPIO_23 GPIO_52
11 22 3 4 R59
GPIO_11 GPIO_22 GPIO_43
12 21 V+ 5 6 EXT_POWERED GND
GPIO_19 GPIO_21 GPIO_42 82R
13 20 6V5 7 8
GPIO_16 GPIO_18 GPIO_41 GREEN
14 19 1V8 9 10
GPIO_6 GPIO_24 GPIO_46
15 18 1V8 11 12
GPIO_13 GPIO_25 GPIO_44
16 17 13 14
GPIO_45
GND 15 16
GRPB082VWQS-RC
Header 8X2 FPGA DONE
V+ 6V5 1V8 1V8 D7
Q3 NDS331N
3V3 GND
GND
GREEN

B FPGA_DONE B

RP1
5 4
GENERAL PURPOSE 6
7
3
2
EXTERNAL POWER D8
8
4X100R
1

Q4 NDS331N
3V3 GND
RED
6V REGULATED INPUT
P9 FX3_GPIO0
D9
Q5 NDS331N
GND EXT
3V3 GND

SC1153-ND GREEN

RP2
GPIO_7 5 4
6 3
D10 7 2
C 8 1 Q6 NDS331N C
3V3 4X100R GND
GREEN RP4
5 4
6 3
GPIO_1 7 2
8 1
D11
Q7 NDS331N 4X10K

3V3 GND
GREEN
GND
RP3
GPIO_8 5 4
6 3
D12 7 2
8 1 Q8 NDS331N
3V3 4X100R GND
GREEN

GPIO_10

D D

Title
Expansion Connectors and Status LEDs
Size Number Revision
A3 3 2
Date: 29/02/2016 Sheet 3 of 7
File: C:\Users\..\Connections.SchDoc Drawn By: Lukas Lao Beyer
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

BYPASS
FB3
FB1 1V2 1V2_USBRX
1V8 1V8_CVDDQ MPZ2012S601A Ball where to install capacitor 2 capacitors per VIO ball.
VBUS 1V2 1V2 1V8
MPZ2012S601A C77 C78 over component designator.
C73 C74 2.2uF 0.1uF
2.2uF 0.1uF
GND
H1 L7 F11 L5 J11 B10 C3 E9 J11 B10
GND C86 C79 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72
FB2 0.1uF 22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF
FB9 1V2 1V2_USBTX
A 1V2 1V2_AVDD MPZ2012S601A A
MPZ2012S601A C75 C76
C188 C189 2.2uF 0.1uF
2.2uF 0.1uF GND GND GND GND
GND
GND

POWER CLOCK & MISC. 1V8

BOOT MODE SEL. GPIF II FPGA INTERFACE
R5 Pull-up/down
U3A
RESET 100K should be 10K IF_PCLK
B7 A7
GND AVSS AVDD 1V2_AVDD
U3E
SW1 1V8
A1 A2 U3B J6 L8
U3VSSQ U3RXVDDQ 1V2_USBRX PCLK INT# IF_INT
B5 C6 C5
U3TXVDDQ 1V2_USBTX XTALIN RESET# GND R6 R8 R10
X2 C7 FX3_RESET DQ0 F10
XTALOUT DNP 10K DNP DQ[0]
B6 7S-19.200MAHE-T DQ1 F9
CVDDQ 1V8_CVDDQ DQ[1] IF_CTL[12..0]

CTL[12..0]
D7 G4 PMODE_0 C82 DQ2 F7
CLKIN PMODE[0] 100nF DQ[2]
H1 D6 H4 PMODE_1 DQ3 G10 K8 CTL0
VDD 1V2 CLKIN_32 PMODE[1] DQ[3] CTL[0]
L7 L4 PMODE_2 DQ4 G9 K7 CTL1
VDD PMODE[2] DQ[4] CTL[1]
J11 B2 DQ5 F8 J7 CTL2
VDD FSLC[0] DQ[5] CTL[2]

PMODE_0

PMODE_1

PMODE_2
L5 C80 C81 B4 DQ6 H10 H7 CTL3
VDD 12pF 12pF GND FSLC[1] R7 R9 R11 DQ[6] CTL[3]
C3 E6 A11 GND DQ7 H9 G7 CTL4
VDD FSLC[2] NC DNP DNP DNP DQ[7] CTL[4]
A8 E9 DQ8 J10 G6 CTL5
VSS VDD DQ[8] CTL[5]
L2 F11 CYUSB3014-BZXC DQ9 J9 K6 CTL6
VSS VDD DQ[9] CTL[6]
K3 B10 DQ10 K11 H8 CTL7
B VSS VDD DQ[10] CTL[7] B
L3 DQ11 L10 G5 CTL8
VSS GND DQ[11] CTL[8]
K4 H11 GND DQ12 K10 H6 CTL9
VSS VIO1 1V8 DQ[12] CTL[9]
B8 L9 DQ13 K9 K5 CTL10
VSS VIO1 DQ[13] CTL[10]
B9 F1 DQ14 J8 J5 CTL11
VSS VIO2 DQ[14] CTL[11]
G1 E3 DQ15 G8 H5 CTL12
FX3 BOOT FLASH MEMORY JTAG
VSS VIO3 DQ[15] CTL[12]
G11 B1
VSS VIO4
L1 C11 CYUSB3014-BZXC
VSS VIO5
L6 U4
VSS
D8 E11 1 6 I2C_SCL J2 P5 U3D DQ[31..0]
VSS VBUS VBUS GND A0 SCL IF_DQ[31..0]
E2 2 5 I2C_SDA E8
VSS A1 SDA VBUS 1 2 TMS
L11 E10 3 DNP F6 U3F
VSS VBATT GND A2 3 4 TCK
C10 DQ16 K2
GND 5 6 TDO DQ[16]
CYUSB3014-BZXC 4 E7 DQ17 J4
C83 GND 7 8 TDI DQ[17]
8 7 B11 DQ18 K1
0.1uF VCC WP GND 9 10 TRST# DQ[18]
J1 DQ19 J2
DQ[19]
AT24C256C Header 5X2 CYUSB3014-BZXC DQ20 J3
1V8 DQ[20]
DQ21 J1
DQ[21]
DQ22 H2
DQ[22]
DQ23 H3
DQ[23]
DQ24 F4
USB 3.0 INTERFACE FX3 GPIO & I2C
DQ[24]
DQ25 G2
DQ[25]
U19 DQ26 G3
DQ[26]
8 10 USB_SSRX_P DQ27 F3
GND NC ESD protection DQ[27]
3 9 USB_SSRX_N FX3_GPIO[57..50]
GND GND NC (place near FX3_GPIO[57..50]
7 USB_SSTX_P CYUSB3014-BZXC
NC connector)
6 USB_SSTX_N
NC
U3G U3H
C 5 2 FX3_GPIO50 D1 DQ28 F5 C
D2- D1- GPIO[50] DQ[28]
4 1 F2 DQ29 E1
D2+ D1+ GPIO[45] DQ[29]
FX3_GPIO51 D2 DQ30 E5

FX3_I2C_SDA
FX3_I2C_SCL
GPIO[51] DQ[30]
TPD4EUSB30DQAR FX3_GPIO52 D3 DQ31 E4
GPIO[52] DQ[31]
FX3_GPIO53 D4
GPIO[53]
FX3_GPIO54 C1 CYUSB3014-BZXC
R12 GPIO[54]
U3C FX3_GPIO55 C2
GPIO[55]
GSB343K33HRCT-ND USB_SSRX_N USB_OTG_ID C9 B3 200R 1% FX3_GPIO56 D5
OTG_ID R_usb3 GPIO[56]
P4 USB 3.0 CONNECTOR USB_SSRX_P C8 FX3_GPIO57 C4
FB4 TP8 R_usb2 R13 GPIO[57]
1 9 A3
VBUS VBUS SSRX- SSRXM
10 A4 6.04K 1% I2C_SCL D9
BLM21PG221SN1D SSRX+ SSRXP I2C_GPIO[58]
C84 USB_PRECAPTX_N A6 I2C_SDA D10
SSTXM I2C_GPIO[59]
5 6 USB_SSTX_N USB_PRECAPTX_P A5
GND GND SSTX- SSTXP
8 7 USB_SSTX_P GND CYUSB3014-BZXC
GND SSTX+ R14 R15
100nF A10
DM 2K2 2K2
2 C85 A9 D11
USB D- DP O[60]
USB_OTG_ID 4 3
OTG ID USB D+
CYUSB3014-BZXC
100nF
1V8
SHELL GND USB_D_N
USB_D_P
11
12
13
14
15
16

FB5 Groundplane
cutout under
BLM21PG221SN1D C84 & C85
C87
D GND D

100nF

Title
USB Interface
Size Number Revision
A3 4 2
Date: 29/02/2016 Sheet 4 of 7
File: C:\Users\..\USB.SchDoc Drawn By: Lukas Lao Beyer
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8
U5A XC7A100T-2FTG256C P6 XILINX_PLAT_CON
K12 GPIO_0 R31 R33 R35 14 13 U5D
IO_0_14 Boot mode 1V8 1V8 1V8 14 13 GND
BANK 14
J13 FPGA_SPI_MISO DNP (1K) DNP (1K) 1K 12 11 GPIO_40 E6
IO_L1P_T0_D00_MOSI_14 FPGA_SPI_MISO select (default: 12 11 IO_0_35

BANK 35
J14 FPGA_SPI_MOSI MODE0 MODE1 MODE2 FPGA_TDI 10 9 GPIO_41 B7

XCVR_DATA_CLK
IO_L1N_T0_D01_DIN_14 FPGA_SPI_MOSI SPI master) 10 9 IO_L1P_T0_AD4P_35

XCVR_MOSI
K15 FPGA_SPI_DQ2 FPGA_TDO 8 7 GPIO_42 A7
IO_L2P_T0_D02_14 FPGA_SPI_DQ2 R32 R34 R36 8 7 IO_L1N_T0_AD4N_35
K16 FPGA_SPI_DQ3 FPGA_TCK 6 5 GPIO_43 B6
IO_L2N_T0_D03_14 FPGA_SPI_DQ3 GND GND GND 6 5 IO_L2P_T0_AD12P_35
L15 1K 1K DNP (1K) FPGA_TMS 4 3 GPIO_44 B5
IO_L3P_T0_DQS_PUDC_B_14 4 3 IO_L2N_T0_AD12N_35
M15 GPIO_1 2 1 GPIO_45 A5
FPGA CONFIG & MISC.
IO_L3N_T0_DQS_EMCCLK_14 1V8 2 1 XCVR_CTRL_OUT[7..0] IO_L3P_T0_DQS_AD5P_35
L14 GPIO_2 GPIO_46 E2
IO_L4P_T0_D04_14 R24 R23 XCVR_CTRL_IN[3..0] IO_L10P_T1_AD15P_35
M14 GPIO_3 GPIO_33T10
IO_L4N_T0_D05_14 DNP (1K) 1K IO_L22N_T3_A04_D20_14
K13 GPIO_4 U5E A3
POWER
IO_L5P_T0_D06_14 IO_L4N_T0_35
L13 GPIO_5 FPGA_TDI N7 GPIO_49 C7
A IO_L5N_T0_D07_14 TDI_0 IO_L5P_T0_AD13P_35 A
L12 FPGA_SPI_SS 1V8 1V8 1V8 FPGA_TDO N8 GPIO_50 C6
IO_L6P_T0_FCS_B_14 TDO_0 IO_L5N_T0_AD13N_35
M12 GPIO_6 FPGA_TCK L7 CTRL_OUT0 G5
IO_L6N_T0_D08_VREF_14 TCK_0 IO_L16P_T2_35
M16 GPIO_7 FPGA_TMS M7 U5F CTRL_OUT1 C2

CTRL_OUT[7..0]
IO_L7P_T1_D09_14 TMS_0 IO_L7N_T1_AD6N_35
N16 GPIO_8 1V8 L6 F8 CTRL_OUT2 D3

RESET
FPGA_SPI_SS
IO_L7N_T1_D10_14 R16 R17 R18 1V8 VCCO_0 VCCBATT_0 GND IO_L11N_T1_SRCC_35
P15 GPIO_9 GND FPGA_SPI_CLK E8 CTRL_OUT3 C1
IO_L8P_T1_D11_14 Pin state at 2K4 4K7 4K7 FPGA_SPI_CLK CCLK_0 IO_L9P_T1_DQS_AD7P_35
P16 GPIO_10 MODE0 M9 L16 G8 CTRL_OUT4 B1
IO_L8N_T1_D12_14 boot M0_0 VCCO_14 VCCADC_0 1V8 IO_L9N_T1_DQS_AD7N_35
R15 GPIO_11 MODE1 M10 M13 CTRL_OUT7 C3
IO_L9P_T1_DQS_14 TP18 M1_0 VCCO_14 IO_L7P_T1_AD6P_35
R16 GPIO_12 MODE2 M11 N10 F7 CTRL_OUT6 H5
IO_L9N_T1_DQS_D13_14 TP17 M2_0 VCCO_14 VCCINT 1V0 IO_L18P_T2_35
T14 GPIO_13 P7 F9 GPIO_52 D6

FPGA_INIT_B

PROGRAM_B
FPGA_SPI_SS
IO_L10P_T1_D14_14 TP16 VCCO_14 VCCINT IO_L6P_T0_35
T15 GPIO_14 FPGA_DONE H10 R14 G6 CTRL_IN0 F3

CTRL_IN[3..0]
IO_L10N_T1_D15_14 FPGA_DONE DONE_0 VCCO_14 VCCINT IO_L14N_T2_SRCC_35
N13 GPIO_15 FPGA_INIT_B K10 T11 H9 CTRL_IN1 E1
IO_L11P_T1_SRCC_14 FPGA_INIT_B INIT_B_0 VCCO_14 VCCINT IO_L15N_T2_DQS_35
P13 GPIO_16 J6 CTRL_IN2 E3
IO_L11N_T1_SRCC_14 VCCINT IO_L11P_T1_SRCC_35

GPIO_[55..0]
N14 FPGA_CLK PROGRAM_B L9 A16 K9 CTRL_IN3 D1
IO_L12P_T1_MRCC_14 PROGRAM_B PROGRAM_B_0 VCCO_15 VCCINT IO_L10N_T1_AD15N_35
P14 GPIO_17 E7 B13 L8 CTRL_OUT5 F4
IO_L12N_T1_MRCC_14 CFGBVS_0 VCCO_15 VCCINT IO_L14P_T2_SRCC_35
N11 GPIO_18 C10 C4
IO_L13P_T2_MRCC_14 For 1.8V GND VCCO_15 IO_L12N_T1_MRCC_35
N12 GPIO_19 1V8 H8 E14 G10 F5
IO_L13N_T2_MRCC_14 VP_0 VCCO_15 VCCAUX 1V8 IO_L13P_T2_MRCC_35
P10 GPIO_20 J7 H15 J10 XCVR_P0_D0N4
IO_L14P_T2_SRCC_14 VN_0 VCCO_15 VCCAUX IO_L6N_T0_VREF_34
P11 GPIO_21 J12 K11 XCVR_P0_D1J1
IO_L14N_T2_SRCC_14 VCCO_15 VCCAUX IO_L22N_T3_35
R12 GPIO_22 J8 L10 XCVR_P0_D2
M2
IO_L15P_T2_DQS_RDWR_B_14 VREFP_0 VCCAUX IO_L2P_T0_34

XCVR_TXNRX
T12 GPIO_23 R19 H7 XCVR_P0_D3H3

XCVR_P0_D[11..0]
IO_L15N_T2_DQS_DOUT_CSO_B_14 330R VREFN_0 IO_L21N_T3_DQS_35
R13 GPIO_24 A6 E10 XCVR_P0_D4L3
IO_L16P_T2_CSI_B_14 VCCO_35 VCCBRAM 1V0 IO_L23P_T3_35
T13 GPIO_25 K8 B3 F11 XCVR_P0_D5H1

XCVR_P0_D[11..0]
IO_L16N_T2_A15_D31_14 DXP_0 VCCO_35 VCCBRAM IO_L20N_T3_35
R10 GPIO_26 K7 D7 XCVR_P0_D6K2
IO_L17P_T2_A14_D30_14 GPIO_[55..0] DXN_0 VCCO_35 IO_L24N_T3_35
R11 GPIO_27 E4 T1 XCVR_P0_D7G1
IO_L17N_T2_A13_D29_14 VCCO_35 VCCO_34 1V8 IO_L17N_T2_35

FPGA_DONE
N9 GPIO_31 XC7A100T-2FTG256C F1 R4 XCVR_P0_D8H2
IO_L18P_T2_A12_D28_14 VCCO_35 VCCO_34 IO_L20P_T3_35
P9 GPIO_32 J2 M3 XCVR_P0_D9J4
IO_L18N_T2_A11_D27_14 VCCO_35 VCCO_34 IO_L19N_T3_VREF_35
M6 GPIO_47 GND XCVR_P0_D10
L2
IO_L19P_T3_A10_D26_14 IO_L23N_T3_35
N6 GPIO_34 XC7A100T-2FTG256C XCVR_P0_D11
G2
B IO_L19N_T3_A09_D25_VREF_14 IO_L17P_T2_35 B
P8 GPIO_35 XCVR_P1_D0N1
IO_L20P_T3_A08_D24_14 IO_L4P_T0_34
R8 GPIO_36 U5G XCVR_P1_D1P3

XCVR_P1_D[11..0]
IO_L20N_T3_A07_D23_14 IO_L5N_T0_34
T7 GPIO_37 G7 XCVR_P1_D2N2
IO_L21P_T3_DQS_14 GNDADC_0 IO_L3N_T0_DQS_34
T8 GPIO_38 XCVR_P1_D3P4
FPGA CLOCK
IO_L21N_T3_DQS_A06_D22_14 IO_L5P_T0_34
T9 GPIO_39 T16 H6 XCVR_P1_D4R2
IO_L22P_T3_A05_D21_14 GND GND GND GND IO_L7P_T1_34
C8 T6 G13 XCVR_P1_D5P5
IO_L1P_T0_AD0P_15 GND GND IO_L10P_T1_34
C9 1V8 R9 G9 XCVR_P1_D6E5

XCVR_P1_D[11..0]
IO_L1N_T0_AD0N_15 GND GND IO_L13N_T2_MRCC_35
M4 P12 G3 XCVR_P1_D7
M5
IO_L1N_T0_34 GND GND IO_L6P_T0_34
R6 GPIO_29 X3 P2 F16 XCVR_P1_D8H4
IO_L24P_T3_A01_D17_14 GND GND IO_L18N_T2_35
R7 GPIO_28 4 3 FPGA_CLK N15 F10 XCVR_P1_D9J3
IO_L24N_T3_A00_D16_14 VDD OUT GND GND IO_L21P_T3_DQS_35
P6 GPIO_30 N5 F6 XCVR_P1_D10
J5
IO_25_14 C140 GND GND IO_L19P_T3_35
2 1 M8 E9 XCVR_P1_D11
M1
100nF GND OE/ST GND GND IO_L2N_T0_34
U5B XC7A100T-2FTG256C L11 D12
GND GND
D10 SiT8008AI-22-18E-100.000000G L1 D2 XC7A100T-2FTG256C
IO_0_15 GND GND
BANK 15

T4 R22 K14 C15

IO_L9P_T1_DQS_34 4K7 GND GND
R1 K6 C5
IO_L7N_T1_34 GND GND
C16 1V8 K4 B8
IO_L10P_T1_AD11P_15 IF_INT GND GND
D14 IF_CTL12 GND J11 A11
IO_L15P_T2_DQS_15 GND GND
J15 IF_DQ0 J9 A1
IO_L23P_T3_FOE_B_15 GND GND
H11 IF_DQ1

XCVR_RX_FRAME
XCVR_TX_FRAME
IO_L19P_T3_A22_15

XCVR_CLK_OUT
E12 IF_DQ2 XC7A100T-2FTG256C

XCVR_SYNC_IN
XCVR_EN_AGC

XCVR_SPI_ENB
XCVR_ENABLE
IO_L13P_T2_MRCC_15

XCVR_FB_CLK
G11 IF_DQ3

XCVR_RESET

RX_BAND_A
IO_25_15

TX_BAND_A
RX_BAND_B
RX_BAND_C
XCVR_SCLK

TX_BAND_B
XCVR_MISO
H12 IF_DQ4
IO_L20P_T3_A20_15
G12 IF_DQ5
BYPASS (X7R OR X5R)
IO_L19N_T3_A21_VREF_15
J16 IF_DQ6
IO_L23N_T3_FWE_B_15
H14 IF_DQ7
IO_L24P_T3_RS1_15
G15 IF_DQ8
IO_L24N_T3_RS0_15
H13 IF_DQ9
VCCO_14 VCCO_15 VCCO_34 VCCO_35
C IO_L20N_T3_A19_15 C
G16 IF_DQ10
IO_L22N_T3_A16_15
D16 IF_DQ11

GPIO_54
IO_L17N_T2_A25_15
E16 IF_DQ12 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8
IO_L17P_T2_A26_15
E15 IF_DQ13
IO_L18N_T2_A23_15
D15 IF_CTL0
IO_L15N_T2_DQS_ADV_B_15
B16 IF_CTL1
IO_L10N_T1_AD11N_15

D4
K1

K5

K3
G4

A2
A4

D5

N3
B2

B4

R5

R3
F14 IF_CTL2

T3

L4

T5

T2

L5
F2
P1
IO_L21N_T3_DQS_A18_15 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 C128 C129 C130 C131 C132 C133 C134 C135 C136 C137
F15 IF_CTL3
IO_L18P_T2_A24_15 4u7 4u7 470nF 470nF 470nF 470nF 4u7 4u7 470nF 470nF 470nF 470nF 4u7 4u7 470nF 470nF 470nF 470nF 4u7 4u7 470nF 470nF 470nF 470nF
F12 IF_CTL4
IO_L16P_T2_A28_15

IO_L12P_T1_MRCC_35
IO_L22P_T3_35
IO_L9N_T1_DQS_34
IO_25_35
IO_L1P_T0_34
IO_L24P_T3_35
IO_L16N_T2_35
IO_L8P_T1_AD14P_35
IO_L8N_T1_AD14N_35
IO_L3N_T0_DQS_AD5N_35
IO_L15P_T2_DQS_35
IO_L4N_T0_34
IO_L6N_T0_VREF_35
IO_L4P_T0_35
IO_L3P_T0_DQS_34
IO_L23N_T3_A02_D18_14
IO_L23P_T3_A03_D19_14
IO_L8N_T1_34
IO_L8P_T1_34
IO_0_34
E11 IF_CTL5
IO_L14P_T2_SRCC_15
A15 IF_CTL6
IO_L9N_T1_DQS_AD3N_15
F13 IF_CTL7
IO_L16N_T2_A27_15
D13 IF_CTL8
IO_L12P_T1_MRCC_15
E13 IF_CTL9 GND GND GND GND GND GND GND GND
VCCADC
IO_L13N_T2_MRCC_15
A14 IF_CTL10
IO_L7N_T1_AD2N_15
C14 IF_CTL11
VCCBRAM VCCAUX
IO_L8P_T1_AD10P_15
C13 C139
VCCINT
IO_L12N_T1_MRCC_15
G14 IF_DQ14
IO_L21P_T3_DQS_15 IF_PCLK GND 1V8
H16 IF_DQ15 1V0 1V0 1V0 1V0 1V8 1V8
IO_L22P_T3_A17_15
A13 IF_DQ16 100nF
IO_L7P_T1_AD2P_15
C11 IF_DQ17
IO_L11P_T1_SRCC_15
B12 IF_DQ18 1V0
IO_L5P_T0_AD9P_15
IF_CTL[12..0]

A12 IF_DQ19
IO_L5N_T0_AD9N_15 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 C103 C104 C105 C107 C108 C109 C110 C111
C12 IF_DQ20
IO_L11N_T1_SRCC_15 4u7 4u7 4u7 4u7 4u7 4u7 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF C1210 470nF 470nF 4.7uF 4.7uF 470nF 470nF 470nF
B11 IF_DQ21 BANK 34
IO_L4N_T0_15 100uF
A10 IF_DQ22 C88
IO_L3N_T0_DQS_AD1N_15
B15 IF_DQ23 T520V U5C
IO_L9P_T1_DQS_AD3P_15
D D9 IF_DQ24 330uF XC7A100T-2FTG256C D
IO_L6N_T0_VREF_15
B14 IF_DQ25
IF_CTL[12..0]

IO_L8N_T1_AD10N_15
B9 IF_DQ26 GND GND GND GND GND GND
VCCO C113 VCCO_0
IO_L3P_T0_DQS_AD1P_15
D8 IF_DQ27
IO_L6P_T0_15
D11 IF_DQ28 C112 Title
IO_L14N_T2_SRCC_15
IO_L4P_T0_15
B10
A9
IF_DQ29
IF_DQ30
GND
1V8 GND 1V8 GND C106 FPGA
IO_L2N_T0_AD8N_15 C1210 C1210 1V8 GND
A8 IF_DQ31 Size Number Revision
IO_L2P_T0_AD8P_15 47uF 47uF C1210
47uF A3 5 2
IF_DQ[31..0] Date: 29/02/2016 Sheet 5 of 7
IF_DQ[31..0]
File: C:\Users\..\FPGA.SchDoc Drawn By: Lukas Lao Beyer
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

POWER CLOCK & MISC. INTERFACE

XCVR_P0_D[11..0]

XCVR_P0_D[11..0]
U1B U1E U1C
A1 F12 J6 A12 F10 E12 XCVR_P0_D0
GND VSSA VDDD1P3_DIG 1V3_XCVR XCVR_CLK_OUT CLK_OUT TX_EXT_LO_IN GND XCVR_FB_CLK FB_CLK_P P0_D0/TX_D0_N
A2 G1 G10 D11 XCVR_P0_D1
VSSA RX_EXT_LO_IN FB_CLK_N P0_D1/TX_D0_P
A4 A7 FA-20H40.0000MF10Z-K3 M11 E11 XCVR_P0_D2
VSSA VDDA1P3_RX_TX XTALP P0_D2/TX_D1_N
A5 A8 M12 C4 G11 D10 XCVR_P0_D3
VSSA VDDA1P3_RX_TX XTALN TEST/ENABLE XCVR_DATA_CLK DATA_CLK_P P0_D3/TX_D1_P
A6 A9 A3 H11 E10 XCVR_P0_D4
VSSA VDDA1P3_RX_TX X1 NC DATA_CLK_N P0_D4/TX_D2_N
B1 A10 L4 M3 GND D9 XCVR_P0_D5

GND
A VSSA VDDA1P3_RX_TX RBIAS NC P0_D5/TX_D2_P A
B2 G8 E9 XCVR_P0_D6
VSSA XCVR_RX_FRAME RX_FRAME_P P0_D6/TX_D3_N
B12 E3 AD9364 G7 D8 XCVR_P0_D7
VSSA VDDA1P3_TX_LO_BUFFER R4 RX_FRAME_N P0_D7/TX_D3_P
C1 E8 XCVR_P0_D8
VSSA GND P0_D8/TX_D4_N
C2 K4 C3 14.3k 1% G9 D7 XCVR_P0_D9
VSSA VDDA1P3_BB C187 XCVR_TX_FRAME TX_FRAME_P P0_D9/TX_D4_P
C7 GND H9 F8 XCVR_P0_D10
VSSA 100nF TX_FRAME_N P0_D10/TX_D5_N
C8 D2 E7 XCVR_P0_D11
VSSA VDDA1P3_RX_RF P0_D11/TX_D5_P XCVR_P1_D[11..0]

XCVR_P1_D[11..0]
C9 D3 100nF (DNP)
VSSA VDDA1P3_RX_TX R60
C10 K11 XCVR_P1_D0
VSSA 49.9R TP1 P1_D0/RX_D0_N
C11 C1 P3 U.FL U1F GND J12 XCVR_P1_D1
VSSA R1 P1_D1/RX_D0_P
C12 A11 B4 B3 K10 XCVR_P1_D2
VSSA VDDA1P1_TX_VCO GND GPO_3 AUXDAC1 P1_D2/RX_D1_N
D1 B11 1R B5 C3 J11 XCVR_P1_D3
VSSA TX_VCO_LDO_OUT GPO_2 AUXDAC2 P1_D3/RX_D1_P
E1 1uF B6 K9 XCVR_P1_D4
VSSA GPO_1 P1_D4/RX_D2_N
F1 C2 B7 L5 J10 XCVR_P1_D5
VSSA R2 GPO_0 AUXADC P1_D5/RX_D2_P
F3 G2 K8 XCVR_P1_D6
VSSA RX_VCO_LDO_OUT GND P1_D6/RX_D3_N
H2 G3 1R GND GND AD9364 J9 XCVR_P1_D7
VSSA VDDA1P1_RX_VCO P1_D7/RX_D3_P
H3 1uF K7 XCVR_P1_D8
VSSA P1_D8/RX_D4_N
H6 J8 XCVR_P1_D9
VSSA P1_D9/RX_D4_P
J2 B9 J7 XCVR_P1_D10
BYPASS
VSSA VDDA1P3_TX_LO 1V3_SYNTH P1_D10/RX_D5_N
K2 B10 H8 XCVR_P1_D11
VSSA VDDA1P3_TX_VCO_LDO Install one 0.1uF cap near every power supply ball. P1_D11/RX_D5_P
L2
VSSA Install 10uF caps next to J3 and K3 balls.
L3 E2 1V3_XCVR 3V3 AD9364
VSSA VDDA1P3_RX_LO XCVR_CTRL_IN[3..0]

CTRL_IN[3..0]
L7 F2
VSSA VDDA1P3_RX_VCO_LDO R3
L8
VSSA 1V8
L9 J3 10K
VSSA VDDA1P3_RX_SYNTH
L10 K3 U1A
VSSA VDDA1P3_TX_SYNTH C31 C32 C33 C34 C35 C36 C37 C38 C39 C40
L11 K5 C5 CTRL_IN0
VSSA 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF XCVR_RESET RESETB CTRL_IN0
L12 C6 CTRL_IN1
VSSA CTRL_IN1
M4 B8 G6 D6 CTRL_IN2
B VSSA VDD_GPO 3V3 XCVR_ENABLE ENABLE CTRL_IN2 B
M6 G5 D5 CTRL_IN3
VSSA XCVR_EN_AGC EN_AGC CTRL_IN3 XCVR_CTRL_OUT[7..0]

CTRL_OUT[7..0]
H12 1V3_SYNTH 1V3_SYNTH 1V8
VDD_INTERFACE 1V8
H5 D4 CTRL_OUT0
XCVR_SYNC_IN SYNC_IN CTRL_OUT0
D12 GND GND E4 CTRL_OUT1
VSSD CTRL_OUT1
F7 K6 E5 CTRL_OUT2
VSSD XCVR_SPI_ENB SPI_ENB CTRL_OUT2
F9 H4 E6 CTRL_OUT3
VSSD C41 C42 C43 C45 C46 C47 C49 C50 C48 XCVR_TXNRX TXNRX CTRL_OUT3
F11 F6 CTRL_OUT4
VSSD 100nF 100nF 100nF 100nF 100nF 100nF 10uF 10uF 0.1uF CTRL_OUT4
G12 J4 F5 CTRL_OUT5
VSSD XCVR_MOSI SPI_DI CTRL_OUT5
H7 L6 F4 CTRL_OUT6
VSSD XCVR_MISO SPI_DO CTRL_OUT6
H10 J5 G4 CTRL_OUT7
VSSD XCVR_SCLK SPI_CLK CTRL_OUT7
K12
VSSD
AD9364
AD9364 GND GND GND

RECEIVE TRANSMIT 5V_TX

1V3_XCVR 1V3_TX C141

FB8 GND
GND
1uF
BLM21AG601SN1D C142
3000-6000 MHz C20 C19 C18 C183 C184
GND
T3 C6 10uF 100nF 1nF 10uF 10uF
GND 2 4 1.2nF
UNBAL BAL 1V3_TX
RXA_P

1 3 C143
GND/DC BAL
C 20pF C
GND
BD3150N50100AHF C7
2800-6000 MHz GND 68pF
RXA_N

C12 GND L3
4

D1 20pF T1 43nH
ESD0P8RFL 3 1
BAL GND/DC
20pF 4 2
1

BAL UNBAL
U1D
GND 1600-3200 MHz M1
RXA_P TXA_P
M7 TXA_P BD3150N50100AHF
C8 M2 M8 TXA_N C21 U2
RXA_N TXA_N
P1 RX C24 S1 SKY13317-373LF T4 S2 SKY13335-381LF C23 ADL5611 C30 P2 TX
1 4 C13 2 3 RXB_P H1 M9 TXB_P 1 5 1 3
RFC RF1 GND/DC BAL RXB_P TXB_P OUT1 RFC
5 1 4 100pF RXB_N J1 M10 20pF 3 2
RF2 UNBAL BAL RXB_N TXB_N 70-3000 MHz OUT2 GND

TXB_N
100pF 2 8 6 5 C9 C4 C22 100pF 100pF

2
NC RF3 NC GND
100pF K1 T2

VCTL2
VCTL1
PAD

RXC_P
V3
V2
V1

BD1631J50100AHF L1 M5 1 4

PAD
RXC_N TX_MON
GND 100pF 100pF 100pF GND
GND GND AD9364 GND GND GND
7
6
3

C5 2 3

4
6
RXC_N
RXC_P

C14

2
JA4220-AL D2
C27 C29 70-1800 MHz C10 GND 100pF ESD0P8RFL

3
100pF T5 GND C26 C25
GND
4 1 L1 L2
GND GND
1nF 1nF 100pF TBD TBD
C11 1nF 1nF
3 2
RX_BAND_C TX_BAND_A
C28 GND
RX_BAND_B JA4220-AL TX_BAND_B
D 100pF D
RX_BAND_A GND 1V3_TX
1nF GND
C15 C16 C17
1nF 100nF 10uF Title
GND Analog Front End
Size Number Revision
A3 7 2
Date: 29/02/2016 Sheet 7 of 7
File: C:\Users\..\AFE.SchDoc Drawn By: Lukas Lao Beyer
1 2 3 4 5 6 7 8