AD8556-EVALZ/AD8556CP-EBZ User Guide

UG-896
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluation Board for Zero-Drift, Digitally Programmable Sensor Signal Amplifier

FEATURES GENERAL DESCRIPTION
Single- or dual-supply operation This user guide describes the evaluation board hardware and soft-
AC and DC signal evaluation ware used to evaluate the AD8555, AD8556, and AD8557 in SOIC
Built-in 100 Ω bridge with unbalancing capability and LFCSP packages. The AD8556-EVALZ/AD8556CP-EBZ
Provision to create low-pass filter evaluation boards allow the quick demonstration and evaluation
Readback feature of programmed values of the AD8555/AD8556/AD8557 zero-drift, digitally program-
External clamp voltage setting mable sensor signal amplifiers.
Interface for PC USB port
The AD8555/AD8556/AD8557 are auto-zero instrumentation
Evaluation software, compatible with Microsoft Windows XP,
amplifiers with programmable gain and output offset
Windows Vista, and Windows 7
adjustment features. The evaluation board enables a PC to
SOIC/LFCSP socket for easy device replacement
communicate with the AD8555/AD8556/AD8557. The user can
Supports AD8555, AD8556, and AD8557 ICs
send commands to the evaluation board and read back the
EQUIPMENT NEEDED programmed values for the device that is being evaluated.
AD8556-EVALZ/AD8556CP-EBZ evaluation board This user guide supplements the information in the AD8555,
Analog Devices, Inc., System Demonstration Platform (SDP) AD8556, and AD8557 data sheets, which should be consulted
SDP-S (EVAL-SDP-CS1Z) or SDP-B (EVAL-SDP-CB1Z) in conjunction with this user guide when working with the
USB cable (included with SDP board) evaluation board.
Power supplies
Voltage source
Voltmeter
BNCs and power cables
PC running Windows XP, Windows Vista, or Windows 7

EVALUATION BOARD CONNECTION DIAGRAM

11886-001

Figure 1. SDP-S board Connected to the AD8556-EVALZ Board (SDP-B Board Also Shown for Reference)

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | Page 1 of 9
UG-896 AD8556-EVALZ/AD8556CP-EBZ User Guide

TABLE OF CONTENTS
Features .............................................................................................. 1  Adjusting for 0 V Differential Input ...........................................3 
Equipment Needed ........................................................................... 1  Quick Initial Hardware Setup and Output Verification ...........4 
General Description ......................................................................... 1  Software ..............................................................................................5 
Evaluation Board Connection Diagram ........................................ 1  Installation......................................................................................5 
Revision History ............................................................................... 2  Removing the Evaluation Software .............................................5 
Hardware Description ...................................................................... 3  Running the Software ...................................................................5 
System Requirements ................................................................... 3  Typical AC Setup and Response ..................................................6 
Communicating with the Evaluation Board............................... 3  Output Clamp Feature ..................................................................7 
Hardware Requirements .............................................................. 3  Evaluation Board Schematics...........................................................8

REVISION HISTORY
11/15—Rev. 0 to Rev. A
Updated Layout ................................................................... Universal
Added AD8556CP-EBZ ..................................................... Universal
Added Equipment Needed Section ................................................ 1
Changes to General Description Section ...................................... 1
Changes to Quick Initial Hardware Setup and Output
Verification Section and Figure 2 ................................................... 4
Added Figure 12................................................................................ 8
Deleted Ordering Guide Section .................................................... 9

10/13—Revision 0: Initial Version

Rev. A | Page 2 of 9
AD8556-EVALZ/AD8556CP-EBZ User Guide UG-896

HARDWARE DESCRIPTION
The AD8556-EVALZ/AD8556CP-EBZ evaluation boards are COMMUNICATING WITH THE EVALUATION BOARD
designed for maximum configuration flexibility. An ac signal The evaluation board connects to the Analog Devices SDP-B or
can be applied to +VIN ac, and the output can be monitored SDP-S board, which connects to the USB port of a PC.
from VOUT ac. DC signals can be differentially applied between
+VIN dc and −VIN dc, and the results can be monitored using a Ensure that the evaluation software provided on the CD is
voltmeter at VOUT. Users can view the filter output signal at the installed before connecting the SDP board and the evaluation
FILT/DIGOUT pin. The board also allows swapping of the board.
polarity of the inputs using the VNEG P1 and VPOS P1 switches. HARDWARE REQUIREMENTS
Four resistors (R1A, R1B, R2A, and R2B) simulate a 100 Ω The following equipment is required:
bridge configuration. The bridge can be unbalanced using the
 Power supplies
provided trim potentiometers (P1 and P2). The top and bottom
 Voltage source
of the bridge are connected to VDD and VSS, respectively.
 Voltmeter
Pulse shaping is performed on this board before applying the  BNCs and power cables
data to the AD8556-EVALZ data input pin. The pulse widths
 SDP board with USB mini-B cable
are set for 5 μs, representing the low level (0 V), and 80 μs,
representing the high level (>2.4 V). This adjustment is made ADJUSTING FOR 0 V DIFFERENTIAL INPUT
using Resistor RT0 and Resistor RT1. The trim potentiometers Prior to initial hardware setup and output verification, complete
are glued to their fixed positions. the following to adjust for differential input offset:
Supply current can be monitored by using a resistor in place of 1. Connect the positive input (high) of a voltmeter to −VIN dc.
R7. Clamp voltage can be applied externally to a level or can be 2. Connect the negative input (low) of the voltmeter to GND
set easily to VDD by placing a jumper from VCLAMP to VDD. of the power supply.
The SOIC/LFCSP socket is soldered for easy programming and 3. Monitor the output (VOUT dc) voltmeter.
removal of the device. Pin 1 is the pin located in the upper left- 4. Adjust trim Potentiometer P1 to be close to 0 V (−0.1 mV).
hand corner of the socket close to R7. Make sure that the device 5. Connect the positive input (high) of a voltmeter to +VIN dc.
is placed in the socket properly. See Figure 11 for the evaluation 6. Connect the negative input (low) of the voltmeter to GND
board schematic. of the power supply.
SYSTEM REQUIREMENTS 7. Monitor the output (VOUT dc) voltmeter.
8. Adjust trim Potentiometer P2 to be close to 0 V (0.1 mV).
The evaluation kit has the following system requirements:
 Analog Devices, Inc., SDP-B or SDP-S system demonstration
platform (SDP) controller board (available for purchase
separately at www.analog.com/SDP)
 PC with available USB 2.0 port
 Microsoft® Windows® operating system with administrator
access

Rev. A | Page 3 of 9
UG-896 AD8556-EVALZ/AD8556CP-EBZ User Guide
QUICK INITIAL HARDWARE SETUP AND OUTPUT 4. Apply 10 mV dc signal between the +VIN dc and −VIN dc
VERIFICATION connectors, and monitor the VOUT dc output using a
voltmeter.
For an initial hardware setup and output verification, follow
5. Place an AD8555/AD8556/AD8557 device in the
these steps:
SOIC/LFCSP socket, connect the VCLAMP pin to the
1. Connect the evaluation board to the SDP board, which VDD pin, and apply dc power to the board using an
connects to the USB port of your PC system using a USB external power supply (±2.5 V).
mini-B cable.
2. Position manual switches to VPOS P2 and VNEG P2. When this procedure is complete, the output is 70 mV, with the
3. Jumper the VCLAMP connector pin to the VDD board in this configuration consuming approximately 4 mA.
connector pin.

STEP 5

APPLY APPLY APPLY

+2.5V GND –2.5V

VDD GND VSS

AD8555/ VOUT STEP 4
MONITOR VOUT
AD8556/
STEP 1 AD8557
CONNECT SDP
SOIC/LFCSP

VCLAMP STEP 3
CONNECT VCLAMP TO VDD

AD8556 EVALUATION BOARD

FILT OUT
–VIN DC +VIN DC VNEG VPOS

11886-011
STEP 4 STEP 2
CONNECT VIN THESE SWITCHES SET INPUT
POLARITY AS NEEDED

Figure 2. Evaluation Board Block Diagram

Rev. A | Page 4 of 9
AD8556-EVALZ/AD8556CP-EBZ User Guide
SOFTWARE
INSTALLATION
To install the evaluation software on the PC,
1. Insert the CD-ROM into the CD drive on your PC. After a
few moments, a message for the installation appears.
2. Double-click setup.exe. (For Windows® 7 onwards, right-
click and select Install as a system administrator.)
3. Follow the instructions until the software installation is
complete.
The evaluation software is developed in LabVIEW®. The
software requires a LabVIEW® runtime engine and USB drivers
for the SDP (both included in install). Install the software with
administrator access, before plugging in the SDP board. The
install detects if the SDP board has been installed previously.
The default install location is C:\Program Files (x86)\Analog
Devices\AD855x.
For the most current data sheet, visit www.analog.com/AD8555,
www.analog.com/AD8556 or www.analog.com/AD8557.
REMOVING THE EVALUATION SOFTWARE
To remove the evaluation software modules,
1. Go to Start > Settings > Control Panel.
2. Double-click Add/Remove Programs and select
AD855x Evaluation Software.
Figure 3. No Programming Dialog Box
Rev. A | Page 5 of 9
UG-896
RUNNING THE SOFTWARE
To run the evaluation software application:
1. After the SDP board is plugged intothe PC via the USB
cable and into the AD8556-EVALZ/AD8556CP-EBZ
evaluation board via the P1 socket, run the evaluation
software. From the Start menu, click AD855x Eval, and
then click AD855xEVAL. The graphical user interface
(GUI) opens.
2. Select the product for which you have samples and the
connector used, and then click Start.
3. Set the appropriate gain and offset values, and then click
Simulate. Monitor the output as the offset is changed to
verify communication.
4. Program the gain between 70 and 1280 and the offset
between 0 V and 5 V. Click Simulate to load these values
into the AD8556-EVALZ/AD8556CP-EBZ and monitor
the output.
5. The output is input × gain and responds to the specified
configuration.
6. After the AD8556-EVALZ/AD8556CP-EBZ has been
simulated to the final values, click Program to
permanently blow the internal fuses to the values in the
GUI.
11886-002
UG-896 AD8556-EVALZ/AD8556CP-EBZ User Guide
Table 1. Evaluation Software Dialog Box Button Functions
Button Function
Start Select the connector and the product, and then click Start to begin evaluation.
Connector Selects the physical connector on the SDP board that is used to connect to the evaluation board. The connectors are
labeled on the top silkscreen of the SDP board.
Product Selects the device under evaluation.
Simulate Configures the device according to the specified pattern. This button does not blow any fuses.
Program Blows fuses according to the specified pattern. Blown fuses cannot be reprogrammed.
Blow Parity Fuse Blows the parity fuse. The parity fuse keeps track of the state of the blown fuses. If, for any reason, the state of this fuse
is changed either intentionally or unintentionally, the parity flag is set and the alarm is set.
Blow Master Fuse Permanently sets the device to the programmed gain and offset and prevents future programming. Click this button
only after selecting and programming the gain and the offset. Prior to blowing the master fuse, make sure to first
blow the parity fuse, if prompted.
Read Fuse Values Reads back the state of the programmed fuses after they have been blown. The options are as follows:
Low sense current: when dropped across a blown fuse (high impedance), creates a voltage that can trigger an internal
comparator and provide the right level in the output.
High sense current: reads back the fuse states to make sure that the fuses are blown. A code for blown fuses appears
in a pop-up box.

See the AD8555/AD8556/AD8557 data sheet for more Figure 4 shows the output on Channel 2 under these conditions
information on the theory of operation; simulation, and configuration.
programming, and read modes; and parity error detection. [ T ]

The AD8555/AD8556/AD8557 data sheet also contains more T

information on programming procedures for the device.

TYPICAL AC SETUP AND RESPONSE 1

AC Input Example
Setup requirements are as follows:
 Power supplies
 Function generator 2
 Scope
 BNCs and cables
Results

11886-003
Ch1 50.0mV BW Ch2 2.00V BW M 400ms A Ch1 2.00mV

When the device is powered with ±2.5 V, and 50 mV of input is T 9.600%

applied, the default conditions are Figure 4. Output on Channel 2

 VCC = 2.5 V Figure 5 shows the results of the previous conditions with
 VSS = −2.5 V VOFF = 2.5 V or Code 128.
 Gain 1 = 4 [ T ]
T
 Gain 2 = 17.5
 Offset = VSS
1
The overall gain is 70.
When the switches are placed in VNEG P1 and VPOS P2, there is one
set of outputs. When the switches are changed to VNEG P2 and
VPOS P1, the exact voltage is produced, but with the opposite
polarity. 2
When both switches are on one side (for example, VNEG P1 and
VPOS P1), the inputs are shorted together.
RT0 and RT1 are the trim potentiometers used for pulse width
11886-004

Ch1 50.0mV BW Ch2 2.00V BW M 400ms A Ch1 2.00mV

shaping. Do not change their settings. RT0 is adjusted to create T 9.600%
a 5 μs pulse; RT1 is adjusted to create an 80 μs pulse. Figure 5. Output on Channel 2, VOFF = 2.5 V

Rev. A | Page 6 of 9
AD8556-EVALZ/AD8556CP-EBZ User Guide UG-896
[ ]
In Figure 6, overall gain = 100 (G1 = default = 4, G2 = Code 1 = T

T
25, offset = 2.5 V or Code 128).
[ T ]
T
1

11886-007
Ch1 20.0mV BW Ch2 2.00V BW M 100ms A Ch1 2.00mV
T 0.00000s

Figure 8. Normal Response

11886-005
Ch1 50.0mV BW Ch2 2.00V BW M 400ms A Ch1 2.00mV
T 9.600% Figure 9 shows the output after VCLAMP is set to 0.8 V.
Figure 6. Output with Overall Gain = 100 [ T ]
T
In Figure 7, VIN = 2 mV p-p, G1 = 6.4, G2 = 35, and offset =
2.5 V or Code 128.
[ T ] 1
T

11886-008
Ch1 20.0mV BW Ch2 2.00V BW M 100ms A Ch1 2.00mV
T 0.00000s

Figure 9. Response with VCLAMP Set

Applying a large gain to an input yields saturation, as shown in

11886-006

Ch1 20.0mV BW Ch2 2.00V BW M 400ms A Ch1 –1.20mV

T 9.600% Figure 10. The conditions are VIN = 20 mV p-p, G1 = 6.4, G2 =
Figure 7. Output at VIN = 2 mV p-p, G1 = 6.4, G2 = 35, Offset = 2.5 V 200, offset = 2.5 V.
[ ]
OUTPUT CLAMP FEATURE T
T

The output of the device can be clamped to the desired level.

The output clamp feature is provided to protect the circuitry
1
that follows the AD8556-EVALZ, in case the input to AD8556-
EVALZ is accidentally larger than anticipated.
In normal situations (VSUPPLIES = ±2.5 V, gain = 70, VOFFSET = 2.5 V,
input = 40 mV p-p), the response to an input is as shown in
Figure 8.
2
11886-009

Ch1 20.0mV BW Ch2 2.00V BW M 400ms A Ch1 –1.20mV

T 9.600%

Figure 10. Results with Saturation

Note that Resistor RT1 and Resistor RT2 are used for pulse
stretching; do not adjust them. They are factory-adjusted for
optimal results.

Rev. A | Page 7 of 9
UG-896 AD8556-EVALZ/AD8556CP-EBZ User Guide

EVALUATION BOARD SCHEMATICS

VDD
EEPROM ID C18
VIO_+3.3V
BLK VDD VDD
14 U2 16 U1 AGND
VDD
GND VCC C9 VCC 0.1UF
C7

100K

100K
C1 C3 0.1UF

R3

R5
BLK 0.1UF GND GND
10UF 0.1UF 7 SN74LV132AD 8 SN74LV123AD
1 2 GND
AGND VSS VSS 8 U4
AGND AGND VCC
VSS 0.1UF
EEPROM_A0 1
E0
C8

BLK C10 2
VSS E1 5 SDA_0
C2 0.1UF 3 SDA
C4 E2
10UF SCL_0 6
0.1UF AGND SCL
7

100K
FIT IN 2.75X4.25 2 LAYER BOARD

R2
AGND WC_N

DNI

DNI
VSS

R4

R6
0

0
3.3V/20MA 4 M24C02-WMN6TP

DELETE NC PIN CONNECTIONS

P1 P1 VDD
120
TP4 1
119
BLK 2

R10

2K
118 TP10
3
117 BLK U1
4 VIO_+3.3V
USB_VBUS 116 C12 1 VDD
5 R1 A
115 EZERO 2
6 B
114 5K
7 1UF 13 VCLAMP
113 15 Q

JP1
8 R/C BLK
112

30K
R8

1000PF
9

C15
111
10 4
110 Q_N
USB_VBUS VIO_+3.3V 11 14 DUT VCLAMP
109 C
12 CLR_N
108
13 3
C72 C6 107 U2
14 VSS VDD VDD VSS
0.1UF 10UF 106 VOUT
C5 15 SIG_ZERO 1

0.1UF

0.1UF
105 BLK

C19

C20
C73 16 SN74LV123AD
10UF 104
0.1UF 17 VDD 3 DUT DIN
103
18 AGND AGND
102 X1 J2
19 2 FILTER_OUT

R20
SIG_ONE

10K
101 49.9K
R11

20 BLK 1 8
100
21 U1 SN74LV132AD FILT OUT 2 7 DUT OUT AMP227161-1
99
22 C13 9 DUT DIN 3 6 DUT VCLAMP AGND VSS
98 R7 A DUT IN-
23 EONE 10 4 5 DUT IN+
97 B -VINDC
24 5K
96 1UF 5 BLK
25 7 Q OTS-8-16-1.27-03
95 R/C
26
30K
R9

1000PF

94
C16

27
93 12
28 Q_N

0.1UF
C21
92 6
29 C
91 CLR_N J1
30

R12

R19
90 11 1

1
31 VDD
89 VSS VDD
32 2
88 SN74LV123AD
33 +VINDC AMP227161-1
87
34 VIO_+3.3V USB_VBUS S1 S2 BLK
86

R14

R17
2K

2K
35
C14

85 VNEG VPOS
0.1UF

0.1UF
C11

2
36 TP1
84 P1 P2 P1 P2
37 BLK
83 TP6

1
3

1
3
CHWT123M1D9AV2Q

CHWT123M1D9AV2Q
38 1 14 U3 U2 U2

0.1UF
C22
R16
R13
82 AGND AGND BLK

200

200
39 VCCAVCCY 12 9
81
40 TP2

3
SDA_0 GPIO0 2 A1 Y1 13 EZERO C17 VSS
80 R21
41 SCL_0 BLK 11 8 FILT OUT 2 2
79
42 TP3 3 A2 Y2 12

CW

CW
78 GPIO1 GPIO1 EONE 0
GPIO0 1UF

1
43 BLK 13 10
GPIO2 77
44 GPIO2 4 A3 Y3 11 SN74LV132AD
76 TP7
45 SN74LV132AD
75 BLK
46 5 A4 Y4 10
74
47

R15

R18
1N5817

2K

2K
73
D1

48 8
72 EN
49 GND
71
50 7
70 ADG3304BRUZ VSS
51
69
52
68
53 AGND
67
54
66
55
EEPROM_A0 65 U2
56
64
57 TP5 4 SIG_ZERO
63
58 BLK
62
59 6
61
60
FX8-120S-SV(21) FX8-120S-SV(21) 5 SIG_ONE
SN74LV132AD

11886-012
AGND

Figure 11. AD8556CP-EBZ Evaluation Board Schematic

VDD EEPROM ID
BLK C18
VDD VDD
VDD 14 U2 16 U1 AGND
C9
P

GND VCC VCC 0.1UF

C7
C3 0.1UF
100UF

BLK C1
C25

0.1UF GND GND VIO_+3.3V

10UF 0.1UF 7 SN74LV132AD 8 SN74LV123AD
SCL
N

1 2 GND U4
8 SDA
AGND VSS VSS BLK VCC
AGND AGND 1 BLK
EEPROM_A0 E0
0.1UF

2
C8

C10 E1 5
JP2

VSS=GND 3 SDA SDA_0

0.1UF E2
6
SCL_0 SCL
VSS AGND 7
WC_N
100K
R2

BLK
VSS
AGND VSS FIT IN 2.75X4.25 2 LAYER BOARD
4 M24C64-WMN6TP
N

C2 3.3V/20MA
100UF

C4
C23

10UF JP3
USB_VBUS VDD
0.1UF
P

DELETE NC PIN CONNECTIONS

P1 P1
VDD
120
5V 1
119
BLK 2
R10
2K

118 3.3V
3 C28 C19 C20
117 BLK U1 C29
4 VIO_+3.3V
USB_VBUS 116 C12 1 10UF 0.1UF VDD
5 R1 A 0.1UF 10UF
115 EZERO 2
6 B
114 5K AGND AGND AGND AGND
7 1UF 13 VCLAMP
113 15 Q
JP1
8 R/C BLK
VDD

VSS

112
30K
R8

1000PF

9
111 VOUT
C15

10 4
FILTER

110 Q_N BLK

0.1UF

USB_VBUS VIO_+3.3V 11 14 DUT VCLAMP

C26

109 C
12 CLR_N
108
13 3 X1
16
15
14
13

C72 C6 107 U2 AGND J2

14 FILTER_OUT
R20

VSS VDD
10K

10UF 106
C5
0.1UF 15 SIG_ZERO 1 BLK 1 12 DUT OUT
C73 105 SN74LV123AD
10UF 16 FILT OUT 2 11 5227161-1
0.1UF 104 VDD VSS
17 3 DUT DIN 3 10 DUT VCLAMP
103 AGND
18 DUT DIN 4 9
102
19 SIG_ONE 2
101
100K
R11

20
5
6
7
8
PAD

100 16QN65K14040
21 U1 SN74LV132AD
99
22 C13 9
98 R7 A DUT IN-
23 EONE 10 DUT IN+
97 B -VINDC
24 5K
96 5 BLK
IN-

25 1UF 7 Q
95 R/C
26
30K
R9

1000PF

94
C16

27
93 12
28 Q_N
0.1UF
BLK

C21
IN+

92 6
29 C
91 CLR_N
BLK

30 J1
R12

R19

90 11
1

31 VDD
89 VSS VDD
32
88 SN74LV123AD 5227161-1
33
87 +VINDC
34 VIO_+3.3V USB_VBUS S1 BLK
86
R14

R17
10K

10K

35 S2
C14

85 VNEG VPOS
0.1UF

0.1UF
C11

36 ZERO
84 P1 P2 P1 P2
37 BLK
83
ET03MD1CBE 1
3

U3 U2 U2
ET03MD1CBE

38 ONE 1 14
0.1UF
C22

82 AGND AGND
200

200

39 VCCA VCCY 12 9
81
40 2 A1 Y1 13 VSS
3

80 SDA_0 GPIO0 EZERO C17

41 SCL_0 BLK 11 8 FILT OUT 2 2
R13

R16

79
42 3 A2 Y2 12
CW

CW

78 GPIO1 GPIO1 EONE

GPIO0 1UF
1

43 BLK 13 10
GPIO2 77
44 GPIO2 4 A3 Y3 11 SN74LV132AD
76 READ_BACK
45 SN74LV132AD
75
46 5 A4 Y4 10
74
21

1000PF

1000PF

47
R15

R18
1N5817

1 2
10K

10K
C27

C24

73
D1

48 8
72 EN
49 GND
71
50 7
70 ADG3304BRUZ VSS
51
69
52
68
53 AGND
67
54
66
55
EEPROM_A0 65 U2
56
64
57 DIGI_IN 4 SIG_ZERO
63
58 BLK
62
59 6
61
60
FX8-120S-SV(21) 5 SIG_ONE
FX8-120S-SV(21)
SN74LV132AD
11886-013

TP1 TP2
BLK BLK

AGND

Figure 12. AD8556-EVALZ Evaluation Board Schematic

Rev. A | Page 8 of 9
AD8556-EVALZ/AD8556CP-EBZ User Guide UG-896

NOTES

ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Legal Terms and Conditions

By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions
set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc.
(“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal,
temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional
limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term
“Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including
ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may
not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to
promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any
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