Expt No:7.

DESIGN AND TESTING OF RING COUNTER

Date: AND JOHNSON COUNTER

AIM:
To design and setup three bit Johnson and Ring counter using JK flip-flop.

RING COUNTER:

Truth Table:

CLK Q0 Q1 Q2

1 1 0 0

2 0 1 0

3 0 0 1

4 1 0 0

5 0 1 0

6 0 0 1

Realization Using Logic Diagram:

Timing Diagram:

8.2.JOHNSON COUNTER:

Theory:
Truth Table:

CLK Q0 Q1 Q2

1 1 0 0

2 1 1 0

3 1 1 1
 4 0 1 1

5 0 0 1

6 0 0 0

7 1 0 0

8 1 1 0

Realization Using Logic Diagram:

Timing Diagram:
 PIN OUT OF IC 7476
Pin Out Configuration of IC 7476:

1 Clk 1 16 1K
1 PRE' 2 15 1Q
1 CLR' 3 14 1 Q'
1J 4 13 GND
IC 7476
Vcc 5 12 2K
2 Clk 6 11 2Q
2 PRE' 7 10 2 Q'
2 CLR' 8 9 2J

PRE LAB QUESTIONS:

1) Why do we need counters in digital electronics?

2) What is the difference between mod n counter and divided mod n counter?
3) Advantage of Johnson counter over ring counter
4) How many flip-flops are needed to build a divide by 12 Johnson counter
5) consider a 4 bit Johnson counter with an initial value of 0000.what is the
counting sequence of this counter?
6) How many flip-flop stages would be required to generate a set of three phase
waveforms in Johnson counter?

POST LAB QUESTIONS:

1) If a 10 bit ring counter has initial state 1101000000, what is the state after
applying second clock pulse?
2) In a 5-bit Johnson Counter how many states or bit patterns are available?