De La Salle University – Dasmarinas

College of Engineering, Architecture and Technology

Computer Engineering Department

Design of Ripple Carry Adders

Experiment #1

Juson, Rio Mar Kheno M.

CPE51
Date Performed: February 19, 2019
Date Submitted: February 26 2019

……………………………………………………………………………..
Engr. Amelia Liwanag
Instructor

I. Objective:

It computes the carries parallely thus greatly speeding up the computation.

1. understanding behaviour of carry lookahead adder from module designed by the student as part of
the experiment
2. understanding the concept of reducing computation time with respect of ripple carry adder by using
carry generate and propagate functions
3. the adder will add two 4 bit numbers

II. Theory:
To reduce the computation time, there are faster ways to add two binary numbers by using carry lookahead
adders. They work by creating two signals P and G known to be Carry Propagator and Carry Generator.
The carry propagator is propagated to the next level whereas the carry generator is used to generate the
output carry ,regardless of input carry. The block diagram of a 4-bit Carry Lookahead Adder is shown here
below -

The number of gate levels for the carry propagation can be found from the circuit of full adder. The signal
from input carry Cin to output carry Cout requires an AND gate and an OR gate, which constitutes two gate
levels. So if there are four full adders in the parallel adder, the output carry C5 would have 2 X 4 = 8 gate
levels from C1 to C5. For an n-bit parallel adder, there are 2n gate levels to propagate through.

Pre-Experiment

Multiple choice questions:

 What is the main difference between half-adders and full-adders?

Nothing basically; full-adders are made up of two half-adders

Full-adders can handle double digit numbers

Full-adders have a carry input capability

Half-adders can only handle single digit numbers

 Which one of the following will give the sum of full adders as output?

Three bit parity checke

Three point majority circuit

Three bit counter

 Three bit comparator

 The MOST commonly used system for representing signed binary numbers is the

2's-complement system

1's-complement system

10's-complement system

Sign-magnitude system

 The time required for a pulse to decrease from 90 to 10 per cent of its maximum value is called

Propagation delay

Rise time

Decay time

Binary level transition period

 Odd parity of word can be conveniently tested by

AND gate

OR gate

XOR gate

NOR gate

Subjective questions:

 What is the reason for using look ahead carry adder?

- it is a fast-parallel adder unlike the other adder and it reduces the propagation delay by more complex
hardware.

 What is the number of gate levels for output carry in a parrel adder composed of 4 full adders?

- If there are four full-adders in the parallel adder, the output carry C5 would have 2*4=8 gate levels from
C1 to C5

 What is the number of gate levels to propagate through for an n-bit parallel adder?

- For an n-bit parallel adder, there are 2n gate levels for the carry to propagate through.

Post-Experiment

Multiple choice questions:

 What distinguishes the look-ahead-carry adder?

It requires advance knowledge of the final answer

It is faster than a ripple-carry adder

It is slower than the ripple-carry adder

It is easier to implement logically than a full-adder

 The time and space complexity of carry look ahead adder are respectively.

O(n), O(nlogn)

O(n), O(1)

O(n), O(n)

O(logn), O(nlogn)

 The number of full and half-adders required to add 16-bit numbers is

 1 half-adder, 5 full-adders

4 half-adders, 12 full-adders

8 half-adders, 8 full-adders

16 half-adders, 0 full-adders

 The MOST commonly used system for representing signed binary numbers is the

2's-complement system

1's-complement system

10's-complement system

Sign-magnitude system

 Ripple carry delay is increased in carry-look-ahead adder

True

False

 Carry of a full adder is a symmetric function

True

False

Subjective questions:

 What is the worst-case delay of an n-bit carry look ahead adder?

- Contrast the delay of the CLA adder with the worst case delay for the ripple carry adder, (2k + 1)D.
Consider the circuit cost of ripple-carry and CLA adders.
  What is the advantage of carry look head adder over ripple carry adder?

-a ripple carry adder passes its carry bit through a long logic chain, which is very straightforward to design,
but can have a very large delay. And a carry-lookahead adder uses a clever algorithm to cut that logic to
only a few layers, and thus keeps the delay pretty short even for a worst-case situation.

 What is the generate and propagate functions expression at level-2?

- A carry-Lookahead adder is a fast-parallel adder as it reduces the propagation delay by more complex
hardware, hence it is costlier. In this design, the carry logic over fixed groups of bits of the adder is
reduced to two-level logic, which is nothing, but a transformation of the ripple carry design.

 What is the number of additions in carry look head adder for adding m numbers?

- In ripple carry adders, for each adder block, the two bits that are to be added are available instantly.
However, each adder block waits for the carry to arrive from its previous block. So, it is not possible to
generate the sum and carry of any block until the input carry is known.

DATA AND RESULTS

A3 A2 A1 A0 B3 B2 B1 B0 OUTPUT TOTAL

0 0 0 0 0 0 0 0 0000 0

0 0 1 0 1 0 1 1 1101 13

0 1 1 1 0 1 1 1 1110 14

1 1 0 1 1 0 0 0 0101 5

1 0 1 1 0 1 1 1 0010 2

0 0 0 1 0 1 1 1 0111 7

1 0 0 1 1 1 0 1 0110 6

0 1 1 0 1 1 0 1 0011 3

1 1 0 0 1 1 1 1 1011 11

0 0 0 0 1 0 1 0 1010 10
Reference

- https://www.electronicshub.org/carry-look-ahead-adder/

-https://www.edaboard.com/showthread.php?310023-ripple-carry-adder-vs-carry-lookahead-adder