Implementing MIPS

 We're ready to look at an implementation of the MIPS instruction set

 Simplified to contain only
 arithmetic-logic instructions: add, sub, and, or, slt
 memory-reference instructions: lw, sw
 control-flow instructions: beq, j

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

op rs rt rd shamt funct R-Format

6 bits 5 bits 5 bits 16 bits

op rs rt offset I-Format
6 bits 26 bits

op address J-Format
Implementing MIPS: the
Fetch/Execute Cycle
 High-level abstract view of fetch/execute implementation
 use the program counter (PC) to read instruction address
 fetch the instruction from memory and increment PC
 use fields of the instruction to select registers to read
 execute depending on the instruction
 repeat…

Data

Register #
PC Address Instruction Registers ALU Address
Instruction Register #
memory Data
Register # memory

Data
Overview: Processor Implementation
Styles
 Single Cycle
 perform each instruction in 1 clock cycle
 clock cycle must be long enough for slowest instruction; therefore,
 disadvantage: only as fast as slowest instruction
 Multi-Cycle
 break fetch/execute cycle into multiple steps
 perform 1 step in each clock cycle
 advantage: each instruction uses only as many cycles as it needs
 Pipelined
 execute each instruction in multiple steps
 perform 1 step / instruction in each clock cycle
 process multiple instructions in parallel – assembly line
Functional Elements
 Two types of functional elements in the hardware:
 elements that operate on data (called combinational elements)
 elements that contain data (called state or sequential elements)
 Combinational Elements
 Works as an input  output function, e.g., ALU
 Combinational logic reads input data from one register and
writes output data to another, or same, register
 read/write happens in a single cycle – combinational element
cannot store data from one cycle to a future one

Combinational logic hardware units

State State State

Combinational logic
element Combinational logic element element
1 2

Clock cycle
State Elements
 State elements contain data in internal storage, e.g., registers
and memory
 All state elements together define the state of the machine
 Flipflops and latches are 1-bit state elements, equivalently,
they are 1-bit memories
 The output(s) of a flipflop or latch always depends on the bit
value stored, i.e., its state, and can be called 1/0 or high/low
or true/false
 The input to a flipflop or latch can change its state depending
on whether it is clocked or not…
State Elements on the Datapath:
Register File
 Registers are implemented with arrays of D-flipflops
Clock

5 bits R ead reg ister

nu m ber 1 R ead 32 bits
data 1
5 bits R ead reg ister
nu m ber 2
Register file
5 bits W rite
re giste r
R ead 32 bits
W rite data 2
32 bits
da ta W rite

Control signal

Register file with two read ports and

one write port
State Elements on the Datapath:
Register File
 Port implementation:
Clock
Clock

Write

Read register C
number 1 0
Register 0
Register 0 1 D
Register 1 M n-to-1 C
Register number
u Read data 1 decoder Register 1
Register n – 1 x D
n– 1
Register n n
Read register
number 2
C
Register n – 1
M D
u Read data 2 C
x Register n
Register data D

Read ports are implemented Write port is implemented using

with a pair of multiplexors – 5 a decoder – 5-to-32 decoder for
bit multiplexors for 32 registers 32 registers. Clock is relevant to
write as register state may change
only at clock edge
Verilog

 All components that we have discussed – and shall discuss –

can be fabricated using Verilog
Single-cycle Implementation of MIPS
 Our first implementation of MIPS will use a single long clock
cycle for every instruction
 Every instruction begins on one up (or, down) clock edge
and ends on the next up (or, down) clock edge
 This approach is not practical as it is much slower than a
multicycle implementation where different instruction
classes can take different numbers of cycles
 in a single-cycle implementation every instruction must take
the same amount of time as the slowest instruction
 in a multicycle implementation this problem is avoided by
allowing quicker instructions to use fewer cycles
 Even though the single-cycle approach is not practical it is
simple and useful to understand first

 Note : we shall implement jump at the very end

 Datapath: Instruction Store/Fetch &
PC Increment

Instruction
address
Add
PC
Instruction Add Sum
Instruction
4
memory

PC Read
address
a. Instruction memory b. Program counter c. Adder
Instruction
Instruction
Three elements used to store memory

and fetch instructions and

increment the PC
Datapath
Animating the Datapath
Instruction <- MEM[PC]
PC <- PC + 4
ADD

PC
ADDR
Memory
RD Instruction
 Datapath: R-Type Instruction

ALU control ALU operation

5 Read 3 Read 3
register 1 register 1
Read Read
Register 5 data 1 data 1
Read Read
numbers register 2 Zero Zero
Registers Data ALU ALU Instruction register 2
5 Write result
Registers ALU ALU
register Write result
Read
data 2 register
Write Read
Data data data 2
Write
RegWrite
data

RegWrite
a. Registers b. ALU

Two elements used to implement Datapath

R-type instructions
Animating the Datapath

add rd, rs, rt

Instruction
op rs rt rd shamt funct R[rd] <- R[rs] + R[rt];

5 5 5 Operation
3
RN1 RN2 WN
RD1
Register File ALU Zero
WD

RD2
RegWrite
 Datapath: Load/Store Instruction

3 ALU operation
Read
MemWrite register 1 Read MemWrite
Read data 1
Instruction register 2 Zero
Registers ALU ALU
Address Read Write result Address Read
data 16 32 register data
Sign Read
extend Write data 2
Data data Data
Write
data memory memory
RegWrite Write
data
16 32
MemRead Sign MemRead
extend

a. Data memory unit b. Sign-extension unit

Two additional elements used Datapath

To implement load/stores
Animating the Datapath

lw rt, offset(rs)
R[rt] <- MEM[R[rs] + s_extend(offset)];
Animating the Datapath

sw rt, offset(rs)
MEM[R[rs] + sign_extend(offset)] <- R[rt]
Datapath: Branch Instruction

PC + 4 from instruction datapath

No shift hardware required:

Add Sum Branch target
simply connect wires from
input to output, each shifted Shift
left 2 bits left 2

ALU operation
Read 3
Instruction register 1 Read
Read data 1
register 2 To branch
Registers ALU Zero
Write control logic
register Read
Write data 2
data
RegWrite

16 32
Sign
extend

Datapath
 Animating the Datapath

PC +4 from
op rs rt offset/immediate instruction
16 datapath ADD
5 5 Operation
<<2
RN1 RN2 WN
RD1
Register File ALU Zero
WD

RD2
RegWrite

16
E
X 32
beq rs, rt, offset
T
N if (R[rs] == R[rt]) then
D
PC <- PC+4 + s_extend(offset<<2)
 MIPS Datapath I: Single-Cycle
Input is either register (R-type) or sign-extended
lower half of instruction (load/store)

Data is either
from ALU (R-type)
or memory (load) Combining the datapaths for R-type instructions
and load/stores using two multiplexors
 Animating the Datapath:
R-type Instruction
Instruction add rd,rs,rt
32 16 5 5 5 Operation
3
RN1 RN2 WN
RD1
Register File ALU Zero
WD

M MemWrite
RD2 U ADDR MemtoReg
RegWrite X
Data
E Memory RD M
X U
16 32 ALUSrc X
T WD
N MemRead
D
 Animating the Datapath:
Load Instruction
Instruction lw rt,offset(rs)
32 16 5 5 5 Operation
3
RN1 RN2 WN
RD1
Register File ALU Zero
WD

M MemWrite
RD2 U ADDR MemtoReg
RegWrite X
Data
E Memory RD M
X U
16 32 ALUSrc X
T WD
N MemRead
D
 Animating the Datapath:
Store Instruction
Instruction sw rt,offset(rs)
32 16 5 5 5 Operation
3
RN1 RN2 WN
RD1
Register File ALU Zero
WD

M MemWrite
RD2 U ADDR MemtoReg
RegWrite X
Data
E Memory RD M
X U
16 32 ALUSrc X
T WD
N MemRead
D
 MIPS Datapath II: Single-Cycle

Separate adder as ALU operations and PC

increment occur in the same clock cycle
Add

Read Registers
ALU operation
register 1 3 MemWrite
PC Read
Read Read MemtoReg
address
register 2 data 1 ALUSrc Zero
Instruction ALU ALU
Write Read Address Read
register data 2 M result data
u M
Instruction Write x u
memory Data x
data memory
Write
RegWrite data
16 Sign 32 MemRead
extend
Separate instruction memory
as instruction and data read
occur in the same clock cycle
Adding instruction fetch
 MIPS Datapath III: Single-Cycle

PCSrc New multiplexor

M
Add u
x
4 Add ALU
result
Shift
left 2 Extra adder needed as both
adders operate in each cycle
Registers
Read 3 ALU operation
MemWrite
Read register 1 ALUSrc
PC Read
address Read data 1 MemtoReg
register 2 Zero
Instruction ALU ALU
Write Read Address Read
register M result data
data 2 u M
Instruction u
memory Write x Data x
data memory
Write
RegWrite data
16 32
Sign
extend MemRead
Instruction address is either
PC+4 or branch target address

Adding branch capability and another multiplexor

Important note: in a single-cycle implementation data cannot be stored
during an instruction – it only moves through combinational logic
 Datapath Executing add

ADD
M
ADD
ADD U
4 X

PC <<2 PCSrc
Instruction
ADDR RD
32 16 5 5 5 Operation
Instruction 3
Memory RN1 RN2 WN
RD1
Register File ALU Zero
WD

M MemWrite
RD2 U ADDR MemtoReg
RegWrite X
Data
E Memory RD M
U
16 X 32 ALUSrc X
T WD
N MemRead
add rd, rs, rt D
 Datapath Executing lw

ADD
M
ADD
ADD U
4 X

PC <<2 PCSrc
Instruction
ADDR RD
32 16 5 5 5 Operation
Instruction 3
Memory RN1 RN2 WN
RD1
Register File ALU Zero
WD

M MemWrite
RD2 U ADDR MemtoReg
RegWrite X
Data
E Memory RD M
U
16 X 32 ALUSrc X
T WD
N MemRead
lw rt,offset(rs) D
 Datapath Executing sw

ADD
M
ADD
ADD U
4 X

PC <<2 PCSrc
Instruction
ADDR RD
32 16 5 5 5 Operation
Instruction 3
Memory RN1 RN2 WN
RD1
Register File ALU Zero
WD

M MemWrite
RD2 U ADDR MemtoReg
RegWrite X
Data
E Memory RD M
U
16 X 32 ALUSrc X
T WD
N MemRead
sw rt,offset(rs) D
 Datapath Executing beq

ADD
M
ADD
ADD U
4 X

PC <<2 PCSrc
Instruction
ADDR RD
32 16 5 5 5 Operation
Instruction 3
Memory RN1 RN2 WN
RD1
Register File ALU Zero
WD

M MemWrite
RD2 U ADDR MemtoReg
RegWrite X
Data
E Memory RD M
U
16 X 32 ALUSrc X
T WD
N MemRead
beq r1,r2,offset D