Any sequential system can be represented with a state

Sequential logic implementation diagram

FSMs 1 FSMs 2

State machine model State Machine Model

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( " (#$ (% $ &&&$ (
) " ) #$ ) %$ &&&$ )
* "+ $ (,
) "+ + $ (,

FSMs 3 FSMs 4

How do we turn a state diagram into logic? FSM design procedure

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FSMs 5 FSMs 6
Design Problem – Run-Length Encoder RLE Design

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00 1" 2 $
00 #" 2
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3 ' 4
$ $ $
! +
7 8

RLE
clk valid

FSMs 7 FSMs 8

Start with Datapath FSM Controller

5 '
START1

eq
= inc=x valid=0
clr=x count=x

START2
7 7 7 valid
cnt
inc=x valid=0
0 7 8 clr=x count=x
SENDING
count 1 ~eq
inc=x valid=1
7 clr=x count=0
inc
cen
+ clr
clr cnt inc=x valid=1
eq
clr=1 count=0
inc=x valid=1
~eq
clr=x count=1
+ eq

$ $ $ $ inc=1 valid=0
clr=0 count=x

COUNTING

FSMs 9 FSMs 10

Verilog For State Machines RLE Module

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7 9
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8 '
module rleFSM (clk, reset, eq, clr, inc, valid, cnttag);
Mealy outputs input clk, reset;
input eq; // current data value == previous data value
output clr; // clear count value (0 means 2, . . .)
next state Moore outputs output inc; // increment count value (clr overrides)
inputs
combinational output valid; // output value is valid
logic output cnttag; // select the count for the output value

current state // Use parameter to define symbolic states

parameter START1 = 0, START2 = 1, SENDING = 2, COUNTING = 3;
reg [1:0] state, // current state
nextState; // next state

FSMs 11 FSMs 12
Verilog for Registers Verilog for FSM Logic
always @(state or eq) begin
// Set defaults
* : ! 63 ; valid = 0; inc = x; clr = x; cnttag = x;
case (state)
$ START1:
* ' nextState = START2;
START2:
nextState = SENDING;
SENDING: begin
valid = 1;
reg [7:0] state, // current state cnttag = 0;
if (eq) begin
nextState; // next state nextState = COUNTING;
end else begin
always @(posedge CLK) begin nextState = SENDING;
if (reset) end
end
state = START1; COUNTING: begin
else if (eq) begin
state = nextState; clr = 0;
inc = 1;
end nextState = COUNTING;
end else begin
valid = 1;
cnttag = 1;
nextState = SENDING;
end
13 end 14
FSMs FSMs
end

Implementing an FSM RLE State Table

#& 9 ?

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+ 9< = # * = 2* # * = 2* % 1
% &!
* = 2* % 87 (7 < 1

1 87 (7 < 87 (7 < # 1
>&
- # 87 (7 < ! ) @ 7 * (7 < # # 1
& &%
1 ! ) @ 7 * (7 < 87 (7 < # #

# ! ) @ 7 * (7 < ! ) @ 7 * (7 < 1 # 1

FSMs 15 FSMs 16

RLE State Table Logic Synthesis

B# B1

A 11 1# ## #1 11 1# ## #1 11 1# ## #1

1 1 # # # 1 # 1 1 1 1 C C C C

# 1 # # # # # 1 # # # C C 1 #

11 1# 1
11 1# ## #1 11 1# ## #1 11 1# ## #1
1# #1 1 1 C C C C 1 1 1 # # 1 C C C 1

# C C # C # 1 1 1 # # C C # 1
1 #1 #1 # 1

# #1 ## # # 1

1 ## #1 # # "! #

# ## ## 1 # 1
!
FSMs 17 FSMs 18
RLE State Table 1-Hot Logic Functions

#
-
/
B 10
B #0B 1
B % 0B#D 4B % DB >
111# 11#1 1 B > 0 B % DB >
0#
11#1 1#11 1 0B%
0 B % D 4B >
1 1#11 1#11 # 1 0B>

# 1#11 #111 # # 1 A

1 #111 1#11 # #

# #111 #111 1 # 1

FSMs 19 FSMs 20

Another Example: Ant Brain Ant Behavior - Case Analysis

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! & !
= " + $ * 6E* 2 E " # $ " # $ !
# !% !%
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&
&
" # $
! !%

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,, ! -
+ # ,
,, &

" + # ,
,,
. + $
! - !

FSMs 21 FSMs 22

Designing an Ant Brain State Transition Truth Table

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) $ , : '; $ , &'
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* ' % *%

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%*% ,*% &0 +/
, &0 +/
,
,, ,
,,,
,, ,
,, ,
,,

FSMs 23 FSMs 24
Synthesis Synthesis of Next State and Output Functions

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F " > C$ G $ H 1 23 18 28 38 +/ +.
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FSMs 25 FSMs 26

Don’t cares in FSM synthesis Don’t Care Example

5 I I #1#$ ##1$ ### J ( " 111$ 1#1$ 1##$ #1#$ ##1

* K -
K $ K
$

,
, , Present State Next State
C B A C+ B+ A+
, 0 0 0 x x x
0 0 1 x x x
% *% 0 1 0 1 0 1
0 1 1 1 1 0
, 1 0 0 0 1 0
, , 1 0 1 0 1 1
, 1 1 0 1 0 0
1 1 1 x x x

,
%*% ,*%
,
! $ 4 $ ! # - ! $ $
$ =
# !
FSMs 27 FSMs 28

Don’t cares in FSMs (cont’d) Self-starting FSMs

- K
8 &8 8

8 &8 8

1 1 1
1 1 1 1 1 1 & & &

& & & Present State Next State

C B A C+ B+ A+
8 0 0 0 0 1 1
;& 0 0 1 0 1 0
0 1 0 1 0 1
0 1 1 1 1 0
&8 ; 8 &< 1 0 0 0 1 0
1 0 1 0 1 1
8 1 1 0 1 0 0
; < <8 1 1 1 1 1 x

FSMs 29 FSMs 30
Self-starting FSMs Mealy vs. Moore Machines

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+
K 5 +
J
$ L $ 4 ' '
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- -
> '
$ )
! % > !

, ' ,*%

FSMs 31 FSMs 32

Specifying outputs for a Moore machine Specifying outputs for a Mealy machine

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" 1# #1 " 1# #1
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# /- # # 0-/- ' - .
1 1 ) # /- # # 0-/-
) + + 1 1 )
+' ' ) +
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+ + )
+ #' + +
# ) ' '
)' & +
+
'
&
' &'
& +
& '

FSMs 33 FSMs 34

Comparison of Mealy and Moore machines Isn’t Mealy Always Better?

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logic for
inputs inputs outputs
combinational outputs
logic for & & & & -
next state logic for combinational
reg outputs logic for reg
outputs
next state 5 ' J

state feedback FSMs state feedback 35 FSMs 36

Moore Implementation - Pipelined

8 " F
-
023 0
& 0!

& & & & -

5 ' J

FSMs 37