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COMPAL CONFIDENTIAL
1 MODEL NAME : BAL20 SKL-U+MEC1404 board 1
PCB NO : DAZ1P600100
BOM P/N : 431A2K31L01
2016-06-21
REV : 1.0 (A00)
@ : Un-pop Component
UMA@/DIS@ : UMA & DIS Type
KBL@/SKL@ : CPU Type
ZZZ
PCB
EC@ : EC
2 DAZ1P600100
PCB@
JP@/PJP@ : JUMP 2
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
COPYRIGHT 2014 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Cover Page
ALL RIGHT RESERVED BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
REV: X00 A00
PWB: 9HTP8
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-D801P
Date: Tuesday, June 21, 2016 Sheet 1 of 61
A B C D E
A B C D E
Block Diagram
DDR4
4GB/8GB
DDR4 1866/2133MHz Channel A
1
GPU (Gen3)
SODIMM A 1
Intel CPU
VRAM(GDDR5)* 4 AMD MESO
R16M-M1-70 PCIe x 4
GDDR5 (15"/17") 25W Skylake - U DDR4
Kabylake - U 4GB/8GB
DDR4 1866/2133MHz Channel B
DIS on board SODIMM B
28W (UMA only)
15W (UMA&DIS)
MIC_IN/GND
SPI
Touch USB2.0 x 1
HP_R/L Screen PS2 Int.
SPI Flash ROM KB
3 Universal Jack 3
16MB
USB3.0 x 1
Port 0 (USB3.0) Intel SBA
USB2.0 x 1
ODD
Right side SATA x2
SB USB2.0 x 1
Port 2 (USB2.0)
SB 2.5"
(Gen3) HDD
SB CardReader
(Gen3) SD 3.0
SSD PCIe x 2 (SATA x 1) USB2.0 x 1 SD Card Slot
4
Realtek 4
RTS5170
Title
Block Diagram
POWER STATES USB PORT# DESTINATION USB3.0 SSIC PCIE SATA DESTINATION
Signal SLP SLP SLP ALWAYS SUS RUN 1 USB3.0 Port1 USB3.0-1 USB3.0 Port1
S3# S4# S5# PLANE PLANE PLANE CLOCKS
State
2 USB3.0 Port2 USB3.0-2 SSIC-1 USB3.0 Port2
S0 (Full ON) / M0 HIGH HIGH HIGH ON ON ON ON 3 IO/DB USB3.0-3 SSIC-2 3D Camera
D D
+3VALW_PCH
+VGA_CORE
+3.3V_ALW_DSW
+VCC_CORE
+5VALW
+0.6V_DDR_VTT
State
Board ID & Model ID table
Item Pull-down Pull-up Voltage Board ID/Model ID
1 100 10.0 3.000 EVT
S0 ON ON ON ON ON
2 100 13.7 2.902 DVT1
A A
PJP200
CPU PWR PJP206 SIO_SLP_S4#
RT8207PGQW
GPU PWR (PU200) +1.2VP +1.2V_DDR SIO_SLP_S3#
SIO_SLP_S0# JP1
Peripheral Device PWR TPS22961
(UZ2) +1.0V_VCCSTG 3.5A Volume +1.0VS_VCCIO 3.4A
0.6V_DDR_VTT_ON PJP203
+0.6VSP +0.6V_DDR_VTT
0ohm 0603
(RC174) +1.0V_MPHYGT 2.8A
P.18
ADAPTER @SIO_SLP_SUS#
D PJP301 POK PJP302 SIO_SLP_S4# D
SYX196DQNC TPS22967
(PU301) +1VALWP +1.0V_PRIM (UZ1) +1.0V_VCCST 240mA
JP7
EM5209VF DGPU_PWR_EN
(UZ5) +0.95VSDGPU
CHARGER
ISL95521HRZ +PWR_SRC
(PU703) (+19VB) PJP1401 DGPU_PWROK PJP1402
SYX196DQNC
(PU1400) +1.35VGPUP +1.35V_MEM_GFX
EDP_VDD_EN
JP5 or
PJP102 SIO_SLP_S3# LCD_TST
ISL95859HRTZ AOZ5019QI EM5209VF RT9724GB
(PU602) (PU604) +3VALWP +3VALW (UZ3) +3VS (U1) +LCDVDD
U23@
(UZ4) +3VGS
PJP501 JP8
+RTC_VCC (NON-DS3)
POK PJP502 DGPU_PWR_EN
+VCC_SA +VCC_CORE +VCC_GT RT8061AZQW EM5209VF
(PU500) +1.8VALWP +1.8V_PRIM (UZ5) +1.8VGS
(DS3)
@SIO_SLP_SUS#
PJP801
SIO_SLP_S4# PJP802
ISL62771HRTZ RT9059GSP
(PU1100) (PU800) +2.5VP +2.5V_MEM
+VGA_CORE
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Power Rail
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 4 of 61
5 4 3 2 1
5 4 3 2 1
W3 SML1CLK U7
SML1CLK VGA_SMB_CK3 SMBCLK
V3 SML1DATA DMN66D U8 dGPU
SML1DATA VGA_SMB_DA3 EXO
SMBDATA SMBus Address: 0x41 / 0x41
U6 U7
I2C_SDA_TP
I2C_SCL_TP
C C
2.2k ohm
2.2k ohm @
2.2k ohm +3VS
+3VALW_EC 2.2k ohm @ 8
SML1CLK THM_SML1_CLK SCL Thermal
SML1CLK DMN66D 7 NCT7718W
SML1DATA THM_SML1_DATA SDA
SML1DATA
SMBus Address: 1001100xb (x is R/W bit)
12 11
+3VS TP_VDD
KBC 4.7k ohm 2.2k ohm
MEC 1404
3
I2C_SCL_TP I2C_SCL_TP_Q
DMN66D 2
I2C_SDA_TP I2C_SDA_TP_Q
B B
8 TP CONN
4.7k ohm CLK_TP_SIO
7
TP_VDD DAT_TP_SIO
4.7k ohm SMBus Address: $2C
78
PS2_CLK0 CLK_TP_SIO
79
PS2_DAT0 DAT_TP_SIO
4.7k ohm
9 100 ohm 6
SMB01_CLK PBAT_CHG_SMBCLK CLK_SMB SCL
SMB01_DATA 8 100 ohm 5 BATT CONN
PBAT_CHG_SMBDAT DAT_SMB SDA
SMBus Address: 0x01
A 3 A
0 ohm
SDA Charger
0 ohm 4 ISL95521HRZ-T
SCL
SMBus Address: 0001001 (R/W#) DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SMbus Block diagram
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 5 of 61
5 4 3 2 1
5 4 3 2 1
+3VS
UC1A SKL-U
SKL_ULT
UC1I
CSI-2
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B B38 CSI2_DN3 CSI2_CLKN3 A26 B
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC7 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7 WLAN_RADIO_DIS#
C33 CSI2_DP4 GPP_D4/FLASHTRIG WLAN_RADIO_DIS# [32]
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP RC8 200_0402_1%
SKL-U_BGA1356 9 OF 20
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MCP(1/14)DDI,EDP,CSI2,EMMC
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 6 of 61
5 4 3 2 1
5 4 3 2 1
SKL-U
UC1B SKL-U UC1C
AU53 DDR_A_CLK#0
[20] DDR_A_D[0..15] DDR_A_D0 AL71 DDR0_CKN[0] AT53 DDR_A_CLK0 DDR_A_CLK#0 [20] [21] DDR_B_D[0..15] DDR_B_D0 AF65 AN45 DDR_B_CLK#0
DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 DDR_A_CLK#1 DDR_A_CLK0 [20] DDR_B_D1 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1 DDR_B_CLK#0 [21]
DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55 DDR_A_CLK1 DDR_A_CLK#1 [20] DDR_B_D2 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDR_B_CLK0 DDR_B_CLK#1 [21]
D DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKP[1] DDR_A_CLK1 [20] DDR_B_D3 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1 DDR_B_CLK0 [21] D
DDR_A_D4 AL70 DDR0_DQ[3] BA56 DDR_A_CKE0 DDR_B_D4 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 [21]
DDR_A_D5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_A_CKE0 [20] DDR_B_D5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR_A_D6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 DDR_A_CKE2 DDR_A_CKE1 [20] DDR_B_D6 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDR_B_CKE1 DDR_B_CKE0 [21]
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 DDR_A_CKE3 DDR_B_D7 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDR_B_CKE2 DDR_B_CKE1 [21]
TP3
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[3] TP4 DDR_B_D8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53 DDR_B_CKE3 TP5
DDR_A_D9 AR68 DDR0_DQ[8] AU45 DDR_A_CS#0 DDR_B_D9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] TP6
DDR_A_D10 AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 DDR_A_CS#1 DDR_A_CS#0 [20] DDR_B_D10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS#0
DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_A_CS#1 [20] DDR_B_D11 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1 DDR_B_CS#0 [21]
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDR_A_ODT1 DDR_A_ODT0 [20] DDR_B_D12 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0 DDR_B_CS#1 [21]
DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[1] DDR_A_ODT1 [20] DDR_B_D13 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDR_B_ODT1 DDR_B_ODT0 [21]
DDR_A_D14 AU70 DDR0_DQ[13] BA51 DDR_A_MA5 DDR_B_D14 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 [21]
DDR_A_D15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9 DDR_A_MA5 [20] DDR_B_D15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 DDR_B_MA5
[20] DDR_A_D[16..31] DDR_A_D16 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDR_A_MA6 DDR_A_MA9 [20] [21] DDR_B_D[16..31] DDR_B_D16 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_MA9 DDR_B_MA5 [21]
DDR_A_D17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8 DDR_A_MA6 [20] DDR_B_D17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6 DDR_B_MA9 [21]
DDR_A_D18 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_MA7 DDR_A_MA8 [20] DDR_B_D18 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_B_MA8 DDR_B_MA6 [21]
DDR_A_D19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BG0 DDR_A_MA7 [20] DDR_B_D19 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7 DDR_B_MA8 [21]
DDR_A_D20 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDR_A_MA12 DDR_A_BG0 [20] DDR_B_D20 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_BG0 DDR_B_MA7 [21]
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 DDR_A_MA12 [20] DDR_B_D21 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_MA12 DDR_B_BG0 [21]
DDR_A_D22 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_ACT# DDR_A_MA11 [20] DDR_B_D22 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_MA11 DDR_B_MA12 [21]
DDR_A_D23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_BG1 DDR_A_ACT# [20] DDR_B_D23 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_ACT# DDR_B_MA11 [21]
DDR_A_D24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_BG1 [20] DDR_B_D24 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_BG1 DDR_B_ACT# [21]
DDR_A_D25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_MA13 DDR_B_D25 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_BG1 [21]
DDR_A_D26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_CAS# DDR_A_MA13 [20] DDR_B_D26 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43 DDR_B_MA13
DDR_A_D27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_WE# DDR_A_CAS# [20] DDR_B_D27 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_CAS# DDR_B_MA13 [21]
DDR_A_D28 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_RAS# DDR_A_WE# [20] DDR_B_D28 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_WE# DDR_B_CAS# [21]
DDR_A_D29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_BS0 DDR_A_RAS# [20] DDR_B_D29 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_RAS# DDR_B_WE# [21]
DDR_A_D30 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2 DDR_A_BS0 [20] DDR_B_D30 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_BS0 DDR_B_RAS# [21]
DDR_A_D31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_BS1 DDR_A_MA2 [20] DDR_B_D31 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_MA2 DDR_B_BS0 [21]
[20] DDR_A_D[32..47] DDR_A_D32 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_MA10 DDR_A_BS1 [20] [21] DDR_B_D[32..47] DDR_B_D32 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_BS1 DDR_B_MA2 [21]
DDR_A_D33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_MA1 DDR_A_MA10 [20] DDR_B_D33 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_MA10 DDR_B_BS1 [21]
DDR_A_D34 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0 DDR_A_MA1 [20] DDR_B_D34 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_MA1 DDR_B_MA10 [21]
C DDR_A_D35 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_A_MA3 DDR_A_MA0 [20] DDR_B_D35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA0 DDR_B_MA1 [21] C
DDR_A_D36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_A_MA4 DDR_A_MA3 [20] DDR_B_D36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDR_B_MA3 DDR_B_MA0 [21]
DDR_A_D37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_A_MA4 [20] DDR_B_D37 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 DDR_B_MA4 DDR_B_MA3 [21]
DDR_A_D38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDR_A_DQS#0 DDR_B_D38 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDR_B_MA4 [21]
DDR_A_D39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS0 DDR_A_DQS#0 [20] DDR_B_D39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDR_B_DQS#0
DDR_A_D40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDR_A_DQS#1 DDR_A_DQS0 [20] DDR_B_D40 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_B_DQS0 DDR_B_DQS#0 [21]
DDR_A_D41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDR_A_DQS1 DDR_A_DQS#1 [20] DDR_B_D41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_B_DQS#1 DDR_B_DQS0 [21]
DDR_A_D42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDR_A_DQS#2 DDR_A_DQS1 [20] DDR_B_D42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_B_DQS1 DDR_B_DQS#1 [21]
DDR_A_D43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2 DDR_A_DQS#2 [20] DDR_B_D43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_B_DQS#2 DDR_B_DQS1 [21]
DDR_A_D44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR_A_DQS#3 DDR_A_DQS2 [20] DDR_B_D44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_B_DQS2 DDR_B_DQS#2 [21]
DDR_A_D45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3 DDR_A_DQS#3 [20] DDR_B_D45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_B_DQS#3 DDR_B_DQS2 [21]
DDR_A_D46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_A_DQS#4 DDR_A_DQS3 [20] DDR_B_D46 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_B_DQS3 DDR_B_DQS#3 [21]
DDR_A_D47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_A_DQS4 DDR_A_DQS#4 [20] DDR_B_D47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_B_DQS#4 DDR_B_DQS3 [21]
[20] DDR_A_D[48..63] DDR_A_D48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_A_DQS#5 DDR_A_DQS4 [20] [21] DDR_B_D[48..63] DDR_B_D48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS4 DDR_B_DQS#4 [21]
DDR_A_D49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_A_DQS5 DDR_A_DQS#5 [20] DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#5 DDR_B_DQS4 [21]
DDR_A_D50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6 DDR_A_DQS5 [20] DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS5 DDR_B_DQS#5 [21]
DDR_A_D51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_A_DQS6 DDR_A_DQS#6 [20] DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_B_DQS#6 DDR_B_DQS5 [21]
DDR_A_D52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_A_DQS#7 DDR_A_DQS6 [20] DDR_B_D52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDR_B_DQS6 DDR_B_DQS#6 [21]
DDR_A_D53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_A_DQS7 DDR_A_DQS#7 [20] DDR_B_D53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_B_DQS#7 DDR_B_DQS6 [21]
DDR_A_D54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_A_DQS7 [20] DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDR_B_DQS7 DDR_B_DQS#7 [21]
DDR_A_D55 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 DDR_A_ALERT# DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[7] DDR_B_DQS7 [21]
DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# DDR_A_ALERT#[20] DDR0_PAR,DDR0_ALERT# for DDR1_DQ[55]
DDR_A_D56 AY27 AT52 DDR_A_PAR DDR4 DDR_B_D56 AT22 AN43 DDR_B_ALERT#
DDR_A_D57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDR_A_PAR [20] DDR_B_D57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43 DDR_B_PAR DDR_B_ALERT# [21]
DDR_A_D58 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 DDR_B_D58 AU21 DDR1_DQ[57] DDR1_PAR AT13 H_DRAMRST# DDR_B_PAR [21]
DDR_A_D59 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA +V_DDR_REFA_R DDR_B_D59 DDR1_DQ[58] DRAM_RESET# SM_RCOMP0 H_DRAMRST# [20]
AW25 AY68 AT21 AR18
DDR_A_D60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR CH - A
DDR0_VREF_DQ BA67 DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1
DDR_A_D61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +V_DDR_REFB_R DDR_B_D61 DDR1_DQ[60] DDR_RCOMP[1] SM_RCOMP2
BA27 AP22 DDR CH - B AU18
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CNTL DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_B_D63 AN21 DDR1_DQ[62]
DDR0_DQ[63]/DDR1_DQ[47] DDR1_DQ[63] DDR1_PAR,DDR1_ALERT# for DDR4
SKL-U_BGA1356 2 OF 20 SKL-U_BGA1356 3 OF 20
B B
A 4
3 Y 0.6V_DDR_VTT_ON [53] CAD Note:
GND 1 Trace width=12~15 mil, Spacing=20 mils
@
74AUP1G07GW_TSSOP5 CC90 Max trace length= 500 mil
100P_0402_50V8J
2
BUFFER
A A
Main: SA00005U600
2nd: SA00007UR00
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MCP(2/14)DDR4
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 7 of 61
5 4 3 2 1
5 4 3 2 1
+3VS
+3VS
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1 QC1A
1
2
PCH EDS R0.7 p.235~236 SKL-U
DMN66D0LDW-7_SOT363-6
RC181 @ UC1E
10K_0402_5% SMBCLK 6 1
SPI - FLASH PCH_SMBCLK [20,21]
SMBUS, SMLINK
SMB -> DDR4
5
PCH_SPI_CLK_R1 AV2 QC1B
2
PCH_SPI_D3_R1 AU4
RC182 PCH_SPI_CS#0_R1 AU3 SPI0_IO3 R9 SML0_SMBCLK
D [25] PCH_SPI_CS#0_R1 AU2 SPI0_CS0# GPP_C3/SML0CLK W2 SML0_SMBDATA D
10K_0402_5% SPI0_CS1# GPP_C4/SML0DATA
AU1 W1 GPP_C5
SPI0_CS2# GPP_C5/SML0ALERT#
SML1 -> EC,DGPU,THM
2
W3 SML1CLK
SPI - TOUCH GPP_C6/SML1CLK SML1CLK [25,30,41]
V3 SML1DATA SML1CLK => GPU_THM_SMBCLK
ONE_DIMM# M2 GPP_C7/SML1DATA GPP_B23 SML1DATA [25,30,41] SML1DATA => GPU_THM_SMBDAT
AM7
M3 GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT#
J4 GPP_D2/SPI1_MISO
V1 GPP_D3/SPI1_MOSI
DIMM Detect V2 GPP_D21/SPI1_IO2
+3VS M1 GPP_D22/SPI1_IO3
HIGH 1 DIMM GPP_D0/SPI1_CS#
LPC
AY13
LOW 2 DIMM GPP_A1/LAD0/ESPI_IO0 BA13
LPC_LAD0 [25]
GPP_A2/LAD1/ESPI_IO1 LPC_LAD1 [25]
1
C LINK
10K_0402_5% BB13
GPP_A3/LAD2/ESPI_IO2 LPC_LAD2 [25]
G3 AY12
RC13
+3VS
AW13 AW9 EMI@ RC15 1 2 22_0402_5%
[25] SIO_RCIN# GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK PCI_CLK_LPC1 CLK_PCI_LPC_MEC [25]
AY9 EMI@ RC16 1 2 22_0402_5%
AY11 GPP_A10/CLKOUT_LPC1 AW11 CLKRUN# CLK_PCI_LPDEBUG [25] PCH_SMBDATA 2 1
[25] SERIRQ GPP_A6/SERIRQ GPP_A8/CLKRUN# CLKRUN# [25]
1 2.2K_0402_5% RC27
1 2 CC88 @RF@ PCH_SMBCLK 2 1
+3VS
RC14 10K_0402_5% SKL-U_BGA1356 5 OF 20 10P_0402_50V8J 2.2K_0402_5% RC28
2 +3VALW_PCH
SMBCLK 1 2
RC29 1K_0402_5%
SMBDATA 1 2
C RC30 1K_0402_5% C
SML1CLK 1 2
+3VALW_PCH +3.3V_SPI RC40 1 CMC@ 2 1K_0402_1% PCH_SPI_D0_R1 RC31 1K_0402_5%
[14] XDP_SPI_SI
SML1DATA 1 2
2 @ 1 RC41 1 CMC@ 2 1K_0402_1% PCH_SPI_D2_R1 RC32 1K_0402_5%
[14] XDP_SPI_IO2 SML0_SMBCLK
RC17 0_0603_5% 1 2
RC40/41 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for XDP RC33 1K_0402_5%
SML0_SMBDATA 1 2
+3.3V_SPI RC34 1K_0402_5%
SUS_STAT#/LPCPD# 1 @ 2
RC35 8.2K_0402_5%
1 2 PCH_SPI_CS#0_R1 +3VS
RC18 4.7K_0402_5%
PCH_SPI_D1_R1 RC22 1 2 33_0402_5% PCH_SPI_D1_R
PCH_SPI_D0_R1 PCH_SPI_D0_R PCH_SPI_D1_R [25]
RC23 1 2 33_0402_5%
PCH_SPI_CLK_R1 RC24 1 2 33_0402_5% PCH_SPI_CLK_R PCH_SPI_D0_R [25] CLKRUN# 1 2
+3.3V_SPI MOW WW06
PCH PCH_SPI_D3_R1 RC25 1 2 33_0402_5% PCH_SPI_D3_R PCH_SPI_CLK_R [25] RC36 8.2K_0402_5%
PCH_SPI_D2_R1 RC26 1 2 33_0402_5% PCH_SPI_D2_R
1 2 PCH_SPI_D2_R1 +3VALW_PCH
RC19 1K_0402_5%
Int. PD.
1 @ 2 PCH_SPI_D3_R1
RC20 1K_0402_5%
PCH_SMB_ALERT# 1 @ 2
RC37 8.2K_0402_5%
TLS CONFIDENTIALITY
HIGH ENABLE
B LOW(DEFAULT) DISABLE B
+3.3V_SPI
+3VALW_PCH
CC3
Int. PD.
1 2
2
33_0402_5%
128Mb Flash ROM
RC21
@EMI@
+3VALW_PCH
1
Modify Value to 150k for WW52 MOW
33P_0402_50V8J
2015/03/03 Jason
CC2
@EMI@
GPP_B23 1 CMC@ 2
RC39 150K_0402_5%
1
EXI BOOT STALL BYPASS
HIGH ENABLE
A LOW(DEFAULT) DISABLE A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MCP(3/14)SPI,SMB,LPC
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 8 of 61
5 4 3 2 1
5 4 3 2 1
+3VALW_PCH
UC1F SKL-U
KB_DET# 1 2
LPSS ISH
RC45 10K_0402_5%
RTC_DET# 1 2
AN8 RC46 10K_0402_5%
AP7 GPP_B15/GSPI0_CS# P2 CAM_DETECT# SIO_EXT_WAKE# 1 2
VBIOS_ID1 AP8 GPP_B16/GSPI0_CLK GPP_D9 P3 DGPU_HOLD_RST# CAM_DETECT# [37]
RC47 10K_0402_5%
NRB_BIT AR7 GPP_B17/GSPI0_MISO GPP_D10 P4 IR_CAM_DETECT# DGPU_HOLD_RST# [40]
GPP_B18/GSPI0_MOSI GPP_D11 P1 RTC_DET# IR_CAM_DETECT# [28]
DBC_EN AM5 GPP_D12 RTC_DET# [22]
D [28] DBC_EN 3D_CAM_EN_PCH AN7 GPP_B19/GSPI1_CS# M4 D
FW_UPDATE_PCH AP5 GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA N3
AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL DIS@
GPP_B22/GSPI1_MOSI N1 DGPU_HOLD_RST# 1 2
AB1 GPP_D7/ISH_I2C1_SDA N2 RC48 10K_0402_5%
BLUETOOTH_EN AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL
[32] BLUETOOTH_EN W4 GPP_C9/UART0_TXD AD11
BOARD_ID2 AB3 GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12
GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
AD1
AD2 GPP_C20/UART2_RXD U1 DGPU_PWR_EN
AD3 GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 DGPU_PWR_EN [39,59]
+3VS [25] SIO_EXT_WAKE# LPSS_UART2_CTS# AD4 GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3 +3VS
GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS# U4
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
U7 AC1 CAM_DETECT# 2 1
1 2 BLUETOOTH_EN [30] I2C_SDA_TP U6 GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 RC63 10K_0402_5%
[30] I2C_SCL_TP GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 IR_CAM_DETECT# 2 1
RC42 10K_0402_5%
U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 RC64 10K_0402_5%
U9 GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_C19/I2C1_SCL AY8 PROJECT_ID1
AH9 GPP_A18/ISH_GP0 BA8 PROJECT_ID2
AH10 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 BB7
GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7 BOARD_ID3 KB_DET# [30]
AH11 GPP_A21/ISH_GP3 AY7 VBIOS_ID3
2 @ 1 LPSS_UART2_CTS# AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW7 VBIOS_ID2
RC43 49.9K_0402_1% GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 AP13
AF11 GPP_A12/BM_BUSY#/ISH_GP6
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
SKL-U_BGA1356 6 OF 20
C C
+3VS +3VS
3D@
3D_CAM_EN_PCH 1 2
3D_CAM_EN [25,37]
DX2 RB751S40T1G_SOD523-2
1
3D@
FW_UPDATE_PCH 1 2 @ @ @ @ @
FW_UPDATE [25,37]
RC51 RC53 RC190 RC61 RC59
DX3 RB751S40T1G_SOD523-2 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
For 3D-CAM 2015/Jason
2
PROJECT_ID1 VBIOS_ID3
PROJECT_ID2 VBIOS_ID2
VBIOS_ID1
1
@ @
RC52 RC54 DIS@ 2G_G5@ 2G_G5@
10K_0402_5% 10K_0402_5% RC191 RC62 RC60
+3VALW_PCH 10K_0402_5% 10K_0402_5% 10K_0402_5%
2
1 @ 2 NRB_BIT
RC44 4.7K_0402_5%
+3VS
NO REBOOT STRAP
+3VS
HIGH No REBOOT
LOW(DEFAULT) REBOOT ENABLE
1
Weak IPD DIS@ SKL@
1
B RC55 RC57 B
10K_0402_5% 10K_0402_5%
RC49 DIS@
2
BOARD_ID2 10K_0402_5%
BOARD_ID3
2
DGPU_PWR_EN
2
UMA@ KBL@
RC56 RC58 RC50 DIS@
10K_0402_5% 10K_0402_5% 150K_0402_5%
1
RC61 2G_D3@ RC59 4G_G5@ VRAM ID VBIOS_ID3 VBIOS_ID2 VBIOS_ID1
(PCBA VRAM Size Config.) (GPP_A22) (GPP_A23) (GPP_B17)
2G GDDR5 0 0 0
10K_0402_5% 10K_0402_5% 4G GDDR5 0 0 1
SD028100280 SD028100280 2G DDR3 0 1 0
Reserved 0 1 1
A RC62 4G_G5@ RC60 2G_D3@ A
DELL CONFIDENTIAL/PROPRIETARY
10K_0402_5% 10K_0402_5%
SD028100280 SD028100280
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MCP(4/14)GSPI,I2C,UART,ISH
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D805P
Date: Tuesday, June 21, 2016 Sheet 9 of 61
5 4 3 2 1
5 4 3 2 1
PEG_HTX_C_GRX_P[0..3]
[40] PEG_HTX_C_GRX_P[0..3]
PEG_HTX_C_GRX_N[0..3]
[40] PEG_HTX_C_GRX_N[0..3]
PEG_GTX_C_HRX_P[0..3]
[40] PEG_GTX_C_HRX_P[0..3] UC1H SKL-U
PEG_GTX_C_HRX_N[0..3]
[40] PEG_GTX_C_HRX_N[0..3]
SSIC / USB3
PCIE/USB3/SATA
H8
USB3_1_RXN G8 USB3_CRX_DTX_N1 [26]
PEG_GTX_C_HRX_P0 H13 USB3_1_RXP C13 USB3_CRX_DTX_P1 [26]
D PEG_GTX_C_HRX_N0 G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13 USB3_CTX_DRX_N1 [26] ---> Port 1, USB3.0 D
PEG_HTX_C_GRX_P0 B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_CTX_DRX_P1 [26]
PEG_HTX_C_GRX_N0 A17 PCIE1_TXN/USB3_5_TXN J6
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6 USB3_CRX_DTX_N2 [26]
PEG_GTX_C_HRX_P1 G11 USB3_2_RXP/SSIC_1_RXP B13 USB3_CRX_DTX_P2 [26]
PEG_GTX_C_HRX_N1 F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 USB3_CTX_DRX_N2 [26] ---> Port 2, USB3.0
PEG_HTX_C_GRX_P1 D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3_CTX_DRX_P2 [26]
PEG_HTX_C_GRX_N1 C16 PCIE2_TXN/USB3_6_TXN J10
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10 USB3_CRX_DTX_N3 [37]
PEG_GTX_C_HRX_P2 H16 USB3_3_RXP/SSIC_2_RXP B15 USB3_CRX_DTX_P3 [37]
GPU ---> PEG_GTX_C_HRX_N2 G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15 USB3_CTX_DRX_N3 [37] ---> 3D CAMERA
PEG_HTX_C_GRX_P2 D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB3_CTX_DRX_P3 [37]
PEG_HTX_C_GRX_N2 C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
PEG_GTX_C_HRX_P3 G15 USB3_4_RXP C15
PEG_GTX_C_HRX_N3 F15 PCIE4_RXN USB3_4_TXN D15
PEG_HTX_C_GRX_P3 B19 PCIE4_RXP USB3_4_TXP
PEG_HTX_C_GRX_N3 A19 PCIE4_TXN AB9
PCIE4_TXP USB2N_1 USB_PN1 [26]
AB10
F16 USB2P_1 USB_PP1 [26] -----> Port 1, USB3.0 (Port 1)
[32] PCIE_CRX_WLANTX_N5 E16 PCIE5_RXN AD6
[32] PCIE_CRX_WLANTX_P5 PCIE5_RXP USB2N_2 USB_PN2 [26]
C19 AD7
WLAN ---> [32] PCIE_CTX_WLANRX_N5_C D19 PCIE5_TXN USB2P_2 USB_PP2 [26] -----> Port 2, USB3.0 (Port 2)
[32] PCIE_CTX_WLANRX_P5_C PCIE5_TXP AH3
USB2N_3 USB_PN3 [27]
G18 AJ3
[34] PCIE_CRX_LANTX_N6 F18 PCIE6_RXN USB2P_3 USB_PP3 [27] -----> Port 3, USB2.0 (IOB)
[34] PCIE_CRX_LANTX_P6 D20 PCIE6_RXP AD9
10/100M LAN ---> [34] PCIE_CTX_LANRX_N6 C20 PCIE6_TXN USB2N_4 AD10
[34] PCIE_CTX_LANRX_P6 PCIE6_TXP USB2P_4
F20 AJ1
[31] SATA3_CRX_HDDTX_N0 PCIE7_RXN/SATA0_RXN USB2N_5 USB_PN5 [28]
E20 AJ2
SATA HDD ---> [31] SATA3_CRX_HDDTX_P0
B21 PCIE7_RXP/SATA0_RXP
USB2
USB2P_5 USB_PP5 [28] -----> CCD
C [31] SATA3_CTX_HDDRX_N0 A21 PCIE7_TXN/SATA0_TXN AF6 C
[31] SATA3_CTX_HDDRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB_PN6 [27]
AF7
[31] SATA_CRX_ODDTX_N1 G21 USB2P_6 USB_PP6 [27] -----> Card Reader (IOB)
F21 PCIE8_RXN/SATA1A_RXN AH1
SATA ODD ---> [31] SATA_CRX_ODDTX_P1
D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2
USB_PN7 [28]
[31]
[31]
SATA_CTX_ODDRX_N1
SATA_CTX_ODDRX_P1 C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB_PP7 [28] -----> Touch Screen
PCIE8_TXP/SATA1A_TXP AF8
USB2N_8 USB_PN8 [32]
E22 AF9
E23 PCIE9_RXN USB2P_8 USB_PP8 [32] -----> BT
B23 PCIE9_RXP AG1
A23 PCIE9_TXN USB2N_9 AG2
PCIE9_TXP USB2P_9
F25 AH7
E25 PCIE10_RXN USB2N_10 AH8
D23 PCIE10_RXP USB2P_10 +3VALW_PCH
C23 PCIE10_TXN AB6 USBCOMP RC66 1 2 113_0402_1%
PCIE10_TXP USB2_COMP AG3 USB2_ID RC67 1 2 1K_0402_5%
PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC68 1 2 1K_0402_5% RPC1
RC65 1 2 100_0402_1% PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE USB_OC#6_7 4 5
PCIE_RCOMPP A9 USB_OC#0_1 USB_OC#0_1 3 6
D56 GPP_E9/USB2_OC0# C9 USB_OC#2_3 USB_OC#0_1 [27] USB_OC#2_3 2 7
[14] XDP_PRDY# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC#4_5 USB_OC#2_3 [27] USB_OC#4_5 1 8
Reserve
1 2[14] XDP_PREQ# PIRQA# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC#6_7 Reserve
+3VS GPP_A7/PIRQA# GPP_E12/USB2_OC3#
RC187 10K_0402_5% 10K_8P4R_5%
[48] PCIE_CRX_SSDTX_N11 E28 J1
E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 SIO_EXT_SCI# HDD_DEVSLP [31]
[48] PCIE_CRX_SSDTX_P11 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 SIO_EXT_SCI# [25]
[48] PCIE_CTX_SSDRX_N11 D24 J3 +3VS
C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
PCIE SSD ---> [48]
[48]
PCIE_CTX_SSDRX_P11
PCIE_CRX_SSDTX_N12 E30 PCIE11_TXP/SATA1B_TXP H2
F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 SATA_LED# 1 2
[48] PCIE_CRX_SSDTX_P12 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1
[48] PCIE_CTX_SSDRX_N12 A25 G4 RC69 10K_0402_5%
B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 M2_SLOT2_PEDET [48] SIO_EXT_SCI# 1 2
[48] PCIE_CTX_SSDRX_P12 PCIE12_TXP/SATA2_TXP
B H1 SATA_LED# RC70 10K_0402_5% B
GPP_E8/SATALED# SATA_LED# [29]
SKL-U_BGA1356 8 OF 20
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MCP(5/14)PCIE,USB,SATA
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 10 of 61
5 4 3 2 1
5 4 3 2 1
CC6
1 2
15P_0402_50V8J
2
1M_0402_1%
3
4
RC80
UC1J SKL_ULT
YC1
CLOCK SIGNALS 24MHZ_12PF_X3G024000DC1H
1
2
D42 SUSCLK 1 2
[40] CLK_PEG_VGA C42 CLKOUT_PCIE_N0 XTAL24_IN
RC110 1K_0402_5% CC7
[40] CLK_PEG_VGA# AR10 CLKOUT_PCIE_P0 XTAL24_OUT 1 2
GPU---> [41] PEG_CLKREQ#
RC71 1 2 10K_0402_5% GPP_B5/SRCCLKREQ0#
+3VS
B42 15P_0402_50V8J
D [32] CLK_PCIE_WLAN_N1 A42 CLKOUT_PCIE_N1 F43 CLK_ITPXDP_N D
TP8
[32] CLK_PCIE_WLAN_P1 AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 CLK_ITPXDP_P
WLAN---> TP9 RC189 2 @ 1 0_0402_5% Change CC6, CC7 for YV1 frequency deviation
[32] CLK_PCIE_WLAN_REQ# 1 2 10K_0402_5% GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P SUSCLK_SSD [48] Eason 2/19
+3VS RC72
D41 BA17 SUSCLK RC74 2 @ 1 0_0402_5%
[34] CLK_PCIE_LAN_N2 C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK_WLAN [32]
[34] CLK_PCIE_LAN_P2 AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN
LAN---> RC75 2 1 0_0402_5%
[34] CLK_PCIE_LAN_REQ# 1 2 10K_0402_5% GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT SUSCLK_EC [25]
+3VS RC73
D40 XTAL24_OUT
[48] CLK_PCIE_SSD_N3 C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF 1 2
[48] CLK_PCIE_SSD_P3 AT10 CLKOUT_PCIE_P3 XCLK_BIASREF RC76 2.71K_0402_1%
+1.0V_CLK5 Follow KBL WW18 MOW
SSD---> [48] CLK_PCIE_SSD_REQ#
RC188 1 2 10K_0402_5% GPP_B8/SRCCLKREQ3# AM18 PCH_RTCX1 RC76 change to 2.71K
+3VS RTCX1 PCH_RTCX2
B40 AM20
A40 CLKOUT_PCIE_N4 RTCX2
AU8 CLKOUT_PCIE_P4 AN18 SRTCRST# RC77 1 2 20K_0402_5%
GPP_B9/SRCCLKREQ4# SRTCRST# +RTC_CELL
AM16 TPS7
E40 RTCRST# CC4 1 2 1U_0402_6.3V6K CC8
E38 CLKOUT_PCIE_N5 PCH_RTCX1 1 2
AU7 CLKOUT_PCIE_P5 PCH_RTCX2
1
CC5 1 2 1U_0402_6.3V6K YC2
RC108 1 @ 2 0_0402_5% RC82 32.768KHZ_9PF_X1A000141000200
SKL-U_BGA1356 10 OF 20 10M_0402_5% 20ppm / 9pF
+3VS ESR <50kohm (MAX)
2
1 2
1
1 2 CC9
[25] RTCRST_ON
5
2 @ 1 PCH_RTCX2_R 1 2
1
PCH_PLTRST# 1 RC83 0_0402_5%
P
2
4 RC164 6.8P_0402_50V8C
O PCH_PLTRST#_EC [25,32,34,40,48]
G
2 10K_0402_5% JCMOS1 JP@
IN2
G
UC4 JCMOS1 must take care short & touch risk on layout placement
SN74AHC1G08DCKR_SC70-5 RC109 3 1
3
2
C C
D
100K_0402_5%
JCMOS1
Always Open
2
QC2
2N7002K_SOT23-3 & Not Solder
+RTC_CELL Buffer with Open Drain Output For VTT power control
+3.3V_ALW_DSW +3VALW
+3VALW
2 1 H_CPUPWRGD INTRUDER# 1 2 CC12
CC15 100P_0402_50V8J 1 2 LAN_WAKE# SIO_SLP_LAN# 1 @ 2 RC91 330K_0402_5% DZ4 @ 0.1U_0402_16V7K 2 1
RC85 10K_0402_5% RC88 10K_0402_5% 1 2
@ESD@ +3VALW UC6
+3VS +3.3V_ALW_DSW RB751S40T1G_SOD523-2 1 5
8/21 can change to 10K for merge to RP NC VCC
Close to CPU side 1 2 SYS_RESET# VRALERT# 1 2 SIO_SLP_S3# 1 RC103 2 2
RC86 10K_0402_5% PCH_BATLOW# 1 2 RC92 10K_0402_5% 10K_0402_1% A 4 ALL_SYS_PWRGD
Y
1
RC89 8.2K_0402_5% CC14 3
2 @ 1 PCH_DPWROK AC_PRESENT 1 2 +3.3V_ALW_DSW @ RC192 GND
RC87 100K_0402_5% RC90 10K_0402_5% 1M_0402_1% 74AUP1G07GW_TSSOP5
2
+3VALW_PCH SIO_PWRBTN# 2 @ 1 1U_0402_6.3V6K
RC93 100K_0402_5%
2
1 @ 2 ME_SUS_PWR_ACK UC1K SKL-U
RC84 10K_0402_5%
SYSTEM POWER MANAGEMENT
AT11 SIO_SLP_S0# Buffer with Open Drain Output For VTT power control
GPP_B12/SLP_S0# AP15 SIO_SLP_S3# SIO_SLP_S0# [17]
PCH_PLTRST# AN10 GPD4/SLP_S3# BA16 SIO_SLP_S4# SIO_SLP_S3# [17,25,36] +3VALW +1.0V_VCCST
TPS1
[14] PCH_RSMRST#_Q SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 SIO_SLP_S5# SIO_SLP_S4# [17,25,53,55]
B 1 2 10K_0402_5% PCH_RSMRST#_Q AY17 SYS_RESET# GPD10/SLP_S5# SIO_SLP_S5# [51] 0.1U_0402_16V7K 2 1 CC13 B
RC94
RSMRST#
2
AN15 SIO_SLP_SUS# TP75
TP7 H_CPUPWRGD_R RC95 1 @ 2 1K_0402_5% H_CPUPWRGD A68 SLP_SUS# AW15 SIO_SLP_LAN# TP10 UC7 RC104
H_VCCST_PWRGD RC96 1 2 60.4_0402_1% VCCST_PWRGD B65 PROCPWRGD SLP_LAN# BB17 SIO_SLP_WLAN# TP11 1 5
VCCST_PWRGD GPD9/SLP_WLAN# NC VCC 1K_0402_5%
AN16 SIO_SLP_A# TPS6
B6 GPD6/SLP_A# ALL_SYS_PWRGD 2
[25] SYS_PWROK
1
BA20 SYS_PWROK BA15 A 4 H_VCCST_PWRGD
PCH_RSMRST#_Q 1 [25]
2 RESET_OUT# PCH_DPWROK BB20 PCH_PWROK GPD3/PWRBTN# AY15 AC_PRESENT SIO_PWRBTN# [25] 2 1 3 Y
@
DSW_PWROK GPD1/ACPRESENT AU13 PCH_BATLOW# ACAV_IN [25,50,51] GND
RC97 0_0402_5% RB751S40T1G_SOD523-2 DZ1
AR13 GPD0/BATLOW# 74AUP1G07GW_TSSOP5
[25] ME_SUS_PWR_ACK AP11 GPP_A13/SUSWARN#/SUSPWRDNACK
GPP_A15/SUSACK# AU11 PME# TP12
RC99 1 @ 2 0_0402_5% PCH_PCIE_WAKE# BB15 GPP_A11/PME# AP16 INTRUDER#
[25,34,48] PCIE_WAKE# 1 2 0_0402_5% LAN_WAKE# AM15 WAKE# INTRUDER#
RC100 @
[25] EC_WAKE# AW17 GPD2/LAN_WAKE# AM10 MPHYP_PWR_EN TP13
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 VRALERT# +3VS
GPD7/RSVD GPP_B2/VRALERT#
1
SKL-U_BGA1356 11 OF 20
RC105
10K_0402_5%
SIO_SLP_S0# TPS2
2
SIO_SLP_S3# TPS3 1.2V_VTT_PWRGD 1 @ 2 ALL_SYS_PWRGD
SIO_SLP_S4# [53] 1.2V_VTT_PWRGD ALL_SYS_PWRGD [25]
TPS4 RC106 0_0402_5%
SIO_SLP_S5# TPS5
1 @ 2
1M_0402_5%
0.1U_0402_10V7K
1
A A
5
CC10
RC102
1
P
[25] PCH_RSMRST#
2
IN1 4 PCH_RSMRST#_Q
2
POK 2 O
[50,52,54,55] POK IN2 DELL CONFIDENTIAL/PROPRIETARY
G
UC5
3
SN74AHC1G08DCKR_SC70-5
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MCP(6/14)CLK,PM,RTC
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 11 of 61
5 4 3 2 1
5 4 3 2 1
+1.0V_VCCST
1 @ 2 H_CATERR#
RC111 49.9_0402_1%
1 2 H_THERMTRIP#
RC112 1K_0402_5%
+1.0V_VCCSTG
1
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
RC119
RC120
RC121
RC122
SKL-U_BGA1356 4 OF 20
2
C C
UC1G SKL-U
AUDIO
‧‧HIGH
RC126 1 2 1K_0402_5% BA21 HDA_SDO/I2S0_TXD
[25] ME_FWP_EC [23] HDA_SDIN0 HDA_SDI0/I2S0_RXD
AY21 AB11
LOW L ENABLE --LME lock, canLt update ME HDA_CODEC_RST# RC127 1 @ 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
L DISABLE --LME un-lock, can update ME TP74 J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
1P_0402_50V8
1 I2S1_SFRM GPP_G3/SD_DATA2
AW20 W11
CC89
HDA_CODEC_BITCLK @RF@ I2S1_TXD GPP_G4/SD_DATA3 W10
AK7 GPP_G5/SD_CD# W8
2 AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7 KB_LED_BL_DET [30]
1 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
EMI@ AK9
CC16 AK10 GPP_F2/I2S2_TXD BA9
B GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9 B
22P_0402_50V8J GPP_A16/SD_1P8_SEL
2
H5 AB7 SD_RCOMP RC130 1 2 200_0402_1%
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
Close to RC124 GPP_D20/DMIC_DATA0
D8 AF13
DGPU_PWROK C8 GPP_D17/DMIC_CLK1 GPP_F23
[59,60] DGPU_PWROK GPP_D18/DMIC_DATA1
AW5
[23] SPKR GPP_B14/SPKR
SKL-U_BGA1356 7 OF 20
+3VALW_PCH +3VALW_PCH
1 @ 2 SPKR 1 @ 2 HDA_SDOUT
RC128 8.2K_0402_5% RC129 4.7K_0402_5%
A
TOP SWAP STRAP Flash Descriptor Security override A
D D
SKL-U_BGA1356 19 OF 20
From WW48 MOW
Stuff 100k(RC138) for Cannonlake
Un-stuff 100k(RC138) for Skylake
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MCP(8/14)CFG,RSVD
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 13 of 61
5 4 3 2 1
5 4 3 2 1
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MCP(9/14)XDP
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 14 of 61
5 4 3 2 1
5 4 3 2 1
1
AM35 K38
100_0402_1%
AM37 VCC_AM35 VCC_K38 K40
AM38 VCC_AM37 VCC_K40 K42
RC150
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43
2
+VCC_CORE_G0 K32 E32 VCCSENSE
TP32 RSVD_K32 VCC_SENSE E33 VSSSENSE VCCSENSE[56]
+VCC_CORE_G1 AK32 VSS_SENSE VSSSENSE [56]
RSVD_AK32
1
B63 H_CPU_SVIDALRT#
100_0402_1%
TP33
AB62 VIDALERT# A63 VIDSCLK
P62 VCCOPC_AB62 VIDSCK D64 VIDSOUT VIDSCLK [56]
RC151
V62 VCCOPC_P62 VIDSOUT
VCCOPC_V62 G20
2
H63 VCCSTG_G20
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
VCC_EDRAM_SENSE AC63
TP34 VSS_EDRAM_SENSE AE63 VCCOPC_SENSE
TP35 VSSOPC_SENSE
+1.0V_VCCSTG
AE62
AG62 VCCEOPIO
VCCEOPIO
VCCEOPIO_SENSE AL63
TP36 VSSEOPIO_SENSE AJ62 VCCEOPIO_SENSE
TP37 VSSEOPIO_SENSE
C C
SKL-U_BGA1356 12 OF 20
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cache)
B B
+1.0V_VCCST
SVID ALERT
1
56_0402_1%
RC152
2 1 H_CPU_SVIDALRT#
[56] VIDALERT_N
RC153 220_0402_5%
+1.0V_VCCST
SVID DATA
100_0402_1%
1
VIDSOUT
[56] VIDSOUT
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MCP(10/14)PWR-VCC CORE
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 15 of 61
5 4 3 2 1
5 4 3 2 1
+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V
+VCC_GT +VCC_GT
UC1M SKL-U
D CPU POWER 2 OF 4 D
N70
A48 VCCGT N71
A53 VCCGT VCCGT R63
A58 VCCGT VCCGT R64
A62 VCCGT VCCGT R65
A66 VCCGT VCCGT R66
AA63 VCCGT VCCGT R67
AA64 VCCGT VCCGT R68
AA66 VCCGT VCCGT R69
AA67 VCCGT VCCGT R70
AA69 VCCGT VCCGT R71
AA70 VCCGT VCCGT T62
AA71 VCCGT VCCGT U65
AC64 VCCGT VCCGT U68
AC65 VCCGT VCCGT U71
AC66 VCCGT VCCGT W63
AC67 VCCGT VCCGT W64
AC68 VCCGT VCCGT W65
AC69 VCCGT VCCGT W66
AC70 VCCGT VCCGT W67
AC71 VCCGT VCCGT W68
J43 VCCGT VCCGT W69
J45 VCCGT VCCGT W70
J46 VCCGT VCCGT W71
J48 VCCGT VCCGT Y62
J50 VCCGT VCCGT +VCC_GT
J52 VCCGT
J53 VCCGT AK42
J55 VCCGT VCCGTX_AK42 AK43
J56 VCCGT VCCGTX_AK43 AK45
J58 VCCGT VCCGTX_AK45 AK46
C J60 VCCGT VCCGTX_AK46 AK48 C
K48 VCCGT VCCGTX_AK48 AK50
K50 VCCGT VCCGTX_AK50 AK52
K52 VCCGT VCCGTX_AK52 AK53
K53 VCCGT VCCGTX_AK53 AK55
K55 VCCGT VCCGTX_AK55 AK56
K56 VCCGT VCCGTX_AK56 AK58
K58 VCCGT VCCGTX_AK58 AK60
K60 VCCGT VCCGTX_AK60 AK70
L62 VCCGT VCCGTX_AK70 AL43
L63 VCCGT VCCGTX_AL43 AL46
L64 VCCGT VCCGTX_AL46 AL50
L65 VCCGT VCCGTX_AL50 AL53
VCCGTX for SKYLAKE-U 2+3e only
L66 VCCGT VCCGTX_AL53 AL56
L67 VCCGT VCCGTX_AL56 AL60
L68 VCCGT VCCGTX_AL60 AM48
+VCC_GT L69 VCCGT VCCGTX_AM48 AM50 +VCC_GT
L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
VCCGT VCCGTX_AM56
1
1
N63 AM58
100_0402_1%
RC157
N67 VCCGT VCCGTX_AU63 BB57 100_0402_1%
N69 VCCGT VCCGTX_BB57 BB66
2
2
VCCGT VCCGTX_BB66
VCC_GT_SENSE J70 AK62 VCCSENSE_VCCGTUS
[56] VCC_GT_SENSE VSS_GT_SENSE J69 VCCGT_SENSE VCCGTX_SENSE AL61 VSSSENSE_VCCGTUS
[56] VSS_GT_SENSE VSSGT_SENSE VSSGTX_SENSE
1
1
100_0402_1%
SKL-U_BGA1356 13 OF 20
GT3@
B B
RC156
RC158
100_0402_1%
2
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MCP(11/14)PWR-VCCGT
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 16 of 61
5 4 3 2 1
5 4 3 2 1
+1.0VS_VCCIO
+1.2V_DDR
Annotation:
BSC BSC
1.35V in DDR3L
BSC PSC
D
1.2V in LPDDR3 and DDR4 D
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1
CC49
CC50
1 1 1 1 1 1
@ CC26
@ CC27
CC28
CC29
CC30
CC31
CC45
CC46
CC47
CC48
2 2 2 2 2 2
2 2 2 2 2 2 +1.0VS_VCCIO
UC1N SKL-U
CPU POWER 3 OF 4
AU23 AK28
BSC PSC AU28 VDDQ_AU23 VCCIO AK30
AU35 VDDQ_AU28 VCCIO AL30
PSC
AU42 VDDQ_AU35 VCCIO AL42
BB23 VDDQ_AU42 VCCIO AM28
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 VDDQ_BB23 VCCIO
BB32 AM30
BB41 VDDQ_BB32 VCCIO AM42 +VCC_SA
@ CC32
CC33
@ CC34
@ CC35
CC36
CC37
CC38
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDDQ_BB41 VCCIO 1 1 1 1
BB47
2 2 2 2 2 2 2 BB51 VDDQ_BB47 AK23
CC51
CC52
CC53
CC54
VDDQ_BB51 VCCSA
@
AK25
VCCSA G23 2 2 2 2
PSC BSC AM40 VCCSA G25
VDDQC VCCSA G27
A18 VCCSA G28
10U_0402_6.3V6M
1U_0402_6.3V6K
VCCST VCCSA J22
1 1 VCCSA
A22 J23
CC39
CC40
1
H21
VSSSA_SENSE H20
CC41
BSC VCCSA_SENSE
100_0402_1%
2
RC160
SKL-U_BGA1356 14 OF 20
+1.2V_DDR 1 2
1U_0402_6.3V6K
1 +VCC_SA
CC42
RC159 100_0402_1%
2
+1.0V_VCCST
2 PSC JP1
Always Short
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CC43
JP1 PJP@
2 1 2
2 1 2
JUMP_43X79 1
CZ8
0.1U_0402_25V6
@
Imax : 3.4 A 2
POP option with Volume
B B
1U_0402_6.3V6K
0.1U_0402_10V7K
@
1 RZ1 2 EN_1.0V_VCCST_ON 3 6 1 4 5
[11,25,53,55] SIO_SLP_S4# ON CT ON GND
CZ4
CZ5
22.1K_0402_1% RZ2
1 0_0402_5%
1
CZ1 4 1 @ 2 2 TPS22961DNYR_WSON8
+5VALW VBIAS 2
@ RZ9 5 CZ3
GND +3VALW 4.4mohm/6A
0.1U_0402_10V7K
0.1U_0402_10V7K
1M_0402_1% 1 9 470P_0402_50V7K
TR=12.5us@Vin=1.05V
2
2 GND
CZ22
2
5
TPS22967DSGR_SON8_2X2
2 1 +1.0V_VCCSTG +1.0V_VCCST
P
[11,25,36] SIO_SLP_S3# IN1 4 VCCSTG_EN 1 2 VCCSTG_EN_R
2 O RZ3 49.9K_0402_1% 1 @ 2
[11] SIO_SLP_S0# IN2 1
G
RZ4 0_0603_5%
UC9 1 2 CZ7
3
SN74AHC1G08DCKR_SC70-5 0.1U_0402_10V7K
DZ2 2 pop option with UZ1
A RB751S40T1G_SOD523-2 A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MCP(12/14)PWR-VCCIO,MEM
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D805P
Date: Tuesday, June 21, 2016 Sheet 17 of 61
5 4 3 2 1
5 4 3 2 1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 close UC1.AG15 and <120mil
+3VALW_PCH +3VALW_PCH
@ CC57
@ CC58
+1.0V_APLLEBB
CC55
CC56
@
1U_0402_6.3V6K
1
SKL-U
@ CC64
UC1O close UC1.T16 and <400mil
+1.0V_MPHYGT source 2 2 2 2
1P_0402_50V8
1U_0402_6.3V6K
CPU POWER 4 OF 4 1 1
2 1 0_0603_5%
CC65
@ CC66
RC162 @
D AB19 2 D
AB20 VCCPRIM_1P0 AK15
VCCPRIM_1P0 VCCPGPPA +3VALW_PCH 2 2
P18 AG15
+1.0V_PRIM +1.0V_MPHYGT VCCPRIM_1P0 VCCPGPPB Y16
close UC1.AF18 and <400mil VCCPGPPC
AF18 Y15
VCCPRIM_CORE VCCPGPPD +3VALW_PCH
RC174 2 @ 1 0_0603_5% AF19 T16
V20 VCCPRIM_CORE VCCPGPPE AF16
VCCPRIM_CORE VCCPGPPF +1.8V_PRIM +3VALW_PCH
V21 AD15
VCCPRIM_CORE VCCPGPPG +3VALW_PCH
Imax : 2.8 A AL1 V19
DCPDSW_1P0 VCCPRIM_3P3_V19
close UC1.V19 and <120mil
K17 T1 +1.8V_PRIM
1U_0402_6.3V6K
VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_PRIM 1
L1
@ CC67
VCCMPHYAON_1P0 AA1
VCCATS_1P8 close UC1.AA1 and <400mil
+1.0V_MPHYGT N15
N16 VCCMPHYGT_1P0_N15 AK17 +RTC_CELL 2
1U_0402_6.3V6K
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3VALW_PCH 1
close UC1.N15 and CC210 <400mil, CC211 <120mil N17
P15 VCCMPHYGT_1P0_N17 AK19
CC68
P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14 close UC1.AK19 and <120mil 2
47U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
1 1 1 1
K15 BB10
@ CC59
+1.0V_AMPHYPLL VCCAMPHYPLL_1P0 DCPRTC
L15
CC60
CC70
CC71
VCCAMPHYPLL_1P0 close UC1.BB10 and <120mil
A14
0.1U_0402_10V7K
2 2 VCCCLK1 +1.0V_PRIM 1 2 2
V15
+1.0V_APLL VCCAPLL_1P0 K19
CC69
VCCCLK2 +1.0V_CLK2
AB17
+1.0V_PRIM VCCPRIM_1P0_AB17 2
Y18 L21
VCCPRIM_1P0_Y18 VCCCLK3
AD17 N20
+3.3V_ALW_DSW VCCDSW_3P3_AD17 VCCCLK4 +1.0V_CLK4
AD18
AJ17 VCCDSW_3P3_AD18 L19 +1.0V_PRIM
VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5
C AJ19 A10 C
+1.0V_SRAM +3.3V_HDA VCCHDA VCCCLK6
close UC1.A10 and <120mil
AJ16 AN11
1U_0402_6.3V6K
+3.3V_SPI VCCSPI GPP_B0/CORE_VID0 1
AN13
@ CC72
AF20 GPP_B1/CORE_VID1
close UC1.AF20 and <400mil VCCSRAM_1P0
AF21
+3VALW_PCH T19 VCCSRAM_1P0 2
1U_0402_6.3V6K
1 VCCSRAM_1P0
T20
@ CC62
+1.0V_PRIM VCCSRAM_1P0
AJ21
2 +1.0V_APLLEBB VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB
close UC1.N18 and <120mil
1U_0402_6.3V6K
1
SKL-U_BGA1356 15 OF 20
CC63
47U_0805_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
close UC1.L19 and <100mil
0.1U_0402_10V7K
0.1U_0402_10V7K
1 RF@ 1 1 1 1 1 1 1
CC76 @
CC77 @
CC61
B B
@ CC74
CC78
@ CC73
@ CC75
CC79
RF@
2 2 2 2
close UC1.K19 and <100mil 2 2 2 2
+1.0V_PRIM +1.0V_APLL
+3VALW +3.3V_ALW_DSW close UC1.V15 and <100mil +1.0V_PRIM +1.0V_CLK4
L1
RC163 2 @ 1 0_0603_5% 1 2
BLM15BD601SN1D_2P RC173 2 @ 1 0_0603_5%
8.2P_0402_50V8D
0.1U_0603_25V7K
1 1
22U_0603_6.3V6M
@ CC80
22U_0603_6.3V6M
@ CC81
CC82
CC83
47U_0603_6.3V6M
RF@ @
2 2
2 2 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1
A A
CC85
CC86
CC87
2 2 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MCP(13/14)PCH PWR
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 18 of 61
5 4 3 2 1
5 4 3 2 1
SKL-U_BGA1356 16 OF 20 SKL-U_BGA1356 17 OF 20
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MCP(14/14)VSS
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 19 of 61
5 4 3 2 1
5 4 3 2 1
[7] DDR_A_D[0..63]
[7] DDR_A_MA[0..13]
[7] DDR_A_DQS#[0..7]
[7] DDR_A_DQS[0..7] +1.2V_DDR JDIMM1 CONN@
Layout Note: Layout Note: +1.2V_DDR
1 2
Place near JDIMM1.257,259 Place near JDIMM1.258 DDR_A_D1 3 VSS1 VSS2 4 DDR_A_D0
5 DQ5 DQ4 6
DDR_A_D5 7 VSS3 VSS4 8 DDR_A_D4
9 DQ1 DQ0 10
DDR_A_DQS#0 11 VSS5 VSS6 12
DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
+2.5V_MEM +0.6V_DDR_VTT 15 DQS0_t VSS7 16 DDR_A_D6
DDR_A_D7 17 VSS8 DQ6 18
Layout Note: DQ7 VSS9 DDR_A_D2
19 20
Place near JDIMM1.255 DDR_A_D3 21 VSS10 DQ2 22
DQ3 VSS11
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
D 23 24 DDR_A_D12 D
VSS12 DQ12
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
DDR_A_D9 25 26
1U_0402_6.3V6K~D DQ13 VSS13
1U_0402_6.3V6K~D
1 1 1 1 27 28 DDR_A_D13
VSS14 DQ8
CD5
CD6
CD7
CD8
1 1 1 1 DDR_A_D8 29 30
DQ9 VSS15
CD3
CD4
31 32 DDR_A_DQS#1
VSS16 DQS1_c
CD1
CD2
33 34 DDR_A_DQS1
2 2 2 2 +3VS 35 DM1_n/DBI_n DQS1_t 36
2 2 2 2 DDR_A_D10 37 VSS17 VSS18 38 DDR_A_D15
39 DQ15 DQ14 40
DDR_A_D11 41 VSS19 VSS20 42 DDR_A_D14
43 DQ10 DQ11 44
VSS21 VSS22
0.1U_0402_16V7K~D
2.2U_0603_6.3V6K~D
DDR_A_D16 45 46 DDR_A_D21
47 DQ21 DQ20 48
1 1 VSS23 VSS24
CD9
CD10
DDR_A_D17 49 50 DDR_A_D20
51 DQ17 DQ16 52
DDR_A_DQS#2 53 VSS25 VSS26 54
2 2 DDR_A_DQS2 55 DQS2_c DM2_n/DBI2_n 56
57 DQS2_t VSS27 58 DDR_A_D19
DDR_A_D22 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_A_D23
DDR_A_D18 63 VSS30 DQ18 64
Layout Note: DQ19 VSS31 DDR_A_D28
65 66
Place near JDIMM1 DDR_A_D24 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_A_D25
DDR_A_D29 71 VSS34 DQ24 72
73 DQ25 VSS35 74 DDR_A_DQS#3
75 VSS36 DQS3_c 76 DDR_A_DQS3
+1.2V_DDR 77 DM3_n/DBI3_n DQS3_t 78
DDR_A_D26 79 VSS37 VSS38 80 DDR_A_D31
81 DQ30 DQ31 82
DDR_A_D30 83 VSS39 VSS40 84 DDR_A_D27
DQ26 DQ27
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
85 86
87 VSS41 VSS42 88
1 1 1 1 1 1 1 1 CB5/NC CB4/NC
CD11
CD12
CD13
CD14
CD15
CD16
CD17
CD18
89 90
91 VSS43 VSS44 92
93 CB1/NC CB0/NC 94
2 2 2 2 2 2 2 2 95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
C 103 CB2/NC VSS49 104 C
105 VSS50 CB7/NC 106
107 CB3/NC VSS51 108 DDR4_DRAMRST#
VSS52 RESET_n DDR4_DRAMRST# [21]
DDR_A_CKE0 109 110 DDR_A_CKE1
[7] DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 [7]
111 112
+1.2V_DDR DDR_A_BG1 113 VDD1 VDD2 114
[7] DDR_A_BG1 BG1 ACT_n DDR_A_ACT# [7]
DDR_A_BG0 115 116 DDR_A_ALERT#
[7] DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# [7]
117 118
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
A9 A7
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
123 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
1 A8 A5
1 1 1 1 1 1 1 1 @ DDR_A_MA6 127 128 DDR_A_MA4
+ CD27 129 A6 A4 130
VDD7 VDD8
CD19
CD20
CD21
CD22
CD23
CD24
CD25
CD26
0.1U_0402_16V7K~D
DDR_A_D36 169 170 DDR_A_D33
171 DQ37 DQ36 172
VSS55 VSS56 1
CD28
DDR_A_D37 173 174 DDR_A_D32
175 DQ33 DQ32 176
+1.2V_DDR DDR_A_DQS#4 177 VSS57 VSS58 178
DDR_A_DQS4 179 DQS4_c DM4_n/DBI4_n 180
+1.2V_DDR 2
181 DQS4_t VSS59 182 DDR_A_D38
B +3VS +3VS +3VS DDR_A_D39 183 VSS60 DQ39 184 B
185 DQ38 VSS61 186 DDR_A_D35
DDR_A_D34 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D45
VSS64 DQ45
1
A A
CD30 RD12
0.022U_0402_25V7K 1K_0402_1%~D
2
1
RD11
24.9_0402_1% DEREN_40-42271-26001RHF
DEREN_40-42271-26001RHF
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 DIMMA_RVS
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 20 of 61
5 4 3 2 1
5 4 3 2 1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
Layout Note: 33 34 DDR_B_DQS0
35 DM1_n/DBI_n DQS1_t 36
1 1 1 1 1 1 1 1 Place near JDIMM2.255 VSS17 VSS18
CD31
CD32
CD35
CD36
DDR_B_D7 37 38 DDR_B_D3
DQ15 DQ14
CD33
CD34
CD37
CD38
39 40
DDR_B_D6 41 VSS19 VSS20 42 DDR_B_D2
2 2 2 2 2 2 2 2 43 DQ10 DQ11 44
DDR_B_D16 45 VSS21 VSS22 46 DDR_B_D21
47 DQ21 DQ20 48
DDR_B_D17 49 VSS23 VSS24 50 DDR_B_D20
+3VS 51 DQ17 DQ16 52
DDR_B_DQS#2 53 VSS25 VSS26 54
DDR_B_DQS2 55 DQS2_c DM2_n/DBI2_n 56
57 DQS2_t VSS27 58 DDR_B_D23
DDR_B_D19 59 VSS28 DQ22 60
DQ23 VSS29
0.1U_0402_16V7K~D
2.2U_0603_6.3V6K~D
61 62 DDR_B_D18
DDR_B_D22 63 VSS30 DQ18 64
1 1 DQ19 VSS31
CD39
CD40
65 66 DDR_B_D25
DDR_B_D29 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_B_D28
2 2 DDR_B_D24 71 VSS34 DQ24 72
73 DQ25 VSS35 74 DDR_B_DQS#3
75 VSS36 DQS3_c 76 DDR_B_DQS3
Layout Note: DM3_n/DBI3_n DQS3_t
77 78
Place near JDIMM2 DDR_B_D26 79 VSS37 VSS38 80 DDR_B_D31
81 DQ30 DQ31 82
DDR_B_D30 83 VSS39 VSS40 84 DDR_B_D27
85 DQ26 DQ27 86
87 VSS41 VSS42 88
89 CB5/NC CB4/NC 90
91 VSS43 VSS44 92
93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
+1.2V_DDR 97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
103 CB2/NC VSS49 104
VSS50 CB7/NC
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
105 106
C 107 CB3/NC VSS51 108 DDR4_DRAMRST# C
1 1 1 1 1 1 1 1 VSS52 RESET_n DDR4_DRAMRST# [20]
CD41
CD42
CD43
CD44
CD45
CD46
CD47
CD48
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
141 142
DDR_B_PAR 143 VDD11 VDD12 144 DDR_B_MA0
1 [7] DDR_B_PAR PARITY A0
1 1 1 1 1 1 1 1 DDR_B_BS1 145 146 DDR_B_MA10
+ [7] DDR_B_BS1 BA1 A10/AP
CD57 147 148
VDD13 VDD14
CD49
CD50
CD51
CD52
CD53
CD54
CD55
CD56
0.1U_0402_16V7K~D
DDR_B_D33 173 174 DDR_B_D37
175 DQ33 DQ32 176
VSS57 VSS58 1
CD58
DDR_B_DQS#4 177 178
DDR_B_DQS4 179 DQS4_c DM4_n/DBI4_n 180
+1.2V_DDR
181 DQS4_t VSS59 182 DDR_B_D39
DDR_B_D34 183 VSS60 DQ39 184 2
185 DQ38 VSS61 186 DDR_B_D38
B DDR_B_D35 187 VSS62 DQ35 188 B
189 DQ34 VSS63 190 DDR_B_D40
DDR_B_D44 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_B_D41
DDR_B_D45 195 VSS66 DQ41 196
197 DQ40 VSS67 198 DDR_B_DQS#5
199 VSS68 DQS5_c 200 DDR_B_DQS5
+3VS +3VS +3VS +1.2V_DDR 201 DM5_n/DBI5_n DQS5_t 202
DDR_B_D43 203 VSS69 VSS70 204 DDR_B_D46
205 DQ46 DQ47 206
DDR_B_D42 207 VSS71 VSS72 208 DDR_B_D47
209 DQ42 DQ43 210
VSS73 VSS74
1
A A
RD19 1 2 2_0402_1% +V_DDR_REFB
1
1 DEREN_40-42261-26001RHF
RD21 DEREN_40-42261-26001RHF
CD59 1K_0402_1%~D
0.022U_0402_25V7K
2
2
1
RD22
24.9_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/01/30 Deciphered Date 2016/12/31 Title
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 DIMMB_STD
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 21 of 61
5 4 3 2 1
5 4 3 2 1
0.1U_0402_25V6
1000P_0402_50V7K
0.1U_0402_25V6
1000P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
1000P_0402_50V7K
1000P_0402_50V7K
EC2201 @EMI@
EC2202 @EMI@
EC2203 @EMI@
EC2204 @EMI@
EC2205 @EMI@
EC2206 @EMI@
EC2207 @EMI@
EC2208 @EMI@
H1 H2 H3 H4 H5 H6 H7
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA 2 2 2 2 2 2 2 2
D D
1
1
H_3P0-G H_3P0-G H_3P0-G H_3P0-G H_3P0-G H_5P6N H_3P0N
1 1 1 1 1 1
1000P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
H8 H9 H10 H11 H12 H13
EC2209 @EMI@
EC2210 @EMI@
EC2211 @EMI@
EC2212 @EMI@
EC2213 @EMI@
EC2214 @EMI@
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
2 2 2 2 2 2
1
1
H_3P5 H_3P5 H_3P5 H_3P2 H_3P2X2P6 H_6P0
1 1 1 1 1 1 1 1
1U_0402_10V6K
1U_0402_10V6K
0.1U_0402_25V6
0.1U_0402_25V6
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1
EC2215 @EMI@
EC2216 @EMI@
EC2222 @EMI@
EC2223 @EMI@
EC2225 @EMI@
EC2226 @EMI@
EC2229 @EMI@
EC2230 @EMI@
C 2 2 2 2 2 2 2 2 C
H_3P7X4P3 H_3P9 H_3P7 H_3P7X4P3
D1 RB551V-30_SOD323-2
R1 2
JRTC1 CONN@ 1K_0402_5% anode 1
1 2 1 RTC_PWR 3 cathode
1 2 anode
2 1
3 BAS40C_SOT23-3 C1 @
GND 4 0.47U_0402_6.3V6K
GND 2
ACES_50271-0020N-001
SP02000RO00
1
R2
2
10M_0402_5%
G
2
3 1 RTC_DET# [9]
S
Q1
2N7002K_SOT23-3
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTC/Screw hole/EMI cap
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 22 of 61
5 4 3 2 1
5 4 3 2 1
S
2A RA4 0_0603_5%
1 1 1
2 @ 1 CA10 CA11
G
2
RA1 0_0805_5% RA42 1 2 33_0402_5% DMIC_DATA CA12
[28] DMIC_DATA_EDP 4.7U_0603_6.3V6K
4.7U_0603_10V6K
CA1 1 CA2 CA3 1 CA4 Place close to Pin 26 +3VS
1
2 2 2
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
EMI@
10U_0603_10V6M
10U_0603_10V6M
L5 1 2 BLM15PX221SN1D_2P DMIC_CLK Close pin40
D [28] DMIC_CLK_EDP D
2
2 2 AUD_AGND
1
@EMI@
CA9 +1.8V_CPVDD
6.8P_0402_50V
2 AUD_AGND
RA6 1 @ 2 0_0402_5%
Layout Note: Layout Note:
Close pin41 Close pin46 1 CA13 1 CA14
.1U_0402_16V7K
4.7U_0603_6.3V6K
2 2
+5V_PVDD
1 1 +3V_DVDD +3V_DVDD
CA5 CA6
+5V_AVDD
2 2 1 1
4.7U_0603_6.3V6K
+1.8V_AVDD
.1U_0402_16V7K
4.7U_0603_6.3V6K
2 2
+1.8V_CPVDD
41
46
26
40
36
1
9
UA1
DVDD
CPVDD
DVDD-IO
PVDD1
PVDD2
AVDD1
AVDD2
11
Delete HDA_RST 12 I2C_SDA 31
C +LINE1_VREFO_L C
I2C_SCL LINE1-VREFO-L 30
LINE1-VREFO-R +LINE1_VREFO_R
10 29
[12] HDA_CODEC_SYNC SYNC MIC2-VREFO +MIC2-VREFO
6 28 AUD_VREFCA23 1 2 2.2U_0603_6.3V6K
[12] HDA_CODEC_BITCLK 5 BIT-CLK VREF 35 CBN 1 2
AUD_AGND moat +3VALW +RTC_CELL
[12] HDA_CODEC_SDOUT 1 2 HDA_CODEC_SDIN0 8 SDATA-OUT CBN 37 CBP CA24 1U_0603_16V7
[12] HDA_SDIN0 RA7 33_0402_5% SDATA-IN CBP RA11 1 @ 2 0_0402_5%
RA9 2 @ 1 0_0402_5% 4 20 V3D3_STB RA12 1 2 0_0402_5%
RA8 1 @ 2 100K_0402_5% DMIC_DATA 2 EAPD/DC DET 5VSTB
+3V_DVDD GPIO0/DMIC-DATA12
DMIC_CLK 3 34 CPVEE CA25 2 1 1U_0603_16V7
47 GPIO1/DMIC-CLK CPVEE
[25] EC_MUTE# 48 PDB
RA41 1 2 100K_0402_5% SPDIFO/GPIO2/DMIC-DATA-34/DMIC-CLK-In/MIC-GPI
CA20 1 2 4.7U_0603_6.3V6K LDO1_CAP 27
AUD_AGND
CA21 1 2 10U_0603_6.3V6M LDO2_CAP 39 LDO1-CAP 17 RING2 [24] Layout Note:
CA22 1 2 4.7U_0603_6.3V6K LDO3_CAP 7 LDO2-CAP MIC2-L/RING2 18 SLEEVE [24]
LDO3-CAP MIC2-R/SLEEVE Width>40mil, to improve Headpohone Crosstalk noise
19 MIC_CAP 1 2
MIC-CAP AUD_AGND Change it to sharp will be better.
24 CA26 10U_0603_6.3V6M
AUD_SPK_L+ 42 LINE2-L 23 Add 2 vias (>0.5A) when trace layer change.
Layout Note: [23] AUD_SPK_L+ AUD_SPK_L- 43 SPK-L+ LINE2-R 22
[23] AUD_SPK_L- AUD_SPK_R- 44 SPK-L- LINE1-L 21 LINE1_L [24]
Speaker trace width >40mil @ 2W4ohm speaker power [23] AUD_SPK_R- SPK-R- LINE1-R LINE1_R [24]
AUD_SPK_R+ 45 16 AUD_PC_BEEP
[23] AUD_SPK_R+ SPK-R+ PCBEEP 32
AUD_SENSE_A 13 HP-OUT-L 33 AUD_HP1_JACK_L [24]
HP/LINE1 JD1 HP-OUT-R AUD_HP1_JACK_R [24]
14
RA3 2 1 100K_0402_5% AUD_SENSE_A AUD_SENSE 1 RA10 2 15 MIC2/LINE2 JD2 25
+3V_DVDD SPDIFO/FRONT JD3/GPIO3 AVSS1 38
200K_0402_1% AVSS2 49
1 THERMAL PAD moat
@ CA7
moat .1U_0402_16V7K Layout Note: ALC3246-CG_MQFN48_6X6
2 Place close to Pin 13 RA17 2 @ 1 0_0402_5%
ALC3246-CG_MQFN48_6X6-S
AUD_AGND RA18 2 @ 1 0_0402_5%
AUD_AGND
B B
AUD_AGND
2 @ 1
1 1 RA22 0_0805_5%
0.1U_0402_25V6
0.1U_0402_25V6
EC2301 @EMI@
EC2302 @EMI@
2 2
Layout Note:
Speaker trace width >40mil @ 2W4ohm speaker power Speaker
CONN Pin Net name AUD_AGND Layout Note:
JSPK1 CONN@ Tied at point only under
RA13 1 EMI@ 2 BLM15PD800SN1D_2P AUD_SPK_R+_C 1 Pin1 SPK_R+
[23] AUD_SPK_R+ AUD_SPK_R-_C 1 Codec or near the Codec
RA14 1 EMI@ 2 BLM15PD800SN1D_2P 2
[23] AUD_SPK_R- RA15 1 EMI@ 2 BLM15PD800SN1D_2P AUD_SPK_L+_C 3 2
[23] AUD_SPK_L+ 3 Pin2 SPK_R-
RA16 1 EMI@ 2 BLM15PD800SN1D_2P AUD_SPK_L-_C 4
[23] AUD_SPK_L- 4
Pin3 SPK_L+ Place on the moat between GND & GNDA.
5
6 GND1
GND2 Pin4 SPK_L-
2
JXT_WB247H-004S10M
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
SP020017K10 DA3
1 1 1 1 3
[12] SPKR
EMI@ CA27
EMI@ CA28
EMI@ CA29
EMI@ CA30
1
@ESD@ @ESD@ AUD_SPK_L-_C BAT54C-7-F_SOT23-3
ZT7
1
RA24
10K_0402_5%
A A
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio Codec ALC3246
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 23 of 61
5 4 3 2 1
5 4 3 2 1
D D
Universal Jack
RA25 1 2 2.2K_0402_5%
+MIC2-VREFO
(Global Headset Jack + mic phone in + line in support)
RA26 1 2 2.2K_0402_5%
[23] SLEEVE
Layout Note:
Close to UA1
C C
JACK_PLUG ZT20
5
[23] JACK_PLUG 5
JACK_PLUG_DET 6
B ZT21 6 B
HPOUT_R 2
ZT22 R/L
RING2_R 4
ZT23 M/G
7
CLOSE TO JHP1 GND
1
10K_0402_5%
RA34
10K_0402_5%
RA30
HPOUT_R YUQIU_PJ753-F07J1BE-B
HPOUT_L 1 1 1 1 DC021512140
100P_0402_50V8J
CA34 ESD@
100P_0402_50V8J
CA35 ESD@
100P_0402_50V8J
CA36 ESD@
100P_0402_50V8J
CA37 ESD@
@ @
ZT64
SLEEVE_R JACK_PLUG_DET
2
RING2_R 10 mils 2 2 2 2
AUD_AGND
1
RA40
3
@ 0_0402_5%
L03ESDL5V0CC3-2_SOT23-3
DA4
AZ5123-02S.R7G_SOT23-3
DA5
2
ESD@
ESD@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio JACK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 24 of 61
5 4 3 2 1
5 4 3 2 1
RPE1 10K_8P4R_5%
+3VALW +3VALW_EC UE1 EC@ RE1 EC@ SD034100280 10K_0402_1% +3VALW_EC +3VALW_EC
+3VALW
5 4 KSI0 SD034137280 13.7K_0402_1%
6 3 KSI1 SD034178280 17.8K_0402_1% Model ID Board ID
EC Chip CPN
1
7 2 KSI2 2 @ 1 SD034221280 22.1K_0402_1%
8 1 KSI3 RE2 0_0603_5% SD034270280 27K_0402_1% RE3 RE1
10U_0603_6.3V6M
0.1U_0402_10V7K
1000P_0402_50V7K
@EMI@
1000P_0402_50V7K
@EMI@
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1 1 2 2 SD034324280 32.4K_0402_1% Ra 100K_0402_1% Ra 100K_0402_1%
1
RPE2 10K_8P4R_5% MEC1404-NU-D0_VTQFP128_14X14 49.9K_0402_1% SD034374280 37.4K_0402_1% DIS@ @
CE5
CE6
CE9
CE10
CE11
CE12
CE13
SD034499280 49.9K_0402_1%
2
5 4 KSI7 SD034576280 57.6K_0402_1% MODEL_ID BOARD_ID
SA000084410 SD034499280
2
6 3 KSI6 2 2 1 1 SD034649280 64.9K_0402_1%
CE7
CE8
7 2 KSI5 For SD00000B180 73.2K_0402_1% 1 1
2
0.1U_0402_10V7K
CE1
0.1U_0402_10V7K
CE2
8 1 KSI4 Board ID Select SD000002780 82.5K_0402_1%
SD034931280 93.1K_0402_1% Rb RE4 Rb
SD034107380 107K_0402_1% 100K_0402_1% RE6
1 8 KSO0 SD034120380 120K_0402_1% 2 UMA@ 2 100K_0402_1%
2 7 KSO1 EVT 10K SD034137380 137K_0402_1%
1
3 6 KSO2 +3VALW_EC DVT1 13.7K SD034154380 154K_0402_1%
D D
4 5 KSO3 DVT2 17.8K SD034200380 200K_0402_1%
2 @ 1 +RTC_CELL_VBAT Pilot 49.9K SD034232380 232K_0402_1%
RPE3 +RTC_CELL RE7 0_0603_5% 1
100K_8P4R_5% SD034100380 100K_0402_1% EC_AGND EC_AGND
1 8 KSO4 CE14
2 7 KSO5 0.1U_0402_10V7K
3 6 KSO6 2
122
103
4 5 KSO7 CE15
43
82
19
65
5
UE1 @
RPE4 54 1 2 +3VALW_EC
VTR
VTR
VTR
VTR
VTR
VTR
VBAT
100K_8P4R_5% VTR_33_18
1 8 KSO10 PECI_EC PBAT_CHG_SMBDAT 1 2
0.1U_0402_25V6 PECI_EC [12]
2 7 KSO11 KSO0 2 RE8 4.7K_0402_5%
GPIO027/KSO00/PVT_IO1
1
3 6 KSO12 KSO1 14 8 PBAT_CHG_SMBDAT PBAT_CHG_SMBCLK 1 2
GPIO015/KSO01/PVT_nCS GPIO007/SMB01_DATA/SMB01_DATA18 PBAT_CHG_SMBCLK PBAT_CHG_SMBDAT [50,51]
4 5 KSO13 KSO2 15 9 RE9 4.7K_0402_5%
GPIO016/KSO02/PVT_SCLK GPIO010/SMB01_CLK/SMB01_CLK18 PBAT_CHG_SMBCLK [50,51]
KSO3 16 11 SML1DATA 1 @ 2
GPIO017/KSO03/PVT_IO0 GPIO012/SMB02_DATA/SMB02_DATA18 SML1DATA [8,30,41] SML1DATA => GPU_THM_SMBDAT
RPE5 KSO4 37 12 DE1 RE10 2.2K_0402_5%
GPIO045/BCM_nINT1/KSO04 GPIO013/SMB02_CLK/SMB02_CLK18 SML1CLK [8,30,41] SML1CLK => GPU_THM_SMBCLK
100K_8P4R_5% KSO5 38 89 AZ5125-01H.R7G_SOD523-2 SML1CLK 1 @ 2
GPIO046/BCM_DAT1/KSO05 GPIO130/SMB03_DATA/SMB03_DATA18 SYS_PWROK [11]
1 8 KSO8 [30] KSI[0..7] KSO6 39 91 @ RE11 2.2K_0402_5%
GPIO047/BCM_CLK1/KSO06 GPIO131/SMB03_CLK/SMB03_CLK18 L_BKLT_EN_EC [6] PCIE_WAKE#
2 7 KSO15 KSO7 50 96 TP71 2 1
3 6 KSO14 KSO8 46 GPIO025/KSO07/PVT_IO2 GPIO141/SMB04_DATA/SMB04_DATA18 97 PBAT_PRES# RE12 10K_0402_5%
[30] KSO[0..16] PBAT_PRES# [50,51]
2
4 5 KSO16 KSO9 68 GPIO055/PWM2/KSO08/PVT_IO3 GPIO142/SMB04_CLK/SMB04_CLK18 RE13 1 2 10K_0402_5% TOUCHPAD_INTR# 1 2
GPIO102/KSO09/CR_STRAP +3VS
KSO10 72 40 FAN1_TACH 1 RE14 100K_0402_5%
GPIO106/KSO10 GPIO050/TACH0 LID_CLOSE# FAN1_TACH [30]
RPE6 KSO11 74 41
100K_8P4R_5% KSO12 75 GPIO110/KSO11 GPIO051/TACH1 CE16 VREF_CPU
GPIO111/KSO12 +1.0V_PRIM
2 1 KSO9 KSO13 76 44 RESET_OUT# 1 2
0.1U_0402_25V6
100P_0402_50V8J
RE15 100K_0402_5% KSO14 77 GPIO112/PS2_CLK1A/KSO13 MEC1404 GPIO053/PWM0 45
KB_LED_PWM [30] 2 RE16 10K_0402_5%
GPIO113/PS2_DAT1A/KSO14 GPIO054/PWM1 BEEP [23]
1
2 1 USB_EN# KSO15 86 ME_FWP_EC 1 2
GPIO125/KSO15
CE17
RE17 100K_0402_5% KSO16 92 47 @ RE19 1K_0402_5%
BAT1_LED# GPIO132/KSO16 GPIO056/PWM3 FAN1_PWM [30] PCH_RSMRST#
2 1 93 34 1 2
[30] CAP_LED# FW_UPDATE [9,37]
2
RE18 100K_0402_5% GPIO140/KSO17 GPIO030/BCM_nINT0/PWM4 35 RE20 10K_0402_5%
BAT2_LED# GPIO031/BCM_DAT0/PWM5 EC_WAKE# [11]
2 1 KSI0 98 36
GPIO143/KSI0/nDTR GPIO032/BCM_CLK0/PWM6 PCIE_WAKE# PS_ID [50]
RE21 100K_0402_5% KSI1 99 4
GPIO144/KSI1/nDCD GPIO002/PWM7 PCIE_WAKE# [11,34,48]
KSI2 6
KSI3 7 GPIO005/SMB00_DATA/SMB00_DATA18/KSI2 1 BAT1_LED#
GPIO006/SMB00_CLK/SMB00_CLK18/KSI3 GPIO157/LED0/TST_CLK_OUT BAT2_LED# BAT1_LED# [29]
KSI4 104 106
GPIO147/KSI4/nDSR GPIO156/LED1 BREATH_LED# BAT2_LED# [29]
C KSI5 105 70 C
GPIO150/KSI5/nRI GPIO104/LED2 BREATH_LED# [29]
KSI6 107
KSI7 108 GPIO151/KSI6/nRTS 80 ME_FWP_EC
GPIO152/KSI7/nCTS GPIO116/TFDP_DATA/UART_RX HOST_DEBUG_TX ME_FWP_EC [12]
81
GPIO117/TFDP_CLK/UART_TX HOST_DEBUG_TX [32]
78
[30] CLK_TP_SIO GPIO114/PS2_CLK0 PTP_DIS#_R PTP_DIS#
79 90 RE22 2 @ 1 0_0402_5% +3VALW
[30] DAT_TP_SIO GPIO115/PS2_DAT0 GPIO035/SB-TSI_CLK PECI_MEC1404 PECI_EC PTP_DIS# [30]
52 94 RE23 1 2 43_0402_1%
[11] SIO_PWRBTN# PCH_RSMRST# GPIO026/PS2_CLK1B GPIO033/PECI_DAT/SB_TSI_DAT
88
[11] PCH_RSMRST# GPIO127/PS2_DAT1B
1
100K_0402_5%
95 VREF_CPU
LPC_LAD0 59 VREF_CPU
[8] LPC_LAD0 GPIO040/LAD0
RE25
LPC_LAD1 60 101 ICSP_CLK RE24 2 @ 1 0_0402_5% EC_MUTE#
[8] LPC_LAD1 LPC_LAD2 GPIO041/LAD1 GPIO145/ICSP_CLOCK ICSP_DAT PTP_DIS#
61 102 RE26 2 @ 1 0_0402_5%
[8] LPC_LAD2 LPC_LAD3 GPIO042/LAD2 GPIO146/ICSP_DATA ICSP_CLR
@EMI@ @EMI@ 62 87
[8] LPC_LAD3
2
CE18 RE27 LPC_LFRAME# 58 GPIO043/LAD3 ICSP_MCLR
[8] LPC_LFRAME# PCH_PLTRST#_EC GPIO044/nLFRAME EC_MUTE#_R EC_MUTE# LID_CLOSE#
0.1U_0402_10V7K 0_0402_5% 56 119 RE28 2 @ 1 0_0402_5%
[11,25,32,34,40,48] PCH_PLTRST#_EC GPIO064/nLRESET BGPO/GPIO004 SYSPWR_PRES EC_MUTE# [23] LID_CLOSE# [28,29]
2 1 1 2 57 120 1 2 +3VLP
GPIO034/PCI_CLK SYSPWR_PRES/GPIO003
0.047U_0402_16V4Z
63 121 RE29 1K_0402_5%
[8] CLK_PCI_LPC_MEC [8]CLKRUN# GPIO067/nCLKRUN VCI_OUT/GPIO036 ALWON [52]
55 126 VCI_IN1 RE30 1 2 100K_0402_5%
[8] SERIRQ GPIO063/SER_IRQ nVCI_IN1/GPIO162 +RTC_CELL
CE19
10 127 POWER_SW_IN#
[6] SIO_EXT_SMI# GPIO011/nSMI/nEMI_INT nVCI_IN0/GPIO163
1
100K_0402_5%
49 128 @
[30] TP_PW_EN# GPIO060/KBRST VCI_OVRD_IN/GPIO164 ACAV_IN [11,50,51]
53
[8] SIO_RCIN#
2
GPIO061/nLPCPD +3VALW_EC
RE32
66 23
[10] SIO_EXT_SCI# GPIO100/nEC_SCI GPIO160/DAC_0 SIO_SLP_S3# [11,17,36]
24
EC_SPI_CLK GPIO161/DAC_1 PLT_RST_VGA# [40]
RE33 1 2 15_0402_1% 32 22
0.1U_0402_25V6
[8] PCH_SPI_CLK_R
2
RE34 1 2 15_0402_1% EC_SPI_MOSI 28 GPIO126/SHD_SCLK DAC_VREF
[8] PCH_SPI_D0_R GPIO133/SHD_IO0
1
RE35 1 2 15_0402_1% EC_SPI_MISO 29 85 CMP_VOUT0
[8] PCH_SPI_D1_R GPIO134/SHD_IO1 GPIO124/CMP_VOUT0 CMP_VOUT0 [52]
CE20
SATA_LED_EN 30 20 CMP_VIN0 2 @ 1
[29] SATA_LED_EN GPIO135/SHD_IO2 GPIO020/CMP_VIN0 VCIN0_PH [30]
31 25 VCREF0 RE37 0_0402_5%
2
RE38 2 @ 1 0_0402_5% [11] RTCRST_ON EC_SPI_CS0# 27 GPIO136/SHD_IO3 GPIO165/CMP_VREF0
[8] PCH_SPI_CS#0_R1 GPIO123/SHD_nCS H_PROCHOT_EC
83 +RTC_CELL
67 GPIO120/CMP_VOUT1 21
[11,17,53,55] SIO_SLP_S4# GPIO101/SPI_CLK GPIO021/CMP_VIN1 GPU_PWR_LEVEL [41]
69 26
[51] AC_DIS GPIO103/SPI_IO0 GPIO166/CMP_VREF1/UART_CLK LCD_TST [28]
1
100K_0402_5%
71
[9,37] 3D_CAM_EN GPIO105/SPI_IO1
RE41
42 118 CMP_STRAP0 RE40 1 2 10K_0402_5%
[11] ME_SUS_PWR_ACK GPIO052/SPI_IO2 GPIO024/CMP_STRAP0 +3VALW
TOUCHPAD_INTR# 33 117
[12,30] TOUCHPAD_INTR# GPIO062/SPI_IO3 GPIO023/ADC6/A20M PANEL_BKEN_EC [28]
3 116
[34] LAN_EN GPIO001/SPI_nCS/32KHZ_OUT GPIO022/ADC5 MODEL_ID SIO_EXT_WAKE# [9]
109
2
13 GPIO153/ADC4 110 I_ADP_R RE64 2 @ 1 0_0402_5%
B [27] USB_EN# nRESET_IN/GPIO014 GPIO154/ADC3 LCD_VCC_TEST_EN_R [28] B
RE42 2 @ 1 0_0402_5% RUNPWROK 48 111 BOARD_ID POWER_SW_IN# 1 2
[11] ALL_SYS_PWRGD GPIO057/VCC_PWRGD GPIO155/ADC2 POWER_SW#_MB [29]
VSS_VBAT
1U_0402_6.3V6K
114 I_BATT_R
GPIO121/ADC0
1
RE45 2 1 0_0402_5% MEC_XTAL2 125 115 RE44
AVSS
+3VALW_EC
CE33
MEC_XTAL1 RE47 2 @ 1 0_0402_5% MEC_XTAL1_R 123
XTAL1
2
+3VALW +3VALW
0.1U_0402_25V6
124
84
51
17
64
100
EC_AGND 112
18
+3VS
0.1U_0402_10V7K
MEC1404-NU-TR_VTQFP128_14X14
1
CE21
1 TP44
CE22
RE46 RE49
EC_AGND 2
10K_0402_1% 100K_0402_5%
2
32 KHz Clock (Un- POP) VR_CAP 1 2
2
2 @ 1 RE51 300_0402_5% VCREF0
5
0.1U_0402_25V6
I_ADP [51]
1
UE2 YE1 @ Close UE1 1 RE52 100K_0402_5%
P
1
4 2 H_PROCHOT_EC MEC_XTAL1 1 2 MEC_XTAL2 RE48
[12,50,51,56] H_PROCHOT# Y A ESR <100m ohms
CE23
CE25 2200P_0402_25V7K EC_AGND
NC
10K_0402_1%
G
2
SN74LVC1G06DCKR_SC70-5 RE53 20ppm / 9pF EC_AGND 2
1 1 1
EC_AGND
1
2
100K_0402_5% ESR <50kohm (MAX) @
CE26 CE3 @ CE4 @ PCH_PLTRST#_EC 1 2
47P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J CE27 0.047U_0402_16V4Z
1
2 2 2 @
FAN1_TACH 1 2
EC_AGND CE28 220P_0402_50V8J
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
RESET_OUT# 1 2
@ RE56
@ RE57
RE59
A 1 2 A
12 10 ICSP_CLK_R RE60 2 @ 1 0_0402_5% ICSP_CLK 2 ACAV_IN 2 1
11 GND 10 9 2 3 ICSP_CLR_R RE61 2 @ 1 0_0402_5% ICSP_CLR CE32 100P_0402_50V8J
2
GND 9 8 LPC_LAD0 3 4
8 7 LPC_LAD1 4 5 ICSP_DAT_R RE63 2 ZT55
@ 1 0_0402_5% ICSP_DAT
Close to UE1 each pin
7 6 LPC_LAD2 5 6
6 5 LPC_LAD3 6 7 EC_AGND
5 4 LPC_LFRAME# 7 8 HOST_DEBUG_TX
4 8 9 ZT57
3 11
3 PCH_PLTRST#_EC [11,25,32,34,40,48] GND 9 10 ZT58
2 12
2 1 GND 10 Pin8 5085_TXD for EC Debug
1
JXT_FP241AH-010GAAM
CLK_PCI_LPDEBUG [8]
JXT_FP241AH-010GAAM pin9 5048_TXD for SBIOS
debug
Security Classification Compal Secret Data Compal Electronics, Inc.
SP010021O00 Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title
SP010021O00
ICSP_CLK_R
ZT53 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC MEC1404
ICSP_CLR_R AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
ZT54
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A00
ICSP_DAT_R
ZT56
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 25 of 61
5 4 3 2 1
5 4 3 2 1
3
8 DC233007O10
2 @EMI@ 1
3
ESD@
RU2 0_0402_5% L05ESDL5V0NA-4_SLP2510P8-10-9
ESD@ AZC199-02SPR7G_SOT23-3
EU2602
1
1
USB3.0 90ohm USB3.0 90ohm
Main SM070003V00(S COM FI_ INPAQ HCM1012GH900BP) Main SM070003V00(S COM FI_ INPAQ HCM1012GH900BP)
2nd SM070004000(S COM FI_ TAIYO MCF12102G900-T) 2nd SM070004000(S COM FI_ TAIYO MCF12102G900-T)
3rd SM070004300(S COM FI_ PANASONIC EXC24CH900U) 3rd SM070004300(S COM FI_ PANASONIC EXC24CH900U)
CU1
1 2 USB3_CTX_DRX_P1_R 2 EMI@ 1 USB3_CTX_DRX_P1_C 2 EMI@ 1 USB3_CRX_DTX_P1_C
[10] USB3_CTX_DRX_P1 [10] USB3_CRX_DTX_P1
RU4 0_0402_5% RU6 0_0402_5%
.1U_0402_16V7K
LU2 LU3
2 1 2 1
C C
3 4 3 4
HCM1012GH900BP_4P HCM1012GH900BP_4P
@EMI@ @EMI@
CU2
1 2 USB3_CTX_DRX_N1_R 2 EMI@ 1 USB3_CTX_DRX_N1_C 2 EMI@ 1 USB3_CRX_DTX_N1_C
[10] USB3_CTX_DRX_N1 [10] USB3_CRX_DTX_N1
RU3 0_0402_5% RU5 0_0402_5%
.1U_0402_16V7K
USB3.0 Port2
USB30_VCCA
JUSB2 CONN@
USB3_CTX_DRX_P2_C 9
1 SSTX+
USB2.0 90ohm VBUS
Main SM070003Z00(S COM FI_ INPAQ MCM1012B900F06BP) USB3_CTX_DRX_N2_C 8
1 @EMI@ 2 USB_PP2_C 3 SSTX-
RU8 0_0402_5%
2nd SM070004U00(S COM FI_ MURATA DLM11SN900HY2L) 7 D+
EMI@ 3rd SM070004400(S COM FI_ PANASONIC EXC24CQ900U) USB_PN2_C 2 GND 10
MCM1012B900F06BP_4P USB3_CRX_DTX_P2_C 6 D- GND 11
2 1 USB_PN2_C EU2603 4 SSRX+ GND 12
[10] USB_PN2 GND GND
USB3_CRX_DTX_N2_C 1 1 10 9USB3_CRX_DTX_N2_C USB3_CRX_DTX_N2_C 5 13
SSRX- GND
3 4 USB_PP2_C USB3_CRX_DTX_P2_C 2 2 9 8USB3_CRX_DTX_P2_C ACON_TARA4-9K1311
[10] USB_PP2
3
B B
DC233007O10
LU4 USB3_CTX_DRX_N2_C 4 4 7 7USB3_CTX_DRX_N2_C
3
ESD@
USB3_CTX_DRX_P2_C 5 5 AZC199-02SPR7G_SOT23-3
6 6USB3_CTX_DRX_P2_C
EU2604
1
1 @EMI@ 2 3 3
1
RU7 0_0402_5%
8
USB3.0 90ohm
Main SM070003V00(S COM FI_ INPAQ HCM1012GH900BP) L05ESDL5V0NA-4_SLP2510P8-10-9
ESD@
2nd SM070004000(S COM FI_ TAIYO MCF12102G900-T)
3rd SM070004300(S COM FI_ PANASONIC EXC24CH900U)
CU3
1 2 USB3_CTX_DRX_P2_R 2 EMI@ 1 USB3_CTX_DRX_P2_C 2 EMI@ 1 USB3_CRX_DTX_P2_C
[10] USB3_CTX_DRX_P2 [10] USB3_CRX_DTX_P2
RU10 0_0402_5% RU12 0_0402_5%
.1U_0402_16V7K
LU5 LU6
2 1 2 1
USB3.0 90ohm
Main SM070003V00(S COM FI_ INPAQ HCM1012GH900BP)
3 4 3 4
2nd SM070004000(S COM FI_ TAIYO MCF12102G900-T)
HCM1012GH900BP_4P HCM1012GH900BP_4P 3rd SM070004300(S COM FI_ PANASONIC EXC24CH900U)
@EMI@ @EMI@
A A
CU4
1 2 USB3_CTX_DRX_N2_R 2 EMI@ 1 USB3_CTX_DRX_N2_C 2 EMI@ 1 USB3_CRX_DTX_N2_C
[10] USB3_CTX_DRX_N2 [10] USB3_CRX_DTX_N2
RU9 0_0402_5% RU11 0_0402_5%
.1U_0402_16V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 26 of 61
5 4 3 2 1
5 4 3 2 1
+5VALW UU1
1 80 mils 80 mils
5 OUT
IN
@
D 2 1 1 1 1 1 1 1 1 1 1 D
GND
1U_0402_10V6K
1U_0402_10V6K
22U_0805_10V6M
22U_0805_10V6M
100U_1206_6.3V6M
1U_0402_10V6K
1U_0402_10V6K
22U_0805_10V6M
22U_0805_10V6M
100U_1206_6.3V6M
USB_EN# 4
EN
CU6
CU18
CU9
CU20
CU22
CU7
CU19
CU8
CU21
CU10
1 3 USB_OC#0_1 [10]
OCB
CU5 SY6288D20AAC_SOT23-5 2 2 2 2 2 2 2 2 2 2
1U_0402_10V6K
2
+5VALW UU3
1
5 OUT
IN 2
4 GND
[25] USB_EN# EN 3
C OCB USB_OC#2_3 [10] C
1
SY6288D20AAC_SOT23-5
CU17
.1U_0402_16V7K
2
USB2.0
1 @EMI@ 2
RU14
EMI@
0_0402_5% I/O Board Connector
MCM1012B900F06BP_4P
3 4 USB_PN3_C JIOB1 CONN@
[10] USB_PN3
1
B 2 1 B
2 1 USB_PP3_C USB_PN6_C 3 2
[10] USB_PP3
LU7 CardReader USB_PP6_C 4
5
3
4
5
6
USB2.0 USB_PP3_C
USB_PN3_C
7
8
6
7
8
1 @EMI@ 2 9
RU13 0_0402_5% 10 9
11 10
12 11
+3VS 12
USB20_VCCA 13
14 13
15 14
80 mils 16 15
CardReader 17
18
16
GND
1 @EMI@ 2 GND
RU15 0_0402_5% ACES_51524-0160N-001
SP01001C600
LU8
2 1 USB_PN6_C
[10] USB_PN6
3 4 USB_PP6_C
[10] USB_PP6
MCM1012B900F06BP_4P
A EMI@ A
1 @EMI@ 2
RU16 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB Power SW/IO Board
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 27 of 61
5 4 3 2 1
5 4 3 2 1
JEDP1 CONN@ R3 F1 850mA EE note: Never change R16 to short pad after MP
1 +DCBAT_LCD 1 2 1 2
41 1 2
42 G1 2 3 +DCBAT_CAM
1 @ 2 0_0805_5% SMD1812P150TF/24 1.5A UL/CSA/TUV +3VS +3VS_CAM
G2 3 4 1 1
R51 0_0805_5% +LCDVDD_LCD C4 C5
4 5
@
5 6
Trace width = 60mil EE note: Never change R3 to short pad after MP
0.1U_0603_50V7K
1000P_0402_50V7K
DMIC_CLK_EDP
6 7 2 2 1 2
7 8 1 1
C2 C3 R16 0_0603_5%
8 9 1U_0402_10V6K
9 10 1
1
+3VS
33P_0402_50V8J
C14
DBC_EN_R R56 C15
0.1U_0402_16V7K
10 11 EDP_HPD 2 2 4.7U_0603_6.3V6K
11 12 EDP_HPD [6]
@EMI@
0_0402_5%
D LCD_TST_C D
2
12 13 2
@
13 14
1
EDP_AUX
2
14 15 EDP_AUX# R5
15 16
16 17 10K_0402_5%
EDP_TX0# 1 C13
17 18 EDP_TX0
2
18 19
@EMI@
10P_0402_50V8J
19 20 EDP_TX1#
20 21 EDP_TX1 DBC_EN_R 1 2 2
21 22 DBC_EN [9]
22 23
R6 0_0402_5% Close JEDP1 Pin28, 29
LCD_BRIGHTNESS
23 24 BLON_OUT_C
24 25
25 26 IR_GND
26 27
27 28 DMIC_CLK_EDP
28 29 DMIC_CLK_EDP [23]
DMIC_DATA_EDP
29 30 DMIC_DATA_EDP [23]
30 31 +3VS_CAM
USB_CAMERA_EDP#
31 32 USB_CAMERA_EDP 1 @EMI@ 2
32 33 R17 0_0402_5%
33 34
34 35 IR_CAM_DETECT# [9] MCM1012B900F06BP_4P
35 36 USB_PN7_TPNL USB_CAMERA_EDP# 1 2
36 37 USB_PN5 [10]
USB_PP7_TPNL
37 38
38 39 TP_EN USB_CAMERA_EDP 4 3
39 40 USB_PP5 [10]
40 +TPAN_VDD L3 EMI@
RP1
ACES_51540-04001-P01
SP010029F00 1 8 BKLT_CTRL
2 7 BLON_OUT_C 1 @EMI@ 2
3 6 EDP_HPD R18 0_0402_5%
4 5
1 @ 2
100K_8P4R_5% R9 0_0402_5%
D3
RP2 eDP_BKLT_CTRL
2
C BLON_OUT_C 1 8 C
LCD_BRIGHTNESS BKLT_CTRL PANEL_BKEN_EC [25]
2 7 1
LCD_TST_C 3 6 LCD_TST
4 5 3 LCD_TST
LCD_TST [25]
BAT54C-7-F_SOT23-3
100_8P4R_5% EC (BIST MODE)
R54 1 @ 2 0_0805_5%
Main Func = TS
IR_GND
Touch Panel
R19
C6 1 2 0.1U_0402_16V7K EDP_TX0# TP_EN 1 2
[6] EDP_TX0_DN TOUCH_SCREEN_PD# [12]
[6] EDP_TX0_DP C7 1 2 0.1U_0402_16V7K EDP_TX0 1 33_0402_5%
C16
@
+3VS +LCDVDD 10P_0402_50V8J
C8 1 2 0.1U_0402_16V7K EDP_TX1# 2
[6] EDP_TX1_DN
C9 1 2 0.1U_0402_16V7K EDP_TX1 C17
[6] EDP_TX1_DP
1U_0402_6.3V6K U1
2 1 5 1 40mil
IN OUT +3VS
EDP_AUX# D5
[6] EDP_AUX_DN C10 1 2 0.1U_0402_16V7K 2
C11 1 2 0.1U_0402_16V7K EDP_AUX GND R57 LID_CLOSE# 1 2 TOUCH_SCREEN_PD#
[6] EDP_AUX_DP [25,29] LID_CLOSE#
4 3 2 1
EN OC 10K_0402_5%
Brightness SY6288C20AAC_SOT23-5
RB551V-30_SOD323-2
R8 1 @ 2 0_0402_5% eDP_BKLT_CTRL D4
[6] L_BKLT_CTRL 2
B
[6] EDP_VDD_EN B
1 LCDVDD_EN
3
[25] LCD_VCC_TEST_EN_R
High Active
1
MCM1012B900F06BP_4P
2
1 2 USB2.0 90ohm
Main SM070003Z00(S COM FI_ INPAQ MCM1012B900F06BP)
4 3
2nd SM070004U00(S COM FI_ MURATA DLM11SN900HY2L)
3rd SM070004400(S COM FI_ PANASONIC EXC24CQ900U)
L4 @EMI@
USB_PN7_TPNL
USB_PP7_TPNL
+3VS +5VS
3
+TPAN_VDD
1
@
R11 R12 DA6 @ESD@
0_0603_5% 0_0603_5% PESD5V0U2BT_SOT23-3
2
F2 @
+TPAN_VDD_F 1 2
1
1.1A_24V_SMD1812P110TF-24
A A
1 2
R13 0_0603_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD/Cam/MIC/T.Panel
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 28 of 61
5 4 3 2 1
5 4 3 2 1
JPWR1 CONN@
using ZT2 insted of TPS8 6 8
WHITE_LED_PWR 5 6 G2 7
ZT1 5 G1
4
POWER_SW#_MB 3 4
ZT2 LID_CLOSE#_C 3
2
ZT3 2
+3VALW 1
1
D D
R22 1 2 100_0402_5% LID_CLOSE#_C JXT_FP226H-006S1BM
[25,28] LID_CLOSE# SP010021Y10
[25] POWER_SW#_MB
1
1 @ESD@ ED2901
1000P_0402_50V7K
AZ5725-01F_DFN2
EC2901
@ESD@
@ 2
2
SW1
TST71-N-220-T170-S017_2P
For EMI Reserved
2
@ESD@
LID_CLOSE#_C EC2902 1 2 .1U_0402_16V7K
EC2901 must be used 1000pF.
3
JLED1 CONN@
2
+3VS 1 2 6
R23 10K_0402_5%
R2
5 GND
1 6 CHG_AMBER_LED_R# 2 Q3 GND
[25] BAT1_LED#
[25] SATA_LED_EN DDTA144VCA-7-F_SOT23-3 4
Q2A
R1
WHITE_LED_BAT 3 4
ZT16 AMBER_LED_BAT 3
DMN66D0LDW-7_SOT363-6 2
ZT17 2
1
1
2
1
G
ACES_51524-0040N-001
3
SP010022M00
5
3 1 BATT_WHITE_LED_R# AMBER_LED_BAT
[10] SATA_LED# R2
S
4 3 BATT_WHITE_LED_R# 2 Q4
[25] BAT2_LED#
DDTA144VCA-7-F_SOT23-3
Q5 Q2B
R1
2N7002K_SOT23-3 DMN66D0LDW-7_SOT363-6
1
WHITE_LED_BAT
B B
+5VALW
1
R53
100K_0402_5%
PWR LED Control
3
2
G
R2
3 1 PWR_LED_R# 2 Q15
[25] BREATH_LED#
DDTA144VCA-7-F_SOT23-3
S
R1
Q16
LN2306LT1G_SOT23-3
1
A
WHITE_LED_PWR A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED Board/Power Button
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 29 of 61
5 4 3 2 1
5 4 3 2 1
[25] KSI[0..7]
Keyboard Backlight (Reserved) NTP_WAKE@
1
+TP_VDD +3VS R36 1 2
KB Backlight Power Consumption: 285mA max. TP_WAKE@ 0_0603_5%
R35
[25] KSO[0..16] +5VS F3 KBBL@ +5V_KB_BL 0_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
2
1
1
2 1
ZT61
R31
R32
R33
R34
JKB1 CONN@ 1
ZT24
30 32 0.5A_13.2V_MF-NSMF050-2 KBBL@ +TP_VDD Discharge
[9]KB_DET# KSI7 29 30 GND 31 C34
ZT25 29 GND Q12 +TP_VDD
KSI6 28 .1U_0402_16V7K
ZT26
2
KSI4 27 28 2 NTK3139PT1G_SOT723-3
ZT27 27 DAT_TP_SIO
KSI2 26
ZT28 26 [25] DAT_TP_SIO
D
KSI5 25 3 1 1 2
ZT29
ZT30
KSI1 24 25
24
KBBL@ JKBBL1 CONN@ EC/PS2 [25] CLK_TP_SIO
CLK_TP_SIO 1
KSI3 23 R26 1 TP_WAKE@ TP_WAKE@ R37
ZT31 23 KB_LED_DET_C 1 I2C_SDA_TP
KSI0 22 1 2 2 C18 100_0603_1%
G
D ZT32 [9] I2C_SDA_TP D
2
22 [12] KB_LED_BL_DET 2
1
KSO5 21 51K_0402_5% 3 5 .1U_0402_16V7K
ZT33 21 3 G1 PCH/I2C
1
KSO4 20 KB_BL_CTRL# 4 6 I2C_SCL_TP 2 D Q13
ZT34 20 4 G2 [9] I2C_SCL_TP TP_ON#_GATE
KSO7 19 KBBL@ [25] TP_PW_EN# 1 2 2 2N7002K_SOT23-3
ZT35 19
@ESD@ C26
@ESD@ C27
KSO6 18 R27 ACES_51575-00401-001 G
ZT36 18
10P_0402_50V8J
10P_0402_50V8J
KSO8 17 100K_0402_5% SP011503261 R38 S
ZT37 17
KSO3 16 20K_0402_1%
ZT38
3
16
1
KSO1 15
ZT39 15
KSO2 14
ZT40 14 KB_LED_DET_C
KSO0 13
ZT41 ZT51
2
KSO12 12 13 KB_BL_CTRL#
ZT42 12 D ZT52
1
KSO16 11 Q8 +TP_VDD +TP_VDD
ZT43 11
KSO15 10 2 KBBL@
ZT44 10 [25] KB_LED_PWM
KSO13 9 G
ZT45 9
1
KSO14 8 S
ZT46
3
KSO9 7 8 LN2306LT1G_SOT23-3 R39
ZT47 7
KSO11 6 ESD depop location 10K_0402_5%
ZT48 6
KSO10 5
ZT49 5
2
CAP_LED 4
G
ZT50
2
3 4
2 3 1 3 INT_TP# I2C_SDA_TP_Q
2 [12,25] TOUCHPAD_INTR# ZT8 I2C_SCL_TP_Q
1
S
1 ZT9 INT_TP#
ZT10 TP_LOCK#
STARC_132C30-100020-A2-R Q9 LN2306LT1G_SOT23-3
SP01001LN00 For EMI Reserved +TP_VDD ZT11
ZT12
DAT_TP_SIO
CLK_TP_SIO
ZT13
@EMI@
KB_BL_CTRL# EC3001 1 2 .1U_0402_16V7K
+3VS
@EMI@
1
+5V_KB_BL EC3002 1 2 .1U_0402_16V7K
R46 +TP_VDD
2.2K_0402_5%
2 1
ZT59
2
0.1U_0402_16V7K C19 JTP1 CONN@
2
Q10B 10
G
I2C_SCL_TP 1 6 I2C_SCL_TP_Q +TP_VDD 4.7K_0402_5% 2 1 R40 9 GND
8 GND
D
DMN66D0LDW-7_SOT363-6 NTP_WAKE@
8
1
1 2 I2C_SDA_TP_Q 7
R47 R41 100K_0402_5% I2C_SCL_TP_Q 6 7
+3VS 2.2K_0402_5% 5 6
5
5
C Q10A D6 INT_TP# 4 C
PTP_DIS# 1 2 TP_LOCK# 3 4
G
[25] PTP_DIS#
2
I2C_SDA_TP 4 3 I2C_SDA_TP_Q DAT_TP_SIO 2 3
+5VS CLK_TP_SIO 1 2
D
DMN66D0LDW-7_SOT363-6 RB551V-30_SOD323-2
1
1
R24 JXT_FP202DH-008M10M
100K_0402_5% SP010020L00
CAP LED Control
3
2
G
R2
3 1 CAP_LED_R# 2 Q7
[25] CAP_LED# DDTA144VCA-7-F_SOT23-3
S
R1
Q6
LN2306LT1G_SOT23-3
1
R25
CAP_LED_Q 1 2 CAP_LED
1K_0402_5%
+3VS +5VS
22U_0805_10V6M
+3VS
10K_0402_5%
10K_0402_5%
C30
@
2
2
R50
R30
+3VS
1
1
R48 JFAN1 CONN@
2.2K_0402_5% 1
ZT14 1
2
[25] FAN1_PWM 2
2
[25] FAN1_TACH 2 1 3
2
Q11B D8 @ 4 3
G
6 1 THM_SML1_DATA SDMK0340L-7-F_SOD323-2 4
[8,25,41] SML1DATA "FAN1_FB" PU 10k on EC side
S
B DMN66D0LDW-7_SOT363-6 5 B
GND1
1
2 @ 1 6
R49 R55 0_0603_5% GND2
SML1DATA => GPU_THM_SMBDAT 2.2K_0402_5% JXT_WB247H-004S10M
SML1CLK => GPU_THM_SMBCLK ZT15
5
+3VS Q11A SP020017K10
2
3 4 THM_SML1_CLK
[8,25,41] SML1CLK
S
DMN66D0LDW-7_SOT363-6
1
10U_0603_6.3V6M
1
C20 @
C21
0.1U_0402_16V7K
2 2
NCT7718_DXP
Q14 U2
1 1 1 8 THM_SML1_CLK
VDD SCL
1
C @
LMBT3904LT1G_SOT23-3
2
NCT7718W_MSOP8
1
@
Layout Note: R42 R43
Layout Note: C23 close U2 24.9K_0402_1% 10K_0402_1%
2
VCIN0_PH [25]
1
1 1
@
A R44 C32 C33 A
THINK_0603_1%_TSM1B104F3591RZ 0.1U_0402_16V7K 100P_0402_50V8J
2 2
2
VD_IN1_C R45 1 2 0_0402_5%
PURE_KBCT8
+3VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Keyboard/Touch Pad/Thermal/FAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 30 of 61
5 4 3 2 1
Main Func = HDD
SATA HDD Connector
Layout Note:
Place near HDD1
RS1 2 1 0_0402_5% HDD_DEVSLP_R
EU3101 [10] HDD_DEVSLP
SATA_RXP0_R 1 1 10 9 SATA_RXP0_R
SATA_RXN0_R SATA_RXN0_R
Reserve, refer to M15 EE Implementation Requirements
2 2 9 8 JHDD1 CONN@
1
SATA_TXN0_R 4 4 SATA_TXN0_R SATA_TXP0_R 1
7 7 CS1 1 2 0.01U_0402_50V7K 2
SATA_TXP0_R 5 5 6 6 SATA_TXP0_R
SOC TX [10] SATA3_CTX_HDDRX_P0
[10] SATA3_CTX_HDDRX_N0 CS2 1 2 0.01U_0402_50V7K SATA_TXN0_R 3
4
2
3
CS3 1 2 0.01U_0402_50V7K SATA_RXN0_R 5 4
3 3 SOC RX [10] SATA3_CRX_HDDTX_N0
[10] SATA3_CRX_HDDTX_P0
CS4 1 2 0.01U_0402_50V7K SATA_RXP0_R 6
7
5
6
8 HDD_DEVSLP_R 8 7
9 8
10 9
+5V_HDD 10
@ESD@ 11
12 11
Swap based on the swap report. +5VS +5V_HDD 12
JP12 13
GND
Always Short 14
GND
JP12 PJP@ ACES_51625-01201-001
80 mils 1 2 80 mils SP010028W00
1 2
1000P_0402_50V7K
0.1U_0402_25V6K
10U_0805_10V6K
JUMP_43X79
1 1 1
CS5 CS6 CS7
2 2 2
1000P_0402_50V7K
0.1U_0402_25V6K
10U_0805_10V6K
JUMP_43X79
1 1 1 2 A+
CS13 CS14 CS15
2 2 2 3 A-
4 GND
5 B-
6 B+
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 31 of 61
5 4 3 2 1
+3VS +3.3V_WLAN
1.1A
RW3 2 1 0_0805_5%
D USB_PN8_R 1 EMI@ 2 D
USB_PN8 [10]
RF@ RW1 0_0402_5%
1 1 1 1 1 1 1
CW3
.1U_0402_16V7K
CW4
.1U_0402_16V7K
CW5
10U_0603_6.3V6M
CW6
10U_0603_6.3V6M
CW7
.1U_0402_16V7K
CW8
.1U_0402_16V7K
CW9
10P_0402_50V8J
@ @ @ LW1 @EMI@
4 3
2 2 2 2 2 2 2
1 2
MCM1012B900F06BP_4P
JWLAN1 CONN@
USB_PP8_R 1 EMI@ 2
USB_PP8 [10]
68 69 RW2 0_0402_5%
MTG76 MTG77
+3.3V_WLAN
67
66 GND 65
64 3.3VAUX RESERVED 63
62 3.3VAUX RESERVED 61
60 RESERVED GND 59
58 RESERVED RSRVD/PERN1 57
56 RESERVED RSRVD/PERP1 55
54 RESERVED GND 53
52 ALERT RSRVD/PETN1 51
50 I2C_CLK RSRVD/PETP1 49
I2C_DATA GND ZT63
C
[6] WLAN_RADIO_DIS# 48 47 C
46 W_DISABLE1# PEWAKE0# 45 CLK_PCIE_WLAN_REQ#_R RW9 2 @ 1 0_0402_5%
[9] BLUETOOTH_EN W_DISABLE2# CLKEQ0# CLK_PCIE_WLAN_REQ# [11]
RW4 2 @ 1 0_0402_5% PLT_RST_NGFF# 44 43
[11,25,34,40,48] PCH_PLTRST#_EC PERST0# GND
42 41 CLK_PCIE_WLAN_N1 [11]
[11] SUSCLK_WLAN SUSCLK REFCLKN0
40 39 CLK_PCIE_WLAN_P1 [11]
38 COEX1 REFCLKP0 37
E51_TX1 36 COEX2 GND 35
COEX3 PERN0 PCIE_CRX_WLANTX_N5 [10]
34 33
RESERVED PERP0 PCIE_CRX_WLANTX_P5 [10]
32 31
E51_TX2 30 RESERVED GND 29 PCIE_CTX_WLANRX_N5 2 1 CW1 .1U_0402_16V7K
RESERVED PETN0 PCIE_CTX_WLANRX_N5_C
[10] EMI request
28 27 PCIE_CTX_WLANRX_P5 2 1 CW2 .1U_0402_16V7K
UART_RTS PETP0 PCIE_CTX_WLANRX_P5_C
[10]
26 25
24 UART_CTS GND
CLK_PCIE_WLAN_N1
CLK_PCIE_WLAN_P1
UART_TX
23
22 SDIO_RESET# 21
20 UART_RX SDIO_WAKE# 19
Reserved for NGFF Debug Card 18
16
UART_WAKE#
GND
SDO_DAT3
SDO_DAT2
17
15
14 LED2# SDO_DAT1 13
+3VALW +3.3V_WLAN 12 PCM_OUT SDO_DAT0 11
10 PCM_IN SDIO_CMD 9
PCM_SYNC SIDO_CLK 1 1
EC3201
33P_0402_50V8J
EC3202
33P_0402_50V8J
+3.3V_WLAN 8 7
PCM_CLK GND
@EMI@
@EMI@
1 @ 2 6 5 USB_PN8_R
RW5 0_0805_5% 4 LED1# USB_D- 3 USB_PP8_R
2 3.3VAUX USB_D+ 1 2 2
1 @ 2 E51_TX1 3.3VAUX GND
B [25] HOST_DEBUG_TX B
RW6 0_0402_5% LCN_DAN05-67406-0100
SP070017R00
E51_TX2
1
@
RW8
100K_0402_5%
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF_WLAN CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 32 of 61
5 4 3 2 1
5 4 3 2 1
5.6_0402_1% 5.6_0402_1%
@EMI@
HCM1012GH900BP_4P LI2
1
CI1 1 2 0.1U_0402_10V7K HDMI_CLK#_R 3 4 2 1
[6] HDMI_CLK# CI2 1 2 0.1U_0402_10V7K HDMI_CLK_R RI3 EMI@ EMI@
[6] HDMI_CLK RI6
150_0402_5%
CI3 1 2 0.1U_0402_10V7K HDMI_DATA0#_R 2 1 3 4 150_0402_5%
[6] HDMI_DATA0# CI4 1 2 0.1U_0402_10V7K HDMI_DATA0_R
2
[6] HDMI_DATA0 LI1 HCM1012GH900BP_4P
D D
@EMI@
8
7
6
5
8
7
6
5
RPI1 RPI2 5.6_0402_1% 5.6_0402_1%
470_8P4R_5% 470_8P4R_5%
@EMI@ @EMI@
HCM1012GH900BP_4P HCM1012GH900BP_4P
1
2
3
4
1
2
3
4
2
3 4 3 4
HDMI_PLL_GND RI9 EMI@ RI12 EMI@
150_0402_5% 150_0402_5%
2 1 2 1
1
LI3 LI4
1
+5VS
D QI1
2 2N7002K_SOT23-3
G
S RI8 EMI@ RI11 EMI@
C HDMI_DATA2#_R 1 2 HDMI_DATA2#_R_C HDMI_DATA1#_R 1 2 HDMI_DATA1#_R_C C
3
5.6_0402_1% 5.6_0402_1%
+5VS +5V_HDMI
W=40mils
2 1
ZT62
FI1 1
1.5A_6V_1206L150PR~D
CI9
.1U_0402_16V7K
2
JHDMI1 CONN@
19
18 HP_DET
17 +5V ZZZ 45@
ZT65 DDC_DATA_HDMI 16 DDC/CEC_GND
ZT66 DDC_CLK_HDMI 15 SDA
SCL RO0000002HM
14
13 Reserved
B HDMI_CLK#_R_C 12 CEC B
+3VS 11 CK-
CK_shield ROYALTY HDMI W/LOGO
HDMI_CLK_R_C 10
+5VS HDMI_DATA0#_R_C 9 CK+
8 D0-
HDMI_DATA0_R_C 7 D0_shield
D0+
1
1M_0402_5%
HDMI_DATA1#_R_C 6
DDC_DATA_PH2
5 D1-
DDC_CLK_PH1
D1_shield
RI15
HDMI_DATA1_R_C 4 20
HDMI_DATA2#_R_C 3 D1+ GND 21
2 D2- GND 22
2
D2_shield GND
2
G
HDMI_DATA2_R_C 1 23
D2+ GND
3 1 HDMI_HPD_B CONCR_099AKAC19NBLCNF
[6] HDMI_HPD
D
DC232003600
2
1
+3VS
20K_0402_5%
2N7002W-7-F_1N_SOT323-3
RI13 RI14 QI3
RI16
2.2K_0402_5% 2.2K_0402_5%
2
2
G
1 6 DDC_CLK_HDMI
[6] PCH_HDMI_CLK
S
QI2B
5
DMN66D0LDW-7_SOT363-6
G
4 3 DDC_DATA_HDMI
[6] PCH_HDMI_DATA
S
QI2A
A DMN66D0LDW-7_SOT363-6 A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI L.Shifter/Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 33 of 61
5 4 3 2 1
5 4 3 2 1
CL10
+LAN_VDD10
CL5: colse to Pin8
LAN CHIP 10/100M 2 1
10P_0402_50V8J
1
YL1
2
LANXIN
XTAL0 GND0
D 40 mils CL6: close to Pin30
3 4 D
XTAL1 GND1
CL11 25MHZ_10PF_7V25000014
2 1 LANXOUT
0.1U_0402_25V6
0.1U_0402_25V6
CL5
CL6
SA000065Y00
2 2
XTAL
SWR mode LDO mode SWR mode LDO mode
0.1U_0402_25V6
0.1U_0402_25V6
32 19 PLT_RST#_LAN
+LAN_VDD33 AVDD33 PERSTB
CL7
CL8
CL14
CL7,CL8: close to Pin32 23
+LAN_VDDREG DVDD33 20 ISOLATE#
2 2 2 CLK_PCIE_LAN_P2 15 ISOLATEB "PCIE_WAKE#" PU 10k on EC side
[11] CLK_PCIE_LAN_P2 CLK_PCIE_LAN_N2 16 REFCLK_P 21 PCIE_WAKE#
[11] CLK_PCIE_LAN_N2 REFCLK_N LANWAKEB PCIE_WAKE# [11,25,48]
C 1 @ 2 CLK_PCIE_LAN_REQ#_R 12 26 LED1 10K_0402_5%2 @ 1 RL1 C
+3VS CLKREQB GPO +LAN_VDD33
RL16 10K_0402_5% LANXIN 28
LANXOUT 29 CKXTAL1
CKXTAL2 3
TP48 27 NC 6
TP49 25 LED0 NC 7 +3VS
LED1 NC 9
2.49K_0402_1%~D 1 2 RL2 31 NC 10
RSET NC 11
NC
1
33 22
GND NC 24 RL3
NC 1K_0402_5%
RTL8106E-CG_QFN32_4X4
RTL8106E-CG_QFN32_4X4-S
2
ISOLATE#
1
RL4
15K_0402_1%
+3VALW OPEN +LAN_VDD33
2
JP11
2 1
CL9
1U_0402_6.3V6K UL3
B B
2 1 5 1
IN OUT +3VALW
2
GND RL7
4 3 2 1
[25] LAN_EN EN OC 10K_0402_5%
SY6288C20AAC_SOT23-5
High Active
2
RL6
100K_0402_5%
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8106
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 34 of 61
5 4 3 2 1
5 4 3 2 1
LAN_MDI1P 4 7 LAN_MDI1P
MCT1
MCT0 LAN_MDI1N 5 6 LAN_MDI1N
@ESD@
2
RL15
RL14
75_0603_5%
75_0603_5%
1
1
MCT
1
CL13
100P_1206_2KV8J
2
C C
1 12 MDO1-
2 RD+ RX+ 11 MDO1+
3 RD- RX- 10 MCT1
[34] LAN_MDI1P RDCT RXCT JLAN1 CONN@
12
4 9 MCT0 GND 11
TDCT TXCT GND
LOM_TCT
B
Main: SANTA_130460-N B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
XFOM&RJ45
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 35 of 61
5 4 3 2 1
5 4 3 2 1
JP9
TPS9 1 2 TPS10 JP9 Short
1 2
+5VS
JUMP_43X79
for NON-DS3
1
JP4 PJP@ JP4
D +5VALW PAD-OPEN1x3m Always Short D
@ UZ3
2
CZ23 2 1 1 14 +5V_OUT 1 2
2 VIN1 VOUT1 13 CZ9 0.1U_0402_10V7K
1U_0402_6.3V6K VIN1 VOUT1
3 12 1 2
ON1 CT1 CZ10 470P_0402_50V7K
4 11
VBIAS GND
5 10 1 2
[11,17,25] SIO_SLP_S3# ON2 CT2 CZ11 470P_0402_50V7K
+3VALW 6 9 JP5 PJP@
7 VIN2 VOUT2 8 +3.3V_OUT 1 2
VIN2 VOUT2 +3VS JP5
1
@ GPAD
15 1 PAD-OPEN1x3m Always Short
CZ25 EM5209VF_DFN14_3X2 CZ12
1U_0402_6.3V6K 0.1U_0402_10V7K
2 2
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
DC to DC
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD A00
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D805P
Date: Tuesday, June 21, 2016 Sheet 36 of 61
5 4 3 2 1
5 4 3 2 1
+5VALW TO +5V_3DCAM
+5VALW +5V_CAM
JP10
Always Open
1 1 2 1
0.1U_0402_10V6K
12P_0402_50V8J
1U_0402_6.3V6K
JP10 JP@
CX2
CX13
12P_0402_50V8J
CX12
CX1
@RF@ 3D@ 1 2 3D@ @RF@
D 1 2 D
2 2 JUMP_43X39 1 2
+3VS
RX1 1 @3D@ 2 10K_0402_5% UX1 3D@
+3VALW_PCH 1 7
RX2 1 3D@ 2 10K_0402_5% 2 VIN VOUT 8
VIN VOUT
3 6
[9,25] 3D_CAM_EN ON CT
1
1
RX3 4 3D@ CX3
100K_0402_5% 3D@ VBIAS 5 2200P_0402_25V7K
GND 9 2
GND
2
CT pin use 2200pf for
TPS22967DSGR_SON8_2X2
soft start tuning
3D@
0.01U_0402_16V7K 1 2 CX4 LX2 3D@EMI@
3 2
0.1U_0402_10V6K 1 2 CX5 3 2
UX2 3D@
3D@ 1 7 RX5 1 3D@ 2 4.99K_0402_1% 4 1 +5V_CAM
13 VCC NC 24 RX6 1 @3D@ 2 0_0402_5% 4 1
C C
3D@ VCC NC MCF12102G900-T_4P
CX6 1 2 0.1U_0402_10V6K USB3_CRX_C_RD_DTX_N3 11 20 USB3_CRX_RD_DTX_N3 J3D1 CONN@
[10] USB3_CRX_DTX_N3 CX7 1 2 0.1U_0402_10V6K USB3_CRX_C_RD_DTX_P3 12 TX2- RX2- 19 USB3_CRX_RD_DTX_P3 RX8 1 @EMI@ 2 0_0402_5% 1
[10] USB3_CRX_DTX_P3 TX2+ RX2+ USB3_CRX_L_DTX_N3 USB3_CTX_L_DRX_N3 2 1
3D@ USB3_OS2_P0 15 USB3_CRX_L_DTX_P3 USB3_CTX_L_DRX_P3 3 2
USB3_DE2_P0 16 OS2 5 USB3_ERD_P0 USB3_CTX_L_DRX_N3 4 3
USB3_EQ2_P0 17 DE2 EN_RXD 14 USB3_CM_P0 USB3_CTX_L_DRX_P3 USB3_CRX_L_DTX_N3 5 4
3D@ EQ2 CM 3D@ USB3_CRX_L_DTX_P3 6 5
CX8 1 2 0.1U_0402_10V6K USB3_CTX_C_RD_DRX_N3 8 23 USB3_CTX_RD_DRX_N3 CX11 1 2 0.1U_0402_10V6K RX4 1 @EMI@ 2 0_0402_5% 7 6
[10] USB3_CTX_DRX_N3 RX1- TX1- [9] CAM_DETECT# 7
CX10 1 2 0.1U_0402_10V6K USB3_CTX_C_RD_DRX_P3 9 22 USB3_CTX_RD_DRX_P3 CX9 1 2 0.1U_0402_10V6K 8
[10] USB3_CTX_DRX_P3 RX1+ TX1+ 9 8
3D@ USB3_OS1_P0 4 3D@ MCF12102G900-T_4P 10 9
USB3_DE1_P0 3 OS1 6 USB3_P0_PIN6 USB3_CTX_C_DRX_N3 3 2 11 10
USB3_EQ1_P0 2 DE1 GND 10 3 2 12 GND
EQ1 GND 18 USB3_P0_PIN18 GND
25 GND 21 USB3_CTX_C_DRX_P3 4 1 ACES_50463-0104A-001
PGND GND 4 1 SP01001G000
LX1 3D@EMI@
PS8713BTQFN24GTR2-A0_TQFN24_4X4
SN65LVPE502CPRGER_VQFN24_4X4-S RX7 1 @EMI@ 2 0_0402_5%
+3VS
+3VS RX10 1 @3D@ 2 10K_0402_5%
DX1 @ESD@
RX16 1 @3D@ 2 4.7K_0402_5% USB3_CTX_L_DRX_N3 1 10 USB3_CTX_L_DRX_N3
RX17 1 @3D@ 2 4.7K_0402_5% USB3_CM_P0
USB3_CTX_L_DRX_P3 2 9 USB3_CTX_L_DRX_P3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3D CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 37 of 61
5 4 3 2 1
5 4 3 2 1
CPU
VCCST_PWRGD
+VCC_CORE 2 +RTC_CELL
PCH
10a VCCST_PWRGD VCC VCCRTC
SLP_SUS#
D +1.0VS_VCCIO D
VCCPGPPG
VCCATS
+1.0V_PRIM
+1.0V_PRIM SIO_SLP_S4#
8
VCCPRIM_CORE SLP_S4# TPS22967 +1.0V_VCCST
PCH_PLTRST#
+3VALW 8a
13 PLTRST#
RT9059GSP +2.5V_MEM
Power Button
+19VB
1BAT 2AC +1.2V_DDR VDDQ
+19VB RT8207 DDR4
ADAPTER 2 +0.6V_DDR_VTT
VTT
EC 1404 ALWON
VL 11
+5VALW PGOOD
SY8286 0.675V_DDR_VTT_ON
+3VLP
+3VALW +19VB 1.2V_VTT_PWRGD
9a
BATTERY
POK SY8286 +1.0V_PRIM
+3VALW 4
B B
+5VALW
POK SY8032 +1.8V_PRIM
SLP_S3#
SIO_SLP_S3# 9
+5VS
EM5209VF
+3VS
SIO_PWRBTN# ME_SUS_PWR_ACK
5a
6 +3VALW
5b +1.0V_PRIM 9a
PCH_RSMRST#
TPS22961 +1.0V_VCCSTG
+1.0VS_VCCIO
SIO_SLP_S4#
8
SIO_SLP_S3#
9
10 +PWR_SRC
RUNPWROK IMVP_VR_ON
10 +VCC_SA
ISL95857 +VCC_CORE
PCH_PLTRST#_EC +VCC_GT
RESET_OUT# 14
11
A A
DELL CONFIDENTIAL/PROPRIETARY
D D
C C
@ CZ31 0.1U_0402_10V7K
CZ29 2 1 1 2
1U_0402_6.3V6K
1
UZ5 DIS@
14 +0.95VSDGPU_OUT 1
JP7 PJP@
2
2300mA
+1.0V_PRIM
2 VIN1 VOUT1 13 1 2 +0.95VSDGPU JP7
VIN1 VOUT1
DGPU_PWR_EN RZ7 1 DIS@ 2 10K_0402_5% +0.95VSDGPU_ON 3 12 2
CZ18 DIS@
1 330P_0402_50V7K
JUMP_43X118 Always Short
@ ON1 CT1
+5VALW
CZ15 1DIS@ 2 0.1U_0402_16V7K CZ30 2 1 4 11
0.1U_0402_10V7K VBIAS GND
RZ8 1 DIS@ 2 10K_0402_5% +1.8VGS_GPU_ON 5 10 2 1 CZ19 DIS@
ON2 CT2 330P_0402_50V7K JP8 PJP@
CZ16 1DIS@ 2 0.1U_0402_16V7K 6 9 +1.8VGS_OUT 1 2
+1.8V_PRIM
7 VIN2
VIN2
VOUT2
VOUT2
8
+1.8VGS
500mA
@
1
15 2 PAD-OPEN1x2m JP8
GPAD
CZ17
1U_0402_6.3V6K EM5209VF_DFN14_3X2 CZ20
Always Short
2
0.1U_0402_10V7K
1
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GPU Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D805P
Date: Tuesday, June 21, 2016 Sheet 39 of 61
5 4 3 2 1
1 2 3 4 5
PEG_HTX_C_GRX_P[0..3]
[10] PEG_HTX_C_GRX_P[0..3]
PEG_HTX_C_GRX_N[0..3] No Use GPU Display Port outpud
[10] PEG_HTX_C_GRX_N[0..3]
PEG_GTX_C_HRX_P[0..3] @
[10] PEG_GTX_C_HRX_P[0..3]
UV1F
PEG_GTX_C_HRX_N[0..3] +VGA_CORE
[10] PEG_GTX_C_HRX_N[0..3]
@ AB11
UV1A VARY_BL AB12
DIGON
A A
AL15
TXCAP_DPA3P AK14
PEG_HTX_C_GRX_P0 DIS@ 2 1 CV312 0.22U_0402_16V7K PEG_HTX_GRX_P0 AF30 AH30 PEG_GTX_HRX_P0 DIS@ 2 1 CV1 0.22U_0402_16V7K PEG_GTX_C_HRX_P0 TXCAM_DPA3N
PEG_HTX_C_GRX_N0 DIS@ 2 1 CV306 0.22U_0402_16V7K PEG_HTX_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PEG_GTX_HRX_N0 DIS@ 2 1 CV2 0.22U_0402_16V7K PEG_GTX_C_HRX_N0 AH16
PCIE_RX0N PCIE_TX0N TX0P_DPA2P AJ15
TX0M_DPA2N
PEG_HTX_C_GRX_P1 DIS@ 2 1 CV308 0.22U_0402_16V7K PEG_HTX_GRX_P1 AE29 AG29 PEG_GTX_HRX_P1 DIS@ 2 1 CV3 0.22U_0402_16V7K PEG_GTX_C_HRX_P1 AL17
PEG_HTX_C_GRX_N1 DIS@ 2 1 CV305 0.22U_0402_16V7K PEG_HTX_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PEG_GTX_HRX_N1 DIS@ 2 1 CV4 0.22U_0402_16V7K PEG_GTX_C_HRX_N1 TX1P_DPA1P AK16
PCIE_RX1N PCIE_TX1N TX1M_DPA1N
AH18
PEG_HTX_C_GRX_P2 DIS@ 2 1 CV307 0.22U_0402_16V7K PEG_HTX_GRX_P2 AD30 AF27 PEG_GTX_HRX_P2 DIS@ 2 1 CV5 0.22U_0402_16V7K PEG_GTX_C_HRX_P2 TX2P_DPA0P AJ17
PEG_HTX_C_GRX_N2 DIS@ 2 1 CV309 0.22U_0402_16V7K PEG_HTX_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PEG_GTX_HRX_N2 DIS@ 2 1 CV6 0.22U_0402_16V7K PEG_GTX_C_HRX_N2 TX2M_DPA0N
PCIE_RX2N PCIE_TX2N AL19
NC_TXOUT_L3P AK18
PEG_HTX_C_GRX_P3 DIS@ 2 1 CV313 0.22U_0402_16V7K PEG_HTX_GRX_P3 AC29 AD27 PEG_GTX_HRX_P3 DIS@ 2 1 CV7 0.22U_0402_16V7K PEG_GTX_C_HRX_P3 NC_TXOUT_L3N
PEG_HTX_C_GRX_N3 DIS@ 2 1 CV304 0.22U_0402_16V7K PEG_HTX_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PEG_GTX_HRX_N3 DIS@ 2 1 CV8 0.22U_0402_16V7K PEG_GTX_C_HRX_N3
PCIE_RX3N PCIE_TX3N TMDP
P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23
N29 P27
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26
M30 P24
L31 NC#M30 NC#P24 P23
NC#L31 NC#P23
L29 M27
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26
C CLOCK C
CLK_PEG_VGA AK30
[11] CLK_PEG_VGA CLK_PEG_VGA# PCIE_REFCLKP
AK32
[11] CLK_PEG_VGA# PCIE_REFCLKN +0.95VSDGPU
CALIBRATION
Y22 RV1 1 DIS@ 2 1.69K_0402_1%
PCIE_CALR_TX
RV2 1 DIS@ 2 1K_0402_1% N10 AA22 RV3 1 DIS@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX
PLT_RST_VGA# AL27
PERSTB
2160856030-A0_FCBGA631
+3VGS
UV2
DIS@
5
PLT_RST#
1
P
DGPU_HOLD_RST#(GPP_D10)
3
RV4
MC74VHC1G08DFT2G_SC70-5 100K_0402_5%
D D
DIS@
2
+3VGS
@
Resistor Divider Lookup Lable
UV1B +1.8VGS
U? 0402 1% resistors are equired PS_0[3:1]L001 Strap Name :
R_pu (ohm) R_pd (ohm) Bitd [3:1] PS_0[5:4]L11
1
RV5 RV6 AF2
PS_0[1] ROM_CONFIG[0]
NC#AF2
5
45.3K_0402_1% AF4 RV8
45.3K_0402_1% NC 4.75k 000 PS_0[2] ROM_CONFIG[1]
G
QV1B DIS@ DIS@ NC#AF4 8.45K_0402_1%
DIS@ TP50 N9 AG3 DIS@
8.45k 2k 001 PS_0[3] ROM_CONFIG[2]
2
TP51 L9 DBG_DATA16 NC#AG3 AG5 PS_0
3 4 VGA_SMB_DA3 TP52 AE9 DBG_DATA15 NC#AG5
DPA 4.53k 2k 010 PS_0[4] N/A
S
[8,25,30] SML1DATA DBG_DATA14
1
Y11 AH3
0.68U_0402_10V
TP53
D
DBG_DATA13 NC#AH3 1
TP54 AE8 AH1 6.98k 4.99k 011 PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
DBG_DATA12 NC#AH1
2
DMN66D0LDW-7 2N SOT363-6 TP55 AD9 CV29 RV9
G
SML1DATA => GPU_THM_SMBDAT QV1A TP56 AC10 DBG_DATA11 AK3 @ 2K_0402_1%
SML1CLK => GPU_THM_SMBCLK DIS@ TP57 AD7 DBG_DATA10 NC#AK3 AK1
4.53k 4.99k 100 2 DIS@
2
TP58 AC8 DBG_DATA9 NC#AK1
A
6 1 VGA_SMB_CK3 TP59 AC7 DBG_DATA8 DVO
AK5
3.24k 5.62k 101 A
S
[8,25,30] SML1CLK AB9 DBG_DATA7 NC#AK5 AM3
TP60
D
TP61 AB8 DBG_DATA6 NC#AM3 3.4k 10k 110
DMN66D0LDW-7 2N SOT363-6 TP62 AB7 DBG_DATA5 AK6
TP63 AB4 DBG_DATA4 NC#AK6 AM5
4.75k NC 111
TP64 AB2 DBG_DATA3 NC#AM5
DPB
TP65 Y8 DBG_DATA2 AJ7
TP66 Y7 DBG_DATA1 NC#AJ7 AH6 +1.8VGS Strap Name :
DBG_DATA0 NC#AH6 PS_1[3:1]L001
AK8
Capacitor Divider Lookup Lable
NC#AK8 PS_1[5:4]L11 PS_1[1] STRAP_BIF_GEN3_EN_A
1
AL7
NC#AL7 DIS@
Cap (nF) Bitd [5:4] RV11
PS_1[2] TRAP_BIF_CLK_PM_EN
W6 8.45K_0402_1% PS_1[3] N/A
V6 NC#W 6
680nF 00
2
NC#V6 V4 PS_1
AC6 NC#V4 U5
PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING
NC#AC5 NC#U5 82nF 01
1
AC5
0.68U_0402_10V
NC#AC6 W3
1
DIS@
PS_1[5] STRAP_TX_DEEMPH_EN
AA5 NC#W 3 V2
10nF 10 CV28 RV12
AA6 NC#AA5 NC#V2 @ 2K_0402_1%
NC#AA6 DPC
Y4
NC 11 2
2
+1.8VGS NC#Y4 W5
NC#W 5
RV82 2 DIS@ 1 4.7K_0402_5% BP_0 U1 AA3 PLL_Analog_out
TP67 FB_VDDCI W1 NC#U1 NC#AA3 Y2
NC#W 1 NC#Y2
1
RV81 2 DIS@ 1 4.7K_0402_5% BP_1 U3
Y6 NC#U3 J8 RV83
TP68 PLL_Analog_in AA1 NC#Y6 NC#J8 16.2K_0402_1% +1.8VGS
NC#AA1 DIS@
PS_2[3:1]L000 Strap Name :
PS_2[5:4]L11
1
@
PS_2[1] N/A
I2C RV28 PS_2[2] N/A
8.45K_0402_1%
TP69 R1 PS_2[3] STRAP_BIOS_ROM_EN
2
TP70 R3 SCL PS_2
SDA
PS_2[4] STRAP_BIF_VGA_DIS
1
AM26
0.082U_0402_16V
R 1
+VGA_CORE AK26
U6
GENERAL PURPOSE I/O AVSSN#AK26 +3VGS CV11 RV13
PS_2[5] N/A
U10 GPIO_0 AL25 @ 4.75K_0402_1%
T10 GPIO_1 G AJ25 2 DIS@
2
GPIO_2 AVSSN#AJ25
1
RV260 2 DIS@ 1 4.7K_0402_5% VGA_SMB_DA3 U8
B +3VGS VGA_SMB_CK3 SMBDATA B
U7 AH24 RV162
T9 SMBCLK B AG25 4.7K_0402_5%
[25] GPU_PWR_LEVEL GPIO_5_AC_BATT AVSSN#AG25
T8 @
T7 GPIO_6 DAC1 AH26
2
P10 GPIO_7_BLON HSYNC AJ27 WAKEB
P4 GPIO_8_ROMSO VSYNC
GPIO_9_ROMSI
1
P2 +1.8VGS
N6 GPIO_10_ROMSCK AD22 RV163
PS_3[3:1]L000 Strap Name :
+VGA_CORE N5 GPIO_11 RSET 4.7K_0402_5%
GPIO_12 PS_3[5:4]L11
1
N3 AG24 DIS@ PS_3[1] BOARD_CONFIG[0] (Memory ID)
Y9 GPIO_13 AVDD AE22 @
VRAM Type
2
+1.8VGS N1 GPIO_14_HPD2 AVSSQ RV15 PS_3[2] BOARD_CONFIG[1] (Memory ID)
JTAG M4
R6
GPIO_15_PW RCNTL_0
GPIO_16 VDD1DI
AE23
AD23
8.45K_0402_1%
PS_3[3] BOARD_CONFIG[2] (Memory ID)
Need reference
X76 Schematic
2
RV152 @ W 10 GPIO_17_THERMAL_INT VSS1DI PS_3
2 1 GPIO19_CTF GPIO19_CTF M2 GPIO_18
GPIO_19_CTF FutureASIC/SEYMOUR/PARK PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
1
+3VGS P8 AM12
0.68U_0402_10V
GPIO_20_PW RCNTL_1 CEC_1 1
10K_0402_5% P7 @
GPIO_21 PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
2
1 @ 2 N8 CV15 RV16
RV154 1 @ 2 5.1K_0402_1% RV151 RV368 10K_0402_5% AK10 GPIO_22_ROMCSB AK12 RV155 1 @ 2 0_0402_5% SVI2_SVD @ 4.75K_0402_1%
AM10 GPIO_29 RSVD#AK12 AL11 1 2 0_0402_5% SVI2_SVT SVI2_SVD [59] 2
10K_0402_5% RV156 @ SD034475180
SVI2_SVT [59]
2
DIS@ 1 @ 2 PEG_CLKREQ#_G N7 GPIO_30 RSVD#AL11 AJ11 RV157 1 @ 2 0_0402_5% SVI2_SVC
[11] PEG_CLKREQ# CLKREQB RSVD#AJ11 SVI2_SVC [59]
RV17 1 DIS@ 2 1K_0402_1% TESTEN RV153 0_0402_5%
1
JTAG_TRSTB L6
JTAG_TDI_GPU L5 JTAG_TRSTB
JTAG_TCK L3 JTAG_TDI
JTAG_TMS_GPU L1 JTAG_TCK AL13
JTAG_TDO_GPU K4 JTAG_TMS GENLK_CLK AJ13
TESTEN K7 JTAG_TDO GENLK_VSYNC
+3VGS AF24 TESTEN
+VGA_CORE NC#AF24 AG13
@ SW APLOCKA AH12
1 8 JTAG_TDO_GPU AB13 SW APLOCKB
2 7 JTAG_TDI_GPU W8 GENERICA
3 6 JTAG_TMS_GPU W9 GENERICB
4 5 JTAG_TRSTB W7 GENERICC AC19 PS_0
AD10 GENERICD PS_0
RP34 10K_8P4R_5% AJ9 GENERICE AD19 PS_1
TP72 AL9 NC#AJ9 PS_1
NC#AL9 AE17 PS_2
AC14 PS_2
TP73 PX_EN AB16 HPD1 AE20 PS_3
2 @ 1 JTAG_TCK PX_EN PS_3
RV369 10K_0402_5%
C AE19 C
AC16 TS_A
DBG_VREFG
DDC/AUX
AE6
PLL/CLOCK DDC1CLK AE5
DDC1DATA
AD2
RV20 DIS@ AUX1P AD4 +VGA_CORE
1M_0402_5% AUX1N
XTALOUT XTALIN AC11
DDC2CLK AC13
YV1 DIS@ DDC2DATA
27MHZ_10PF_7V27000050 XTALIN AM28 AD13
XTALOUT AK28 XTALIN AUX2P AD11
3 1 XTALOUT AUX2N
3 1 RV29 1 DIS@ 2 10K_0402_5% AC22 AD20 FB_GND RV158 1 @ 2 0_0402_5% VSSSENSE_VGA VSSSENSE_VGA [59]
1 GND GND 1 XO_IN NC#AD20
CV18 CV17 RV59 1 DIS@ 2 10K_0402_5% AB22 AC20 FB_VDDC RV159 1 @ 2 0_0402_5% VCCSENSE_VGA VCCSENSE_VGA [59]
10P_0402_50V8J 10P_0402_50V8J XO_IN2 NC#AC20
DIS@ 4 2 DIS@ AE16
2 2 NC#AE16 AD16
NC#AD16
SEYMOUR/FutureASIC AC1
+1.8VGS T4
DPLUS THERMAL
DDCVGACLK
DDCVGADATA
AC3 +1.8VGS M1-70 use +1.8v
LV2 DIS@ T2
1 2 13mA DMINUS
BLM15BD121SN1D_0402
DIS@ GPIO28 R5
Change CV17, CV18 for YV1 frequency deviation CV19 2 1 10U_0603_6.3V6M +TSVDD AD17 GPIO28_FDO
Eason 2/19 DIS@ AC17 TSVDD
TSVSS
2
CV20 2 1 1U_0402_6.3V4Z
DIS@ @
CV21 2 1 0.1U_0402_10V6K RV84 RV87
216-0842024-A11-MAR_FCBGA631 10K_0402_5% 10K_0402_5% Boot-VID Code
RV21 1 @ 2 10K_0402_5% ? DIS@
Voltage
1
TOPAZ Thermal Address-->0x82 SVC SVD
SVI2_SVD
Selected (V)
Enable MLPS SVI2_SVC
0 0 1.1
0 1 1.0
2
D D
@ RV88 1 0 0.9
RV89 10K_0402_5%
10K_0402_5% DIS@ 1 1 0.8
1
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2015/07/09 Deciphered Date 2016/07/31 MESO_(2/5)_MSIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom A00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-D801P
Tuesday, June 21, 2016 Sheet 41 of 61
1 2 3 4 5
1 2 3 4 5
A A
@
UV1E U?
AA27 A3
370mA (HDMI) No Use GPU Display Port outpud AB24 GND GND A30
GND GND
+1.8VGS
188mA (Display Port) @ AB32
AC24 GND GND
AA13
AA16
RV27 2 @ 1 0_0603_5% +DP_VDDR UV1G AC26 GND GND AB10
U? GND GND
AC27 AB15
B GND GND B
CV26
CV27
CV35
DP POWER NC/DP POWER AD25 AB6
AD32 GND GND AC9
1 1 1 GND GND
AG15 AE11 AE27 AD6
@ @ @ AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
AF16 DP_VDDR#AG16 NC#AF11 AE13 AG27 GND GND AE7
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 AG17 DP_VDDR#AF16 NC#AE13 AF13 AH32 GND GND AG12
AG18 DP_VDDR#AG17 NC#AF13 AG8 K28 GND GND AH10
AG19 DP_VDDR#AG18 NC#AG8 AG10 K32 GND GND AH28
AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
DP_VDDR#AF14 M32 GND GND B12
N25 GND GND B14
N27 GND GND B16
P25 GND GND B18
AG20 AF6 P32 GND GND B20
AG21 DP_VDDC#AG20 NC#AF6 AF7 R27 GND GND B22
+0.95VSDGPU AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
280mA AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
RV30 2 @ 1 0_0603_5% +DP_VDDC AD14 DP_VDDC#AG22 NC#AF9 U25 GND GND B6
DP_VDDC#AD14 U27 GND GND B8
GND GND
CV30
CV33
CV34
V32 C1
W25 GND GND C32
1 1 1 GND GND
AG14 AE1 W26 E28
@ @ @ AH14 DP_VSSR NC#AE1 AE3 W27 GND GND F10
AM14 DP_VSSR NC#AE3 AG1 Y25 GND GND F12
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 AM16 DP_VSSR NC#AG1 AG6 Y32 GND GND F14
AM18 DP_VSSR NC#AG6 AH5 GND GND F16
AF23 DP_VSSR NC#AH5 AF10 GND F18
AG23 DP_VSSR NC#AF10 AG9 GND F2
AM20 DP_VSSR NC#AG9 AH8 GND F20
AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
AF19 DP_VSSR NC#AM8 AG7 N16 GND GND F26
AF20 DP_VSSR NC#AG7 AG11 N18 GND GND F6
AE14 DP_VSSR NC#AG11 N21 GND GND
GND F8
DP_VSSR P6 GND GND G10
C C
P9 GND GND G27
R12 GND GND G31
AF17 AE10 R15 GND GND G8
DPAB_CALR NC#AE10 R17 GND GND H14
R20 GND GND H17
T13 GND GND H2
T16 GND GND H20
216-0842024-A11-MAR_FCBGA631 GND GND
? T18 H6
T21 GND GND J27
T6 GND GND J31
U15 GND GND K11
U17 GND GND K2
U20 GND GND K22
U9 GND GND K6
V13 GND GND
V16 GND
V18 GND
Y10 GND
Y15 GND
Y17 GND
Y20 GND
R11 GND A32
T11 GND VSS_MECH AM1
AA11 GND VSS_MECH AM32
M12 GND VSS_MECH
N11 GND
V11 GND
GND
216-0842024-A11-MAR_FCBGA631
?
D D
A
+VGA_CORE 10uF 1uF 0.1uF A
VDDC TBD 4 30 0 @
UV1D +1.8VGS
+1.35V_MEM_GFX
U?
100mA
AM30 +PCIE_PVDD
VDDCI 3.5A 1 3 3 1.5A PCIE_PVDD
PCIE
MEM I/O
CV38
CV46
CV39
0.01U_0402_16V7K CV179
H13 AB23 1 1 1 1
H16 VDDR1 NC#AB23 AC23
VDDR1 NC#AC23
CV43
CV44
CV45
CV40
CV47
CV48
CV41
CV42
CV49
CV50
CV51
CV52
CV53
H19 AD24 DIS@ DIS@ DIS@ DIS@
J10 VDDR1 NC#AD24 AE24
0.01U_0402_16V7K CV174
0.01U_0402_16V7K CV175
0.01U_0402_16V7K CV176
0.01U_0402_16V7K CV177
0.01U_0402_16V7K CV178
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDDR1 NC#AE24 2 2 2 2
J23 AE25
+0.95VSDGPU 10uF 1uF 0.1uF DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ DIS@ DIS@ DIS@ DIS@
J24 VDDR1 NC#AE25 AE26
J9 VDDR1 NC#AE26 AF25
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 K10 VDDR1 NC#AF25 AG26
K23 VDDR1 NC#AG26
PCIE_VDDC 2.5A 2 7 0 K24 VDDR1
K9 VDDR1 L23
L11 VDDR1 PCIE_VDDC L24
L12 VDDR1 PCIE_VDDC L25
BIF_VDDC 1.4A 1 2 0 L13 VDDR1 PCIE_VDDC L26
L20 VDDR1 PCIE_VDDC M22 +0.95VSDGPU
L21 VDDR1 PCIE_VDDC N22 2.5A
L22 VDDR1 PCIE_VDDC N23 +PCIE_VDDC 2 @ 1
SPLL_VDDC 100mA 1 1 1 VDDR1 PCIE_VDDC
CV54
CV55
CV56
CV57
CV58
CV59
CV60
N24
CV120
CV121
RV364 0_0603_5%
PCIE_VDDC R22
PCIE_VDDC 1 1 1 1 1 1 1 1 1
T22
+1.8VGS 13mA LEVEL PCIE_VDDC U22 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
LV3 DIS@ TRANSLATION PCIE_VDDC V22
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 2 +VDD_CT AA20 PCIE_VDDC 2 2 2 2 2 2 2 2 2
+1.35V_MEM_GFX 10uF 2.2uF 0.1uF 0.01uF BLM15BD121SN1D_0402 AA21 VDD_CT
VDD_CT
CV61
CV62
CV63
AB20 AA15
B
AB21 VDD_CT CORE VDDC N15 B
1 1 1 VDD_CT VDDC N17
VDDR1 1.5A 3 5 5 5 DIS@ DIS@ DIS@ +3VGS VDDC R13
LV4 DIS@ 25mA I/O VDDC R16
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 1 2 +VDDR3 AA17 VDDC R18
BLM15BD121SN1D_0402 AA18 VDDR3 VDDC Y21
VDDR3 VDDC
CV123
CV64
CV65
CV66
AB17 T12
AB18 VDDR3 VDDC T15 +VGA_CORE
+1.8VGS 10uF 1uF 0.1uF 1 1 1 1 VDDR3 VDDC T17 TBD
DIS@ DIS@ DIS@ DIS@ V12 VDDC T20
VDDR4 VDDC
CV67
CV68
CV69
CV70
CV71
CV72
CV73
CV74
CV75
CV76
CV77
CV78
CV79
CV80
Y12 U13
10U_0402_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 U12 VDDR4 VDDC U16
PCIE_PVDD 100mA 1 1 1 VDDR4 VDDC U18
1 1 1 1 1 1 1 1 1 1 1 1 1 1
VDDC V21 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
VDDC V15
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VDDC V17 2 2 2 2 2 2 2 2 2 2 2 2 2 2
MPLL_PVDD 130mA 1 1 1 VDDC V20
VDDC
POWER
Y13
VDDC Y16
VDDC Y18
SPLL_PVDD 75mA 1 1 1 VDDC AA12
VDDC M11
VDDC N12
VDDC U11
VDDR4 (300mA) 0 0 0 CIS SYMBOL VDDC
CV101
CV104
CV100
CV106
CV103
CV109
CV102
CV107
CV108
CV105
+1.8VGS
LV6 DIS@ 130mA PLL
1 1 1 1 1 1 1 1 1 1
1 2 +MPLL_PVDD DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
VDD_CT 13mA 1 1 1
CV81
CV82
CV124
BLM15BD221SN1D_2P
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2 2
1 1 1
R21 1.4A
DIS@ DIS@ DIS@ BIF_VDDC U21 +BIF_VDDC
+TSVDD 13mA 1 1 1 BIF_VDDC
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 L8
+1.8VGS MPLL_PVDD
C
LV7 DIS@ 75mA C
+DP_VDDR 0 0 0 1 2 +SPLL_PVDD
ISOLATED
CORE I/O
CV84
CV85
CV111
CV114
CV110
CV117
CV113
CV118
CV112
CV116
CV119
CV115
+DP_VDDC 0 0 0 DIS@ DIS@ DIS@ VDDCI M17 1 1 1 1 1 1 1 1 1 1
+0.95VSDGPU VDDCI M18
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 LV8 DIS@ 100mA VDDCI M20 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
1 2 +SPLL_VDDC H8 VDDCI M21
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
SPLL_VDDC VDDCI 2 2 2 2 2 2 2 2 2 2
CV91
CV92
CV93
BLM15BD121SN1D_0402 N20
J7 VDDCI
+3VGS 10uF 1uF 0.1uF 1 1 1 SPLL_PVSS
DIS@ DIS@ DIS@
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2
VDDR3 25mA 1 3 0 216-0842024-A11-MAR_FCBGA631
?
+0.95VSDGPU
+BIF_VDDC 2 @ 1
RV31 0_0603_5%
+VGA_CORE
CV122
CV181
CV180
1 2 2
3.5A (DDR3)
CV88
CV89
CV90
CV87
CV125
CV126
CV127
DIS@ DIS@ DIS@
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 1 1 1 1 1 1 1 1 1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 2 2 2
D D
M_DA[63..0]
[45,46] M_DA[63..0]
M0_MA[8..0]
[45] M0_MA[8..0]
A A
M1_MA[8..0]
[46] M1_MA[8..0] @
UV1C U?
GDDR5/DDR3 GDDR5/DDR3
M_DA0 K27 K17 M0_MA0
M_DA1 J29 DQA0_0 MAA0_0/MAA_0 J20 M0_MA1
M_DA2 H30 DQA0_1 MAA0_1/MAA_1 H23 M0_MA2
M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M0_MA3
M_DA4 G29 DQA0_3 MAA0_3/MAA_3 G24 M0_MA4
M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M0_MA5
M_DA6 F32 DQA0_5 MAA0_5/MAA_5 J19 M0_MA6
+1.35V_MEM_GFX +1.35V_MEM_GFX M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M0_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M0_MA8
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
DQA0_10
1
1
M_DA11 C28 J14 M1_MA0
M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M1_MA1
RV33 RV32 M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M1_MA2
40.2_0402_1% 40.2_0402_1% M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M1_MA3
DIS@ DIS@ M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M1_MA4
2
MEMORY INTERFACE
M_DA21 F23 DQA0_20 MAA1_9/RSVD
RV34 CV94 RV35 CV95 M_DA22 D22 DQA0_21 E32 M_WCKA0_0
100_0402_1% 1U_0402_6.3V4Z 100_0402_1% 1U_0402_6.3V4Z M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_WCKA0_0# M_WCKA0_0 [45]
DIS@ 2 DIS@ DIS@ 2 DIS@ M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_WCKA0_1 M_WCKA0_0# [45]
2
D D
5.49K_0402_1%
G13 T12
VDDQ VDDQ
1
1 H1 L13 G13
VSS VDDQ VDDQ
CV394 DIS@
RV53 DIS@
K1 B14 H1 L13
B5 VSS VDDQ D14 K1 VSS VDDQ B14
G5 VSS VDDQ F14 B5 VSS VDDQ D14
2 L5 VSS VDDQ M14 G5 VSS VDDQ F14
2
H2 U1
VSSQ VSSQ
1
B
G1 K2 H2 B
VDD VSSQ VSSQ
RV54 DIS@
L1 A3 G1 K2
G4 VDD VSSQ C3 L1 VDD VSSQ A3
L4 VDD VSSQ E3 G4 VDD VSSQ C3
C5 VDD VSSQ N3 L4 VDD VSSQ E3
2
5.49K_0402_1%
1 L11 M5 G11 F5
VDD VSSQ VDD VSSQ
CV395 DIS@
RV55 DIS@
CV198
CV213
CV230
CV235
CV233
CV210
CV211
CV157
CV155
CV158
L14 C11 G14 M10
2 VDD VSSQ R11 L14 VDD VSSQ C11
1 1 1 1 1 1 1 1 1 1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
VSSQ R12 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ VSSQ N12
170-BALL VSSQ U12 VSSQ R12
VSSQ H13 170-BALL VSSQ U12
SGRAM GDDR5 VSSQ K13 VSSQ H13
VSSQ A14 SGRAM GDDR5 VSSQ K13
VSSQ C14 VSSQ A14
VSSQ E14 VSSQ C14
VSSQ N14 VSSQ E14
VSSQ R14 VSSQ N14
VSSQ U14 VSSQ R14
VSSQ Stitching Caps OPTION for MEM signals that have a change of reference plane voltage VSSQ U14
H5GC4H24AJR-R0C_BGA170 Add stitching caps when required, one cap per three signals VSSQ
H5GC4H24AJR-R0C_BGA170
+1.35V_MEM_GFX
CV238
CV248
CV243
CV242
CV247
CV342
CV344
CV343
CV341
A A
1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MESO_GDDR5_A0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 45 of 61
5 4 3 2 1
5 4 3 2 1
MF=0
UV14 @
M_DA[32..63]
UV15 @ MF=1
MF=0 MF=1 MF=1 MF=0
[44] M_DA[32..63] MF=0 MF=1 MF=1 MF=0
A4 M_DA41
M_EDC_5 C2 DQ24 DQ0 A2 M_DA42 A4 M_DA60
[44] M_EDC_5 EDC0 EDC3 DQ25 DQ1 M_DA43 M_EDC_7 DQ24 DQ0 M_DA62
C13 B4 C2 A2
M_EDC_6 EDC1 EDC2 DQ26 DQ2 M_DA40 [44] M_EDC_7 EDC0 EDC3 DQ25 DQ1 M_DA63
R13 B2 C13 B4
[44] M_EDC_6 EDC2 EDC1 DQ27 DQ3 M_DA47 M_EDC_4 EDC1 EDC2 DQ26 DQ2 M_DA61
R2 L E4 L R13 B2
+1.35V_MEM_GFX +1.35V_MEM_GFX EDC3 EDC0 DQ28 DQ4 M_DA44 [44] M_EDC_4 EDC2 EDC1 DQ27 DQ3 M_DA57
E2 R2 H E4 H
BYTE0 DQ29 DQ5 F4 M_DA46 BYTE1 +1.35V_MEM_GFX EDC3 EDC0 DQ28 DQ4 E2 M_DA58
M_DBI5# D2 DQ30 DQ6 F2 M_DA45 BYTE3 DQ29 DQ5 F4 M_DA56 BYTE3
D [44] M_DBI5# DBI0# DBI3# DQ31 DQ7 DQ30 DQ6 D
D13 A11 M_DBI7# D2 F2 M_DA59
M_DBI6# DBI1# DBI2# DQ16 DQ8 [44] M_DBI7# DBI0# DBI3# DQ31 DQ7
P13 A13 D13 A11
M_CLK1 [44] M_DBI6# DBI2# DBI1# DQ17 DQ9 M_DBI4# DBI1# DBI2# DQ16 DQ8
1 DIS@ 2 P2 B11 P13 A13
DBI3# DBI0# DQ18 DQ10 [44] M_DBI4# DBI2# DBI1# DQ17 DQ9
RV85 120_0402_1% B13 P2 B11
M_CLK1 J12 DQ19 DQ11 E11 DBI3# DBI0# DQ18 DQ10 B13
[44] M_CLK1 M_CLK#1 CK DQ20 DQ12 M_CLK1 DQ19 DQ11
J11 E13 J12 E11
M_CLK#1 [44] M_CLK#1 M_CKE1 CK# DQ21 DQ13 M_CLK#1 CK DQ20 DQ12
1 DIS@ 2 J3 F11 J11 E13
[44] M_CKE1 CKE# DQ22 DQ14 M_CKE1 CK# DQ21 DQ13
RV86 120_0402_1% F13 J3 F11
DQ23 DQ15 U11 M_DA52 CKE# DQ22 DQ14 F13
M1_MA2 H11 DQ8 DQ16 U13 M_DA54 DQ23 DQ15 U11 M_DA33
[44] M1_MA2 M1_MA5 BA0/A2 BA2/A4 DQ9 DQ17 M_DA50 M1_MA4 DQ8 DQ16 M_DA32
K10 T11 H11 U13
[44] M1_MA5 M1_MA4 BA1/A5 BA3/A3 DQ10 DQ18 M_DA55 M1_MA3 BA0/A2 BA2/A4 DQ9 DQ17 M_DA34
K11 T13 K10 T11
[44] M1_MA4 M1_MA3 BA2/A4 BA0/A2 DQ11 DQ19 M_DA49 M1_MA2 BA1/A5 BA3/A3 DQ10 DQ18 M_DA35
H10 H N11 H K11 T13
[44] M1_MA3 BA3/A3 BA1/A5 DQ12 DQ20 M_DA53 M1_MA5 BA2/A4 BA0/A2 DQ11 DQ19 M_DA36
N13 H10 L N11 L
BYTE2 DQ13 DQ21 M11 M_DA48 BYTE2 BA3/A3 BA1/A5 DQ12 DQ20 N13 M_DA39
M1_MA7 K4 DQ14 DQ22 M13 M_DA51 BYTE1 DQ13 DQ21 M11 M_DA38 BYTE0
[44] M1_MA7 M1_MA1 A8/A7 A10/A0 DQ15 DQ23 M1_MA0 DQ14 DQ22 M_DA37
H5 U4 K4 M13
[44] M1_MA1 M1_MA0 A9/A1 A11/A6 DQ0 DQ24 M1_MA6 A8/A7 A10/A0 DQ15 DQ23
H4 U2 H5 U4
[44] M1_MA0 M1_MA6 A10/A0 A8/A7 DQ1 DQ25 M1_MA7 A9/A1 A11/A6 DQ0 DQ24
K5 T4 H4 U2
[44] M1_MA6 M1_MA8 A11/A6 A9/A1 DQ2 DQ26 M1_MA1 A10/A0 A8/A7 DQ1 DQ25
J5 T2 K5 T4
[44] M1_MA8 A12/RFU/NC DQ3 DQ27 M1_MA8 A11/A6 A9/A1 DQ2 DQ26
N4 J5 T2
A5 DQ4 DQ28 N2 A12/RFU/NC DQ3 DQ27 N4
U5 VPP/NC DQ5 DQ29 M4 A5 DQ4 DQ28 N2
VPP/NC DQ6 DQ30 M2 U5 VPP/NC DQ5 DQ29 M4
DQ7 DQ31 +1.35V_MEM_GFX VPP/NC DQ6 DQ30 M2
RV116 2 DIS@ 1 1K_0402_1% J1 +1.35V_MEM_GFX DQ7 DQ31
RV118 2 DIS@ 1 1K_0402_1% J10 MF RV117 2 DIS@ 1 1K_0402_1% J1 +1.35V_MEM_GFX
RV120 2 DIS@ 1 121_0402_1% J13 SEN B1 RV119 2 DIS@ 1 1K_0402_1% J10 MF
ZQ VDDQ D1 RV121 2 DIS@ 1 121_0402_1% J13 SEN B1
VDDQ F1 ZQ VDDQ D1
M_ADBI1 J4 VDDQ M1 VDDQ F1
[44] M_ADBI1 M_RAS#1 ABI# VDDQ M_ADBI1 VDDQ
G3 P1 J4 M1
[44] M_RAS#1 M_CS1B#0 RAS# CAS# VDDQ M_CAS#1 ABI# VDDQ
G12 T1 G3 P1
[44] M_CS1B#0 M_CAS#1 CS# W E# VDDQ M_WE#1 RAS# CAS# VDDQ
L3 G2 G12 T1
[44] M_CAS#1 M_WE#1 CAS# RAS# VDDQ M_RAS#1 CS# W E# VDDQ
L12 L2 L3 G2
[44] M_WE#1 W E# CS# VDDQ M_CS1B#0 CAS# RAS# VDDQ
B3 L12 L2
VDDQ D3 W E# CS# VDDQ B3
C VDDQ VDDQ C
F3 D3
M_WCKA1_0# D5 VDDQ H3 VDDQ F3
[44] M_WCKA1_0# M_WCKA1_0 W CK01# W CK23# VDDQ M_WCKA1_1# VDDQ
D4 L K3 D5 H3
[44] M_WCKA1_0 W CK01 W CK23 VDDQ M_WCKA1_1 W CK01# W CK23# VDDQ
+1.35V_MEM_GFX M3 D4 H K3
M_WCKA1_1# P5 VDDQ P3 W CK01 W CK23 VDDQ M3
[44] M_WCKA1_1# M_WCKA1_1 W CK23# H W CK01# VDDQ M_WCKA1_0# VDDQ
P4 T3 P5 P3
[44] M_WCKA1_1 W CK23 W CK01 VDDQ M_WCKA1_0 W CK23# W CK01# L VDDQ
E5 P4 T3
VDDQ W CK23 W CK01 VDDQ
2.37K_0402_1%
N5 E5
VDDQ VDDQ
1
5.49K_0402_1%
P12 M12
VDDQ VDDQ
1
1 T12 P12
VDDQ VDDQ
CV390 DIS@
RV49 DIS@
G13 T12
H1 VDDQ L13 VDDQ G13
K1 VSS VDDQ B14 H1 VDDQ L13
2 B5 VSS VDDQ D14 K1 VSS VDDQ B14
2
K14 R1 H14 N1
VSS VSSQ VSS VSSQ
1
+1.35V_MEM_GFX U1 K14 R1
VSSQ +1.35V_MEM_GFX VSS VSSQ
RV50 DIS@
H2 U1
G1 VSSQ K2 VSSQ H2
L1 VDD VSSQ A3 G1 VSSQ K2
B VDD VSSQ VDD VSSQ B
G4 C3 L1 A3
2
5.49K_0402_1%
R10 C4 C10 U3
VDD VSSQ VDD VSSQ
1
1 D11 R4 R10 C4
VDD VSSQ VDD VSSQ
CV391 DIS@
RV51 DIS@
CV162
CV166
CV216
CV221
CV219
CV165
CV164
CV161
CV153
CV160
L14 C11 G14 M10
VDD VSSQ R11 L14 VDD VSSQ C11
VSSQ 1 1 1 1 1 1 1 1 1 1 VDD VSSQ
A12 R11
VSSQ C12 VSSQ A12
VSSQ E12 VSSQ C12
VSSQ N12 2 2 2 2 2 2 2 2 2 2 VSSQ E12
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
VSSQ R12 VSSQ N12
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
170-BALL VSSQ U12 VSSQ R12
VSSQ H13 170-BALL VSSQ U12
SGRAM GDDR5 VSSQ K13 VSSQ H13
VSSQ A14 SGRAM GDDR5 VSSQ K13
VSSQ C14 VSSQ A14
VSSQ E14 VSSQ C14
VSSQ N14 VSSQ E14
VSSQ R14 VSSQ N14
VSSQ U14 VSSQ R14
VSSQ Stitching Caps OPTION for MEM signals that have a change of reference plane voltage VSSQ U14
H5GC4H24AJR-R0C_BGA170 Add stitching caps when required, one cap per three signals VSSQ
H5GC4H24AJR-R0C_BGA170
+1.35V_MEM_GFX
CV225
CV227
CV170
CV169
CV173
CV335
CV334
CV336
CV333
A 1 1 1 1 1 1 1 1 1 A
2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MESO_GDDR5_A1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 46 of 61
5 4 3 2 1
5 4 3 2 1
Power-Up/Down Sequence 1. All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/µs.
2. It is recommended that the 3.3-V rail ramp up first.
3. It is recommended that the 0.95-V rail reach at least 90% of its nominal value
no later than 2 ms from the start of VDDC ramping up.
4. The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example
AMD PowerXpress? idle state), all the power rails are removed from the dGPU.
D The gate circuits must meet the slew rate requirement (such as ? 50 mV/µs). D
5. VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).
PCH_PLTRST#
AND PCH_PLTRST#_EC
GPU
GPP_B13
< 20mS < 20mS MCP GATE AND PLT_RST_VGA# PERSTB
GATE
VDDR3(3.3V)
>10uS
+3VGS DGPU_HOLD_RST#
(DGPU_PWR_EN) GPP_D10
PCIE_VDDC(0.95V) GPP_D13 DGPU_PWR_EN
+0.95VSDGPU
(DGPU_PWR_EN with RC delay) DGPU_PWROK
GPP_D18
1.8V_IO(1.8V)
+1.8VGS
(DGPU_PWR_EN with RC delay)
VDDC/VDDCI(0.8~1.15V)
+VGA_CORE
(DGPU_PWR_EN)
VMEMIO(1.35V or 1.5V) +3VS +3VGS
C +1.35V_MEM_GFX > 100mS > 100mS (SW) C
No requirements
B B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MESO_Note
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 47 of 61
5 4 3 2 1
5 4 3 2 1
D D
JSSD1 CONN@
30 35
+3VS 30 G5 34
29
28 29 G4 33
27 28 G3 32
26 27 G2 31
25 26 G1
24 25
23 24
[11,25,32,34,40] PCH_PLTRST#_EC 22 23
[11] SUSCLK_SSD 21 22
20 21
[11] CLK_PCIE_SSD_REQ# 19 20
[11,25,34] PCIE_WAKE# 18 19
[10] M2_SLOT2_PEDET 17 18
16 17
15 16
[10] PCIE_CRX_SSDTX_P12 14 15
[10] PCIE_CRX_SSDTX_N12 13 14
CS16 1 2 0.22U_0402_16V7K PCIE_CTX_C_SSDRX_N12 12 13
[10] PCIE_CTX_SSDRX_N12 1 2 PCIE_CTX_C_SSDRX_P12 11 12
CS17 0.22U_0402_16V7K
[10] PCIE_CTX_SSDRX_P12 10 11
9 10
[10] PCIE_CRX_SSDTX_P11 8 9
C [10] PCIE_CRX_SSDTX_N11 7 8 C
CS18 1 2 0.22U_0402_16V7K PCIE_CTX_C_SSDRX_N11 6 7
[10] PCIE_CTX_SSDRX_N11 1 2 PCIE_CTX_C_SSDRX_P11 5 6
CS19 0.22U_0402_16V7K
[10] PCIE_CTX_SSDRX_P11 4 5
3 4
[11] CLK_PCIE_SSD_N3 2 3
[11] CLK_PCIE_SSD_P3 1 2
1
ACES_50406-03071-001
"M2_SLOT2_PEDET" PU 10k on DB
0 SATA
1 PCIE
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 48 of 61
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
5 4 3 2 1
A B C D
@ PJP1
2 1
2 1
JUMP_43X79
EMI@ PL1
+19V_VIN PR4 PSID@
HCB3225KF-151T50_2P 33_0402_5%
@ PJPDC1 +19V_ADPIN 1 2 1 3 PSID-3 1 2 PS_ID [25]
S
8 PQ6 PSID@
GND 7 FDV301N_G 1N SOT23-3
GND ZT103
1000P_0402_50V7K
1000P_0402_50V7K
G
2
1
100K_0402_1%
2200P_0402_50V7K
2200P_0402_50V7K
6
6 PR8
2
5 PSID@ PR3 PSID@
5
EMI@ PC1
EMI@ PC2
EMI@ PC3
EMI@ PC4
PR6
4 PSID-2 2 1
PSID@
4 +5VALW 2.2K_0402_5%
3
3
2
3 2 @ PD4
2
2 1 1 2 10K_0402_1%
TVNST52302AB0_SOT523-3 +3VALW
1
1
1
1 EMI@ PL4 C 1
HCB3225KF-151T50_2P PSID-1 2
15K_0402_1%
ACES_50458-00601-001 B
MMST3904-7-F_SOT323
@ PJP2 E
3
PR9
2 1 @ PR11 3
PSID@
PSID@
ZT102 2 1 +5VALW
1 2 1
JUMP_43X79 PL2 2
BLM15AG102SN1D_2P
1
ZT101 100K_0402_1%
PQ5
PSID 2 1 @ PD5
EMI@
BAV99W_SC70-3
1
@ PD6
BAV99W_SC70-3
+17.4V_BATT+ @ PJP3
2 1 +17.4V_BATT++
+17.4V_BATT+
2 1
3
JUMP_43X79
EMI@ PL3
HCB3225KF-151T50_2P
1 2 +17.4V_BATT++
+5VALW
1
1000P_0402_50V7K
0.01U_0402_25V7K
1
PC8
1
EMI@ PC7
PD2 PD3
2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMI@
ESD@ ESD@
3
Battery Bot Side
3 3
3.3K_1206_5%
keep @ in BOM since battery can not till SW PROCHOT# is issued by EC
1
be removed by end user [11,25,51] ACAV_IN @ PR12 0_0402_5%
PR5
1 2
H_PROCHOT#
[12,25,51,56] H_PROCHOT# +19V_VIN +3VALW @ PR7 @
2
10K_0402_1%
3 2
1
1M_0402_1%
[11,52,54,55] POK
PR28
@ PR13 0_0402_5%
6
PR31 PC16 1 2
L2N7002DW1T1G_SC88-6
2
.1U_0402_16V7K PQ1B
L2N7002DW1T1G_SC88-6
1
PQ2A
1M_0402_1% 5
3 2
PC14 1 2 2
6
.1U_0402_16V7K @
L2N7002WT1G_SC70-3
L2N7002DW1T1G_SC88-6
4
1
D
PQ2B
100K_0402_1%
L2N7002DW1T1G_SC88-6
1
1
1
PQ3
PBAT_PRES#
PQ1A
1 2 2 @ PR10
PR29
G 5 2
1M_0402_1%
100K_0402_1%
S PR33 1M_0402_1%
3
1
1
PR2 1
@
4
1
PR32
1M_0402_1%
2
4 @ 4
2
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/03/23 Deciphered Date 2014/12/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_DCIN/BATT CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 21, 2016 Sheet 50 of 61
A B C D
A B C D
Iada=0~3.33A(65W)
Iada=0~2.30A(45W)
ADP_I = 32*Iadapter*Rsense
1 1
+19VB
L2N7002WT1G_SC70-3
1
D
PQ709
2
G
S
3
2 1 2 1
PR738 PR737
1M_0402_1% 3M_0402_5% PQ718
PR703
MDU1512RH_POWERDFN56-8-5 MDU1512RH_POWERDFN56-8-5 0.01_1206_1%
PQ740 @EMI@ PL704
1 1 1 4 1 2
2 2
2200P_0402_25V7K
5 3 3 5 2 3
1000P_0402_25V8J
1000P_0402_25V8J
1UH_PCMB053T-1R0MS_7A_20%
0.1U_0402_25V7K
+19V_VIN
EMI@
EMI@
EMI@
EMI@
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
5600P_0402_25V7K
PC764
@ PJP701
4
2
1
PC744
PC760
@ PC762
@ PC763
1 2
1 2
PC765
PC705
PC780
PC781
1
1
2_0402_5%
PC742
JUMP_43X118
1
2
1
PR740
@ @ PR772
@ PR778 0_0402_5%
@ 0_0402_5%
2
2
PC747
0.1U_0402_25V6
2 1
4.02K_0402_1%
4.02K_0402_1%
2 2
1
MDU1512RH_POWERDFN56-8-5
PR745
392K_0402_1%
100_0402_1%
2
2
1
5
PR762
PR763
+17.4V_BATT+
PR729
1 2
PC750 0.22U_0603_25V7K
2
1 2 4
0.01UF_0402_25V7K
@ PR773
1
53.6K_0402_1%
0_0603_5%
L2N7002WT1G_SC70-3
1
PR732
0.1U_0402_25V7K
3
2
1
1
D
PC711
2
PQ712
PQ717
PC779
2 CMSRC
[25] AC_DIS
1
2
G
1 VDD_CHG
2
S ASGATE
3
1
@
5
@
AON7408L_DFN8-5
100K_0402_1%
32
31
30
29
28
27
26
25
PU703 ISL88739HRZ-T_QFN32_4X4
For Learn Mode
PQ704
PR741
CSIN
CMSRC
OPCN
CSIP
ASGATE
QPCP
BGATE
VBAT
@ PR771 PC721 4
0_0603_5% 0.22U_0402_16V7K
ACIN_CHG 1 24 1 2 1 2
2
3
2
1
[11,25,50] ACAV_IN ACOK UGATE 4.7UH_5.5A_20%_7X7X3_M +17.4V_BATT+
1
22 PHASE_CHG
158K_0402_1%
21 LGATE_CHG
680P_0603_50V7K 4.7_1206_5%
1 2 @ PR770 0_0402_5% 4 2 3
[25,50] PBAT_CHG_SMBCLKPR777 SCL LGATE
@EMI@ PR766
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0_0402_5%
0.1U_0402_25V7K
5
3
1 2 5 20 VDDP_CHG 3
AON7506_DFN33-8-5
2
1
19 VDD_CHG
PC778
PC775
PC776
PC777
PC761
PC766
1 2 6 1 2
[25] I_ADP @ PR775 0_0402_5% AMON VDO
2
PQ708
1 2 7 18 PR760 4.7_0402_5%
2
[25] I_BATT BMON DCIN
1U_0402_16V6K
1U_0402_16V6K
4 @ @
2
8 17
BATGONE
[25,56] I_SYS PSYS NTC
1
100K_0402_1%
@EMI@ PC767
CCLIM
ACLIM
COMP
PROG
AGND
CSON
CSOP
2200P_0402_25V7K
PC768
PC769
0.1U_0402_25V7K
FSET
1
2
10.5K_0402_1%
3
2
1
2
1
PR757
Delay adaptor OC H_PROCHOT#
1
2
PC748
PC749
PR727
33
10
11
12
13
14
15
16
3
2ms while hybrid power PQ710
transition
2
0_0603_5%
@ LMUN5113T1G_SOT323-3
2
PR780
2
+3VALW PD704
1U_0603_25V6
VDD_CHG
2
VDD_CHG PR743 10_1206_5% 2
+19V_VIN
1
H_PROCHOT# @ PR779 1 2 1 @
1
1
2
PC757
0_0402_5% 3 BA
PR791
1
1
200K_0402_1%
200K_0402_1%
10K_0402_5% @ PR790
1
1
160K_0402_1% LRB715FT1G_SOT323-3 [11] SIO_SLP_S5# 2
1
PR781 D CCLIM
2
2
PR749
PR750
10K_0402_5% 1 2 2 PQ721
G PQ711
0.01U_0402_16V7K
RUM002N02GT2L_VMT3
BA
2
10K_0402_1%
RUM002N02GT2L_VMT3
ACLIM
3
1
1
PC790
D S PROG 1 2 LTC015EUBFS8TL_UMT3F
3
PQ720
PROH 2
1
2
PC708
182K_0402_1%
100_0402_1%
102K_0402_1%
S 0.1U_0402_25V6
3
1
560P_0402_50V7K
PR764
1
2
PR753
PR754
PR755
1 2
2
75K_0402_1%
66.5K_0402_1%
PC751
4 10K_0402_1% 4
1
2
1 2
PR751
PR752
0.015U_0402_25V7K
+3VALW
1
10P_0402_50V8J
PC752
PC753
1
PBAT_PRES# [25,50]
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/03/23 Deciphered Date 2014/12/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 21, 2016 Sheet 51 of 61
A B C D
A B C D E
1 1
@EMI@ PL102
HCB3225KF-151T50_2P PR102
1 2 499K_0402_1%
ENLDO_3V5V 1 2
+19VB
@ PJP105 PC102
1
1 2 3V_VIN BST_3V1 2 1 2
150K_0402_1%
+19VB 1 2
PR103
JUMP_43X79 @ PR100 0.1U_0402_10V7K
2200P_0402_50V7K
0_0603_5%
1000P_0402_25V8J
1
PU100
2
EMI@ PC100
EMI@ PC103
@EMI@ PC130
EMI@ PC131
10U_0805_25V6K
10U_0805_25V6K
1000P_0402_25V8J
0.1U_0402_25V6
IN
IN
IN
IN
BS
1
1
LX_3V
PC105
@ PC104
6 20 PL100
2 LX LX 1.5UH_9A_20%_7X7X3_M
2
7 19 LX_3V 1 2
GND LX +3VALWP
@EMI@ PR106
8 SY8286BRAC_QFN20_3X3 18
GND GND
4.7_1206_5%
9 17
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PG LDO +3VLP
1
PC106
PC107
PC108
PC109
@ PC110
10 16
NC NC
3VALWP
OUT
2
EN2
EN1
1
21
NC
FF
GND PC111 TDC 3.3 A
1 3V_SN 2
PR107 4.7U_0603_6.3V6M
Peak Current 4.2 A
11
12
13
14
15
680P_0603_50V7K
10K_0402_1%
@EMI@ PC112
1 2
+3VALWP 3.3V LDO 150mA~300mA OCP Current 9 A fix by IC
2 2
ENLDO_3V5V
Vout is 3.234V~3.366V
POK [11,50,54,55]
2
POK
@ PJP102
1 2
150K_0402_1%
PC113 PR108 +3VALWP +3VALW
1 2
1
@ PR109
1000P_0402_25V8J 1K_0402_5%
EN_3V 3V_FB 1 2 1 2 JUMP_43X118
@EMI@ PL103
2
HCB3225KF-151T50_2P
1 2
1
150K_0402_1%
@ PJP103
1 2
@ PR110
+5VALWP 1 2 +5VALW
@ PJP106 PC114
1 2 5V_VIN BST_5V 1 2 1 2 JUMP_43X118
+19VB 1 2
2
JUMP_43X79 @ PR111 0.1U_0402_10V7K
2200P_0402_50V7K
0_0603_5%
1000P_0402_25V8J
1
EMI@ PC115
EMI@ PC116
@EMI@ PC132
EMI@ PC133
PU102
10U_0805_25V6K
10U_0805_25V6K
1000P_0402_25V8J
0.1U_0402_25V6
1
IN
IN
IN
IN
BS
PC117
PC118
LX_5V 6 20 PL101
2
LX LX 2.2UH_7.8A_20%_7X7X3_M
7 19 LX_5V 1 2 +5VALWP
GND LX
8 SY8286CRAC_QFN20_3X3 18
GND GND
1
3 3
PR112
PC119
680P_0603_50V7K 4.7_1206_5%
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
@EMI@
9 17 1 2
PC120
PC121
PC122
PC123
PC124
PG VCC
10 16
2
NC NC 4.7U_0603_6.3V6M
15V_SN
OUT
LDO
2
EN2
EN1
@ PR121 0_0402_5% 21
FF
EN_3V 1 2 GND
11
12
13
14
15
PC125
@ PR113
+3VALWP VL
@EMI@
@ PR120 0_0402_5% 10K_0402_1%
2
EN_5V 1 2 1 2
ENLDO_3V5V
5V LDO 150mA~300mA
1
EN_5V
PC126
POK
4.7U_0603_6.3V6M
PR114
2.2K_0402_5%
5VALWP
2
1 2
150K_0402_1%
[25] ALWON
TDC 6 A
1
@ PR115
PD102
SDMK0340L-7-F_SOD323-2 Peak Current 7.5 A
[25] CMP_VOUT0
1 2 1 2 OCP Current 9 A fix by IC
2
@ PR116
4.7U_0402_6.3V6M
0_0402_5%
1
1
PC128
150K_0402_1%
PR122 PC127 PR117
@ PR118
1M_0402_5% 1000P_0402_25V8J 1K_0402_5%
5V_FB 1 2 1 2
2
2
EN1 and EN2 dont't floating
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_3.3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 52 of 61
A B C D E
5 4 3 2 1
@ PR200
0_0603_5%
BST_1.2V_R 1 2 BST_1.2V 0.6Volt +/- 5%
+1.2VP TDC 1.2A
@EMI@ PL201
HCB3225KF-151T50_2P Peak Current 1.5A
1
1 2
PC200
D 0.1U_0402_10V7K D
2
@ PJP206
+19VB 2 1 +19VB_1.2V UG_1.2V
2 1
+0.6VSP
JUMP_43X79
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
1000P_0402_25V8J
1000P_0402_25V8J
0.1U_0402_25V6
1
1
LX_1.2V
10U_0805_6.3V6K
10U_0805_6.3V6K
EMI@ PC208
EMI@ PC201
PC206
PC212
EMI@ PC230
EMI@ PC231
1
PC205
PC211
2
16
17
18
19
20
@ PU200
2
PHASE
UGATE
BOOT
VLDOIN
VTT
21
PAD
LG_1.2V 15 1
LGATE VTTGND
14 2
PGND VTTSNS
1
PR205
PQ201 11K_0402_1%
D1
D1
D1
G1
AON7934_DFN3X3A8-10 1 2 CS_1.2V 13 3
+1.2V_MEM PC204 CS RT8207PGQW_WQFN20_3X3 GND
TDC 6.7 A 10
D1 D2/S1
9 1U_0603_10V6K
1 2 12 4 VTTREF_1.2V
Peak Current 8.375 A PR206 VDDP VTTREF
5.1_0603_5%
OCP Current 10.2 A
G2
S2
S2
S2
1 2 VDD_1.2V 11 5
VDD VDDQ
+1.2VP
1
PGOOD
5
1
PC210
TON
+5VALW
1
C PR210 0.033U_0402_16V7K C
FB
S5
S3
2
PC209 2.2_0603_5%
1U_0603_10V6K @ PC214
10
6
220P_0402_25V8J
2
1 2
+5VALW
FB_1.2V
TON_1.2V
PR207
EN_1.2V
EN_0.6VSP
60.4K_0402_1%
[11] 1.2V_VTT_PWRGD 1 2 +1.2VP
PR208
@ PR209 +19VB_1.2V 1 2
10K_0402_1%
453K_0402_1%
1
1 2
+3VALW
1
@ PC213
For RT8207P PR204
.1U_0402_16V7K
100K_0402_1%
2
1 2
[11,17,25,55] SIO_SLP_S4#
2
PL200
1UH_11A_20%_7X7X3_M @ PR201 0_0402_5%
+1.2VP
1
1 2 @ PC202
0.1U_0402_10V7K
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 2
[7] 0.6V_DDR_VTT_ON
1
1
1
PC220
PC218
PC217
PC216
PC215
PC219
1
B 680P_0402_50V7K 0_0402_5% B
2
@ PC203
2
@ 0.1U_0402_10V7K
2
1
@EMI@ PR203
4.7_1206_5%
2
@ PJP200
+1.2VP 1 2 +1.2V_DDR
1 2
JUMP_43X118
Mode S3 S5 +1.2V_MEN +V_DDR_REF +0.6V_P
S5 L L off off off
S3 L H on on off
@ PJP203
S0 H H on on on 2 1
+0.6VSP 2 1 +0.6V_DDR_VTT
JUMP_43X79
A A
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data
Issued Date 2015/03/23 Deciphered Date 2014/12/15 Title
PWR_+1.2V_MEN/+0.6V_DDR_VTT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom X00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 21, 2016 Sheet 53 of 61
5 4 3 2 1
5 4 3 2 1
D D
@EMI@ PL302
HCB3225KF-151T50_2P @EMI@ PR307 @EMI@ PC308 @ PJP302
1 2 4.7_1206_5% 680P_0603_50V7K +1VALWP 1
1 2
2 +1.0V_PRIM
1 2 SNUB_+1VALW 1 2
JUMP_43X118
PU300
@ PJP301
+19VB_+1VALW
+19VB 1
1 2
2 2
IN PG
9 @ PR306 PC307
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
0_0603_5% 0.1U_0402_10V7K
2200P_0402_50V7K
2200P_0402_50V7K
3 1 BST_+1VALW 1 2BST_+1VALW_R 1 2
JUMP_43X79 IN BS
1
1
EMI@ PC301
@EMI@ PC302
PC303
@EMI@ PC320
@EMI@ PC321
PL301
4
IN LX
6 LX_+1VALW 1 2 +1VALWP
330P_0402_50V7K
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
5 19 1UH_6.6A_20%_5X5X3_M
IN LX
2
1
1
PC309
PC310
PC311
PC312
PC313
7 20 PR308
GND LX 10_0402_5%
8 14 FB_+1VALW
2
GND FB
R1
1
18 17 LDO_+1VALW
GND VCC 1 2
1
1 2 EN_+1VALW 11 10
EN NC
[11,50,52,55] POK PC306 PR309
@ PR301 ILMT_+1VALW 13 12 2.2U_0402_6.3V6M
2
ILMT NC 21.5K_0402_1%
1
0_0402_5% @ PC304
+3VALW1
1
PR302 0.1U_0402_25V6 2 15 16 FB=0.6V
1M_0402_1% BYP NC
2
@ PR303 21 PR310
+3VALW 0_0402_5% PAD Vout=0.6V* (1+R1/R2) R2 31.6K_0402_1%
2
SY8286RAC_QFN20_3X3 =0.6*(1+(21.5/31.6))
2
1
C C
PC305
Vout=1.0V
1
1U_0402_6.3V6K
2
@ PR304
0_0402_5%
2
1
@ PR305
0_0402_5%
2
+1.0V_PRIM
TDC 6 A
Peak Current 8.6 A
OCP Current 12 A Fix by IC
The current limit is set to 6A, 9A or 12A when this pin TYP MAX
is pull low, floating or pull high
Choke DCR 11.0mohm , 12.0mohm
A A
@ PJP502
JUMP_43X79
D D
1 2
+1.8VALWP 1 2 +1.8V_PRIM
4
@ 1UH_6.6A_20%_5X5X3_M
1 2 10 2 LX_1.8VALW 1 2
+3VALW
PG
1 2 PVIN LX +1.8VALWP
22P_0402_50V8J
JUMP_43X79 9 3
PVIN LX
2
4.7_1206_5%
1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC503
PC501 8 PR503
SVIN
1
@EMI@ PR506
22U_0603_6.3V6M 10_0402_5%
FB_1.8VALW
PC505
PC506
PC507
6
2
EN_1.8VALW 5 FB
2
1
EN
NC
NC
TP
1 2
FB=0.6Volt
11
1
PR504
1 2
[11,50,52,54] POK
680P_0402_50V7K
20K_0402_1%
@EMI@ PC504
0.1U_0402_10V7K
@ PR501
PC502
0_0402_5%
2
1
PR502
1M_0402_5%
@
2
1
1
PR505
10K_0402_1%
2
C C
+1.8V_PRIM
TDC 1 A
Peak Current 1.25 A
OCP Current 3.5A fix by IC
PJP802 @
1 2
+5VALW +2.5VP 1 2 +2.5V_MEM
JUMP_43X79
1
PC801
1U_0402_6.3V6K
2
4 9 5
@
PJP801 VDD GND NC
1 2 2.5V_VIN 3 6
+3VALW 1 2 VIN VOUT +2.5VP
1
10U_0805_10V6K
21.5K_0402_1%
JUMP_43X79 2 7
EN ADJ
1
1
B B
10U_0805_10V6K
PC802
PR801
1 8 @ PC803
PGOOD GND
1
0.01U_0402_25V7K
2
PC804
2
PU800
2
RT9059GSP_SO8 ADJ_2.5V
@ PR803
1
0_0402_5%
1 2 EN_2.5V
[11,17,25,53] SIO_SLP_S4#
PR802 +2.5V
10K_0402_1% TDC 0.45 A
Peak Current 0.57 A
2
1
0.1U_0402_10V6K
PC805
2
A A
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/12/15 Title
2015/03/23 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.8V_PRIM and +2.5V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C X00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 21, 2016 Sheet 55 of 61
5 4 3 2 1
5 4 3 2 1
VCC_SA
+1.0V_VCCST Loadline : 10.3m-ohm
@ PJP603
@ PR602
TDC 5A 1 2
10P_0402_25V8J
@RF@ 0_0402_5% Peak Current 5A VCCSA_B+ CPU_B+
0.1U_0402_25V6
1
1
1 2 OCP current 7A
PC602
45.3_0402_1%
75_0402_1%
100_0402_1%
+5VALW PAD-OPEN1x1m
1
PC695
PR605
PR601
PR604
Local sense put on HW site Choke DCR 12 +-5%m ohm
2
2
@ PR606 @ 1 2 CPU_B+
0.22U_0603_25V7K
2
2
0_0402_5%
1U_0603_10V6K
D 1 2 1 2 VR_SCLK @ PR603 D
[15] VIDSCLK
1
49.9_0402_1% PR618 0_0402_5%
PC603
PC604
[15] VIDALERT_N 1 2 @ PR607 1 2 VR_ALERT#
0_0402_5% @ PR625 0_0402_5%
2
[15] VIDSOUT 1 2 1 2 VR_SDA
10_0402_1% PR626
[12,25,50,51] H_PROCHOT# PR678 @ PR609 VCCSA_B+
100_0402_1% 0_0402_5%
1 2 1 2
1 2
PC605 47P_0402_50V8J~D
U22@ PR608
PH601 PR610 78.7K_0402_1%
10U_0805_25V6K
10U_0805_25V6K
470K_0402_5%_ TSM0B474J4702RE 10K_0402_1% 1 2
1 2 1 2 PR613 1.91K_0402_1% PR612
1
1 2
PC612
PC608
90.9K_0402_1% PR611
1 2 1 2 +3VS 48.7K_0402_1%
PR631 PC613
2
27.4K_0402_1% 330P_0402_50V8J @ PR616
1 2 1 2
[11,57] IMVP_VR_ON
U22@ PC614 PR617
2200P_0402_50V7K 3.6K_0402_1% 0_0402_5%
1 2 1 2
40
39
38
37
36
35
34
33
32
31
PU602
PC616 PR619
VR_ENABLE
VR_READY
VR_HOT#
SCLK
ALERT#
SDA
PROG1
PROG2
VCC
VIN
33P_0402_50V8J @ PR620 1 2
1 2 U22@ PC617 U22@ PR621 0_0402_5%
220P_0402_50V7K 1K_0402_1% 1 2 1 30 PWM_VSA 0_0603_5% PU606 AON7934_DFN3X3A-8-10
[25,51] I_SYS PSYS PWM_C
1
1 2 1 2 2 29 FCCM_VSA ISL95808HRZ-TS2378_DFN8_2X2 PQ601
[16] VCC_GT_SENSE IMON_B FCCM_C
PR622 3 28 PL601
D1
D1
D1
G1
@ PC618 U22@ 1.96K_0402_1% 4 NTC_B ISUMN_C 27 1 8 0.68UH +-20% 7.9A
1 2 1 2 5 COMP_B ISUMP_C 26 PC611 UGATE PHASE
0.082U_0402_16V7K
COMP_VSA
PR627 @EMI@
330P_0402_50V7K 7 24 0.22U_0402_16V7K
U22@ PC621 PR623 8 ISUMP_B COMP_C 23 IMON_VSA PWM_VSA 3 6 3 2
C
PC619 680P_0402_50V7K 2K_0402_1% 9 ISUMN_B IMON_C 22 PWM VCC C
4.7_1206_5%
G2
S2
S2
S2
2
1
1 2 @ 1 2 1 2 10 21 4 5
ISEN2_B FCCM_A FCCM_IA [57] GND LGATE
1
TP
ISUMN_A
ISUMP_A
PR624
PWM1_B
PWM2_B
COMP_A
8
FCCM_B
IMON_A
0.01U_0402_50V7K 41
NTC_A
RTN_A
AGND 3.65K_0603_1%
1
FB_A
[16] VSS_GT_SENSE
ISUMP_VSA 2
11
12
13
14
15
16
17
18
19
20
SA_SNUB
ISUMN_VSA
ISL95859HRTZ-T_TQFN40_5X5 @ PR679
+5VALW
2
1
0_0402_5%
1U_0402_10V6K
[57] ISUMP_GT
FCCM_VSA
IMON_IA
FB_IA
[57] FCCM_GT
NTC_IA
COMP_IA
PC685
4.42K_0402_1%
[57] PWM1_GT
2
1
@ PR637
1
PR628
PC625
680P_0603_50V7K
20M_0402_5% 330P_0402_50V7K
10K_0402_5%_ERTJ0ER103J
1
1 2
@EMI@ PC622
0.033U_0402_16V7K
2
0.068U_0402_16V7K
84.5K_0402_1%
2
1
1
1 2
PC624
20M_0402_5%
4.02K_0402_1%
10P_0402_50V8J
U22@ PC626
PR630
PC627 PH603
1
1
PR632 470K_0402_5%_ TSM0B474J4702RE
11K_0402_1%
2200P_0402_50V7K
1200P_0402_50V7K
2
2
1
1K_0402_1% 2200P_0402_50V7K 1 2 1 2
PH602
PR633
PC628
1 2 1 2 ISUMP_VSA
2
PR647 27.4K_0402_1% PR635 1 2
255_0402_1%
1
U22@ PR638 1 2 10K_0402_1%
2.61K_0402_1%
2
1
PC630
PR640
274_0402_1% PR636 1.24K_0402_1%
2
1 2 PC629
PC631
PR639
PR642
[57] ISUMN_GT 2200P_0402_50V7K 3K_0402_1% 1 2 1 2
2
1 2 1 2
10KB_0402_5%_ERTJ0ER103J
2
U22@SKL@
PC632 PR641
0.033U_0402_16V7K
2
2
PC636 2200P_0402_25V7K 1K_0402_1%
1K_0402_1%
11K_0402_1%
33P_0402_50V8J
6800P_0402_25V7K
PR643
1
1
1 2
PR644
PC633
PC637
1
B PC639 PR645 PR646 PC640 B
1
2200P_0402_25V7K 316_0402_1% 1 2 1 2 @
1 2 1 2
330P_0402_50V7K
.1U_0402_16V7K
2
1
316_0402_1% 2200P_0402_25V7K
PH604
+5VALW
PC641
U22@SKL@ PR648
2
1 2 PR649
2
1
1 2
U22@ PR651
147K_0402_1%
1
1.37K_0402_1% PC642 ISUMN_VSA
0.047U_0402_25V7K 1.69K_0402_1% PC644
PC643
680P_0402_50V7K 2K_0402_1%
1
1
1 2 .1U_0402_16V7K
2K_0402_1%
2
1 2
PR652
.1U_0402_16V7K
2
1
PR650
PC645
2
1 2
PC646
680P_0402_50V7K
0.047U_0402_25V7K
2
1 2 VSA_SEN- [17]
PC647
PC601
2
PR640 U22@KBL@
1
PC649
0.01U_0402_50V7K
0.082U_0402_16V7K
1 2
PR656
U22@SKL U22@KBL 11K_0402_1%
[15] VCCSENSE
2
1 2
PC650
280_0402_1%
PR640 255 280 PR648 U22@KBL@ PR657
@ PC652
1
@ PC651 PH605 @ 330P_0402_50V7K
1 2 4.42K_0402_1% 10KB_0402_5%_ERTJ0ER103J 1 2
PR648 1.37K 1.5K 1 2 1 2
0.082U_0402_16V7K
PC653
330P_0402_50V7K
1
@ PR653
97.6K_0402_1% [15] VSSSENSE
20M_0402_5% DELL CONFIDENTIAL/PROPRIETARY
Local sense put on HW site
2
VCC_core VCC_GT
U22 - 15W U22 - 15W
Loadline : 2.4m-ohm Loadline : 3.1m-ohm
U23e - 15W U23e - 15W
Loadline : 2.4m-ohm Loadline : 2m-ohm
TDC 21A U22-15W
D
Peak Current 29A (KBL : 32A) TDC 18A D
OCP current 34A (KBL : 36A) Peak Current 31A
Choke DCR 0.66 +-7%m ohm OCP current 37A
+19VB Choke DCR 0.66 +-7%m ohm
@ PJP601
1 2
EMI@
EMI@
@EMI@
HCB3225KF-151T50_2P
Choke DCR 0.66 +-7%m ohm
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
1000P_0402_25V8J
1000P_0402_25V8J
0.1U_0402_25V6K~D
PWM_IA [56]
1
5.11K_0402_1%
1 1
PR662
33U_25V_M
33U_25V_M
1
1
+ +
PC690
PC656
PC657
PC658
PC659
PC660
PC694
PC691
PC606
2
2
2 2 @
+5VALW
@ PR655
1U_0402_10V6K
1
0_0402_5%
DRMOS_EN 2 1
PC661
IMVP_VR_ON [11,56]
PU603
2
AOZ5019QI_QFN23_5X3P5
CPU_B+
13
[56] FCCM_IA 2 1 1 PWM 12 PL603
0_0603_5% 2 SMOD EN 11 .15UH +-20% 29A 7X7X4 MOLDING
@ PR659 1 PR660 2 3 VCC VIN 10
C
0_0402_5% 4 BOOT CGND 9 C
0.22U_0402_16V7K GH GL CORE_SW
1 2 5 8 4 1
PC655
6 VSWH
VIN
VSWH
PGND
7 PR663 @EMI@ +VCC_CORE
3 2
10P_0402_25V8J
4.7_1206_5%
1
1
PC686
PC680
1
1000P_0402_50V7K PR661
2
2
3.65K_0603_1%
2
2
CORE_SNUB
[56]
[56]
ISUMP_IA
ISUMN_IA
680P_0603_50V7K
1
@EMI@ PC662
2
CPU_B+
PC666 @EMI@
EMI@
EMI@
EMI@
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
1000P_0402_25V8J
1000P_0402_25V8J
B B
0.1U_0402_25V6K~D
PWM1_GT [56]
1
1
PC672
PC673
PC667
PC692
PC693
5.11K_0402_1%
PR680
2
+5VALW @ PR671
0_0402_5%
2 1 DRMOS_EN
[56] FCCM_GT
PU605
AOZ5019QI_QFN23_5X3P5
1U_0402_10V6K
CPU_B+
1
13
PC677
1 PWM 12 PL605
2
6 7
PC671 VIN PGND 3 2
10P_0402_25V8J
4.7_1206_5%
GT1P
1
PC679 GT1N
PC688
1000P_0402_50V7K
2
PR674 PR673
2
3.65K_0603_1% 10_0402_1%
1 2
2
[56]
ISUMN_GT
A A
GT_SNUB1
ISUMP_GT
[56]
DELL CONFIDENTIAL/PROPRIETARY
680P_0603_50V7K
1
@EMI@ PC678
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+VCC_core and +VCC_GT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 21, 2016 Sheet 57 of 61
5 4 3 2 1
4
3
2
1
+VCC_CORE
A
A
2
1
+
220U 2V Y D2 2 1 2 1
2
1
PC1127
PC1099 PC1083 @ PC1076
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
SKL :
2
1
+
2 1 2 1
2
1
2
1
220U 2V Y D2
@
@
PC1062
PC1095 PC1030 PC1081 PC1078
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
Back Side.
2
1
2
1
@
@
2
1
2
1
@
@
2 1 2 1
2
1
2
1
@
@
B
B
2
1
2
1
2
1
2
1
Back Side.
@
Primary Side.
2
1
2
1
22U_0603 * 5 pcs+330u_D2*2 pcs
Issued Date
@
+VGA_CORE
2
1
+
C
C
Security Classification
22U_0603 * 15 pcs +1U_0201*35 pcs
PC836
PC1125
VCC_SA Place on CPU
2
1
+
1U_0201_6.3V6M
VGA@ 330U_2V_M
PC837
2
1
+
VGA@ 330U_2V_M
PC838
2
1
+
2014/11/05
VGA@ 330U_2V_M
PC839
22U_0603 * 6 pcs + 1U_0201*7 pcs
+VCC_GT
2
1
+
330U_2V_M
PC1128
2 1
2
1
2
1
For VGACORE
2
1
+
@
PC1063 2 1
2
1
2
1
+VCC_SA
@
D
D
PC1153 PC1057 2 1 2 1
2
1
2
1
1U_0201_6.3V6M 22U_0603_6.3V6M
@
2
1
PC1147 PC1058 2 1 2 1
2
1
2
1
1U_0201_6.3V6M 22U_0603_6.3V6M
2014/12/15
PC1148 PC1059 2 1 2 1
VCC_GT Place on CPU
2
1
2
1
1U_0201_6.3V6M 22U_0603_6.3V6M
@
PC1149 PC1060 2 1 2 1
2
1
2
1
1U_0201_6.3V6M 22U_0603_6.3V6M
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
@
1U_0201_6.3V6M 22U_0603_6.3V6M
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Title
Date:
@
1U_0201_6.3V6M 22U_0603_6.3V6M
22U_0603 * 19 pcs +1U_0201*12 pcs
1U_0201_6.3V6M 22U_0603_6.3V6M
Document Number
22U_0603_6.3V6M
Tuesday, June 21, 2016
22U_0603_6.3V6M
@
2
1
22U_0603_6.3V6M
Sheet
22U_0603_6.3V6M
2
1
of
PC1146
22U_0603_6.3V6M
DELL CONFIDENTIAL/PROPRIETARY
61
PWR_CPU&VGA bulk and MLCC
Rev
X00
4
3
2
1
5 4 3 2 1
+19VB_GPU @ PJP1101
2 1
2 1
JUMP_43X79
@VGA@EMI@ PL1101
HCB3225KF-151T50_2P
1 2
+19VB
2200P_0402_50V7K
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
5
1
VGA@ PC1103
VGA@ PC1104
VGA@ PC1105
@EMI@ PC1106
VGA@EMI@ PC1107
@EMI@ PC1190
@EMI@ PC1191
AON6552_DFN5X6-8-5
D D
2
VGA@ PQ1101
UG2_VGA 4
SH000011H00 (DCR:0.98m± 5% )
VGA@ PL1102
3
2
1
10K_0402_1% VGA@
10K_0402_1% VGA@
@ 0.22UH_24A_20%_7X7X4_MOLDING
LX2_VGA
32.4K_0402_1%
4 1
VGA@
PC1108 VGA@ PR1104 3 2
+VGA_CORE
0.22U_0402_16V7K @EMI@ 10K_0402_1%
1
BST2_VGA 1 2 1 2 PR1107 ISEN2_VGA1 2
1
4.7_1206_5%
@ PR1103 VGA@ PR1108
5
AON6554_DFN5X6-8-5
AON6554_DFN5X6-8-5
0_0603_5% 3.65K_0603_1%
+5VALW VSUM+_VGA
PR1140
PR1105
PR1106
@EMI@ 1 2
1 2
PC1109
VGA@ PQ1102
VGA@ PQ1103
680P_0603_50V7K VGA@ PR1110
1_0402_1%
LG2_VGA 4 4 VSUM-_VGA
1 2
2
VGA@
41
40
39
38
37
36
35
34
33
32
31
PU1100
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
3
2
1
3
2
1
VGA_CORE (M70)
VGA@ PR1101 100K_0402_1% TDC 28A
1 2 1 30 BST2_VGA
VGA@ PR1111 100K_0402_1% NTC_NB BOOT2 Peak Current 42A
1 2 2
IMON_NB UGATE2
29 UG2_VGA OCP current 50A
3 28 LX2_VGA Load line -1mV/A
[41] SVI2_SVC SVC PHASE2
4 27 LG2_VGA +5VALW
OCP_L
@ PR1112 100K_0402_1%
VR_HOT_L LGATE2 FSW=300kHz
+3VS 1 2 5 26
[41] SVI2_SVD SVD VDDP +19VB_GPU
ISL62771HRTZ-T_TQFN40_5X5 VGA@ PR1114
1 2 VGA@ PR1113 0_0402_5% VDDIO_VGA
6 25 1 2
+1.8VGS VDDIO VDD
1U_0603_10V6K
1_0603_5%
1
LG1_VGA
2200P_0402_50V7K
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
@ PR1115 0_0402_5% 7 24
[41] SVI2_SVT SVT LGATE1
1
C C
1U_0603_10V6K
1 2
0.1U_0402_25V6
0.1U_0402_25V6
+3VGS @ PR1116 0_0402_5%
PC1226 2 ENABLE_VGA LX1_VGA
VGA@ PC1111
1 8 23
[9,39] DGPU_PWR_EN
2
ENABLE PHASE1
VGA@ PC1110
0.1U_0402_25V6K
1
PWRGD_VGA UG1_VGA
VGA@ PC1112
VGA@ PC1113
VGA@ PC1114
@EMI@ PC1115
VGA@EMI@ PC1116
@EMI@ PC1192
@EMI@ PC1193
VGA@ 9 22
PWROK UGATE1
AON6552_DFN5X6-8-5
1 2 IMON_VGA 10 21 BST1_VGA
2
IMON BOOT1 +3VS
PR1117 VGA@
VGA@ PQ1104
PGOOD
133K_0402_1%
ISUMN
ISUMP
COMP
ISEN2
ISEN1
UG1_VGA
VSEN
4
NTC
RTN
1 2 VGA@ FB
1
1000P_0402_50V7K VGA@ VGA@
PC1117 PR1120 PR1121 SH000011H00 (DCR:0.98m± 5% )
11
12
13
14
15
16
17
18
19
3
2
1
1 2 1 2 100K_0402_1% 1 2 0.22UH_24A_20%_7X7X4_MOLDING
DGPU_PWROK [12,60]
2
@ PR1122 LX1_VGA 4 1
1 2
PWRGD_VGA 0_0402_5% VGA@
PC1118 VGA@ PR1124 3 2
+VGA_CORE
@ PH1101 0.22U_0402_16V7K @EMI@ 10K_0402_1%
1
470K_0402_5%_TSM0B474J4702RE PC1119 VGA@ BST1_VGA 1 2 1 2 PR1125 ISEN1_VGA1 2
0.22U_0402_10V6K 4.7_1206_5%
1 2 ISEN2_VGA @ PR1123 VGA@ PR1126
5
AON6554_DFN5X6-8-5
AON6554_DFN5X6-8-5
0_0603_5% 3.65K_0603_1%
PC1120 VGA@ @EMI@ VSUM+_VGA1 2
1 2
0.22U_0402_10V6K PC1121
VGA@ PQ1105
VGA@ PQ1106
VSUM-_VGA 1 2 ISEN1_VGA 680P_0603_50V7K VGA@ PR1128
1_0402_1%
VGA@ VGA@ VGA@ PC1123 LG1_VGA 4 4 VSUM-_VGA
1 2
2
PC1122 PR1129 180P_0402_50V8J @ PR1130
1000P_0402_50V7K 301_0402_1% 121K_0402_1%
VSUM+_VGA 1 2 1 2 1 2 1 2
PR1131 VGA@
330P_0402_50V7K
3
2
1
3
2
1
@ PC1124
2.61K_0402_1%
VGA@ VGA@
VGA@ PR1133
1
PR1134 PC1228
10K_0402_5%_ERTJ0ER103J
0.033U_0402_16V7K
0.15U_0603_16V7K
11K_0402_1%
1 2 1 2 1 2
2
1
1
VGA@ PR1132
VGA@ PC1232
VGA@ PC1230
VGA@ VGA@
1 2
PR1135 PC1233
2
2K_0402_1% 330P_0402_50V
2
1 2 1 2
VGA@
PH1102
B VGA@ B
PR1136
2
470_0402_1%
VSUM-_VGA 1 2
@ PC1227 @ PR1138
1
1 2
0.01U_0402_50V7K
VSSSENSE_VGA [41]
@ PR1139
0_0402_5%
VGA@ PC1229
1
2
A A
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/03/23 Deciphered Date 2014/12/15 Title
PWR_VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom X00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 21, 2016 Sheet 59 of 61
5 4 3 2 1
5 4 3 2 1
+3VS
@ PJP1402
1
D D
+1.35VGPUP 1 2 +1.35V_MEM_GFX
PR1401 @ 1 2
@VGA@EMI@ PL1402 100K_0402_5% JUMP_43X118
HCB3225KF-151T50_2P @EMI@ PR1408 @EMI@ PC1408
1 2 4.7_1206_5% 680P_0603_50V7K
2
VGA@ 1 2 SNUB_+1.35VGPU1 2
PU1400
@ PJP1401 VGA@
+19VB_+1.35VGPU 2
+19VB 1
1 2
2
IN PG
9 @ PR1402 PC1407
1000P_0402_25V8J
10U_0805_25V6K
0.1U_0402_25V6
0_0603_5% 0.1U_0402_10V7K VGA@
2200P_0402_50V7K
1000P_0402_25V8J
3 1 BST_+1.35VGPU 1 2BST_+1.35VGPU_R1 2
JUMP_43X79 IN BS PL1401
1
1
1
VGA@EMI@ PC1401
VGA@ PC1403
EMI@ PC1421
@EMI@ PC1402
EMI@ PC1420
4
IN LX
6 LX_+1.35VGPU 1 2
+1.35VGPUP
330P_0402_50V7K
2
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
5 19 1UH_6.6A_20%_5X5X3_M
IN LX
2
VGA@
1
VGA@
PC1409
VGA@ PC1412
VGA@ PC1413
VGA@ PC1414
VGA@ PC1411
7 20 PR1409
GND LX 10_0402_5%
8 14 FB_+1.35VGPU
2
GND FB
R1
1
@ PR1403 18 17 LDO_+1.35VGPU
[12,59] 0_0402_5% GND VCC 1 2
1
1 2 EN_+1.35VGPU 11 10 VGA@
DGPU_PWROK EN NC PC1406 PR1410
ILMT_+1.35VGPU13 12 2.2U_0402_6.3V6M 30.1K_0402_1%
2
ILMT NC
1
1
PR1404 0.1U_0402_25V6 2 15 16 FB=0.6V
1M_0402_1% BYP NC
2
@ PR1405 21 PR1411
+3VALW 0_0402_5% PAD Vout=0.6V* (1+R1/R2) R2 24K_0402_1%
2
2
1
VGA@
PC1405
Vout=1.35V
1
1U_0402_6.3V6K
2
@ PR1406
0_0402_5%
C C
2
1
@ PR1407
0_0402_5%
+1.35VGPU
TDC 4.9A
Peak Current 6.125A
2
OCP current 9A
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.35VGPU
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D801P
Date: Tuesday, June 21, 2016 Sheet 60 of 61
5 4 3 2 1
5 4 3 2 1
0.1(X00)
2 P56 PWR 20160321 COMPAL design change for IA_Core Iccmax 32A Change the PR640 to 280 Ohm
Change the PR648 to 1.5k
Change the PR629 to 93.1k
0.1(X00)
C 3 P58 PWR 20160321 COMPAL design change delete PC1003,PC1004,PC1006,PC1012,PC1013,PC1014,PC1015,PC1017,PC1019, C
PC1020,PC1021,PC1025,PC1027,PC1058,PC1059,PC1060,PC1068,PC1070,PC1071,
PC1073,PC1074,PC1075,PC1076,PC1077,PC1078,PC1079,PC1080,PC1081,PC1082
add PC1170,PC1171,PC1172,PC1173,PC1174,PC1175,PC1176,PC1177,PC1180,
PC1181,PC1182,PC1183
4 P50 PWR 20160504 COMPAL Reserve Erp lot6 Reserve PR2,PR5 ,PR7,PR10,PQ1 0.3(X02)
5 P51 PWR 20160504 COMPAL PQ740 damage issue Change PQ740 to SB00000SY00 (MDU1512R) 0.3(X02)
B 1.0(A00) B
7 P51 PWR 20160614 COMPAL Change SOT23-6P to SOT23-3P change PQ709 to SB00000ST00 (PQ709,PQ712)
1.0(A00)
8 P51 PWR 20160614 COMPAL Add pull high resistance Add PR781
A A
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/12/22 Deciphered Date 2017/01/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_Change list
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 21, 2016 Sheet 61 of 61
5 4 3 2 1