MODULE TITLE : COMBINATIONAL AND SEQUENTIAL LOGIC

TOPIC TITLE : SEQUENTIAL LOGIC

TUTOR MARKED ASSIGNMENT 3 (v1.1)

NAME........................................................................................................................................

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Student declaration:

I declare that all the work submitted is my own work and that no part of it has been copied from
any other source without full acknowledgement and complies with the University's guiding
principles as stated in the Regulations Relating To Academic Misconduct*.

Student signature:.....................................................................................................

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*http://www.tees.ac.uk/docs/index.cfm?folder=Student%20Regulations&name=Academic%20Regulations

CSL - 3 - TMA (v1.1)

© Teesside University 2011

 Published by Teesside University Open Learning (Engineering)
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 1

IMPORTANT

Before you start please read the following instructions carefully.

1. This assignment forms part of the formal assessment for this module. If
you fail to reach the required standard for the assignment then you will be
allowed to resubmit but a resubmission will only be eligible for a Pass
grade, not a Merit or Distinction.

You should therefore not submit the assignment until you are reasonably
sure that you have completed it successfully. Seek your tutor's advice if
unsure.

2. Ensure that you indicate the number of the question you are answering.

3. Make a copy of your answers before submitting the assignment.

4. Complete all details on the front page of this TMA and return it with
the completed assignment including supporting calculations where
appropriate. The preferred submission is via your TUOL(E) Blackboard
account:
https://eat.tees.ac.uk

5. Your tutor’s comments on the assignment will be posted on Blackboard.

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Assessment Criteria

This assignment relates to the analysis, design and software emulation of linear
and non-linear operational amplifier circuits. The assignment forms Element 3
of the module’s assessment criteria that covers in part Learning Outcomes 1, 2,
3 and 4 as indicated below.

MODULE LEARNING OUTCOMES

Knowledge and Understanding

1. Demonstrate a detailed knowledge of the design and operation of

combinational and sequential logic circuits.

Cognitive and Intellectual Skills

2. Interpret manufacturers’ data sheet and design and test circuits to solve a
variety of design applications.

Practical and Professional Skills

3. Use a specialist software package to simulate and evaluate combinational and

sequential logic circuits.

Key Transferable Skills

4. Use appropriate analytical and numerical methods within applied engineering

contexts in the solution of problems involving combinational and sequential
logic circuits.

PASS MERIT DISTINCTION

Criteria in excess of the pass Criteria in excess of the
grade. merit grade.

Substantially correct Demonstrate ability to Demonstrate ability to

solutions are given to satisfy transfer learning to a related research and develop the
the learning outcomes. but unfamiliar situation. subject in more complex
circumstances.

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Note, unless stated otherwise, designations DCBA, CBA and BA, indicate
MSB → LSB.

1. (a) State :

(i) the main disadvantage of an S – R bistable

(ii)the main disadvantage of the D-type bistable.

(b) State an advantage and a disadvantage of the master-slave J – K

bistable compared to a basic J – K bistable.

(c) Identify the symbols shown in FIGURES 1(a) and 1(b).

CK CK

(a) (b)

FIG. 1

(d) There are two types of sequential logic circuits that can be classified
on the basis of how they are clocked. What are they?

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 4

2. (a) The input and clock waveforms for a D-type transparent latch are
shown in FIGURE 2. Complete the timing diagram showing the Q
output waveform.

INPUT D

Clock

'1'
OUTPUT

FIG. 2

(b) The inputs shown in the timing diagram of FIGURE 3 are applied to
a negative edge triggered J – K bistable. Draw the waveform of the
output Q and briefly explain how the states of Q come about.

Clock 1 2 3 4 5 6 7 8 9 10

PRESET

CLEAR

OUTPUT Q

FIG. 3

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3. FIGURE 4 shows a clocked NAND S – R bistable.

S
2 3 Q

Clock

R 1 4 Q

FIG. 4

Complete the truth table shown below and, by constructing a Karnaugh

map, show that the next output state after clocking, Qt + 1, is given by the
Boolean equation:
Qt + 1 = S + Qt R

The states of Qt + 1 and Qt + 1 are not permitted to be the same. Any 'not
permitted' states are marked on the Karnaugh map as X, 'don't care'.

Use a Karnaugh map format of:

SR
00 01 11 10
Qt

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 6

Truth table for a NAND S – R bistable.

S R Qt Qt + 1
Qt + 1

0 0 1

0 0 0

1 0 1

1 0 0

0 1 1

0 1 0

1 1 1

1 1 0

4. It is found with the circuit of FIGURE 4, that when S = R = 1, and the

clock = 1, the outputs are both 1. When the clock reverts to a 0, it is
observed that Q always becomes a 1 and Q = 0. If, however, two series
NAND gate inverters are inserted in the feedback line from the Q output
to the input of gate 3, as shown in FIGURE 5, then when the clock
becomes a 0, Q = 1 and Q = 0.

Briefly explain the reason why this should happen. Assume gates 1 and 4
switch faster than gates 2 and 3.

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 7

S
2 3 Q

Clock

R 1 4 Q

FIG. 5

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 Question
No.

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 Question
No.

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(Engineering)