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Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
• Dynamic dV/dt Rating
VDS (V) 100
Available
• Repetitive Avalanche Rated
RDS(on) () VGS = 10 V 0.54
• For Automatic Insertion RoHS*
Qg (Max.) (nC) 8.3 COMPLIANT
Qgs (nC) 2.3 • End Stackable
Qgd (nC) 3.8 • 175 °C Operating Temperature
Configuration Single • Fast Switching and Ease of Paralleling
D • Compliant to RoHS Directive 2002/95/EC
HVMDIP DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
G ruggedized device design, low on-resistance and
S cost-effectiveness.
G The 4 pin DIP package is a low cost machine-insertable
D S case style which can be stacked in multiple combinations on
standard 0.1" pin centers. The dual drain serves as a thermal
N-Channel MOSFET
link to the mounting surface for power dissipation levels up
to 1 W.
ORDERING INFORMATION
Package HVMDIP
IRFD110PbF
Lead (Pb)-free
SiHFD110-E3
IRFD110
SnPb
SiHFD110
VGS
101
Top 15 V
101 10 V 25 °C
8.0 V
ID, Drain Current (A)
7.0 V
4.5 V
VGS 3.0
RDS(on), Drain-to-Source On Resistance
7.0 V
6.0 V 2.0
(Normalized)
5.5 V
5.0 V
100 Bottom 4.5 V 4.5 V 1.5
1.0
Fig. 2 - Typical Output Characteristics, TA = 175 °C Fig. 4 - Normalized On-Resistance vs. Temperature
400
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
240 100
Ciss 25 °C
160 Coss
80
10-1
Crss
VGS = 0 V
0
100 101 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
91127_05 VDS, Drain-to-Source Voltage (V) 91127_07 VSD, Source-to-Drain Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage
20 102
ID = 5.6 A Operation in this area limited
VGS, Gate-to-Source Voltage (V)
5 by RDS(on)
VDS = 80 V
16
VDS = 50 V 2
ID, Drain Current (A)
VDS = 20 V 10
12 10 µs
5 100 µs
2
8 1 ms
1
5 10 ms
4
TA = 25 °C
For test circuit 2 TJ = 175 °C
see figure 13 Single Pulse
0 0.1 2 5 2 5 2 5 2 5
0 2 4 6 8 10 0.1 1 10 102 103
91127_06 QG, Total Gate Charge (nC) 91127_08 VDS, Drain-to-Source Voltage (V)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area
RD
VDS
1.0 VGS
D.U.T.
Rg
+
0.8 - VDD
ID, Drain Current (A)
10 V
0.6 Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
0.2
VDS
90 %
0.0
25 50 75 100 125 150 175
Fig. 9 - Maximum Drain Current vs. Ambient Temperature Fig. 10b - Switching Time Waveforms
103
Thermal Response (ZthJA)
102
0 - 0.5
0.2
10 0.1
0.05
0.02 PDM
1 0.01
t1
Single Pulse t2
0.1 (Thermal Response) Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-2
10-5 10-4 10-3 10-2 0.1 1 10 102 103
L
VDS VDS
Vary tp to obtain
tp
required IAS
VDD
Rg D.U.T. +
V DD
- VDS
I AS
10 V
tp 0.01 W
IAS
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
350
ID
EAS, Single Pulse Energy (mJ)
Top 0.82 A
300
1.4 A
Bottom 2.0 A
250
200
150
100
50
VDD = 25 V
0
25 50 75 100 125 150 175
Current regulator
Same type as D.U.T.
QG 50 kΩ
10 V 12 V 0.2 µF
0.3 µF
QGS QGD +
VDS
D.U.T. -
VG
VGS
3 mA
Charge
IG ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
- +
-
Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test
VGS = 10 Va
Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD
Re-applied
voltage
Body diode forward drop
Inductor current
Ripple ≤ 5 % ISD
Note
a. VGS = 5 V for logic level devices
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91127.
0.248 [6.29]
0.240 [6.10]
0.180 [4.57]
0.160 [4.06]
0.094 [2.38]
A L
0.086 [2.18]
0.160 [4.06]
0.140 [3.56]
0° to 15°
0.017 [0.43] 2x 0.045 [1.14]
0.013 [0.33] 2 x 0.035 [0.89]
0.024 [0.60]
E min. 4x
0.020 [0.51]
0.100 [2.54] typ.
E max.
INCHES MILLIMETERS
DIM. MIN. MAX. MIN. MAX.
A 0.310 0.330 7.87 8.38
E 0.300 0.425 7.62 10.79
L 0.270 0.290 6.86 7.36
ECN: X10-0386-Rev. B, 06-Sep-10
DWG: 5974
Note
1. Package length does not include mold flash, protrusions or gate burrs. Package width does not include interlead flash or protrusions.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
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including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.