A 36-bit Balanced Moduli MAC Architecture
AP. Preethy and D. Radhakrishnan
Division of Computer Engineering, School of Applied Science
Nanyang Technological University, Nanyang Ave.
Singapore 639798
email: asdrkrishnan@ntu.edu.sg
-
Absirucr Recently a renewed interest is seen in RNS
(Residue Number System) which stems out from the fact that
these systems are inherently parallel and modular and thus are
fast and simple. In many DSP applications Multiply-Accumulate
(MAC) operation turns out to be the most basic one and hence
an RNS based 36-bit MAC architecture is presented in this
paper to speed up the whole operation. A further enhancement
in speed up is achieved by exploiting the logarithmic properties
of Galois fields and integer rings. The choice of forward and
reverse converters used in the design results in considerable
savings in silicon real estate. The adder cells used is based on
pass transistor design which attribute to very low power
consumption.
I. INTRODUCTION
Residue Number System (RNS) eliminates the speed-
draining carry propagation in arithmetic computations, thus
making it attractive in heavily computation intensive
applications. The parallel arithmetic nature of RNS offers a
potential speed up in FIR filtering, discrete Fourier
transforms, matrix multiplications, and similar other
computations [13. A Multiply-Accumulate (MAC!) unit is an
integral part of an arithmetic processor used in such
applications. In a MAC unit, multiplication speed is of
paramount importance and it becomes necessary to search for
new strategies for increasing the speed. One such strategy is
the use of index calculus for doing multiplication. Even
though it speeds up multiplication by converting it to
addition, its domain was limited to the set of prime moduli.
When a large range such as 32 or 36 bits is aimed at, with a
set of prime moduli, the moduli chosen will eventually result
in non-uniform word length. This necessitates exploring
additional moduli with similar properties that will provide
extra flexibility with uniform word length. It has been shown
that index calcuius techniques could be extended to non-
prime moduli that are powers of 2 [2,3]. This was further
extended to powers of odd primes in [4,5]. Thus by
combining both primes and powers of prime moduli a very
fast and less complex multiplier could be implemented.
Evaluation of the summation of the products obtained is
the next phase of the computation. This is achieved by
performing addition in residue domain using modulo adders.
Since the proposed MAC is a multiplierless unit, the main
logic units are modulo adders. Hence the performance of the
design mainly depends on the choice of modulo adder used.
Hence a modulo adder which outperforms other counterparts
is chosen [ 6 ] . Another design issue equally important is the
0-7803-5491-5/99/$10.00 0 1999 IEEE
type of binary adder cell employed in the modulo adder. So to
make the MAC efficacious, a new low power CMOS adder
cell is used which plays a pivotal role in scaling down the
power requirements of the entire MAC unit [7].
The MAC operation is completely done in residue
domain. So the operands have to be initially transformed intc
residue domain (forward conversion) and after the
completion of the MAC operation the sum residues have to
be converted back to binary form (reverse conversion). In
order to effect these conversions, a forward and a reverse
converter are also incorporated in the proposed design. With
these, the design represents a complete MAC unit with both
the inputs and outputs in standard binary form.
11. RNS OVERVIEW
In RNS, an integer X is uniquely represented by an r-tuple
of integers (x1,x2,....,xr) which is called the residue
representation of X. The integers xi, i = 1,2,.,..,r are called
the residues and are obtained as remainders when the number
X is divided by a set of distinct relatively prime integers mi, i
= 1,2,. ..,r, which are called the moduli of the residue number
system. Thus, xi = X mod mi, denoted by lXlmi , where
O<xixi<mi.It follows from the Chinese Remainder Theorem
(CRT) that, for any given r-tuple satisfying the above
relationships, there exists one and only one integer X such
that OIX<M where M = n;=,mi defines the range of the
number system. The number X can be evaluated from the r-
tuple (x,, x2,...,xr) using (1):
Arithmetic operations on two operands X and Y are
defined as: Z = X O Y , where X = (x1,x2, ...,xr), Y = (yI,y2,
and zi = xi yi for i = 1,..., r. The
...,yr), Z = (ZI,ZZ, ...,q), O
symbol denotes any of the operations of addition,
subtraction or multiplication. From the above definition, it is
seen that these operations are performed in parallel in each of
the residue channels, independent of one another. This
inherent parallelism and the cany-free arithmetic between
different residue channels provide speed up during arithmetic
processing.
380
 111. MULTIPLICATION
USING INDEX CALCULUS TECHNIQUES
The relatively prime moduli for a maximum dynamic
range of 36 bits using 5-bits take any one of the three forms
p, 2m,and p,"' wher p is prime and m is any integer. It follows
from Number Theory that the groups formed by p, 2m, and
pm integer elements fall into the category of Galois Field
GF(p), and integer rings Z/(2m) and Z/(p"). When the
modulus happens to be a prime number p, the normal index
mapping in GF(p) is used and multiplication is done by index
addition. This can be speeded up in cases where p-1 is
factorable into relatively prime submoduli, these submoduli
being chosen with equal number of bits, wherever possible
[lo]. The only primes where p-1 cannot be factored into
relatively prime integers are those of the form 2"+1, where m
is an integer. A procedure for finding an index set for the
elements of Z/(2m) is given in [2,3]. Using this, any integer
X E [I, 2" -13 can be coded using a triplet index code a , p , y >
with the relationship X = 2a ISp (-1)'I 2m ' where
a~{O,l, ...,m-l}, PE(O,I ,...,(2"''2-1)} and y~{0,1).
Multiplication of two integers can now be carried out as
follows: let XI,X2 E Z/(2'"), XI f 0, X2 f 0, and
I I2m I
x1=2n' SDI (-1)yI , x 2 =2Q2 5P2 (-1)Y2 , then the product
12m
Ix,x~~~,,, = 2al+a2 5pl+p2(-1)YI+Y2
l2m.
The indices are added
subject to the following constraints: PI and p2 are added
mod 2m-2,y1 and y2 are added mod 2, and al and a2 are
added in normal binary mode. When ai + a2 equals m-1 the
corresponding p and y are made zero, and when it exceeds
m-1, the final result is made zero. Thus, by storing the index
and inverse index tables, multiplication of the nonzero
elements can be repIaced by index addition. Similarly, in the
case of Z/(p"), where p is odd, an index pair coding (a$)is
used, where X is given by X=(g"pP)modp"[4,5]. The
product of two numbers (XIX2 ) mod pm can now be
calculated as follows: let XI= (gal p P 1)mod p'" and
X2 = ( g a 2 p P 2 ) m o d p ' " ,then their product (XIX2) mod
Prn is given by:
IXIX21,,,,,= ( g a 1 p P 1 g a 2 p P 2 p"'
)mod
- (gal+a2P PI+&) mod pj'l
The indices are added subject to the following constraints:
a1and a2 are added mod $(pm),and PI and p2 are added in
normal binary mode. When PI + Pz exceeds m-1, the final
result is made zero. It may be noted that more than one index
pair <a$> generated during index addition may correspond
to the same residue value. From the above it can be seen that
prime and powers of prime moduli emerge as ideal
candidates for the design of index transform based
multipliers. For the design of a 36 bit multiplier we decided
to go with moduli of up to 5 bits in length. The prime moduli
include 17,19, 23, 29, and 31, and powers of prime moduli
381
include 25, 27 and 32. All these moduli together give an
overall range of 36 bits. The above multiplication is valid for
all the nonzero elements of the corresponding field or ring.
When the residue becomes zero, index cannot be defined.
Hence extra logic is incorporated in the design as proposed in
[8]. By performing multiplication exclusively in logarithmic
domain considerable savings in ROM requirements are
achieved. The formulae for the computation of the ROM
requirements for the three types of moduli are shown in Table
1, In this table, ROM 1 stores the index table and ROM 2
stores the inverse index table, where si refers to the
submoduli of p-1 and sl is the smallest of these. The (sl+l)
term used in the prime modulus formula accounts for the
extra code added to handle the zero operands.
IV. MACARCMTECTURE
The basic operation involved in the MAC is the
summation of a number of products, given by CEiXiyi.
Consider that the operands Xi and Yi are represented in
residue form using a moduli set {ml,m2,...,mr} as Xi =
( x I I , x ~...,
~xir}
, and Yi = {yil,yil,...,yir}. In residue notation,
the above summation thus becomes r independent
summations, z[* ,.-,Ci=ixirYir .
xjlyjl , C jN= I x i 2 ~ , 2,-.,Ci=ixq~u
N N
Hence a MAC unit is implemented by using r separate
channels each working independently and in parallel. As
mentioned earlier, the moduli set is chosen so as to
implement multiplication by transforming to logarithmic
addition. For our 36-bit processor, we selected the 5-bit
balanced moduli set { 17,19,23,25,27,29,31,321 which
enables exclusive logarithmic addition: A block schematic of
a MAC unit for one of the residue channels is shown in Fig.
1. The two residues qj and yij of channelj address two index
ROMS that are used to find the logarithm corresponding to
these operands. The output from the index ROMs are added
using a modulo mi adder.
TABLE I. MULTIPLIER
ROM REQUIREMENTS
Modulus
Prime
p=2m+1
Prime
p#2m+I I
2"'
P"'
 Xij Yij

Index Index

A U U B -
Inverse Index ROM
H

+
Register 1 1
H=ACBB

S = H €BCi,

r-7 Modulo Adder

Fig. 2. A Fully Restored CMOS Full Adder Cell

These residues are generated simultaneously and are

Fig. 1. A single channel of MAC unit
The adder output addresses an inverse index ROM to
generate the residue product. In the non-prime modulo
channels, the modulo adder comprises two or three
submodules depending on the use of odd or even values for p
respectively. This is for performing the individual index
additions C W and, y~. The accumulate stage consists of a
modulo adder and a register (accumulator) which is
initialized to zero.
The modulo adders shown in Fig. 1 employ the standard
biased-addition scheme given in [ 6 ] .An offset value of 2"-mi
is added to a 2" bit adder to make a modulo mi adder, when
added using modulo adders to get the final residue. A total of
r-1 similar stages are needed to generate the residues
x l ,x2 ,..., x,.-~. It is obvious that modulus of the form 2"
(32) does not require extra logic and for cases of the form 2"-
1 and 2"+1 (31 and 17) the ROMs needed otherwise can be
eliminated. For mod 31, the most significant partition is a
single bit and hence a simple logic circuitry instead of ROM
is used to generate its equivalent residue.
The reverse converter design chosen here is based on CRT
and is shown in Fig. 4 [SI.The conversion is performed by
evaluating the quotient alone so that it always uses less
hardware. The only requirement imposed is that one of thc
moduli is of the form 2". By storing the contents of ROM
with respect to modulus e instead of M, the ROM widths

mi is less than 2"-1, A modification is also done based on the
fact that the offset value to be added is known a-priori. So the
logic requirements of the second adder in a cascade of two
can be brought down to half. Thus the primitive cells of the
basic mod mi adder are constructed from a full adder (FA)
followed by a zero- primitive (one-primitive) for a zero-offset
(one-offset). To bring down the power and area requirements,
the transmission gate adder used in the above adder is
replaced with a new low power counterpart given in [7]. This
14 transistor pass logic adder implementation which
outperforms all other counterparts is shown in Fig. 2.
have been reduced by 5 bits. This amounts to an overall
reduction of 2 " x n x r (1280) bits of ROM for the entirp
design. The reduction in total hardware requirements due to
this is about 14% compared to earlier ones. There is also a
14% delay reduction assuming the use of carry propagate
adders.
1- n+ Register 1
t n-+

V. FORWARD
AND REVERSE CONVERTERS

To generate the residues in the forward conversion stage

a logic as shown in Fig. 3 is used. The k bits of Register 1
which stores the input binary operand are partitioned into 1
partitions, each of n bits wide. When k # nl, the width of the
last (leftmost) partition will be k mod n bits. Each partition Fig. 3. Residue Generation Logic for xj
group of Register 1 addresses a ROM that is programmed to
produce its residue with respect to mj.

382
 XI Binary to Residue MAC Residue to Binary
Converter Converter

Fig. 4. Residue-to-Binary Converter

C
Finally, a block schematics of a 36-bit MAC unit
---+
complete with the forward and reverse converters is shown in
Fig. 5 .

VI. CONCLUSIONS

A high speed 36-bit MAC unit is presented in this paper.

It uses eight 5-bit moduli which map into prime and powers
of prime integers, by virtue of which multiplication is done
exclusively by using index calculus techniques. This makes
the multiplier faster than conventional ones thereby
enhancing the performance of the entire system. The chosen
forward and reverse converters make the design further space
efficient and the CMOS pass logic adder cells used contribute
to a reduction in power consumption. The totai hardware
requirements is less than 3Kbytes of ROM, sixty four 5-bit
modulo adders and a few registers and other logic elements.
Fig. S. A 36-bit 8 moduli MAC unit
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