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1144 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-20, NO.

6, DECEMBER 1985

Low-Voltage Operational Amplifier with


Rail-to-Rail Input and Output Ranges
JOHAN H. HUIJSING, SENIOR MEMBER, IEEE, AND DANIEL LINEBARGER, MEMBER, IEEE

Abstract — An operational amplifier is described which can perform sister pairs are connected in parallel to the input. The
precision signal operations in nearly the full supply voltage range, even input of the n-p-n pair Ql, Q1 can reach the positive
when thk range is as slow as 1.5 V totally. The untrimmed input offset
supply provided the voltage drops across the collector
voltage is typically 0.3 mV in an input common-mode (CM) voltage range
which extends beyond both supply voltages for about 200 mV. The ,output resistances RIO and Rll do not cause significant saturation
voltage can reach each supply rail within 150 mV. A nested-loop of these transistors. Similarly, the input of the p-n-p pair”
frequency-compensation scheme yields a stable unity-gain bandwidth of 0.6 Q3, Q4 can reach the negative supply. The collector cur-
MHz while the low-frequency open-loop voltage gain is 110 dB. The op rents of the input transistors are summed by four folded
amp is integrated in a standard low-cost bipolar process and the chip
cascode transistors Q8 – Qll into one output current. Tran-
measures 1.5 X 1.7 mmz.
sistor Q8 is connected as a diode to ensure that the outputs
of Qz, QA are properly subtracted from those of Ql, Q3.
I. INTRODUCTION Three common-mode input voltage ranges can be dis-
tinguished.

o PERATIONAL amplifiers
should be able to utilize the largest possible part of
the supply-voltage range for input and output signal oper-
for low supply voltages 1) In the range from the negative
VEE + 0.7 V only the p-n-p pair Ql, Qz is operating.
2) In the range from the positive
supply voltage

supply voltage
V~~

Vcc
to

to
ations in order to get the best signal-to-noise ratio. Usually, V== – 0.7 V only the n-p-n pair Q3, Qd is operating.
base–emitter or gate–source voltages prevent the input 3) In the intermediate range both pairs are operating.
and/or output from reaching the positive and/or negative When the CM voltage moves from one range into ano~her
supply voltages within about 0.7 V [1]. This becomes a the transconductance of the input stage changes by a factor
problem when the supply voltage is low as in battery- of two. This prevents frequency compensation from being
powered systems or in low-power applications. optimal since the bandwidth is proportional to that
The operational-amplifier design presented here includes transconductance. Moreover, transient distortion occurs
three new solutions to low supply-voltage operation: firstly, when fast changes in the common-mode voltage abruptly
an input stage with a rail-to-rail common-mode input-volt- saturate and restore the tail-current sources.
age range which achieves a constant transconductance over These drawbacks can be overcome by the activation of
the full common-mode range; secondly, a rail-to-rail class- only that input transistor pair which is able to function
All output stage; and thirdly, a simple overall frequency properly. In Fig. 2 [4] the n-p-n pair is normally activated
compensation structure that allows a large gain with three by the current source 1~1 via Q5 and the current mirror
or more common-emitter stages in cascade. With these Q,, Q,, while the p-n-p pair is nonconducting. That is the
measures an operational amplifier capable of performing case when the common-mode input voltage is at least 60
precision operations on signals in the nearly full supply- mV higher than the reference voltage V~l = 0.8 V at the
voltage range has been obtained. base of Q5. When the input CM voltage decreases through
the reference voltage VB1, the emitter current is gradually
steered from the emitter of Q5 to the p-n-p pair, removing
II. INPUT STAGE
current from the n-p-n pair. A turnover between 10 and 90
Rail-to-rail common-mode voltage swing at the input percent of the current takes place in a voltage turnover
can only be obtained by using two input stages in parallel range of about 120 mV, centered around the reference
such that the common-mode (CM) voltage of one can voltage VB1. Since the transconductance of bipolar tran-
reach the positive supply rail and that of the other the sistors is proportional to their emitter current, and since we
negative supply rail. keep the sum of the emitter currents constant, the
An example of such an existing input stage is given in transconductance of the combination of the p-n-p and
Fig. 1. [2], [3]. Two complementary emitter-coupled tran- n-p-n pairs is also constant. When the total supply voltage
sinks below a value of about 1.5 V at 25 ‘C. the transcon-
ductance strongly decreases in the middle of the CM range
Manuscriptreceived April 15, 1985; rewsed August 7, 1985.
J. H Huijsing was with the Signetlcs Corporation, Sunnyvale, CA in which the current source 1~1 becomes saturated.
94086 He is now with the Delft Umversity of Technology, Department of
Electrical Engineering, Mekelweg 4,2628 DC Delft, Holland,
The CM range extends above the positive as well as
D Linebarger is with the Slgnetlcs Corporation, Sunnyvale, CA 94086, below the negative supply-rail voltage for about 0.2 V at 25

0018 -9200/85 /1200-1144$01 .00 @I1985 IEEE


HUIJSING AND LINEBARGER: LOW-VOLTAGE OPERATIONAL AMPLIFIER 1145

1.~ ‘
Vc c

6 ‘BE3 +
10) I 02
% Q3

l,n
2 > Qs

cMIB— — 06 1’0’

4 (“t
c MIA= =
1,”, >

K ‘2 1’0”
+

4+ VBE3

R8 h) R9
‘D 1

L. D, z
1
K
+ 02
VD2 ,1[’”1 ~, ,$’” ~,, “
complementary summing 1- ‘ z
$ ‘FF
Inl)ut stage ctrcubt L
Y
J
~ ‘-
Fig. 1. Input stage with rail-to-rail common-mode voltage range. class - AB control push and PU!I
Darljnglon output transistors

Fig. 3. Output stage with rail-to-rail output-voltage swing and accurate


class-.4 B control.

Combining biasing and driving in this configuration


would lead to a complex feedforward signal path, for
example, like that in the low-voltage op amp LM1O [1].
The present design separates the functions of driving
and biasing, as can be seen in Fig, 3 [5]. The n-p-n output
transistor QI is connected with the emitter follower Qz in a
two-transistor combination. The p-n-p output transistor Q3
is connected with the emitter followers QA and Q5 in a
three-transistor combination. These output transistor com-
binations can directly be accessed by two driving signals, in
current control summing c!rcutt
equal phase, on their input bases. The biasing of the output
~~
complementary input stage transistor combinations is controlled, in opposite phase, by
the two collector signals of the differential amplifier con-
Fig. 2. Input stage with rail-to-rail common-mode voltage range and a
constant transconducttice over the full common-mode range. sisting of the transistors Q8, Qg. To this end the differen-
tial amplifier compares the summed voltages across two
diodes D1 and D2 at the base of Q8 with the summed
‘C, assuming the voltage across the resistors R ~–Rll is voltages across the two base–emitter junctions of the out-
about 0.2 V. put transistors QI arid Q3 at the base of Qg. To realize the
An undesirable property of these kinds of input stages is summing of the base–emitter voltage of Q3 this voltage is
that the input offset voltage will change between that of converted into a current by the base–emitter junction of
the n-p-n and p-n-p transistor pair when the CM input Qc and resistor R6 and reconverted into a voltage across
volkage crosses the turnover range. Proper circuit layout the base–emitter junction of Q7 and resistor R ~. The
with a cross-coupled quad for each input pair can typically summed voltage across the emitter-base junctions of the
keep the untrimmed offset voltage change below 0,1 mV. output transistors QI and Q3 ( V~~l + V~~3 ) is proportional
The impact on signal operations is that the CM rejection to the logarithm of the product of th~ push and pull
ratio (CMRR) for signals within the turnover range will currents 10P and ION, respectively. The cdihbined voltages
roughly be restricted to a value of minimally 120 mV/O.l across diodes D1 and D2 ( V~l + V~2) are proportional to
mV = 1200, or 62 dB. Moreover, the input supply current the logarithm of the square of the reference current l~l.
changes direction when the CM input voltage crosses the When the diode characteristics and temperatures of the
turnover range. To cope with this problem the bias current pairs Ql, ~i and Q3, D2 are equal, the feedback control
of the input transistors has-been kept as low as 2 PA, will cause ( VE~l + V~~3 ) to equal ( V~l + V~2 ). As a result
leaving about a 30-nA bias current. The input offset cur-
rent can be kept as small as a few nanoamperes.
Iop X ION= I;l. (1)

This relation shows an efficient dass-AB $siasing, in which


III. OUTPUT STAGE
none of the output transistors is ever completely cut off.
The dc and ac performance of the output stage, when
Rail-to-rail output voltage swing cannot be obtained by implemented in a standard bipolar process, is dominated
the popular class-AB voltage-follower configuration. In- by the relatively poor performance of the lateral p-n-p
stead, the push-and-pull output transistors must be con- output transistor Q3. A 16X emitter provides a reasonable
netted in a common-emitter configuration. current gain at a 10-mA positive output current. To in-
1146 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-20, NO. 6, DECEMBER 1985

case the third pole is shifted to higher frequencies by


reducing the gain of the output stage with local resistive
feedback and in the second case the third pole is broad-
banded with a relatively low output resistance. A method
which more efficiently utilizes the gain for both the high-
frequency linearization of the output stage and the low-
frequency external loop is the nested differentiating feed-
back loop described by Cherry [10]. However, this method
uses a rather complicated structure with poles and zeros
which would require too many on-chip capacitors.
I I I I I 1 [ I ! ! 4
The present high-frequency design (Fig. 4.) uses two
vE~
—-Y----~+- +Wv
nested Miller integrators with only two low-value capaci-
Input mterm edlate
f2 out put fl tors C~l and C~2 [11]. C~l is connected between the final
stage (3) stage [2) stage(l)
output and the output of the intermediate stage. C~2 is
Fig. 4, High-frequency design with three common-mode emitter stages
(simplified) and a nested Miller-compensation structure.
connected between the final output and the output of the
first stage.
The frequency characteristic of the intermediate and
crease the current capability of the driver transistor IQq, its
output stages is shown in Fig. 5(a). This combination has
current gain is boosted by a factor of 4 with a current
two pole frequencies ~1 and ~z. Insertion of the first Miller
mirror D3, QIO. When the total supply voltage decreases
capacitor C~l splits these frequencies such that jz is
below a value of about 1.5 V the p-n-p output transistor
shifted to a higher frequency ~~ and ~1 to a lower frequency
combination Q3, QQ is the first output transistor combina-
~,’. The result is a well-compensated combination of the
tion which cannot support 10 mA of output current. More-
intermediate and output stages which allows feedback by a
over, the bandwidth of the output stage at positive output
second Miller-integrator capacitor.
currents is limited by that of the lateral p-n-p output
The frequency characteristic of the whole amplifier is
transistor Qq to a value of the order of 1 MHz.
shown in Fig. 5(b). It has the additional third-pole
There is no doubt that the amplifier characteristics such
frequency ~~ of the input stage. After the first Miller
as output current capability, bandwidth, and slew rate
capacitor C~l is inserted, the frequency characteristic con-
would be much improved if Q3 could be implemented with
tains the pole frequencies ~( and ~~. The second Miller
a vertical p-n-p transistor.
capacitor C~2 splits these frequencies such that f3 is
Separation of the functions of biasing and driving pre-
shifted to a higher frequency j: and f( to a lowest
vents the driving signals from being delayed by the biasing
frequency f:.
circuitry. The output transistor combinations are directly
The result is a straight 6-dB/octave roll-off from one
accessible by driving signals on their input bases, as shown
dominating pole frequency f{’ down to O dB. No pole-zero
in Fig. 3. This is very important for a simple high-frequency
cancellation has been applied, so that the frequency re-
compensation. For example, the output transistor com-
sponse has no pole-zero doublets in the passband. The
binations can be HF compensated by Miller capacitors
nesting can basically be repeated by placing another non-
C~l~ and C~l~ between their collectors and their bases.
inverting amplifier in front of the left-hand stage and using
another Miller capacitor.
IV. HIGH-FREQUENCY DESIGN

Having fulfilled the requirements at the input and out- V. POLE FREQUENCIES

put by the input stage and the output stage, respectively,


we can now consider the overall design. The simplest The pole frequencies of the uncompensated intermediate

approach would be to connect the output of the input stage and output stages (Fig. 5(a)) are at fl = 1/2 mRIC1 = 10
with the input of the output stage [2], [6]. However, that kHz and f2 = l/2rRzC2 = 100 kHz with RI= 3 kfl, Cl=
combination does not have enough voltage gain for a 500 pF, R ~ = 300 kfi, Cz = 5 pF, while the transconduc-
general-purpose op amp when the output is loaded with a tances are GMI = 10-2 mho and G~2 = 10-4mh0, respec-
lK resistance. Such a situation could be compared with a tively. The p-n-p output transistor combination brings
pA741 without an emitter-follower output stage [7]. about a bandwidth-limiting pole frequency at fL = 4 MHz.
The only way to increase the gain is to insert a Insertion of C~l = 10 pF shifts f2 to a second band-
common-emitter intermediate stage between the output width-limiting pole frequency f~
stages. This is shown in a simplified form in Fig. 4. The
circuit has three dominating poles, one at the output of
each common-emitter gam stage. Simple pole splitting does The factor in parentheses represents the attenuation in the
not remove the third pole. feedback path through C~l by C2. Frequency f; should
This situation is similar to that of the power op amp not exceed 1/2 fL, otherwise complex poles would arise
pA791 [8] or the BiMos op amp CA3130 [9]. In the first causing a “bump” in the frequency response near 1/2 fL
HUIJSING AND LINEBARGER: LOW-VOLTAGE OPERATIONAL AMPLIFIER 1147

.
I
Voltage
80
GmI RG
I m2R>

\
Gain
\
(dB)
\
60-
\
\
\
Insert Cm,
LO - \
\
\
\
20-
\
\
\
\*j
o I 1 I I 1 I I
01 I 10 100 Ik 10k 100 k ,&f f~
\
_ frequency (Hz)

(a)

I
Voltage
120
/ f(~fj~fl

\
Gam .
(dB) \

100 \
\
\ Insert Cm,\
\
\
80 \
\

\
insert Cm, and Cm2.
60

\
\

\
.

20

0 1— -———
01 1 10 100 lk 10 k 100 k

— frequency ‘\
\
(b)

Fig. 5. (a) Frequency response of the output and intermediate stages of the amplifier of Fig. 4 with single Miller
compensation. (b) Frequency response of the complete amplifier of Fig. 4 with nested Miller compensation.

[7]. Special care must be taken with the design of the p-n-p and C3 = 2.5 pF, while the transconductance is G~,3= 5 x
output transistor combination to avoid the “bump” at 10-5 mho, the overall frequency response with C~l again
positive output currents higher’than 0.25 mA, at which Gnl shows (Fig. 5(a)) two dominant pole frequencies ~{ and ~~
would increase too much. and a frequency-limiting pole f;. Insertion of CM2 =14 pF
The values of C~l and G~2 are generally chosen such shifts f3 to a third bandwidth-limiting pole frequency f{:
that the frequency ~~ at which the 6-dB/octave slope in
the frequency response of the intermediate and output
fi = G~2/2TCm(l + C,/CMz) ‘1.3 MHz < l/2f;. (6)
stage crosses the O-dB line is lower than ~~; hence

fo’ = Gm2/zITCMI ‘1.6 MHz ~ f;. (3) The factor in parentheses represents the attenuation in the
feedback through C~2 by C3. If C~l and GM2 had been
Thle low-frequency gain A12 in the intermediate and output chosen such that ~~ would exceed 1/2 f;, complex poles
stages equals would have resulted. In fact, the present example has
slightly complex poles. In addition, to the poles, two zeros
appear above 10 MHz, one of which is a right half plane
The resulting lower pole frequency f{ equals zero. These zeros can be disregarded.
The values of CM2 and G~3 are generally chosen such
fz’ = f{/A12 = 160 Hz. (5)
that the frequency f; at which the 6-dB/octave slope
When the input stage (Fig. 4) is included with the third crosses the O-dB line is lower than 1/2 f{ in order that the
pole frequency f3= l/2nR ~C3= 30 kHz with R ~= 2 M!J unity-gain feedback amplifier shows no overshoot in the
1148 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-20, NO. 6, DECEMBER 1985

~ ~~ ~ ~ “
complementary input stage ,ntermed, ate stage class-AB control push and pull

w,th current control and Dart, ngton output Iranslstors


surnm”g c,rcutt
Fig, 6. Overall circuit of the low-voltage operational amplifier without
circuitry for protection, clipping, and biasing.

pulse response. Hence necessitates the use of an extra capacitor CP2 which bal-
ances out the second Miller capacitor C~2 and provides
fo’”= 1/2f3’. (7)
‘rn3/2TcM2 = ‘-6 ‘Hz< this stage with the right high-frequency ground reference.
The left-hand output side of the intermediate stage delivers
With an overall low-frequency gain of
two in-phase driving currents for the n-p-n and p-n-p
A ~23= GmlRlGm2R2Gm3R3 = 106 (8) output transistor combinations.
The “bump” in the frequency characteristic due to the
the resulting dominant pole frequency f{’ equals p-n-p output transistor combination is reduced by the
parallel diode capacitor CPI = 9 pF, the parallel diode
fi’ = fo’’/A123
= 0.6 Hz. (9)
Q130, and the driver booster QIAO, QIAI.
The resulting frequency response offers a low-frequency The bias circuit is given in Fig. 7. It includes a propor-
gain of 120 dB, equal to that of the uncompensated tional-to-absolute-temperature (PTAT) generator with the
amplifier, and a 6-dB/octave roll-off down to below unity four transistors Q61- Q6A. The transistors QG5, Q66 and
gain with a O-dB bandwidth of 0.6 MHz. Most of the Q68)Q69 Provide a low output impedance at the bias fines
high-frequency loop gain which has been spent for the V~cc and V~cc. The cascodes QCT and QTO reduce the
compensation is used internally to linearize the class-AB supply-voltage sensitivity. The emitter resistor of Q61 can
output stage and to lower its output impedance. be partly short circuited by an external pin for bias adjust-
ment. When short circuited its bias current is about 10 p A
and the total supply current is 0.5 mA. In this situation the
VI. OVERALL DESIGN
amplifier produces its normal characteristics. When open
The circuit of the complete low-voltage operational the bias current is about 2 p A and the total supply current
amplifier is drawn in Fig. 6 without the circuitry for is 0.1 rnA. In that situation the characteristics such as
protection. clipping, and biasing. output-current capability, bandwidth and slew rate are
The intermediate stage has not come up for discussion reduced by a factor of 3.
yet. Extending the symmetry of the input stage into the
intermediate stage improves the common-mode rejection
ratio. This ratio would otherwise suffer from the signal- VII. PERFORMANCE
dependent changes of the common-mode currents in the
summing circuit. Instead of a single output, the input stage The photomicrograph of the chip (Fig. 8) shows (left
delivers a symmetrical pair of output currents to the inter- middle) a quad layout for both the n-p-n and p-n-p input
mediate stage at the bases of Q35 and Q36. The common- pairs. The typical offset is only 0.3 mV. The offset change
mode component of these currents is controlled by feed- when crossing a voltage range of 100 mV between 0.75 and
back from the common-emitter point of the intermediate 0.85 V above the negative supply voltage is typically 0.1
stage to the bases of Qql and QA2 which are a part of the mV. The total MOS capacitance on the chip is only 26 pF.
summing circuit. The symmetry of the intermediate stage On the right-hand side the 16X output p-n-p and the 8 x
HIJIJSING AND LINEBARGER: LOW-VOLTAGE OPERATIONAL AMPLIFIER 1149

vcc
+

v
Bcc
%4

Q 67
4 VB1

+ ‘BEE

Q~1

d-l
76

Fig. 9. Open-loop frequency and phase characteristics of the low-volt-


Bias
age operational amplifier with Vc- – V~~ = 1.8 V and R ~ =10 kf).
adjust
‘E E

Fig. ,7. Bias circuit.

Vo(tage
TABLE I
Gam 100 TYPICAL CHARACTERISTICS OF THE LOW-VOLTAGE OPERATIONAL
(dB) AMPLIFIER AT A TOTAL SUPPLY VOLTAGE ( L’cc – V~~) BETWEEN
80
1.8 AND 15 V AND AT AN AMBIENT TEMPERATURE OF 25° C
60

Lo
Input offset voltage v~~ 0.3 mv
20
Temperature coefficient of VOS 4 /Iv/”c
0 -—T-––—T- r , Input offset current 10S 20 nA
1 10 100 lk 10k 100k 1 M 10M _ frequency i Hzl
N Input bias’ currrent IB 40 nA

IOM _ frequency Common mode rejection ratio CMRR


1 10 100 lk 10k 100k lM
o ld~ rail-to-rail at (VCC - VEE) ❑ 15V 97 dB

rail-to-rail at (Vcc - VEE) = 1.8V 85 dB


-90
between 0.6V and O 8V above VEE 66 dB
-180
Phase Common-mode range v~“ (Vcc + o 2) v
[degrees). 270
to (vE[ - 0 2)
I P Large s[gnal open-loop gain Avac 300 V/mV

Fig. 8. Photomicrograph of the low-voltage operational amplifier chip with R~=l OkQ
(1.5X 1,7 mm2). Output voltage swing Vout (Vcc -0 2) v
w[th RL:l OkQ to (vEE + o 2)
Quiescent supply current
output n-p-n can be distinguished. The chip measures 05 mA
bias pin to VIE
1.5 X 1.7 mm2. bias pin open 01 mA
The open-loop frequency and phase characteristics are Short-c !rcu[t output current 1s[

shown in Fig. 9. The dc gain is 110 dB with a resistive load bias pin to VIE +20/-40 mA
of 10 kfl. The bandwidth is 0.6 MHz and the unity-gain bias pin open + 8/-15 MA

phase margin is 79°. Open -1oop output resistance R,

freq. = 1 Hz 20k Q
The open-loop output impedance decreases from about
freq = 20kHz 1 Q
ZOI k~ at 1 HZ @ 1 Q at 20 kHZ. The unity-gain feedback
Slew rate SR
output impedance is as low as 30 mL? below 20 kHz. The
bias pin toVEE 0.25 V//is
op amp is stable with capacitive loads up to 1 nF. 01 v/ps
bias pin open
Typical characteristics are listed in Table I. The slew rate Smal l-signal gain-bandwidth product
is 0.25 V/p s. The input referred noise spectral density at 5 bias pin toVEc 0.6 MHz

kHz is 25 nV/Hzl/2. The low-frequency CMRR measured bias pin open 0.2 MHz

with a rail-to-rail input voltage swing is 97 dB at a total Unity-gain phase margin 70 Degrees

with R~ . 10kQ
supply voltage of 15 V and 85 dB at 1.8 V. The CMRR is
Input refered noise spectral denstty
66 dB when the CM voltage is in the range between 0.6 and
freq. = 5 kHz 25 nV/dHz
0.8 V above the negative supply voltage.
1150 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-20, NO. 6, DECEMBER 1985

a
‘L R3FERENCE5
*
.x *A
‘EE
. v ,. [1] R, J. Widlar, “Low voltage techniques,” IEEE J. Solid-State Cir-
. -!
. cuits, vol. SC-13, pp. 838–846, Dec. 1978.
[2] A. J, M. van Tuyl, “ LOCOMOS operational amplifier,” Electrical
. ~cc
.
~cc
Instrumentation Lab., Department of Electrical Engineering, Delft
v,.

~-
I ‘EE

_l-
g
“ lout
— RL
[3]

[4]
Univ. Technol.. Delft. The Netherlands.
B. Blauschild, ““Differential amplifier
U.S. Pat. Appl. Ser. No. 525.181, filed August 23, 1983.
J. H. Huijsing
Rem 051.547. Feb. 1979.
with’ rail-to-r~l

and R. J. van de Plassche, “Differential


capability,”

amplifier
with rail-to-rail input capability and controlled transconductance,”
(a) (b)
U.S. Pat. Appl. Ser. No. 602.231, filed April 19, 1984.
[5] J. H. Huijsing, “Integrated circuits for accurate linear anatogue
Fig. 10. (a) Voltage-to-current converter for negative currents. IOU, =
signat processing,” Ph.D. thesis, Delft Univ. Technol., Delft, The
Vin /R ~~ with – IOut > J~IA~ suPPLY. (b) Voltage-to-current converter
Netherlands 1981, pp. 103-112.
for positive currents. Iou, = ~n /R EE with Iou, > lBl~s ~uPPLY.
[6] J. M, van Tuyl, “An integrated low-voltage dual headphone ampli-
fier with no external components for mono operation,” in Proc.
IEEE Int. Conf. Consumer Electron., June 6, 1984, pp. 54-55.
A typical application of the rail-to-rail input common- [7] J. E. Solomon, “The monolithic op amp: A tutorial study,” IEEE J.
mode range is that the low-voltage op amp can be con- Solid-State Circuits, vol. SC.-9, pp 314-332, Dec. 1974.
[8] P. E, Gray, “A 15-W monolithic power operational amplifier,”
nected as a self-contained voltage-to-current converter for IEEE J. Solid-State Circuits, vol. SC-7, pp. 478-481, Dec. 1972.
either negative output currents (Fig. 10(a)) or positive [9] 0. H. Schande, “CMOS/bipolar linear integrated circuits;’ in
Proc. IEEE Int. So[id-State Circuits Con f.. Die. Tech. PaO..
J,” .> Feb.
currents (Fig. 10(b)). In Fig. 10(a) the differential input of 1974, pp. 136-137.
the op amp equates the input voltage and the voltage [10] D, M. Cherry, “A high quality audio power amplifier,” in Moniror
Proc. IREE Au.w.. Jan/Feb. 1978. DrI. 1-8.
across the current-measuring resistor R ~E. The negative [11] J. H. Huijsing, “ Mul(i-stage ampl;f]er with capacitive nesting for
supply terminal controls the current through R ~E. The frequency compensation,” U.S. Pat. Appl. Ser. No. 602.234, filed
Apiil 19; 1984.
output and positive supply terminals collect the current
through R ~E and deliver it to the output load. The nega-
tive output current equals

– Iout = Vin/R ~E. (lo)


The converter in Fig. 10(b) performs the same function
for positive currents. The lower threshold of the output
current is set by the amplifier bias current. The converter
can be used in combination with sensors to obtain a Johan H. Huijsing (SM81) was born in Ban-
dung, Indonesia on May 21, 1938. He received
two-wire supply-voltage-independent current signal.
the ingenieurs (M. S.) degree in electrical en-
gineering from Delft University of Technology,
Delft, The Netherlands, in 1969, and the Ph.D.
VIII. CONCLUSION degree from the same university in 1981 for work
on operational amplifiers.
The design goal of integrating a low-voltage operational Since 1969 he has been a member of the re-
amplifier which can perform precision signal operations on search and teaching staff of the Electronic Instru-
mentation Laboratory, Department of Electrical
nearly the full supply voltage range has been achieved. The Engineering, Delft University of Technology. His
usable signal range is about 0.2 V lower than the supply-rail interest is in research on analog integrated circuits and integrated ;ensors
voltages and is only limited by the saturation voltage of the for instrumentation systems.

output transistors. The lowest total supply voltage is 1.5 V


at 20 “C. At that voltage the input stage still has a constant
transconductance over the full supply voltage range and
the output transistors can deliver the full output current.
The highest supply voltage in the present process is 18 V.
Qualities such as output current capability, bandwidth, and
slew rate largely depend on the lateral p-n-p output tran-
sistor. When using an integration process which allows
Daniel Lkebarger (S’82-M77) was born in
better p-n-p’s these qualities can strongly be improved. Mount Shasta, CA on October 1, 1958. He re-
ceived the B. S.E.L. degree from California Poly-
technic State University, San Luis Obispo, CA,
ACKNOWLEDGMENT in 1982.
He joined Signetics Linear Division, Sun-
nyvale, CA, in 1982, where he is currently in-
The authors are indebted to B. Blausc@ld for his advice volved in the design and development of anatog
and to L. Burgyan and R. Lovelace for their support in the integrated circuits.
final design phase.

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