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Combinational Logic
circuits
HCMC_International University IT208_Digital Logic Design
Designing method
Consider the statements of the problem.
Define the inputs and outputs
The inputs are considered the variables.
The outputs are considered functions
Draw the block diagram of the circuit
Write the Truth Table to express the relationship
between the inputs and outputs so that the requirements
of the problem is met.
1. Decoder:
The most common decoder is binary decoder.
+ It has n inputs, 2n outputs.
+ There are enable inputs.
x1 x0 y3 y2 y1 y0 y0 x1.x0
x0 y0
x1 y1 0 0 0 0 0 1 y1 x1.x0
2 to 4 y 0 1 0 0 1 0
2
y2 x1.x0
y3 1 0 0 1 0 0
1 1 1 0 0 0 y3 x1.x0
x1 x0
y0
y1
y2
y3
x1 x0 y3 y2 y1 y0 y0 x1 x0 x1.x0
x0 y0
x1 y1 0 0 1 1 1 0 y1 x1 x0 x1.x0
2 to 4 y 0 1 1 1 0 1
2 y2 x1 x0 x1.x0
y3 1 0 1 0 1 1
y3 x1 x0 x1.x0
1 1 0 1 1 1
x1 x0
y0
y1
y2
y3
y0 G x1 x0 y3 y2 y1 y0 y0 G x1 x0 G.x1.x0
x0
x1 y1 0 0 0 1 1 1 0 y1 G x1 x0 G.x1.x0
2 to 4 y 0 0 1 1 1 0 1
2 y2 G x1 x0 G.x1.x0
y3 0 1 0 1 0 1 1 y3 G x1 x0 G.x1.x0
0 1 1 0 1 1 1
1 x x 1 1 1 1
x1 x2
G
y0
y1
y2
y3
74LS139D
74LS138N
U1
N0 1 A Y0 15 DEC0
N1 2 B Y1 14
Two decoders n to 2n 3 13 .
N2 C Y2 .
Y3 12
N3 6 11 .
G1 Y4
/E 4 ~G2A Y5 10 .
5 9
can be connected together ~G2B Y6
Y7 7
.
DEC7
74LS138N
to create a decoder (n+1) to U2
2n+1. 1
2
3
A
B
Y0
Y1
15
14
13
DEC8
.
C Y2 .
Y3 12
6 G1 Y4 11 .
4 ~G2A Y5 10 .
5 ~G2B Y6 9 .
Y7 7
DEC15
74LS138N
HCMC_International University IT208_Digital Logic Design
Combinational logic circuits
F1 x, y, z m0 m1 m3 m0 m1 m3
m0 .m1.m3 M 0 .M 1.M 3
F2 x, y, z 1,4,5 M 1.M 4 .M 5
F3 x, y, z 1,3,7 M 1.M 3 .M 7
HCMC_International University IT208_Digital Logic Design
Combinational logic circuits
VCC
U1
XZ 1 A Y0 15
YY 2 B Y1 14 F1
ZX 3 C Y2 13
Y3 12
6 G1 Y4 11
4 ~G2A Y5 10 F2
5 ~G2B Y6 9
Y7 7
F3
74LS138N
x0 x3 x2 x1 x0 y1 y0
x1
y0
y1 0 0 0 1 0 0
y1 x2 x3
x2 4 to 2 0 0 1 0 0 1
x3 0 1 0 0 1 0 y0 x1 x3
1 0 0 0 1 1
y1
x2
Priority encoder:
is the encoder having the priority property.
In case of having 2 or more inputs are active at the
same time, the input having the most priority will impact
on the output
y1
y0
74LS148D