`timescale 1ns/1ns

module tb();
reg clk,reset,in;
wire detect;
reg [8:0] data=9`b001101000;
initial
begin
clk=0;
reset=0;
#2 reset=1;
in=0;
#10;
in=0;
#10;
in=1;
#10;
in=1;
#10;
in=0;
#10;
in=1;
#10;
in=0;
#10;
in=1;
#10;
in=1;
#10;
in=0;
#10;
in=1;
#20;
$finish;
end
end
always #5 clk=~clk;
endmodule

module sequence_detect (output reg detect,

input clk,reset,in);
parameter WAIT_1=0,
WAIT_11=1,
WAIT_110=2,
WAIT_1101=3;
reg [1:0] state,next_state;
always @(posedge clk or negedge reset)
begin
if(!reset) begin
state<=WAIT_1;
end
else begin
state<=next_state;
end
end
always @(*)
begin
next<=x;
case(state)
WAIT_1: begin
 if(in==1) next_state=WAIT_11;
else next_state=WAIT_1;
end
WAIT_11: begin
if(in==1) next_state=WAIT_110;
else next_state=WAIT_1;
end
WAIT_110: begin
if(in==1) next_state=WAIT_110;
else next_state=WAIT_1101;
end
WAIT_1101: begin
if(in==1) next_state=WAIT_11;
else next_state=WAIT_1;
end
endcase
end
always @(posedge clk or negedge reset)
begin
if(!reset) begin
detect<=0;
end
else begin
detect<=0;
case(next_state)
WAIT_1,WAIT_11,WAIT_110 : ;
WAIT_1101: begin
if(in==1) detect<=1;
else detect<=0;
end

endcase
end
end
endmodule
////////////////////////////////////
module fm_onehot (input clk,reset,in,
output reg detect);

parameter WAIT_1=0,
WAIT_11=1,
WAIT_110=2,
WAIT_1101=3;
reg [3:0] state,next;
always@(posedge clk or negedge reset)
begin
if(!reset) begin
state<=0;
state[WAIT_1]<=1;
end
else begin
state<=next;
end
end
always@(*)
begin
next=0;
case(1'b1)
 state[WAIT_1] : if(in) next[WAIT_11]=1;
else next[WAIT_1]=1;
state[WAIT_11]: if(in) next[WAIT_110]=1;
else next[WAIT_1]=1;
state[WAIT_110]: if(in) next[WAIT_110]=1;
else next[WAIT_1101]=1;
state[WAIT_1101]: if(in) next[WAIT_11]=1;
else next[WAIT_1]=1;

endcase
end
always@(posedge clk or negedge reset)
begin
if(!reset) begin
detect<=0;
end
else begin
detect<=0;
case(1'b1)
next[WAIT_1],next[WAIT_11],next[WAIT_110] : ;//default
next[WAIT_1101] : if(in) detect<=1;
else detect<=0;
endcase
end
end
endmodule