Lenovo Yoga 510-14ikb Compal BIUS4S5 & CIUY0Y1 LA-E221P Rev 1.0 Схема PDF

A B C D E
Compal Confidential
1 1
BIUS4/S5 & CIUY0/Y1

2
DIS M/B Schematics Document 2
Intel KabyLake U Processor with DDR4

AMD R16M-M1-30/R16M-M2-50
3
2016-06-27 3
LA-E221P
REV!
!1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

2016/04/07 2017/02/16 Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E221P
Date: Tuesday, June 28, 2016 Sheet 1 of 50
A B C D E
1 2 3 4 5
BOM Structure Table

Voltage Rails Item BOM Structure
LAN 10/100 Transformer 100@
LAN Giga Transformer GIGA@
+5VS For Giga LAN Chip 8111H@
+3VS For 10/100 LAN Chip 8107E@
power
plane +1.35VS For DIS DIS@
A +1.0VS_VCCOPC For UMA UMA@ A
+5VALW +1.5V +VCC_CORE For GPU M1 Chip M1@

B+ +VGA_CORE For GPU M2 Chip M2@
+3VALW +VCC_GFXCORE_AXG For NFC Option NFC@
+1.8VS For Thermal Chip EX_THM@
State +0.75VS For Keyboard backlight KBL@
+1.0VALW No Keyboard backlight NOKBL@
For K/B 15 inch NUM LED 15_NUM@ *
For VARM X76 GM_X76@
For Hynix Memory H2G@
For Samsung Memory S2G@
For Micron Memory M2G@
S0
O O O O For EMI EMI@
For ESD ESD@
No EMI @EMI@
S3
O O O X No ESD @ESD@
No RF @RF@
S5 S4/AC
O O X X For RF RF@ CV194_RF@ only for DIS
Connector ME@
B S5 S4/ Battery only
O X X X For Test Point TP@ B
For 2+3E power 23E@

S5 S4/AC & Battery
X X X X For YOGA series only YOGA@
don't exist
For 14 inch only S14@
For 15 inch only S15@
For 15 inch UMA_EXTRA UMA_EXTRA@
6500U@
6200U@
For SKL CPU Type
6100U@
4405U@ USB 2.0 Port Table
EC SM Bus1 address EC SM Bus2 address EC SM Bus4 address ME SM Bus address
For KBL CPU Type KS@ External
Port USB Port
Device Address Device
NCT7718W
Address
1001 100x 98h
Device
BMA250E
Address
0001 100X 18h
Device
NFC
Address
0010 1000 28h
JW@
Smart Battery 0001 011x 16h 1 Touch panel (for YOGA only)
2 USB2/3 MB(JUSB1)
PCH SM Bus address GPU SM Bus address 3 USB2/3 MB(JUSB2)
4 USB2 IO Board(Charger)
Device Address Device Address
DDR_JDIMM1 1010 000x A0h Internal thermal sensor 1001 111x 9Eh
5 Camera
Touch Pad 6
C C
7 NGFF WLAN+BT
Port USB 3.0 Port Table

1
2 USB2/3 MB(JUSB1) PCIE Port Table
3 USB2/3 MB(JUSB2)
Port Lane
4
5 1 1
GPU
6 2 2
3 3
SATA Port Table 4 4
5 LAN
Port
6 NGFF WLAN+BT
0 HDD 7
1 8
9
10
D SIGNAL D
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
Issued Date 2016/04/07 Deciphered Date 2017/02/16
Size
Notes List
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-E221P
Tuesday, June 28, 2016 Sheet 3 of 50
1 2 3 4 5
5 4 3 2 1
BIVS3/ VE3 -PowerMap_SKL-U22_DDR3L_Volume_NON CS]
B+
D D
C C
B B
A A

Issued Date 2016/04/07 Deciphered Date 2017/02/16 Title
Power MAP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
5 4 3 2 1
5 4 3 2 1
[AAX05-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]
G3->S0 S0->S3/DS3 S0/ DS3 ->S0 S0->S5

+3VL_RTC +3VL_RTC
tPCH01_Min : 9 ms
SOC_RTCRST# SOC_RTCRST#
B+ B+
D D
+3VLP/+5VLP +3VLP/+5VLP
EC_ON EC_ON
tPCH04_Min : 9 ms
+5VALW/+3VALW/+3VALW_DSW +5VALW/+3VALW/+3VALW_DSW
Pull-up to DSW well if not implemented.
PM_BATLOW# PM_BATLOW#
PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)
+3V_PRIM +3V_PRIM
+1.8V_PRIM +1.8V_PRIM
EXT_PWR_GATE# If EXT_PWR_GATE# Toffmin is too small, Pwr EXT_PWR_GATE#

gate may choose to completely ignore it
+1.0V_MPHYPLL +1.0V_MPHYPLL
+1.0V_PRIM_CORE +1.0V_PRIM_CORE
tPCH34_Max : 20 ms
+1.0V_PRIM tPCH06_Min : 200 us +1.0V_PRIM
SUSACK# SUSACK#
tPCH02_Min : 10 ms
PCH_DPWROK PCH_DPWROK
tPCH03_Min : 10 ms
EC_RSMRST# EC_RSMRST#
tPLT02_Min : 0 ms Max : 90 ms
C C
AC_PRESENT AC_PRESENT
ON/OFF ON/OFF
tPCH43_Min : 95 ms
PBTN_OUT# PBTN_OUT#
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#
PM_SLP_S5# PM_SLP_S5#
tPCH18_Min : 90 us
ESPI_RST# ESPI_RST#
SYSON SYSON
+1.0V_VCCST/+1.0V_VCCSFR +1.0V_VCCST/+1.0V_VCCSFR
+1.35V_VDDQ/+1.35V_VCCSFR_OC +1.35V_VDDQ/+1.35V_VCCSFR_OC
SUSP# SUSP#
tCPU04 Min : 100 ns
+1.0VS_VCCSTG +1.0VS_VCCSTG
tCPU10 Min : 1 ms
B
+1.0VS_VCCIO +1.0VS_VCCIO B
T <=10msec
+5VS/+3VS/+1.5VS/+1.05VS
+5VS/+3VS/+1.5VS/+1.05VS
T = 10msec
EC_VCCST_PG EC_VCCST_PG
VR_ON VR_ON
tCPU19 Max : 100 ns
SM_PG_CTRL SM_PG_CTRL
tCPU18 Max : 35 us
+0.675VS_VTT +0.675VS_VTT
tCPU09 Min : 1 ms
+VCC_SA +VCC_SA
+VCC_CORE +VCC_CORE
+VCC_GT +VCC_GT
VR_PWRGD VR_PWRGD
tCPU16 Min : 0 ns
PCH_PWROK PCH_PWROK
H_CPUPWRGD H_CPUPWRGD
SYS_PWROK SYS_PWROK
A A
SUS_STAT# SUS_STAT#
SOC_PLTRST#
SOC_PLTRST#

2016/04/07 2017/02/16 Title
Issued Date Deciphered Date
Power Sequence
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
5 4 3 2 1
A B C D E
UC1A @ SKL-U
Rev_1.0
E55 C47
F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXN0 <26>
DDI1_TXP[0] EDP_TXP[0] EDP_TXP0 <26>
E58 D46 <eDP>
DDI1_TXN[1] EDP_TXN[1] EDP_TXN1 <26>
F58 C45
F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TXP1 <26>
G53 DDI1_TXN[2] EDP_TXN[2] B45
F56 DDI1_TXP[2] EDP_TXP[2] A47
G56 DDI1_TXN[3] EDP_TXN[3] B47
DDI1_TXP[3] EDP_TXP[3]
1 1
C50 E45
<27> HDMI_TX2-_CK DDI2_TXN[0] DDI EDP EDP_AUXN EDP_AUXN <26>
D50 F45
<27> HDMI_TX2+_CK DDI2_TXP[0] EDP_AUXP EDP_AUXP <26>
C52
<27> HDMI_TX1-_CK DDI2_TXN[1]
D52 B52
<27> HDMI_TX1+_CK DDI2_TXP[1] EDP_DISP_UTIL
A50
<HDMI> <27> HDMI_TX0-_CK B50 DDI2_TXN[2] G50
<27> HDMI_TX0+_CK DDI2_TXP[2] DDI1_AUXN
D51 F50
<27> HDMI_CLK-_CK C51 DDI2_TXN[3] DDI1_AUXP E48
<27> HDMI_CLK+_CK DDI2_TXP[3] DDI2_AUXN F48
DDI2_AUXP G46
DISPLAY SIDEBANDS RSVD F46
L13 RSVD
L12 GPP_E18/DDPB_CTRLCLK L9
GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7
GPP_E14/DDPC_HPD1 TMDS_B_HPD <27> From HDMI
N7 L6
<27> HDMICLK_NB N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9
HDMI DDC (Port C) <27> HDMIDAT_NB GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 EC_SCI# <10,34>
GPP_E17/EDP_HPD EDP_HPD <26> From eDP
N11
N12 GPP_E22 R12
<26> TS_I2C_RST# GPP_E23 EDP_BKLTEN ENBKL <26,34>
R11
EDP_COMP E52 EDP_BKLTCTL U13 INVPWM <26>
1 OF 20
EDP_RCOMP EDP_VDDEN PCH_ENVDD <26>
< Compensation PU For eDP > SKL-U_BGA1356
+1.0VS_VCCIO
RC3 1 2 EDP_COMP
2 24.9_0402_1% 2
Trace width=20 mils, Spacing=25mil, Max length=100mils

+1.0VS_VCCIO
1
If routed MS, PECI requires 18 mils spacing to other signals
+1.0V_VCCST RC4 UC1D @ SKL-U
1K_0402_5% Rev_1.0
SOC_CATERR# D63 < PU/PD for CMC Debug >
T99 TP@ CATERR# +1.0VS_VCCIO
H_PECI A54
<34> H_PECI
2
1 2 H_THERMTRIP# 1 2 H_PROCHOT#_R C65 PECI

<34> H_PROCHOT# PROCHOT# JTAG
RC5 1K_0402_5% RC6 499_0402_1% H_THERMTRIP# C63
SOC_OCC# A65 THERMTRIP# SOC_XDP_TMS RC11 1 @ 2 51_0402_5%
T100 TP@ SKTOCC#
CPU MISC B61 CPU_XDP_TCK0
XDP_BPM#0 C55 PROC_TCK D60 SOC_XDP_TDI SOC_XDP_TDI RC12 1 @ 2 51_0402_5%
T103 TP@ BPM#[0] PROC_TDI
XDP_BPM#1 D55 A61 SOC_XDP_TDO
T105 TP@ BPM#[1] PROC_TDO
XDP_BPM#2 B54 C60 SOC_XDP_TMS SOC_XDP_TDO RC13 1 @ 2 51_0402_5%
T107 TP@ BPM#[2] PROC_TMS
XDP_BPM#3 C56 B59 SOC_XDP_TRST#
T109 TP@ BPM#[3] PROC_TRST#
A6 B56 PCH_JTAG_TCK1
A7 GPP_E3/CPU_GP0 PCH_JTAG_TCK D59 SOC_XDP_TDI CPU_XDP_TCK0 RC14 1 @ 2 51_0402_5%
<26> TS_INT# GPP_E7/CPU_GP1 PCH_JTAG_TDI
ZZZ S14@ ZZZ YOGA@ BA5 A56 SOC_XDP_TDO
AY5 GPP_B3/CPU_GP2 PCH_JTAG_TDO C59 SOC_XDP_TMS PCH_JTAG_TCK1 RC15 1 @ 2 51_0402_5%
GPP_B4/CPU_GP3 PCH_JTAG_TMS C61 PCH_XDP_TRST#
PCH_TRST# T116 TP@
RC7 2 1 49.9_0402_1% CPU_POPIRCOMP AT16 A59 CPU_XDP_TCK0
RC8 2 1 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP JTAGX
RC9 2 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
2 1 EOPIO_RCOMP H65 OPCE_RCOMP
PCB BIUS4 LA-E221P LS-D451P 02 PCB CIUY0 LA-E221P LS-D452P/D453P 02 RC10 49.9_0402_1%
OPC_RCOMP SOC_XDP_TRST# RC23 1 @ 2 51_0402_5%
3 DAZ1PR00101 DAZ1R400100 3
4 OF 20
SKL-U_BGA1356
ZZZ S15@
KBL-U CPU SKL-U CPU

PCB BIUS5 LA-E221P LS-E221P 02 UC1 UC1
SA000094250 SA00009E620
DAZ1PQ00201
S IC FJ8066201930905 QJ8Q D0 2.1G C38 S IC FJ8066202499000 QK2Z K1 3.3G C38
4405@ 6567@
UC1 UC1
UC1 UC1 SA000092OA0 SA00009E510
SA0000A3870 SA0000A3730 S IC FJ8066201930409 SR2EY D1 2.3G BGA S IC FJ8066202499000 QK2Z K1 3.3G C38
S IC FJ8067702739738 SR2ZW H0 2.4G C38! S IC FJ8067702739739 SR2ZU H0 2.5G C38! 6200@ 6267@
ZZZ UMA_EMC_FP@ ZZZ DIS_EMC_FP@ ZZZ UMA_EMC_NFP@ ZZZ DIS_EMC_NFP@ I3@ I5@
UC1
UC1 SA000092P80
SA0000A3430 S IC FJ8066201930408 SR2EZ D1 2.5G BGA
S IC FJ8067702739740 SR2ZV H0 2.7G C38! 6500@
I7@
UC1
Part Number = X4EA4C38L01 Part Number = X4EA4C38L02 Part Number = X4EA4C38L03 Part Number = X4EA4C38L04 SA000092NA0
UMA_EMC with FP DIS_EMC with FP UMA_EMC without FP DIS_EMC without FP S IC FJ8066201931104 SR2EU D1 2.3G BGA
6100@
4 4
For EMC X4EJ BOM

Security Classification
2016/04/07
Compal Secret Data
2017/02/16 Title
SKL-U(1/12)DDI,EDP,MISC,CMC
LA-E221P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
Date: Thursday, July 14, 2016 Sheet 6 of 50
A B C D E
5 4 3 2 1
Interleaved Memory
SKL-U
UC1C @
UC1B @ SKL-U Rev_1.0
Rev_1.0
<18> DDR_A_D[0..15] Interleave / Non-Interleaved
DDR_A_D0 AL71 AU53 DDR_A_CLK#0 DDR_A_CLK#0 <18> AF65 AN45
DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKN[0] AT53 DDR_A_CLK0 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46
DDR0_DQ[1] DDR0_CKP[0] DDR_A_CLK0 <18> DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1]
D DDR_A_D2 AN68 AU55 DDR_A_CLK#1 DDR_A_CLK#1 <18> AK65 AP45 D
DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKN[1] AT55 DDR_A_CLK1 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46
DDR0_DQ[3] DDR0_CKP[1] DDR_A_CLK1 <18> DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1]
DDR_A_D4 AL70 AF66
DDR_A_D5 AL69 DDR0_DQ[4] BA56 DDR_A_CKE0 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56
DDR0_DQ[5] DDR0_CKE[0] DDR_A_CKE0 <18> DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0]
DDR_A_D6 AN70 BB56 DDR_A_CKE1 DDR_A_CKE1 <18> AK67 AP55
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[1] AW56 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55
DDR0_DQ[7] DDR0_CKE[2] TP@ T119 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2]
DDR_A_D8 AR70 AY56 TP@ T118 AF70 AP53
DDR_A_D9 AR68 DDR0_DQ[8] DDR0_CKE[3] AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDR_A_D10 AU71 DDR0_DQ[9] AU45 DDR_A_CS#0 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDR0_DQ[10] DDR0_CS#[0] DDR_A_CS#0 <18> DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0]
DDR_A_D11 AU68 AU43 DDR_A_CS#1 DDR_A_CS#1 <18> AH68 AY42
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_CS#[1] AT45 DDR_A_ODT0 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42
DDR0_DQ[12] DDR0_ODT[0] DDR_A_ODT0 <18> DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0]
DDR_A_D13 AR69 AT43 DDR_A_ODT1 DDR_A_ODT1 <18> AF69 AW42
DDR_A_D14 AU70 DDR0_DQ[13] DDR0_ODT[1] AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
DDR_A_D15 AU69 DDR0_DQ[14] AH69 DDR1_DQ[14]/DDR0_DQ[30]
DDR0_DQ[15] DDR3L / LPDDR3 / DDR4 DDR1_DQ[15]/DDR0_DQ[31] DDR3L / LPDDR3 / DDR4
BA51 DDR_A_MA5 DDR_A_MA5 <18> AT66 AY48
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50
<18> DDR_A_D[16..31] Interleave / Non-Interleaved DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA9 <18> DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR_A_D16 BB65 BA52 DDR_A_MA6 DDR_A_MA6 <18> AP65 BA48
DDR_A_D17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48
DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_MA8 <18> DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR_A_D18 AW63 AW52 DDR_A_MA7 DDR_A_MA7 <18> AN66 AP48
DDR_A_D19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BG0 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52
DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_BG0 <18> DDR1_DQ[21]/DDR0_DQ[53] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR_A_D20 BA65 AW54 DDR_A_MA12 DDR_A_MA12 <18> AT65 AN50
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48
DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR_A_MA11 <18> DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR_A_D22 BA63 BA55 M_A_ACT# <18> AT61 AN53
DDR_A_D23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52
DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_BG1 <18> DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR_A_D24 BA61 AU46 DDR_A_MA13 DDR_A_MA13 <18> AP60 BA43
DDR_A_D25 AW61 DDR0_DQ[24]/DDR0_DQ[40] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_MA15 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43
DDR0_DQ[25]/DDR0_DQ[41] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_MA15 <18> DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR_A_D26 BB59 AT46 DDR_A_MA14 DDR_A_MA14 <18> AN61 AY44
DDR_A_D27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_MA16 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44
DDR0_DQ[27]/DDR0_DQ[43] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_MA16 <18> DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR_A_D28 BB61 AU52 DDR_A_BA0 DDR_A_BA0 <18> AT60 BB44
DDR_A_D29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47
DDR0_DQ[29]/DDR0_DQ[45] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_A_MA2 <18> DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR_A_D30 BA59 AT48 DDR_A_BA1 DDR_A_BA1 <18> AU40 BA44
DDR_A_D31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_MA10 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46
C <18> DDR_A_D[32..47] DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_A_MA10 <18> DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] C
DDR_A_D32 AY39 BB50 DDR_A_MA1 DDR_A_MA1 <18> AT37 AY46
DDR_A_D33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46
DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_A_MA0 <18> DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR_A_D34 AY37 AR40
DDR_A_D35 AW37 DDR0_DQ[34]/DDR1_DQ[2] BA50 DDR_A_MA3 AP40 DDR1_DQ[36]/DDR1_DQ[20] BB46
DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDR_A_MA3 <18> DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[3]
DDR_A_D36 BB39 BB52 DDR_A_MA4 DDR_A_MA4 <18> AP37 BA47
DDR_A_D37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] AM70 DDR_A_DQS#0 AR37 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[4]
DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQSN[0] DDR_A_DQS#0 <18> DDR1_DQ[39]/DDR1_DQ[23]
DDR_A_D38 BA37 AM69 DDR_A_DQS0 DDR_A_DQS0 <18> AT33
DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSP[0] DDR1_DQ[40]/DDR1_DQ[24] Interleave / Non-Interleaved
DDR_A_D39 BB37 AT69 DDR_A_DQS#1 DDR_A_DQS#1 <18> AU33 AH66
DDR_A_D40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSN[1] AT70 DDR_A_DQS1 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[0]/DDR0_DQSN[2] AH65
DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSP[1] DDR_A_DQS1 <18> DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[0]/DDR0_DQSP[2]
DDR_A_D41 AW35 AT30 AG69
DDR_A_D42 AY33 DDR0_DQ[41]/DDR1_DQ[9] AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[1]/DDR0_DQSN[3] AG70
DDR0_DQ[42]/DDR1_DQ[10] Interleave / Non-Interleaved DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[1]/DDR0_DQSP[3]
DDR_A_D43 AW33 BA64 DDR_A_DQS#2 DDR_A_DQS#2 <18> AP33 AR66
DDR_A_D44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[2]/DDR0_DQSN[6] AR65
DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS2 <18> DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[2]/DDR0_DQSP[6]
DDR_A_D45 BA35 AY60 DDR_A_DQS#3 DDR_A_DQS#3 <18> AP30 AR61
DDR_A_D46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[3]/DDR0_DQSN[7] AR60
DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS3 <18> DDR1_DQSP[3]/DDR0_DQSP[7]
DDR_A_D47 BB33 BA38 DDR_A_DQS#4 DDR_A_DQS#4 <18> AU27 AT38
<18> DDR_A_D[48..63] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSN[4]/DDR1_DQSN[0] DDR1_DQ[48] DDR1_DQSN[4]/DDR1_DQSN[2]
DDR_A_D48 AY31 AY38 DDR_A_DQS4 DDR_A_DQS4 <18> AT27 AR38
DDR_A_D49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_A_DQS#5 AT25 DDR1_DQ[49] DDR1_DQSP[4]/DDR1_DQSP[2] AT32
DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_A_DQS#5 <18> DDR1_DQ[50] DDR1_DQSN[5]/DDR1_DQSN[3]
DDR_A_D50 AY29 BA34 DDR_A_DQS5 DDR_A_DQS5 <18> AU25 AR32
DDR_A_D51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6 AP27 DDR1_DQ[51] DDR1_DQSP[5]/DDR1_DQSP[3]
DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_A_DQS#6 <18> DDR1_DQ[52]
DDR_A_D52 BB31 AY30 DDR_A_DQS6 DDR_A_DQS6 <18> AN27 AR25
DDR_A_D53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_A_DQS#7 AN25 DDR1_DQ[53] DDR1_DQSN[6] AR27
DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[7]/DDR1_DQSN[5] DDR_A_DQS#7 <18> DDR1_DQ[54] DDR1_DQSP[6]
DDR_A_D54 BA29 BA26 DDR_A_DQS7 DDR_A_DQS7 <18> AP25 AR22
DDR_A_D55 BB29 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSP[7]/DDR1_DQSP[5] AT22 DDR1_DQ[55] DDR1_DQSN[7] AR21
DDR_A_D56 AY27 DDR0_DQ[55]/DDR1_DQ[39] AW50 AU22 DDR1_DQ[56] DDR1_DQSP[7] AN43
DDR0_DQ[56]/DDR1_DQ[40] DDR0_ALERT# DDR_A_ALERT# <18> DDR1_DQ[57] DDR1_ALERT#
DDR_A_D57 AW27 AT52 DDR_A_PARITY <18> AU21 AP43 TP@ T123
DDR_A_D58 AY25 DDR0_DQ[57]/DDR1_DQ[41] DDR0_PAR AT21 DDR1_DQ[58] DDR1_PAR AT13 DDR_DRAMRST#
DDR0_DQ[58]/DDR1_DQ[42] DDR1_DQ[59] DRAM_RESET# DDR_DRAMRST# <18>
DDR_A_D59 AW25 DDR CH - A AY67 +0.6V_VREFCA <18> AN22 DDR CH - B AR18
DDR_A_D60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR_VREF_CA AY68 AP22 DDR1_DQ[60] DDR_RCOMP[0] AT18
DDR_A_D61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR0_VREF_DQ BA67
+0.6V_A_VREFDQ <18> Trace width/Spacing >= 20mils AP21 DDR1_DQ[61] DDR_RCOMP[1] AU18 SM_RCOMP0 RC16 1 2 121_0402_1%
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] DDR1_VREF_DQ AN21 DDR1_DQ[62] 3 OF 20 DDR_RCOMP[2] SM_RCOMP1 RC17 1 2 80.6_0402_1%
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] 2 OF 20 AW67 DDR_PG_CTRL DDR1_DQ[63] SM_RCOMP2 RC18 1 2 100_0402_1%
B DDR0_DQ[63]/DDR1_DQ[47] DDR_VTT_CNTL SKL-U_BGA1356 B
SKL-U_BGA1356
DDR_VTT_CNTL to DDR +1.2V

VTT supplied ramped +1.2V
<35uS
1
+3VS
(tCPU18)
RC20
470_0402_5%
0.1U_0201_10V6K 2 1 CC101
2
UC7
1 5 RC54 DDR_DRAMRST#
NC VCC 220K_0402_5% 2
DDR_PG_CTRL 2 ESD@
2
A 4 CC96
Y DDR_VTT_PG_CTRL <41> 100P_0402_50V8J
3
GND 1
2
74AUP1G07GW_TSSOP5
SA00007WE00 RC19
@ 2M_0402_5%
Close to CPU
+1.2V
1
2
G
3 1
S
A A
Reserve for cost test. @ Q2009
MESS138W-G_SOT323-3
2016/04/07
Compal Secret Data
2017/02/16 Title
SKL-U(2/12)DDR3L
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E221P 1.0

5 4 3 2 1
5 4 3 2 1
SML0ALERT# (Internal Pull Down):

+3VS eSPI or LPC
0 = LPC is selected for EC ==> Default

RC112 1 2 10K_0402_5% KB_RST#
1 = eSPI is selected for EC
D UC1E @ SKL-U D
+3VALW Rev_1.0
SPI - FLASH
SMBUS, SMLINK
SOC_SPI_CLK AV2 R7 PCH_SMB_CLK SMB
SPI0_CLK GPP_C0/SMBCLK PCH_SMB_CLK <18,32>
RC21 1 @ 2 1K_0402_5% SOC_SPI_IO2 SOC_SPI_SO AW3 R8 PCH_SMB_DATA PCH_SMB_DATA <18,32>
SOC_SPI_SI AV3 SPI0_MISO GPP_C1/SMBDATA R10 SOC_SMBALERT# TP@ T124 (Link to DDR,TP)
SOC_SPI_IO2 AW2 SPI0_MOSI GPP_C2/SMBALERT#
SOC_SPI_IO3 AU4 SPI0_IO2 R9 SOC_SML0CLK
SOC_SPI_CS#0 AU3 SPI0_IO3 GPP_C3/SML0CLK W2 SOC_SML0DATA
SOC_SML0CLK <29> SML0
SPI0_CS0# GPP_C4/SML0DATA SOC_SML0DATA <29>
RC22 1 @ 2 1K_0402_5% SOC_SPI_IO3 AU2 W1 SOC_SML0ALERT# TP@ T125 (Link to NFC)
AU1 SPI0_CS1# GPP_C5/SML0ALERT#
RC24 1 @ 2 1K_0402_5% SPI0_CS2# W3
GPP_C6/SML1CLK V3
EC_SMB_CK2 <20,31,34> SML1
SPI - TOUCH GPP_C7/SML1DATA EC_SMB_DA2 <20,31,34>
AM7 SOC_SML1ALERT# (Link to EC,DGPU,Thermal Sensor)
M2 GPP_B23/SML1ALERT#/PCHHOT#
M3 GPP_D1/SPI1_CLK
From WW36 MOW for SKL-U ES sample J4 GPP_D2/SPI1_MISO
V1 GPP_D3/SPI1_MOSI
V2 GPP_D21/SPI1_IO2 AY13 LPC_AD0
GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 LPC_AD0 <34>
+1.8VS_3VS_PGPPA M1 LPC BA13 LPC_AD1
GPP_D0/SPI1_CS# GPP_A2/LAD1/ESPI_IO1 LPC_AD1 <34>
BB13 LPC_AD2
GPP_A3/LAD2/ESPI_IO2 LPC_AD2 <34>
AY12 LPC_AD3
C LINK GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <34>
RC25 1 2 8.2K_0402_5% SERIRQ BA12 LPC_FRAME#
GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# <34>
G3 BA11
G2 CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET#
G1 CL_DATA
CL_RST# AW9 LPC_CLK0 RC26 1 EMI@ 2 22_0402_5%
GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_EC <34>
AY9
KB_RST# AW13 GPP_A10/CLKOUT_LPC1 AW11 PM_CLKRUN#
<34> KB_RST# GPP_A0/RCIN# GPP_A8/CLKRUN#
C C
SERIRQ AY11
<34> SERIRQ GPP_A6/SERIRQ 5 OF 20
SKL-U_BGA1356
+3VS
RPC1, RPC3 and RC30 are close to UC3

RPC1
SOC_SPI_SO 1 8 SOC_SPI_SO_0_R SOC_SML0CLK 1 2
SOC_SPI_CLK 2 7 SOC_SPI_CLK_0_R RC28 499_0402_1%
SOC_SPI_SI 3 6 SOC_SPI_SI_0_R SOC_SML0DATA 1 2
SOC_SPI_IO3 4 5 SOC_SPI_IO3_0_R RC29 499_0402_1%
From SOC 33_0804_8P4R_5% SOC_SML1ALERT# 1 @ 2
EMI@ RC113 150K_0402_5%
SOC_SPI_IO2 1 2 SOC_SPI_IO2_0_R RPC2

RC30 EMI@ 33_0402_5% PCH_SMB_CLK 1 8
PCH_SMB_DATA 2 7
EC_SMB_CK2 3 6
EC_SMB_DA2 4 5
RPC3
EC_SPICLK 1 8 SOC_SPI_CLK_0_R 1K_0804_8P4R_5%
B <34> EC_SPI_CLK B
EC_MOSI 2 7 SOC_SPI_SI_0_R
<34> EC_SPI_MOSI
From EC EC_SPICS# 3 6 SOC_SPI_CS#0
<34> EC_SPI_CS0#
EC_MISO 4 5 SOC_SPI_SO_0_R +1.8VS_3VS_PGPPA
<34> EC_SPI_MISO
33_0804_8P4R_5%
EMI@ PM_CLKRUN# 1 @ 2
RC31 8.2K_0402_5%
Follow 543016_SKL_U_Y_PDG_0_9
< SPI ROM - 8M >

+3VALW
@
UC3 CC2 1 2 0.1U_0201_10V K X5R
SOC_SPI_CS#0 1 8
SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R
SOC_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_CLK_0_R
4 /WP(IO2) CLK 5 SOC_SPI_SI_0_R
GND DI(IO0)
1
W 25Q128FVSIQ_SO8
CC3
10P_0402_50V8J
2 @EMI@
A A
2016/04/07
Compal Secret Data
2017/02/16 Title
SKL-U(3/12)SPI,SMB,LPC,ESPI
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
LA-E221P 1.0

5 4 3 2 1
5 4 3 2 1
D D
UC1G @ SKL-U
Rev_1.0
< HD AUDIO >
AUDIO
RPC4
<28> HDA_BITCLK_AUDIO 1 8 HDA_BIT_CLK HDA_SYNC BA22
2 7 HDA_SYNC HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
<28> HDA_SYNC_AUDIO HDA_BLK/I2S0_SCLK
<28> HDA_SDOUT_AUDIO 3 6 HDA_SDOUT HDA_SDOUT BB22 SDIO / SDXC
4 5 BA21 HDA_SDO/I2S0_TXD
<28> HDA_SDIN0 HDA_SDI0/I2S0_RXD
AY21 AB11
33_0804_8P4R_5% AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
EMI@ J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
I2S1_TXD GPP_G4/SD_DATA3 W10
< To Enable ME Override > AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL
H5 AB7 1 @ 2
D7 GPP_D19/DMIC_CLK0 SD_RCOMP RC76 200_0402_1%
GPP_D20/DMIC_DATA0
D8 AF13
C C8 GPP_D17/DMIC_CLK1 GPP_F23 C
RC116 2 1 0_0402_5% HDA_SDOUT GPP_D18/DMIC_DATA1
<34> ME_EN
<28> HDA_SPKR HDA_SPKR AW5
GPP_B14/SPKR
7 OF 20
SKL-U_BGA1356
UC1I @ SKL-U
Rev_1.0
+3VS CSI-2
A36 C37
RC33 1 @ 2 2.2K_0402_5% HDA_SPKR B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
SPKR (Internal Pull Down): D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
TOP Swap Override B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13 1 @ 2
0 = Disable TOP Swap mode. ==> Default D31 CSI2_DN4 CSI2_COMP B7 RC80 100_0402_1%
B C33 CSI2_DP4 GPP_D4/FLASHTRIG B
D33 CSI2_DN5
1 = Enable TOP Swap Mode. A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
9 OF 20 AT1 1 @ 2
EMMC_RCOMP RC129 200_0402_1%
SKL-U_BGA1356
A A
2016/04/07
Compal Secret Data
2017/02/16 Title
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
Custom
LA-E221P 1.0

5 4 3 2 1
5 4 3 2 1
+3VS
@
+3VS SOC_XTAL24_IN
RPC5
2
8 1 CLKREQ_PCIE#4
7 2 CLKREQ_PCIE#5 RC134 SOC_XTAL24_OUT
6 3 UMA@ 10K_0402_5% 1 2
5 4 UC1J @ SKL-U RC34 1M_0402_5%
Rev_1.0
1
10K_0804_8P4R_5% VGA_CLKREQ# CLOCK SIGNALS
YC1
D42 24MHZ_12PF_5YEA24000122IF40Q3
RPC6 <19> CLK_PEG_VGA# CLKOUT_PCIE_N0
2
DGPU C42
8 1 <19> CLK_PEG_VGA AR10 CLKOUT_PCIE_P0 3 1
CR_CLKREQ# RC135 <20> VGA_CLKREQ# VGA_CLKREQ#
7 2 WLANCLK_REQ# DIS@ GPP_B5/SRCCLKREQ0# 3 1
10K_0402_5%
GND GND
15P_0402_50V8J
15P_0402_50V8J
6 3 B42
EC_SCI# <6,34> <35> CLK_PCIE_LAN# CLKOUT_PCIE_N1
1
D
5 4 LANCLK_REQ# LAN A42 F43
<35> CLK_PCIE_LAN D
1
CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N 4 2
CC4
CC5
<35> LANCLK_REQ# LANCLK_REQ# AT7 E43
10K_0804_8P4R_5% GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
2
D41 BA17 SUSCLK
<30> CLK_PCIE_WLAN# CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK <30>
NGFF WL+BT(KEY E) C41
<30> CLK_PCIE_WLAN CLKOUT_PCIE_P2
<30> WLANCLK_REQ# WLANCLK_REQ# AT8 E37 SOC_XTAL24_IN
GPP_B7/SRCCLKREQ2# XTAL24_IN E35 SOC_XTAL24_OUT
D40 XTAL24_OUT
+3VL_RTC <33> CLK_PCIE_CR# CLKOUT_PCIE_N3
Card Reader RTS5220 C40 E42 XCLK_BIASREF
<33> CLK_PCIE_CR CLKOUT_PCIE_P3 XCLK_BIASREF +1.0V_CLK5_F24NS
AT10
<33> CR_CLKREQ# GPP_B8/SRCCLKREQ3# AM18 SOC_RTCX1
RC36 1 2 20K_0402_5% SOC_SRTCRST# B40 RTCX1 AM20 SOC_RTCX2 XCLK_BIASREF 1 2
A40 CLKOUT_PCIE_N4 RTCX2 RC35 2.7K_0402_1%
CC6 1 2 1U_0402_6.3V6K CLKREQ_PCIE#4 AU8 CLKOUT_PCIE_P4 AN18 SOC_SRTCRST# 1 @ 2
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 SOC_RTCRST# RC110 60.4_0402_1%
E40 RTCRST#
E38 CLKOUT_PCIE_N5
CLKREQ_PCIE#5 AU7 CLKOUT_PCIE_P5
RC37 1 2 20K_0402_5% SOC_RTCRST# RC38 1 2 0_0402_5% GPP_B10/SRCCLKREQ5#
EC_CLEAR_CMOS <34>
CC7 1 2 1U_0402_6.3V6K 10 OF 20
Follow 546765_2014WW48_Skylake_MOW_Rev_1_0
CLRP2 1 2 SHORT PADS CLR CMOS SKL-U_BGA1356 Stuff 2.7k ohm(RC35) PU for SkyLake-U
RC39 1 2 1M_0402_5% SM_INTRUDER#

Stuff 60.4 ohm(RC110) PD for CannonLake-U
< PCH PLTRST Buffer >

RC42 1 2 0_0402_5%
C +3VS C
SOC_RTCX2
5
UC4
SOC_PLTRST# 1
P
B 4 SOC_RTCX1
Y PCI_RST# <19,30,33,34,35>
2
A
G
@ 1 2
1
TC7SH08FUF_SSOP5 RC41 10M_0402_5%
1
RC44
100K_0402_5%
SA007080100
+3VALW CC8
100P_0402_50V8J
2
ESD@ YC2
RPC7
2
1 2
8 1 PCH_PWROK
7 2 EC_RSMRST# 32.768KHZ 9PF 20PPM 9H03280012
6 3 LAN_WAKE#
5 4 SYS_RESET#
10K_0804_8P4R_5% 1 1
CC9 CC10
6.8P_0402_50V8C 6.8P_0402_50V8C
2 2
UC1K @ SKL-U
Rev_1.0
ESD@ 1 2 SYS_RESET# SYSTEM POWER MANAGEMENT
CC97 100P_0402_50V8J AT11 PM_SLP_S0#
GPP_B12/SLP_S0# TP@T130
ESD@ 1 2 EC_RSMRST# AP15 PM_SLP_S3#
GPD4/SLP_S3# PM_SLP_S3# <34>
CC94 100P_0402_50V8J SOC_PLTRST# AN10 BA16 PM_SLP_S4#
GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S4# <34,39,41>
ESD@ 1 2 SYS_PWROK SYS_RESET# B5 AY16 PM_SLP_S5# TP@T131
CC95 100P_0402_50V8J EC_RSMRST# AY17 SYS_RESET# GPD10/SLP_S5#
<34> EC_RSMRST# RSMRST# AN15
H_CPUPWRGD A68 SLP_SUS# AW15
Only For Power Sequence Debug T132 TP@ PROCPWRGD SLP_LAN#
B EC_VCCST_PG B65 BB17 SLP_WLAN# TP@T133
B
VCCST_PWRGD GPD9/SLP_WLAN# AN16 PM_SLP_A#
GPD6/SLP_A# TP@T134
SYS_PWROK B6
<34,44> SYS_PWROK SYS_PWROK
PCH_PWROK BA20 BA15 PBTN_OUT#
<34,44> PCH_PWROK PCH_PWROK GPD3/PWRBTN# PBTN_OUT# <34>
EC_RSMRST# BB20 AY15 AC_PRESENT RC103 1 @ 2 0_0402_5%
+3VALW DSW_PWROK GPD1/ACPRESENT VCIN1_AC_IN <20,34,39>
AU13 PM_BATLOW#
AR13 GPD0/BATLOW#
1 2 WAKE# AP11 GPP_A13/SUSWARN#/SUSPWRDNACK +3VALW
RC47 1K_0402_5% GPP_A15/SUSACK# AU11
WAKE# BB15 GPP_A11/PME# AP16 SM_INTRUDER#
LAN_WAKE# AM15 WAKE# INTRUDER# PM_BATLOW# 1 2
AW17 GPD2/LAN_WAKE# AM10 RC46 8.2K_0402_5%
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 SOC_VRALERT# AC_PRESENT 1 @ 2
GPD7/RSVD 11 OF 20 GPP_B2/VRALERT# RC48 10K_0402_5%
SOC_VRALERT#1 @ 2
+1.0V_VCCST SKL-U_BGA1356 RC50 10K_0402_5%
From EC (Open-Drain)
1
RC52
1K_0402_5%
2
RC53 1 2 60.4_0402_1% EC_VCCST_PG

<34> VCCST_PWRGD
100P_0402_50V8J
CA47 ESD@
A A

SKL-U(5/12)CLK,PM,GPIO
Custom
LA-E221P 1.0

5 4 3 2 1
5 4 3 2 1
GSPI0_MOSI (Internal Pull Down):

No Reboot
0 = Disable No Reboot mode. ==> Default

1 = Enable No Reboot Mode. (PCH will disable the TCO
D Timer system reboot feature). This function is useful D
when running ITP/XDP.
GSPI1_MOSI (Internal Pull Down):
Boot BIOS Strap Bit
0 = SPI Mode ==> Default
1 = LPC Mode
+3VS UC1F @ SKL-U

Rev_1.0
1 2 4.7K_0402_5% GSPI0_MOSI LPSS ISH
RC59 @
AN8 P2
<29> NFC_DWL GPP_B15/GSPI0_CS# GPP_D9
RC60 1 @ 2 150K_0402_5% GSPI1_MOSI AP7 P3
AP8 GPP_B16/GSPI0_CLK GPP_D10 P4
GSPI0_MOSI AR7 GPP_B17/GSPI0_MISO GPP_D11 P1
C GPP_B18/GSPI0_MOSI GPP_D12 C
AM5 M4
AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3
AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
<34> SENSOR_EC_INT GPP_B21/GSPI1_MISO
GSPI1_MOSI AN5 N1
+3VS RPC10 GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
AB1 GPP_D8/ISH_I2C1_SCL
<29> NFC_RST GPP_C8/UART0_RXD
1 8 UART0_RTS AB2 AD11
2 7 UART0_CTS W4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12
3 6 UART0_RX AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
<30> WLBT_OFF# GPP_C11/UART0_CTS#
4 5 UART0_TX
<30> UART0_RX AD1 U1
49.9K_0804_8P4R_1% AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2
<30> UART0_TX GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
<30> UART0_RTS AD3 U3
+3VS AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4
<30> UART0_CTS GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
AC1 DGPU_PWR_EN
GPP_C12/UART1_RXD/ISH_UART1_RXD DGPU_PWR_EN <21,34,48>
U7 AC2 DGPU_HOLD_RST#
<34> I2C0_SDA_SEN GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD DGPU_HOLD_RST# <19>
U6 AC3 DGPU_PWROK DGPU_PWROK <48>
<34> I2C0_SCL_SEN GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# +3VS
RC27 1 @ 2 1K_0402_5% I2C1_SDA_TS AB4 DGPU_PRSNT#
U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
<26> I2C1_SDA_TS GPP_C18/I2C1_SDA
RC32 1 @ 2 1K_0402_5% I2C1_SCL_TS U9 AY8 MB_ID RPC8
<26> I2C1_SCL_TS GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 DGPU_PWR_EN 1 8
AH9 GPP_A19/ISH_GP1 BB7 DGPU_HOLD_RST# 2 7
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7 DGPU_PWROK 3 6
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7 WLBT_OFF# 4 5
AH11 GPP_A22/ISH_GP4 AW7
B GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 B
AH12 AP13 10K_0804_8P4R_5%
GPP_F7/I2C3_SCL Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6
AF11
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL 6 OF 20 +3VS S15@ RC146
SD028100280
SKL-U_BGA1356 S RES 1/16W 10K +-5% 0402
DGPU_PRSNT#
2
S14@ Function (GPP_C15)
RC146
10K_0402_5% DIS 0
UMA Only 1
1
MB_ID
2
YOGA@ +3VS
RC147
10K_0402_5% R73 1 UMA@ 2 10K_0402_5% DGPU_PRSNT#
R74 1 DIS@ 2 10K_0402_5%
1
A A
2016/04/07
Compal Secret Data
2017/02/16 Title
SKL-U(6/12)GPIO,I2C,GSPI

5 4 3 2 1
5 4 3 2 1
UC1H @ SKL-U
Rev_1.0
PCIE / USB3 / SATA SSIC / USB3

D H8 D
USB3_1_RXN G8
H13 USB3_1_RXP C13
<19> PCIE_PRX_DTX_N1 PCIE1_RXN/USB3_5_RXN USB3_1_TXN
<19> PCIE_PRX_DTX_P1 G13 D13
CC11 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N1 B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP
<19> PCIE_PTX_C_DRX_N1 PCIE1_TXN/USB3_5_TXN
<19> PCIE_PTX_C_DRX_P1 CC14 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_P1 A17 J6 USB3_RX2_N <33>
PCIE1_TXP/USB3_5_TXP USB3_2_RXN / SSIC_RXN H6
USB3_2_RXP / SSIC_RXP USB3_RX2_P <33>
G11 B13 USB2/3 MB(JUSB1)
<19> PCIE_PRX_DTX_N2 PCIE2_RXN/USB3_6_RXN USB3_2_TXN / SSIC_TXN USB3_TX2_N <33>
F11 A13
<19> PCIE_PRX_DTX_P2 PCIE2_RXP/USB3_6_RXP USB3_2_TXP / SSIC_TXP USB3_TX2_P <33>
CC15 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N2 D16
<19> PCIE_PTX_C_DRX_N2 CC16 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_P2 C16 PCIE2_TXN/USB3_6_TXN J10
<19> PCIE_PTX_C_DRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN USB3_RX3_N <33>
H10 USB3_RX3_P <33>
H16 USB3_3_RXP B15
dGPU <19> PCIE_PRX_DTX_N3 PCIE3_RXN USB3_3_TXN USB3_TX3_N <33> USB2/3 MB(JUSB2)
G16 A15
<19> PCIE_PRX_DTX_P3 PCIE3_RXP USB3_3_TXP USB3_TX3_P <33>
CC12 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N3 D17
<19> PCIE_PTX_C_DRX_N3 PCIE3_TXN
CC13 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_P3 C17 E10
<19> PCIE_PTX_C_DRX_P3 PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
<19> PCIE_PRX_DTX_N4 F15 PCIE4_RXN USB3_4_TXN D15
<19> PCIE_PRX_DTX_P4 CC17 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N4 B19 PCIE4_RXP USB3_4_TXP
<19> PCIE_PTX_C_DRX_N4 PCIE4_TXN
CC18 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_P4 A19 AB9 USB20_N1
<19> PCIE_PTX_C_DRX_P4 PCIE4_TXP USB2N_1 USB20_N1 <26>
AB10 USB20_P1 Touch panel (for YOGA only)
USB2P_1 USB20_P1 <26>
F16
<35> PCIE_PRX_DTX_N5 E16 PCIE5_RXN AD6 USB20_N2
<35> PCIE_PRX_DTX_P5 PCIE5_RXP USB2N_2 USB20_N2 <33>
LAN CC19 1 2 0.1U_0201_10V K X5R PCIE_PTX_DRX_N5 C19 AD7 USB20_P2 USB2/3 MB(JUSB1)
<35> PCIE_PTX_C_DRX_N5 PCIE5_TXN USB2P_2 USB20_P2 <33>
CC20 1 2 0.1U_0201_10V K X5R PCIE_PTX_DRX_P5 D19
<35> PCIE_PTX_C_DRX_P5 PCIE5_TXP AH3 USB20_N3
USB2N_3 USB20_N3 <33>
<30> PCIE_PRX_DTX_N6 G18 AJ3 USB20_P3 USB2/3 MB(JUSB2)
PCIE6_RXN USB2P_3 USB20_P3 <33>
<30> PCIE_PRX_DTX_P6 F18
1 2 0.1U_0201_10V K X5R PCIE_PTX_DRX_N6 D20 PCIE6_RXP AD9
C NGFF WLAN+BT <30> PCIE_PTX_C_DRX_N6
CC102
PCIE6_TXN USB2N_4
USB20_N4
USB20_N4 <33>
C
CC103 1 2 0.1U_0201_10V K X5R PCIE_PTX_DRX_P6 C20 AD10 USB20_P4 USB2 IO Board(Charger)
<30> PCIE_PTX_C_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 <33>
F20 AJ1 USB20_N5
<29> SATA_PRX_DTX_N0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_N5 <26>
E20 AJ2 USB20_P5 Camera
<29> SATA_PRX_DTX_P0 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 <26>
HDD B21 USB2
<29> SATA_PTX_DRX_N0 A21 PCIE7_TXN/SATA0_TXN AF6 USB20_N6
<29> SATA_PTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_N6 <29>
AF7 USB20_P6 Finger Printer
USB2P_6 USB20_P6 <29>
G21
F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N7 <30>
D21 AH2 USB20_P7 NGFF WLAN+BT
PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <30>
C21
PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9
<33> PCIE_PRX_DTX_N9 E23 PCIE9_RXN USB2P_8
<33> PCIE_PRX_DTX_P9 1 2 0.1U_0201_10V K X5R PCIE_PTX_DRX_N9 B23 PCIE9_RXP AG1
Card Reader <33> PCIE_PTX_C_DRX_N9
CC104
PCIE9_TXN USB2N_9
CC105 1 2 0.1U_0201_10V K X5R PCIE_PTX_DRX_P9 A23 AG2
<33> PCIE_PTX_C_DRX_P9 PCIE9_TXP USB2P_9
F25 AH7
E25 PCIE10_RXN USB2N_10 AH8
D23 PCIE10_RXP USB2P_10
C23 PCIE10_TXN AB6 USB2_COMP RC70 1 2 113_0402_1%
PCIE10_TXP USB2_COMP AG3 RC104 1 2 1K_0402_5%
RC71 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 RC105 1 2 1K_0402_5%
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9
GPP_E9/USB2_OC0# USB_OC0# <33>
T147 TP@ XDP_PRDY# D56 C9 USB_OC1# <33>
XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2#
T148 TP@ PROC_PREQ# GPP_E11/USB2_OC2#
BB11 B9 NFC_IRQ <29>
B GPP_A7/PIRQA# GPP_E12/USB2_OC3# B
E28 J1 +3VALW
PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 NFC_RST_KBL <29>
E27 J2 W L_OFF# <30>
D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3
C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
When PCIE8/SATA1A is used as SATA Port 1 (ODD), then E30 PCIE11_TXP/SATA1B_TXP H2
RPC9
PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1. F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 USB_OC0# 8 1
A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 USB_OC1# 7 2
B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 USB_OC2# 6 3
PCIE12_TXP/SATA2_TXP H1 5 4
8 OF 20 GPP_E8/SATALED#
10K_0804_8P4R_5%
SKL-U_BGA1356
+3VS
W L_OFF# RC139 1 @ 2 10K_0402_5%

NFC_IRQ RC138 1 @ 2 100K_0402_5%
A A
2016/04/07
Compal Secret Data
2017/02/16 Title
SKL-U(7/12)PCIE,USB,SATA
Custom
LA-E221P 1.0

5 4 3 2 1
5 4 3 2 1
+1.2V +1.0VS_VCCIO
UC1N @ SKL-U
Rev_1.0
+VL +1.0VALW CPU POWER 3 OF 4
AU23 AK28
+1.0V_VCCST AU28 VDDQ_AU23 VCCIO AK30
AU35 VDDQ_AU28 VCCIO AL30
VDDQ_AU35 VCCIO
1U_0402_6.3V6K
1U_0402_6.3V6K
I(Max) : 0.16 A(+1.0V_VCCST) AU42 AL42
+1.0VALW TO +1.0V_VCCST 1 1 VDDQ_AU42 VCCIO
CC21
CC22
RON(Max) : 25 mohm BB23 AM28
+1.0V_VCCST_R 2 1 BB32 VDDQ_BB23 VCCIO AM30
D V drop : 0.004 V D
VDDQ_BB32 VCCIO +VCCSA
0.1U_0201_10V K X5R
@ RC136 0_0402_5% 1 BB41 AM42
2 2 +1.0VS_VCCIO VDDQ_BB41 VCCIO
CC23
BB47
BB51 VDDQ_BB47 AK23
VDDQ_BB51 VCCSA AK25
UC5 2 VCCSA G23
1 14 +1.0V_VCCST AM40 VCCSA G25
2 VIN1 VOUT1 13 VDDQC VCCSA G27
VIN1 VOUT1 A18 VCCSA G28
RC74 2 1 0_0402_5% 3 12 1 2 VCCST VCCSA J22
EN_1.0V_VCCSTU
ON1 CT1
Follow 543977_SKL_PDDG_Rev0_91 VCCSA
<34,41> SYSON CC24 A22 J23
CC24 10PF ->22us(Spec:<= 65us) VCCSTG_A22 VCCSA
4 11 10P_0402_50V8J J27
VBIAS GND AL23 VCCSA K23
RC75 2 1 0_0402_5% EN_1.8VS 5 10 1 2 VCCPLL_OC VCCSA K25
<34,36,41> SUSP# ON2 CT2 CC25 K20 VCCSA K27
6 9 1000P_0402_50V7K K21 VCCPLL_K20 VCCSA K28
+1.8VALW 7 VIN2 VOUT2 8 +1.8VS VCCPLL_K21 VCCSA K30
VIN2 VOUT2 VCCSA
15 AM23
GPAD +1.8VS_R 2 1 VCCIO_SENSE AM22
EM5209VF DFN 14P DUAL LOAD SW RC137 0_0402_5% VSSIO_SENSE
+1.8VALW TO +1.8VS
1U_0402_6.3V6K
0.1U_0201_10V K X5R
1 1 H21 VSSSA_SENSE
VSSSA_SENSE VSSSA_SENSE <45>
CC26
CC27
H20 VCCSA_SENSE
VCCSA_SENSE VCCSA_SENSE <45>
14 OF 20
@
2 2 Trace Length Match < 25 mils
I(Max) : 0.2 A(+1.8VS) SKL-U_BGA1356
RON(Max) : 25 mohm
V drop : 0.005 V
C C
+1.0VALW TO +1.0VS_VCCIO
+1.0V_VCCST +1.0VS_VCCIO
+VL +1.0VALW I(Max) : 3.04 A(+1.0VS_VCCIO)
RON(Max) : 6.2 mohm PSC Side BSC Side
V drop : 0.019 V
0.1U_0201_10V K X5R
1U_0402_6.3V6K
1 1
CC30
CC32
UC6
+1.0VS_VCCIO
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
@ 1 1 1 1
2 2 2 VIN1
VIN2
CC28
CC34
CC35
7 6 +1.0VS_VCCIO_STG RC79 1 2 0_0805_5% @
VIN thermal VOUT 2 2 2
1
3
VBIAS CC33
SUSP# RC81 2 1 0_0402_5% 4 5 @ 0.1U_0201_10V K X5R
ON GND 2
B B
TPS22961DNYR_W SON8 Close to A18 Close to K20 Close to A22
change pakage of 1U from 0201 to 0402 change pakage of 1U from 0201 to 0402
+1.0VS_VCCIO +1.2V
BSC Side PSC Side BSC Side PSC Side BSC Side
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
22U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1
CC36
CC37
CC45
CC46
CC38
CC39
CC40
CC41
CC48
CC49
CC50
CC42
CC29
CC43
CC47
CC44
@ @ @ @ @ @
2 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2
change pakage of 10U
from 0402 to 0603
Underneath CPU Close to CPU Close to AL23 Close to AM40 Close to CPU Underneath CPU
A A
2016/04/07
Compal Secret Data
2017/02/16 Title
SKL-U(8/12)Power
Custom
LA-E221P 1.0

5 4 3 2 1
5 4 3 2 1
+1.0VALW +1.0V_APLL +1.0VALW +1.8VALW
RF@ UC1O SKL-U
LC1 Rev_1.0 +3VALW
MURATA BLM15EG221SN1D CPU POWER 4 OF 4
1 2 CC51 1 2 1U_0402_6.3V6K AB19
VCCPRIM_1P0
0.1U_0201_10V K X5R
SM01000HC00 AB20 AK15 +3V_1.8V_PGPPA
@ P18 VCCPRIM_1P0 VCCPGPPA AG15
D R_0402 2 VCCPRIM_1P0 VCCPGPPB D
CC31
RF@
Y16
CC54 1 2 1U_0402_6.3V6K AF18 VCCPGPPC Y15
AF19 VCCPRIM_CORE VCCPGPPD T16
1 @
Imax : 2.57A V20 VCCPRIM_CORE VCCPGPPE AF16
VCCPRIM_CORE VCCPGPPF
VCCPGPPF support 1.8V only
V21 AD15
VCCPRIM_CORE VCCPGPPG
CC55 1 2 1U_0402_6.3V6K DCPDSW AL1 V19
DCPDSW _1P0 VCCPRIM_3P3_V19
Follow 543016_SKL_U_Y_PDG_1_0 CC56 1 2 1U_0402_6.3V6K K17 T1 +1.0VALW
L1 VCCMPHYAON_1P0 VCCPRIM_1P0_T1
Close to K17 VCCMPHYAON_1P0
+1.0V_AMPHYPLL AA1 CC57 1 2 1U_0402_6.3V6K
CC60 1 2 22U_0603_6.3V6M N15 VCCATS_1P8
N16 VCCMPHYGT_1P0_N15 AK17
RC148
@
Imax : 1.54A N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
1 2 CC61 1 2 1U_0402_6.3V6K P15 VCCMPHYGT_1P0_N17 AK19
VCCMPHYGT_1P0_P15 VCCRTC_AK19 +3VL_RTC
22U_0603_6.3V6M
1U_0402_6.3V6K
Close to P15 P16 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14
0_0603_5% 1 1
CC58
CC59
+1.0V_AMPHYPLL K15 BB10 DCPRTC CC62 1 2 0.1U_0201_10V K X5R

L15 VCCAMPHYPLL_1P0 DCPRTC
@ @ VCCAMPHYPLL_1P0 A14
2 2 VCCCLK1 +1.0V_CLK6_24TBT
+1.0V_APLL V15
VCCAPLL_1P0 K19
AB17 VCCCLK2
Y18 VCCPRIM_1P0_AB17 L21
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_APLL
+3VALW AD17 N20 +1.0V_CLK4_F100OC

AD18 VCCDSW _3P3_AD17 VCCCLK4
+1.0V_CLK5_F24NS AJ17 VCCDSW _3P3_AD18 L19
C +1.0V_CLK5_F24NS C
VCCDSW _3P3_AJ17 VCCCLK5
+3V_1.8V_HDA AJ19 A10 +1.0V_CLK6_24TBT
RC85 1 2 0_0603_5% +3V_1.8V_HDA VCCHDA VCCCLK6
+3VALW RC115 RF@ AJ16 AN11
VCCSPI GPP_B0/CORE_VID0
22U_0603_6.3V6M
22U_0603_6.3V6M
MURATA BLM15EG221SN1D AN13

1 2 1 2 AF20 GPP_B1/CORE_VID1
1 1 VCCSRAM_1P0
CC63
CC64
0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
SM01000HC00 CC65 1U_0402_6.3V6K AF21
@ T19 VCCSRAM_1P0
R_0402 Close to AF20 VCCSRAM_1P0
@ @ 1 1 T20
2 2 VCCSRAM_1P0
CC99
@
CC66
RF@
1 2 AJ21
CC67 1U_0402_6.3V6K VCCPRIM_3P3_AJ21
2 2 @ Close to AJ21 AK20
VCCPRIM_1P0_AK20
1 2 N18
CC68 1U_0402_6.3V6K VCCAPLLEBB_1P0 15 OF 20
+1.0V_CLK4_F100OC Close to N18
Follow 543016_SKL_U_Y_PDG_1_0 +3V_1.8V_PGPPA SKL-U_BGA1356
@
RC87 1 2 0_0603_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1
CC70
CC69
+3VALW
@ @ LPC 3.3V
2 2
Follow 543016_SKL_U_Y_PDG_1_0 RTC Battery
B B
RC89 1 2 0_0402_5%
+1.0VALW +3VALW +1.8VALW +3VALW +3VL_RTC +RTCBATT
W=20mils
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+1.0V_CLK6_24TBT 1 1 1 1 1 1 RC90 1 2 0_0402_5%
CC73
CC71
CC72
CC74
CC75
CC76
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0201_10V K X5R
1U_0402_6.3V6K
+1.8VS_3VS_PGPPA 1 1 1 1 1
Follow 543016_SKL_U_Y_PDG_1_0 1
CC80
CC77
CC81
CC79
CC78
@ @ @ @ @ @ @ @ @ CC82
RC91 1 2 0_0603_5% 2 2 2 2 2 2 1U_0402_6.3V6K
2 2 2 2 2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
+3VS
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
CC85
CC86
Close to AG15 Close to Y16 Close to T16 Close to AK17

CC83
CC84
LPC 3.3V
@ @ @ @ Safty suggestion remove EE side ,Keep PWR side
2 2 2 2 RC93 1 2 0_0402_5%
A A
2016/04/07
Compal Secret Data
2017/02/16 Title
SKL-U(9/12)Power
Custom
LA-E221P 1.0

5 4 3 2 1
5 4 3 2 1
+VCCCORE +VCCCORE +VCCGT +VCCGT

UC1M SKL-U
UC1L SKL-U Rev_1.0
Rev_1.0 CPU POWER 2 OF 4
CPU POWER 1 OF 4
N70
A30 G32 A48 VCCGT N71
A34 VCC_A30 VCC_G32 G33 A53 VCCGT VCCGT R63
D D
AK33 VCC_A44 VCC_G37 G38 A66 VCCGT VCCGT R66
AK35 VCC_AK33 VCC_G38 G40 AA63 VCCGT VCCGT R67
AK37 VCC_AK35 VCC_G40 G42 AA64 VCCGT VCCGT R68
AK38 VCC_AK37 VCC_G42 J30 AA66 VCCGT VCCGT R69
AK40 VCC_AK38 VCC_J30 J33 AA67 VCCGT VCCGT R70
AL33 VCC_AK40 VCC_J33 J37 AA69 VCCGT VCCGT R71
AL37 VCC_AL33 VCC_J37 J40 AA70 VCCGT VCCGT T62
AL40 VCC_AL37 VCC_J40 K33 AA71 VCCGT VCCGT U65
AM32 VCC_AL40 VCC_K33 K35 AC64 VCCGT VCCGT U68
AM33 VCC_AM32 VCC_K35 K37 AC65 VCCGT VCCGT U71
AM35 VCC_AM33 VCC_K37 K38 AC66 VCCGT VCCGT W63
G30 VCC_AM38 VCC_K42 K43 AC69 VCCGT VCCGT W66
VCC_G30 VCC_K43
Trace Length Match < 25 mils VCCGT VCCGT
AC70 W67
K32 E32 AC71 VCCGT VCCGT W68
RSVD VCC_SENSE VCCCORE_SENSE <45> VCCGT VCCGT
E33 J43 W69
+1.0VS_VCCOPC AK32 VSS_SENSE VSSCORE_SENSE <45> VCCGT VCCGT
J45 W70
RSVD B63 SOC_SVID_ALERT# J46 VCCGT VCCGT W71
AB62 VIDALERT# A63 VR_SVID_CLK J48 VCCGT VCCGT Y62
VCCOPC_AB62 VIDSCK VR_SVID_CLK <45> VCCGT VCCGT
P62 D64 VR_SVID_DATA J50
+1.8VALW V62 VCCOPC_P62 VIDSOUT J52 VCCGT
VCCOPC_V62 G20 J53 VCCGT AK42
VCCSTG_G20
ALERT signal must be routed between CLK and DATA signals VCCGT VCCGTX_AK42
1 23E@ 2 +1.8V_VCCOPC H63 J55 AK43
RC111 0_0402_5% VCC_OPC_1P8_H63 +1.0VS_VCCIO J56 VCCGT VCCGTX_AK43 AK45
G61 J58 VCCGT VCCGTX_AK45 AK46
VCC_OPC_1P8_G61 J60 VCCGT VCCGTX_AK46 AK48
C VCCOPC_SENSE AC63 K48 VCCGT VCCGTX_AK48 AK50 C
T157 TP@ VCCOPC_SENSE VCCGT VCCGTX_AK50
For CPU 23e SKU T158 TP@ VSSOPC_SENSE AE63 K50 AK52
VSSOPC_SENSE K52 VCCGT VCCGTX_AK52 AK53
AE62 K53 VCCGT VCCGTX_AK53 AK55
AG62 VCCEOPIO K55 VCCGT VCCGTX_AK55 AK56
VCCEOPIO K56 VCCGT VCCGTX_AK56 AK58
AL63 K58 VCCGT VCCGTX_AK58 AK60
AJ62 VCCEOPIO_SENSE K60 VCCGT VCCGTX_AK60 AK70
VSSEOPIO_SENSE 12 OF 20 L62 VCCGT VCCGTX_AK70 AL43
L63 VCCGT VCCGTX_AL43 AL46
VCCGT VCCGTX_AL46
For CPU GT3 SKU
SKL-U_BGA1356 L64 AL50
@ L65 VCCGT VCCGTX_AL50 AL53
L68 VCCGT VCCGTX_AL60 AM48
L69 VCCGT VCCGTX_AM48 AM50
M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
N64 VCCGT VCCGTX_AM58 AU58
SVID ALERT N66 VCCGT
VCCGT
VCCGTX_AU58
VCCGTX_AU63
AU63
+1.0V_VCCST N67 BB57
Place the PU VCCGT VCCGTX_BB57
N69 BB66
resistors close to CPU VCCGT VCCGTX_BB66
VCCGT_SENSE J70 AK62 VCCGTX_SENSE T161 TP@
<45> VCCGT_SENSE VCCGT_SENSE VCCGTX_SENSE
1
VSSGT_SENSE J69 AL61 VSSGTX_SENSE T162 TP@

<45> VSSGT_SENSE VSSGT_SENSE
RC94 13 OF 20VSSGTX_SENSE
56_0402_5%
B B
Trace Length Match < 25 mils SKL-U_BGA1356
@
2
SOC_SVID_ALERT# 1 2 (To VR) For CPU GT3 SKU

VR_ALERT# <45>
RC95 220_0402_5%
+1.0VS_VCCOPC
BSC Side BSC Side
+1.0V_VCCST Intel recommended on 2016/2/2
SVID DATA Place the PU

resistors close to CPU
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1
1
CC87
CC88
CC89
CC90
CC91
CC107
CC106
CC92
CC93
CC108
RC96 @
@
23E@
23E@
23E@
23E@
23E@
23E@
23E@
100_0402_1%
2 2 2 2 2 2 2 2 2 2
2
VR_SVID_DATA
VR_SVID_DATA <45> (To VR)
Close to AE62,AG62 Close to AB62,P62,V62
A A
2016/04/07
Compal Secret Data
2017/02/16 Title
SKL-U(10/12)Power,SVID
Custom
LA-E221P 1.0

5 4 3 2 1
5 4 3 2 1
D D
UC1P SKL-U UC1Q SKL-U
Rev_1.0 Rev_1.0 UC1R SKL-U
GND 1 OF 3 GND 2 OF 3 Rev_1.0
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
C AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10 C
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15 18 OF 20
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356
AJ20 VSS VSS AR28 B22 VSS VSS E46 @
AJ4 VSS VSS AR35 B30 VSS VSS E50
AK11 VSS VSS AR42 B34 VSS VSS E53
B AK27 VSS VSS AR5 B58 VSS VSS F1 B
AK63 VSS VSS AR50 B62 VSS VSS F13
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL52 VSS VSS AT4 F68 VSS VSS F40
AL58 VSS VSS AT56 VSS VSS BA41
AL64 VSS VSS AT58 VSS
VSS VSS
16 OF 20 17 OF 20
SKL-U_BGA1356 SKL-U_BGA1356
@ @
A A
2016/04/07
Compal Secret Data
2017/02/16 Title
SKL-U(11/12)GND
Custom
LA-E221P 1.0

5 4 3 2 1
5 4 3 2 1
D D
UC1S SKL-U UC1T SKL-U

Rev_1.0 Rev_1.0
RESERVED SIGNALS-1 +1.8VALW SPARE
E68 BB68 AW69 F6

B67 CFG[0] RSVD_TP_BB68 BB69 AW68 RSVD_AW69 RSVD_F6 E3
D65 CFG[1] RSVD_TP_BB69 AU56 RSVD_AW68 RSVD_E3 C11
D67 CFG[2] AK13 RC98 AW48 RSVD_AU56 RSVD_C11 B11
CFG4 E70 CFG[3] RSVD_TP_AK13 AK12 0_0402_5% C7 RSVD_AW48 RSVD_B11 A11
C68 CFG[4] RSVD_TP_AK12 1 @ 2 U12 RSVD_C7 RSVD_A11 D12
D68 CFG[5] BB2 1 @ 2 U11 RSVD_U12 RSVD_D12 C12
CFG[6] RSVD_BB2 RSVD_U11 RSVD_C12
1U_0402_6.3V6K
C67 BA3 1 H11 F52
F71 CFG[7] RSVD_BA3 RC102 RSVD_H11 RSVD_F52
CFG[8]
CC98
G69 0_0402_5% 20 OF 20
F70 CFG[9] AU5 @
G68 CFG[10] TP5 AT5 2 SKL-U_BGA1356
H70 CFG[11] TP6 @
G71 CFG[12]
H69 CFG[13] D5
G70 CFG[14] RSVD_D5 D4
CFG[15] RSVD_D4 B2
E63 RSVD_B2 C2
F63 CFG[16] RSVD_C2
CFG[17] B3
E66 RSVD_B3 A3
F66 CFG[18] RSVD_A3
C CFG[19] AW1 C
CFG_RCOMP E60 RSVD_AW1
CFG_RCOMP E1
XDP_ITP_PMODE E8 RSVD_E1 E2
T183 TP@ ITP_PMODE RSVD_E2
AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
RSVD_AY1 RSVD_BB4
D1 A4
D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5
K45 RSVD_K46 TP4
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 RC97 1 @ 2 0_0402_5%
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
BA68 RSVD_TP_BA70 TP1 BB3 +3VS
RSVD_TP_BA68 TP2
J71 AY71 LPM_ZVM# 1 23E@ 2
J68 RSVD_J71 VSS_AY71 AR56 LPM_ZVM# RC114 10K_0402_5%
B RSVD_J68 ZVM# LPM_ZVM# <44> B
F65 AW71
G65 VSS_F65 RSVD_TP AW70
VSS_G65 RSVD_TP For 2+3e Solution
F61 AP56 PM_MSM# T185 TP@
LPM_ZVM#
E61 RSVD_F61 MSM# C64 SKL_CNL# +1.0V_VCCST PM_MSM#
RSVD_E61 PROC_SELECT#
19 OF 20 1 @ 2
RC99 100K_0402_5%
1 2 CFG_RCOMP SKL-U_BGA1356
RC100 49.9_0402_1% @
1 2 CFG4
Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0
RC101 1K_0402_5%
Stuff 100k(RC99) for CannonLake-U
Un-stuff 100k(RC99) for SkyLake-U
Display Port Presence Strap
1 : Disabled;
No Physical Display Port attached to Embedded Display Port
CFG4
0 : Enabled;
A An external Display Port device is connected to the Embedded Display Port A
2016/04/07
Compal Secret Data
2017/02/16 Title
SKL-U(12/12)CFG,RSVD
Custom
LA-E221P 1.0

5 4 3 2 1
A B C D E
<7> DDR_A_DQS#[0..7]
Reverse Type
<7> DDR_A_D[0..63]
<7> DDR_A_DQS[0..7]
Interleaved Memory 2-3A to 1 DIMMs/channel
+1.2V +1.2V
<7> DDR_A_MA[0..16]
JDIMM1
<7> DDR_A_BA0 1 2 +1.2V
<7> DDR_A_BA1 DDR_A_D4 3 VSS VSS 4 DDR_A_D1
<7> DDR_A_BG0 5 DQ5 DQ4 6
<7> DDR_A_BG1 DDR_A_D5 7 VSS VSS 8 DDR_A_D0
9 DQ1 DQ0 10
DDR_A_DQS#0 11 VSS VSS 12 +DIMM_VREF_DQ
DDR_A_DQS0 13 DQS0_C DM0*/DBI0* 14
DQS0_T VSS
2
1 15 16 DDR_A_D6 1
<7> DDR_A_CLK0 17 VSS DQ6 18
DDR_A_D7 RD2001 2 0_0402_5% +0.6V_VREFCA_R RD194
<7> DDR_A_CLK#0 19 DQ7 VSS 20 DDR_A_D2 <7> +0.6V_VREFCA
<7> DDR_A_CLK1 VSS DQ2 1K_0402_1%
DDR_A_D3 21 22 RD10
<7> DDR_A_CLK#1 23 DQ3 VSS 24 DDR_A_D9 20mil 2_0402_1%
1
DDR_A_D11 25 VSS DQ12 26 RD2011 @ 2 0_0402_5% 2 1
27 DQ13 VSS 28 DDR_A_D8 <7> +0.6V_A_VREFDQ
<7> DDR_A_CKE0 DDR_A_D12 29 VSS DQ8 30
<7> DDR_A_CKE1 31 DQ9 VSS 32 DDR_A_DQS#1
VSS DQS1_C 1
33 34 DDR_A_DQS1
<7> DDR_A_CS#0 35 DM1*/DBI1* DQS1_T 36 CD21
<7> DDR_A_CS#1 DDR_A_D13 37 VSS VSS 38 DDR_A_D14 0.022U_0402_16V7K
39 DQ15 DQ14 40 2
DDR_A_D15 41 VSS VSS 42 DDR_A_D10
DQ10 DQ11
2
43 44
DDR_A_D16 45 VSS VSS 46 DDR_A_D17 RD12 RD199
47 DQ21 DQ20 48
VSS VSS 24.9_0402_1% 1K_0402_1%
DDR_A_D20 49 50 DDR_A_D21
51 DQ17 DQ16 52
1
DDR_A_DQS#2 53 VSS VSS 54
<8,32> PCH_SMB_DATA 57 DQS2_T VSS 58 DDR_A_D23
<8,32> PCH_SMB_CLK DDR_A_D22 59 VSS DQ22 60
61 DQ23 VSS 62 DDR_A_D19
DDR_A_D18 63 VSS DQ18 64
<7> DDR_A_ODT0 65 DQ19 VSS 66 DDR_A_D29
<7> DDR_A_ODT1 DDR_A_D24 67 VSS DQ28 68
69 DQ29 VSS 70 DDR_A_D25
DDR_A_D28 71 VSS DQ24 72
73 DQ25 VSS 74 DDR_A_DQS#3
75 VSS DQS3_C 76 DDR_A_DQS3
77 DM3*/DBI3* DQS3_T 78
Note: 81 DQ30 DQ31 82
Layout Note: Check voltage tolerance of 83 VSS VSS 84
DDR_A_D26 DDR_A_D27
Place near JDIMM1 VREF_DQ at the DIMM socket 85 DQ26 DQ27 86
87 VSS VSS 88
89 CB5_NC CB4_NC 90
91 VSS VSS 92
93 CB1_NC CB0_NC 94
1 2 95 VSS VSS 96
2 +1.2V 6/16 INTEL suggest 1
RD165 2
240_0402_1% 97 DQS8_C DM8*/DBI8* 98 2
RD166 240_0402_1% 99 DQS8_T VSS 100

101 VSS CB6_NC 102
103 CB2_NC VSS 104
VSS CB7_NC
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
105 106
107 CB3_NC VSS 108 DDR_DRAMRST#_R
1 1 1 1 1 1 1 1 VSS RESET*
DDR_A_CKE0 109 110 DDR_A_CKE1
CKE0 CKE1
CD7
CD18
CD4
CD5
CD6
CD8
CD9
CD17
111 112 1
DDR_A_BG1 113 VDD1 VDD2 114 ESD@
2 2 2 2 2 2 2 2 DDR_A_BG0 115 BG1 ACT* 116 M_A_ACT# <7>
CD34
117 BG0 ALERT* 118 DDR_A_ALERT# <7> 100P_0201_25V8J
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11 2
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
123 A9 A7 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
4 as near side of the DIMM close to VDD pins A8 A5
DDR_A_MA6 127 128 DDR_A_MA4
129 A6 A4 130
+1.2V DDR_A_MA3 131 VDD7 VDD8 132 DDR_A_MA2
DDR_A_MA1 133 A3 A2 134
135 A1 EVENT* 136
VDD9 VDD10
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_A_CLK0 137 138 DDR_A_CLK1

DDR_A_CLK#0 139 CK0_T CK1_T 140 DDR_A_CLK#1
141 CK0_C CK1_C 142
1 VDD11 VDD12
1 1 1 1 1 1 1 1 @ 143 144 DDR_A_MA0
<7> DDR_A_PARITY PARITY A0
CD12
CD13
CD15
CD20
CD10
CD11
CD14
CD19
+ CD35
330U_D3_2.5VY_R6M
DDR_DRAMRST#_R RD45 1 2 0_0402_5%
2 2 2 2 2 2 2 2 2 DDR_A_BA1 145 146 DDR_A_MA10 DDR_DRAMRST# <7>
147 BA1 A10_AP 148
DDR_A_CS#0 149 VDD13 VDD14 150 DDR_A_BA0
DDR_A_MA14 151 S0* BA0 152 DDR_A_MA16
153 A14_WE* A16_RAS* 154 +DIMM_VREF_DQ
DDR_A_ODT0 155 VDD15 VDD16 156 DDR_A_MA15
DDR_A_CS#1 157 ODT0 A15_CAS* 158 DDR_A_MA13
159 S1* A13 160
DDR_A_ODT1 161 VDD17 VDD18 162
+3VS 163 ODT1 S2*/C0 164
165 VDD19 VREFCA 166
Place these caps on the VTT plane close to DIMM S3*/C1 SA2
167 168
3 +0.6VS 171 DQ37 DQ36 172 3
+3VS_DIMM 175 DQ33 DQ32 176
DDR_A_DQS#4 177 VSS VSS 178
DQS4_T VSS
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 1 1 1 181 182 DDR_A_D39

VSS DQ39
CD22
CD23
CD30 CD31 CD32 CD33 DDR_A_D38 183 184

C2142 CD28 185 DQ38 VSS 186 DDR_A_D35
VSS DQ35
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2U_0402_6.3V6M 0.1U_0201_10V6K DDR_A_D34 187 188

2 2 2 2 2 2 2 2 189 DQ34 VSS 190 DDR_A_D44
DDR_A_D41 191 VSS DQ45 192
193 DQ44 VSS 194 DDR_A_D45
DDR_A_D40 195 VSS DQ41 196
197 DQ40 VSS 198 DDR_A_DQS#5
close to DIMM VSS DQS5_C
199 200 DDR_A_DQS5
201 DM5*/DBI5* DQS5_T 202
205 DQ46 DQ47 206
209 DQ42 DQ43 210
213 DQ52 DQ53 214 +3VS +3VS
217 DQ49 DQ48 218
VSS VSS
2
2
DDR_A_DQS#6 219 220
DDR_A_DQS6 221 DQS6_C DM6*/DBI6* 222 RD109 RD108
223 DQS6_T VSS 224 DDR_A_D54
VSS DQ54 10K_0402_5% 10K_0402_5%
DDR_A_D55 225 226
+2.5V DQ55 VSS @ @
227 228 DDR_A_D51
1
1
DDR_A_D50 229 VSS DQ50 230
231 DQ51 VSS 232 DDR_A_D63
DDR_A_D58 233 VSS DQ60 234 DDR_A_SA1 DDR_A_SA0
235 DQ61 VSS 236 DDR_A_D62
DDR_A_D56 237 VSS DQ57 238
DQ56 VSS
1
239 240 DDR_A_DQS#7
VSS DQS7_C
1
+2.5V 241 242 DDR_A_DQS7 RD138
243 DM7*/DBI7* DQS7_T 244 RD139
+0.6VS 0_0402_5%
VSS VSS
10U_0603_6.3V6M
1 1 DDR_A_D57 245 246 DDR_A_D60 0_0402_5%

C2140 CD29 247 DQ62 DQ63 248
VSS VSS
2
DDR_A_D59 249 250 DDR_A_D61
DQ58 DQ59
2
1U_0402_6.3V6K
251 252
4 2 2 PCH_SMB_CLK 253 VSS VSS 254 PCH_SMB_DATA 4
+3VS_DIMM 255 SCL SDA 256 DDR_A_SA0

257 VDDSPD SA0 258
259 VPP1 VTT 260 DDR_A_SA1
VPP2 SA1
261
GND 262
GND
DEREN_40-42271-26001RHF
LTCX006KS00

ME@
Security Classification Compal Secret Data
DDR4_DIMM
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev

A B C D E
1 2 3 4 5
UV1A
AC Coupling Capacitor
PCIe Gen3: Recommended value is 220 nF
PCIe Gen1 and Gen2 only: Recommended value is 100 nF
DIS@
AF30 AH30 PCIE_PRX_C_DTX_P1 CV1 1 2 0.22U_0402_6.3V6K
<12> PCIE_PTX_C_DRX_P1 PCIE_RX0P PCIE_TX0P PCIE_PRX_DTX_P1 <12>
AE31 AG31 PCIE_PRX_C_DTX_N1 CV2 1 2 0.22U_0402_6.3V6K
<12> PCIE_PTX_C_DRX_N1 PCIE_RX0N PCIE_TX0N PCIE_PRX_DTX_N1 <12>
DIS@
DIS@
AE29 AG29 PCIE_PRX_C_DTX_P2 CV3 1 2 0.22U_0402_6.3V6K
A AD28 AF28 PCIE_PRX_C_DTX_N2 CV4 1 2 0.22U_0402_6.3V6K A
DIS@
DIS@
AD30 AF27 PCIE_PRX_C_DTX_P3 CV5 1 2 0.22U_0402_6.3V6K
AC31 AF26 PCIE_PRX_C_DTX_N3 CV6 1 2 0.22U_0402_6.3V6K
DIS@
DIS@
AC29 AD27 PCIE_PRX_C_DTX_P4 CV7 1 2 0.22U_0402_6.3V6K
AB28 AD26 PCIE_PRX_C_DTX_N4 CV8 1 2 0.22U_0402_6.3V6K
DIS@
AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N
AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N
Y30 AB27
W 31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N
W 29 Y27
V28 PCIE_RX7P PCIE_TX7P Y26
PCIE_RX7N PCIE_TX7N No Use GPU Display Port outpud
V30 W 24
U31 NC#V30 NC#W 24 W 23 UV1F @ +VGA_CORE
B NC#U31 NC#W 23 B
U29 V27
T28 NC#U29 NC#V27 U26 AB11 VARY_BL RV177 2 M2@ 1 0_0402_5%
NC#T28 NC#U26 VARY_BL AB12 DIGON RV176 2 M2@ 1 0_0402_5%
DIGON
PCI EXPRESS INTERFACE

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23
AL15
R29 T26 TXCAP_DPA3P AK14
P28 NC#R29 NC#T26 T27 TXCAM_DPA3N
NC#P28 NC#T27 AH16
TX0P_DPA2P AJ15
P30 T24 TX0M_DPA2N
N31 NC#P30 NC#T24 T23 AL17
NC#N31 NC#T23 TX1P_DPA1P AK16
TX1M_DPA1N
N29 P27 AH18
M28 NC#N29 NC#P27 P26 TX2P_DPA0P AJ17
NC#M28 NC#P26 TX2M_DPA0N
AL19
M30 P24 NC_TXOUT_L3P AK18
L31 NC#M30 NC#P24 P23 NC_TXOUT_L3N
NC#L31 NC#P23
TMDP
L29 M27
K30 NC#L29 NC#M27 N26 AH20
NC#K30 NC#N26 TXCBP_DPB3P AJ19
C C
TXCBM_DPB3N
AL21
TX3P_DPB2P AK20
CLOCK
CLK_PEG_VGA AK30 TX3M_DPB2N
<10> CLK_PEG_VGA PCIE_REFCLKP
CLK_PEG_VGA# AK32 AH22
<10> CLK_PEG_VGA# PCIE_REFCLKN +1.0VGS TX4P_DPB1P AJ21
+3VGS TX4M_DPB1N
CALIBRATION AL23
Y22 RV1 1 DIS@ 2 1.69K_0402_1% TX5P_DPB0P AK22
PCIE_CALR_TX TX5M_DPB0N
RV2 1 DIS@ 2 1K_0402_5% N10 AA22 RV3 1 DIS@ 2 1K_0402_1% AK24
TEST_PG PCIE_CALR_RX NC_TXOUT_U3P
5
UV2 DIS@ AJ23

DGPU_HOLD_RST# 1 NC_TXOUT_U3N
P
<11> DGPU_HOLD_RST# B 4 GPU_RST# AL27

PCI_RST# 2 Y PERSTB
<10,30,33,34,35> PCI_RST# A
G
TC7SH08FUF_SSOP5
3
SA007080100 RV4 @ ? PRO S3

216-0841018 A0 SUN
216-0841018 A0 SUN PRO S3
100K_0402_5%
DIS@
UV1
2
SA000087TA0
S IC 216-0867-071 A0 R16M-M1-30 C38!
M1@
UV1
SA00008B140
S IC 216-0864-018 A0 R16M-M2-50 C38!
D D
M2@

EXO/MESO(1/5)_PCIE/DP
Custom 1.0
1 2 3 4 5
1 2 3 4 5
+3VGS
+1.8VGS
PS_0[3:1]=001 Strap Name :
1
DIS@ DIS@ UV1B U?
2
RV157 RV158 PS_0[5:4]=11
1
47K_0402_5% 47K_0402_5% PS_0[1] ROM_CONFIG[0]
DIS@
AF2 RV12 PS_0[2] ROM_CONFIG[1]
2
6 1 VGA_SMB_DA2 NC#AF2 AF4 8.45K_0402_1%
S
<8,31,34> EC_SMB_DA2 NC#AF4
D
PS_0[3] ROM_CONFIG[2]
2
5
DIS@ QV9A N9 AG3 PS_0
G
2N7002KDW_SOT363-6 L9 DBG_DATA16 NC#AG3 AG5
DBG_DATA15 NC#AG5 Resistor Divider Lookup Lable PS_0[4] N/A
1
AE9 1
0.68U_0402_10V
DPA
Y11 DBG_DATA14 AH3 DIS@
3 4 VGA_SMB_CK2 AE8 DBG_DATA13 NC#AH3 AH1 CV30 RV7
PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
R_pu (ohm) R_pd (ohm) Bitd [3:1]
S
<8,31,34> EC_SMB_CK2 AD9 DBG_DATA12 NC#AH1 2K_0402_1%
D
A AC10 DBG_DATA11 AK3 @ 2 A
2
DIS@ QV9B AD7 DBG_DATA10 NC#AK3 AK1
2N7002KDW_SOT363-6 AC8 DBG_DATA9 NC#AK1 NC 4.75k 000
DVO
AC7 DBG_DATA8 AK5
AB9 DBG_DATA7 NC#AK5 AM3
8.45k 2k 001
AB8 DBG_DATA6 NC#AM3
AB7 DBG_DATA5 AK6
4.53k 2k 010
AB4 DBG_DATA4 NC#AK6 AM5
AB2 DBG_DATA3 NC#AM5 6.98k 4.99k 011 +1.8VGS
Y8 DBG_DATA2 DPB
AJ7
Y7 DBG_DATA1 NC#AJ7 AH6
4.53k 4.99k 100
DBG_DATA0 NC#AH6 PS_1[5:4]=11
1
AK8
3.24k 5.62k 101 DIS@
PS_1[1] STRAP_BIF_GEN3_EN_A
NC#AK8 AL7 RV9
FOR M2-50 only NC#AL7 3.4k 10k 110 8.45K_0402_1%
PS_1[2] TRAP_BIF_CLK_PM_EN
4.75k NC 111 PS_1[3] N/A
2
+1.8VGS W6 PS_1
V6 NC#W6
NC#V6 0402 1% resistors are equired PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING
1
V4 1
0.68U_0402_10V
AC6 NC#V4 U5 DIS@
AC5 NC#AC5 NC#U5 CV31 RV14
PS_1[5] STRAP_TX_DEEMPH_EN
NC#AC6 W3 2K_0402_1%
NC#W3
2
2
AA5 V2 @ 2
Capacitor Divider Lookup Lable
2
RV16 RV11 AA6 NC#AA5 NC#V2
DPC
4.7K_0402_5% 4.7K_0402_5% NC#AA6 Y4
M2@ M2@ NC#Y4 W5
NC#W5 Cap (nF) Bitd [5:4]
1
1
U1 AA3 PLL_ANALOG_OUT 1 DIS@ 2
1 FB_VDDCI W1 NC#U1 NC#AA3 Y2 RV17
TV23 U3 NC#W1 NC#Y2 16.2K_0402_1%
680nF 00
Y6 NC#U3 J8 +1.8VGS
1 PLL_ANALOG_IN AA1 NC#Y6 NC#J8 82nF 01 PS_2[3:1]=000 Strap Name :
TV18 NC#AA1
10nF 10 PS_2[5:4]=11
1
AMD recommend 09/25 @
PS_2[1] N/A
NC 11 RV57
8.45K_0402_1%
PS_2[2] N/A
I2C
PS_2[3] STRAP_BIOS_ROM_EN
2
B GPU_VID3 RV182 1 M1@ 2 0_0402_5% GPU_SVD R1 PS_2 B
GPU_VID1 RV183 1 M1@ 2 0_0402_5% GPU_SVC R3 SCL
SDA PS_2[4] STRAP_BIF_VGA_DIS
1
1
0.68U_0402_10V
+3VGS AM26 @ DIS@
REAK CURRENT CONTROL ( M2 only ) +VGA_CORE R AK26 CV32 RV19
PS_2[5] N/A
GENERAL PURPOSE I/O AVSSN#AK26
U6 +3VGS 4.75K_0402_1%
GPIO_0
2
RV170 1 M2@ 2 0_0402_5% GPU_GPIO1 U10 AL25 2
2
RV10 RV174 1 M2@ 2 0_0402_5% GPU_GPIO2 T10 GPIO_1 G AJ25
GPIO_2 AVSSN#AJ25
2
10K_0402_5% VGA_SMB_DA2 U8
VGA_SMB_CK2 U7 SMBDATA AH24 RV371
@ SMBCLK B
RV15 @ DV1 1 2 GPU_GPIO5 T9 AG25 4.7K_0402_5%
<10,34,39> VCIN1_AC_IN
1
1K_0402_5% GPU_GPIO6 T8 GPIO_5_AC_BATT AVSSN#AG25 @

GPU_GPIO6 1 2 GPU_PROCHOT# RB751V_SOD323 T7 GPIO_6 DAC1 AH26
GPU_PROCHOT# <48>
1
@ @ DV2 1 2 P10 GPIO_7_BLON HSYNC AJ27
1 <34> AC_BATT GPIO_8_ROMSO VSYNC
P4 +1.8VGS
2
CV17 RB751V_SOD323 P2 GPIO_9_ROMSI
+VGA_CORE RV374 1 2 0_0402_5% N6 GPIO_10_ROMSCK AD22 RV372
0.1U_0201_10V7K GPIO_11 RSET PS_3[5:4]=11
1
2 N5
@
N3 GPIO_12 AG24
4.7K_0402_5%
DIS@ X76@
PS_3[1] BOARD_CONFIG[0] (Memory ID)
RV172 1 M2@ 2 0_0402_5% GPU_GPIO14 Y9 GPIO_13 AVDD AE22 RV21 PS_3[2] BOARD_CONFIG[1] (Memory ID)
1
GPU_VID3 N1 GPIO_14_HPD2 AVSSQ 8.45K_0402_1%
M4 GPIO_15_PWRCNTL_0 AE23 Pull down for none OBFF design
PS_3[3] BOARD_CONFIG[2] (Memory ID)
2
FOR M2-50 VGA_CORE POWER USE THM_ALERT# RV194 1 2 0_0402_5% THM_ALERT#_R R6 GPIO_16 VDD1DI AD23 PS_3
<31> THM_ALERT# GPIO_17_THERMAL_INT VSS1DI
RV173 1 M2@ 2 0_0402_5% GPU_GPIO18 W10 PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
GPIO_18
1
GPIO19_CTF M2 1
0.68U_0402_10V
GPIO_19_CTF FutureASIC/SEYMOUR/PARK
GPU_VID1 P8 AM12
CV33
X76@ PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
+1.8VGS P7 GPIO_20_PWRCNTL_1 CEC_1 @ RV24
N8 GPIO_21 2K_0402_1%
1 RV13 2 GPIO19_CTF AK10 GPIO_22_ROMCSB AK12 SVI2_SVD RV166 1 M2@ 2 0_0402_5% GPU_SVD 2
GPU_SVD <48>
2
10K_0402_5% AM10 GPIO_29 RSVD#AK12 AL11 SVI2_SVT RV167 1 M2@ 2 0_0402_5% GPU_SVT
GPIO_30 RSVD#AL11 GPU_SVT <48>
@ N7 AJ11 SVI2_SVC RV168 1 M2@ 2 0_0402_5% GPU_SVC GPU_SVC <48>
<10> VGA_CLKREQ# CLKREQB RSVD#AJ11
2
RV22 JTAG_TRSTB L6 FOR M2

JTAG_TDI L5 JTAG_TRSTB M1 doesn't have native SVI2
10K_0402_5%
DIS@ JTAG_TCK L3 JTAG_TDI
1 @ 2 JTAG_TMS L1 JTAG_TCK AL13
+3VGS
1
RV26 5.11K_0402_5% 1 JTAG_TDO K4 JTAG_TMS GENLK_CLK AJ13

TV24 JTAG_TDO GENLK_VSYNC
+3VGS 1 DIS@ 2 TESTEN K7
C RV27 1K_0402_5% AF24 TESTEN C
RV18 2 @ 1 4.7K_0402_5% THM_ALERT# +VGA_CORE NC#AF24 AG13
SWAPLOCKA AH12
RV169 1 M2@ 2 0_0402_5% GENERICA AB13 SWAPLOCKB
W8 GENERICA
RV171 1 M2@ 2 0_0402_5% GENERICC W9 GENERICB
W7 GENERICC AC19 PS_0
AD10 GENERICD PS_0
AJ9 GENERICE AD19 PS_1
+3VGS 1 AL9 NC#AJ9 PS_1
TV22 NC#AL9 AE17 PS_2
RV175 1 M2@ 2 0_0402_5% GPU_HPD1 AC14 PS_2
DIS@ 1 PX_EN AB16 HPD1 AE20 PS_3
TV25 PX_EN PS_3
RV58 2 1 4.7K_0402_5% GPU_GPIO5 RV373 2 @ 1 4.7K_0402_5%
RV20 1 2 JTAG_TDO AE19

S5 S4
@ 10K_0402_5% AC16 TS_A ZZZ
DBG_VREFG
VGA_AC_BATT X7666738L51
pull up DDC/AUX Samsung 2G X7666738L52
+3VGS AE6
PLL/CLOCK DDC1CLK AE5 X7666738L53
DDC1DATA S2G@
RPV1 @ AD2 OPTIAN FOR 3.3V tolerance VR, Part Number = X7669538L01
1 8 JTAG_TRSTB AUX1P AD4 +VGA_CORE Check with VR vendor
2 7 JTAG_TDI AUX1N +1.8VGS +3VGS ZZZ
3 6 JTAG_TMS AC11 GPU_DDC2_CLK RV178 1 M2@ 2 0_0402_5% RV185 RV186
4 5 JTAG_TCK DDC2CLK AC13 GPU_DDC2_DAT RV179 1 M2@ 2 0_0402_5% 1 M2@ 2 1 M1@ 2
DDC2DATA 0_0402_5% 0_0402_5%
2
10K_8P4R_5% XTALIN AM28 AD13 Micron 2G
XTALOUT AK28 XTALIN AUX2P AD11 RV164 RV163
XTALOUT AUX2N 10K_0402_5% 10K_0402_5%
RV28 RV29 1 DIS@ 2 10K_0402_5% AC22 AD20 FB_GND RV37 1 M2@ 2 0_0402_5% DIS@ @ M2G@
XTALIN 1M_0402_5% XTALOUT RV31 1 DIS@ 2 10K_0402_5% AB22 XO_IN NC#AD20 AC20 FB_VDDC RV51 1 M2@ 2 0_0402_5% GPU_VDD_RUN_FB_L <48> Part Number = X7669538L02
1
DIS@ XO_IN2 NC#AC20 ONLY AVAILABLE ON M2-50, NC BALLS ON M1-30 GPU_VDD_SEN <48> GPU_SVD
AE16 GPU_SVC ZZZ
NC#AE16 AD16
NC#AD16
2
D YV1 DIS@ D
4 3 SEYMOUR/FutureASIC AC1
NC OSC REMOTE1+ T4 DDCVGACLK AC3 @ DIS@ Hynix 2G
<31> REMOTE1+ DPLUS THERMAL DDCVGADATA
1 2 TO EXTERNAL THERMAL SENSOR REMOTE1- T2 RV165 RV184
OSC NC <31> REMOTE1- DMINUS 10K_0402_5% 10K_0402_5%
1
27MHZ 10PF +-10PPM 7V27000050 +1.8VGS H2G@
2 2
SJ10000FH00 Enable MLPS RV33 1 M1@ 2 10K_0402_5% GPIO28 R5 Part Number = X7669538L03
DIS@ CV19 DIS@ CV20 AD17 GPIO28_FDO
8.2P_0402_50V_NPO 8.2P_0402_50V_NPO LV4 1 2 0_0402_5% +TSVDD AC17 TSVDD
1 1 TSVSS
1
CV21
1U_0402_6.3V6K Security Classification Compal Secret Data Compal Electronics, Inc.
DIS@ 2016/04/07 2017/02/16 Title
2 216-0841018 A0 SUN PRO ?S3 @
EXO/MESO(2/5)_MSIC
Custom 1.0
1 2 3 4 5
1 2 3 4 5
+1.8VALW TO +1.8VGS
+1.0VALW TO +1.0VGS UV1E @ U?
Load switch
+1.8VGS
No Use GPU Display Port outpud AA27
AB24
AB32
GND
GND
GND
GND
A3
A30
AA13
AC24 GND GND AA16
UV1G @ AC26 GND GND AB10
U?
AC27 GND GND AB15
AD25 GND GND AB6
CV23
CV24
DP POWER NC/DP POWER
A
AD32 GND GND AC9 A
1 1 GND GND
AG15 AE11 AE27 AD6
AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
+1.0VALW AF16 DP_VDDR#AG16 NC#AF11 AE13 AG27 GND GND AE7
1U_0402_6.3V6K
10U_0603_6.3V6M
2 2 AG17 DP_VDDR#AF16 NC#AE13 AF13 AH32 GND GND AG12
AG18 DP_VDDR#AG17 NC#AF13 AG8 K28 GND GND AH10
DIS@
DIS@
C29 AG19 DP_VDDR#AG18 NC#AG8 AG10 K32 GND GND AH28
AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
DP_VDDR#AF14 GND GND
1U_0402_6.3V6K
1 M32 B12
@ N25 GND GND B14
N27 GND GND B16
+1.0VGS P25 GND GND B18
2 U1895V AG20 AF6 P32 GND GND B20
1 14 +1.0VGS_LS RV5 1 2 0_0603_5% AG21 DP_VDDC#AG20 NC#AF6 AF7 R27 GND GND B22
DIS@ 2 VIN1 VOUT1 13 +1.0VGS AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
R1642 VIN1 VOUT1 AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
DP_VDDC#AG22 NC#AF9 GND GND
2
DGPU_PWR_EN 2 1 DGPU_PWR_EN_R 3 12 @ 1 2 DIS@ AD14 U25 B6
150K_0402_5% ON1 CT1 2200P_0402_50V7K C28 C32 DP_VDDC#AD14 U27 GND GND B8
4 11 V32 GND GND C1
CV28
CV29
+VL 0.1U_0201_10V7K
1
VBIAS GND W25 GND GND C32
1 1 GND GND
0.1U_0402_16V7K
DIS@
5 10 @ 1 2 AG14 AE1 W26 E28

ON2 CT2 DP_VSSR NC#AE1 GND GND
1
2200P_0402_50V7K C27 +1.8VGS AH14 AE3 W27 F10

+1.8VALW 6 9 AM14 DP_VSSR NC#AE3 AG1 Y25 GND GND F12
1U_0402_6.3V6K
0.1U_0201_10V7K
7 VIN2 VOUT2 8 +1.8VGS_LS RV6 1 2 0_0603_5% 2 2 AM16 DP_VSSR NC#AG1 AG6 Y32 GND GND F14
2
VIN2 VOUT2 DP_VSSR NC#AG6 GND GND

C1380
AM18 AH5 F16
DIS@
DIS@
15 AF23 DP_VSSR NC#AH5 AF10 GND F18
GPAD DP_VSSR NC#AF10 GND
2
DIS@ AG23 AG9 F2
APE8990GN3B DFN 14P C31 AM20 DP_VSSR NC#AG9 AH8 GND F20
DIS@ AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
0.1U_0201_10V7K
1
SA00007PM00 AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
1 DP_VSSR NC#AM8 GND GND
@ C30 AF19 AG7 N16 F26
AF20 DP_VSSR NC#AG7 AG11 N18 GND GND F6
B B
DP_VSSR NC#AG11 GND GND
1U_0402_6.3V6K
AE14 N21 GND F8

2 DP_VSSR P6 GND GND G10
P9 GND GND G27
R12 GND GND G31
AF17 AE10 R15 GND GND G8
DPAB_CALR NC#AE10 R17 GND GND H14
R20 GND GND H17
T13 GND GND H2
T16 GND GND H20
216-0841018 A0 SUN PRO? S3 T18 GND GND H6
T21 GND GND J27
T6 GND GND J31
U15 GND GND K11
U17 GND GND K2
U20 GND GND K22
U9 GND GND K6
V13 GND GND
V16 GND
V18 GND
Y10 GND
Y15 GND
Y17 GND
Y20 GND
R11 GND A32
GND VSS_MECH TP@T186
T11 AM1
GND VSS_MECH TP@T187
AA11 AM32
+3VS to +3VGS M12
N11
GND
GND
GND
VSS_MECH TP@T188
V11
GND
C C
?
216-0841018 A0 SUN PRO S3
+3VGS
+3VALW
3
S
1 4.7U_0603_6.3V6K
1
1U_0402_6.3V6K
1 1 @
DIS@ QV16 CV36 RV40
G
2
CV37
ME2301DC-G_SOT23-3 680_0603_5%
SB000013I00 DIS@ @ +1.0VGS
3VGS_EN#
2 2 +VGA_CORE +1.8VGS
1 2
+5VALW
2
2
2
D RV56
2 RV39 RV53 470_0603_5%
DIS@ G 470_0603_5% 470_0603_5% @
RV42 DIS@ DGPU_PWR_EN# 1 2 S @ DIS@ @
1
RV43 10K_0402_5% 2N7002K_SOT23-3
3
6 1
1 1
20K_0402_5% QV17
1
3
D D
D 1 D 2 DGPU_PWR_EN# 5 DGPU_PWR_EN#
DIS@
R1640 2 1 0_0402_5% DGPU_PWR_EN_3VGS 2 DGPU_PWR_EN# DGPU_PWR_EN# 2 G G
<11,34,48> DGPU_PWR_EN CV38
G G
0.1U_0201_10V7K
1
DIS@ QV18 S DIS@ QV11 S S QV21A @ S QV21B @
4
RV41 2N7002K_SOT23-3 2 2N7002K_SOT23-3 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
3
3
@
D 100K_0402_5% D
2

EXO/MESO(3/5)_PWR/GND
Custom 1.0
1 2 3 4 5
1 2 3 4 5
+1.5VGS
UV1D @ +1.8VGS
U?
AM30
PCIE_PVDD
PCIE
MEM I/O
CV47
CV48
H13 AB23 1 1
H16 VDDR1 NC#AB23 AC23
VDDR1 NC#AC23
CV75
CV88
CV74
CV80
CV83
CV87
CV76
CV77
CV78
CV79
CV81
CV82
CV89
CV86
CV85
CV84
H19 AD24
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
220U_B2_2.5VM_R35
1 VDDR1 NC#AD24
J10 AE24
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDDR1 NC#AE24 2 2
A + J23 AE25 A
J24 VDDR1 NC#AE25 AE26
DIS@
DIS@
@
J9 VDDR1 NC#AE26 AF25
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VDDR1 NC#AF25
@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
K10 AG26
K23 VDDR1 NC#AG26
K24 VDDR1
K9 VDDR1 L23
L11 VDDR1 PCIE_VDDC L24
L20 VDDR1 PCIE_VDDC M22 +1.0VGS
L21 VDDR1 PCIE_VDDC N22
L22 VDDR1 PCIE_VDDC N23
VDDR1 PCIE_VDDC N24
PCIE_VDDC R22
PCIE_VDDC
CV49
CV50
CV51
CV52
CV53
CV54
T22
+1.8VGS LEVEL PCIE_VDDC U22
PCIE_VDDC 1 1 1 1 1 1
TRANSLATION V22
AA20 PCIE_VDDC
AA21 VDD_CT
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDD_CT 2 2 2 2 2 2
CV55
AB20 AA15
VDD_CT CORE VDDC
@
AB21 N15
DIS@
DIS@
DIS@
DIS@
DIS@
1 VDD_CT VDDC N17
+3VGS VDDC R13
I/O VDDC R16
1U_0402_6.3V6K
2 AA17 VDDC R18
B AA18 VDDR3 VDDC Y21 B
DIS@
VDDR3 VDDC
CV56
AB17 T12
AB18 VDDR3 VDDC T15 +VGA_CORE
1 VDDR3 VDDC T17
V12 VDDC T20
Y12 VDDR4 VDDC U13
1U_0402_6.3V6K
2 U12 VDDR4 VDDC U16
VDDR4 VDDC
DIS@
U18
VDDC V21 VGA_CORE Caps in power side sheet
VDDC V15
VDDC V17
VDDC V20
VDDC
POWER
Y13
VDDC Y16
VDDC Y18
VDDC AA12
VDDC M11
VDDC N12
VDDC U11
VDDC
+1.8VGS
PLL
LV1 1 2 0_0603_5% +MPLL_PVDD
+1.0VGS
CV39
CV40
CV41
10U_0603_6.3V6M
10U_0603_6.3V6M
R21
1U_0402_6.3V6K
C BIF_VDDC U21 C
1 1 1 BIF_VDDC
L8
+1.8VGS MPLL_PVDD
2 2 2 +VGA_CORE
CV62
DIS@
DIS@
DIS@
ISOLATED
LV2 1 2 0_0402_5% +SPLL_PVDD CORE I/O 1
M13
VDDCI
CV42
CV43
10U_0603_6.3V6M
H7 M15
1U_0402_6.3V6K
SPLL_PVDD VDDCI M16
1U_0402_6.3V6K
1 1 VDDCI 2
M17
+1.0VGS VDDCI
@
M18
VDDCI M20
2 2 1 2 0_0402_5% H8 VDDCI M21
DIS@
DIS@
LV3 +SPLL_VDDC
SPLL_VDDC VDDCI N20
J7 VDDCI
SPLL_PVSS
CV46
CV90
1U_0402_6.3V6K
0.1U_0201_10V7K
1 1
VGA_CORE Caps in power side sheet
216-0841018 A0 SUN PRO S3

?
2 2
DIS@
DIS@
D D

EXO/MESO(4/5)_PWR
Custom 1.0
1 2 3 4 5
1 2 3 4 5
@
M_DA[63..0] UV1C U?
<24,25> M_DA[63..0]
M_MA[15..0] GDDR5/DDR3 GDDR5/DDR3
<24,25> M_MA[15..0]
M_DA0 K27 K17 M_MA0
M_DQM[7..0] M_DA1 J29 DQA0_0 MAA0_0/MAA_0 J20 M_MA1
<24,25> M_DQM[7..0] DQA0_1 MAA0_1/MAA_1
M_DA2 H30 H23 M_MA2
M_DQS[7..0] M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M_MA3
<24,25> M_DQS[7..0] DQA0_3 MAA0_3/MAA_3
M_DA4 G29 G24 M_MA4
M_DQS#[7..0] M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M_MA5
A <24,25> M_DQS#[7..0] DQA0_5 MAA0_5/MAA_5 A
M_DA6 F32 J19 M_MA6
M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M_MA13
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17 M_MA15
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
M_DA11 C28 DQA0_10 J14 M_MA8
M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M_MA9
M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M_MA10
M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M_MA11
M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M_MA12
M_DA16 A25 DQA0_15 MAA1_4/MAA_12 G11 M_BA2
DQA0_16 MAA1_5/MAA_BA2 M_BA2 <24,25>
M_DA17 C25 J16 M_BA0
DQA0_17 MAA1_6/MAA_BA0 M_BA0 <24,25>
M_DA18 E25 L15 M_BA1
DQA0_18 MAA1_7/MAA_BA1 M_BA1 <24,25>
M_DA19 D24 G14 M_MA14
M_DA20 E23 DQA0_19 MAA1_8/MAA_14 L16
MEMORY INTERFACE
M_DA21 F23 DQA0_20 MAA1_9/RSVD
M_DA22 D22 DQA0_21 E32 M_DQM0
+1.5VGS M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_DQM1
M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_DQM2
M_DA25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 M_DQM3
M_DA26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 M_DQM4
1 M_DA27 A19 DQA0_26 WCKA1_0/DQMA1_0 D12 M_DQM5
DIS@ M_DA28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 M_DQM6
RV44 M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_DQM7
40.2_0402_1% M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3
M_DA31 C17 DQA0_30 H28 M_DQS0
2
B M_DA32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 M_DQS1 B

M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_DQS2
M_DA34 F15 DQA1_1 EDCA0_2/QSA0_2 E19 M_DQS3
M_DA35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 M_DQS4
DQA1_3 EDCA1_0/QSA1_0
1
1 M_DA36 D14 D10 M_DQS5

DIS@ DIS@ M_DA37 F13 DQA1_4 EDCA1_1/QSA1_1 D6 M_DQS6
RV46 CV65 M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_DQS7
100_0402_1% 1U_0402_6.3V6K M_DA39 C13 DQA1_6 EDCA1_3/QSA1_3
2 M_DA40 E11 DQA1_7 H27 M_DQS#0
2
M_DA41 A11 DQA1_8 DDBIA0_0/QSA0_0B A27 M_DQS#1

M_DA42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 M_DQS#2
M_DA43 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 M_DQS#3
M_DA44 A9 DQA1_11 DDBIA0_3/QSA0_3B C15 M_DQS#4
M_DA45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 M_DQS#5
M_DA46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 M_DQS#6
M_DA47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 M_DQS#7
+1.5VGS M_DA48 E7 DQA1_15 DDBIA1_3/QSA1_3B
M_DA49 A7 DQA1_16 L18 VRAM_ODT0
DQA1_17 ADBIA0/ODTA0 VRAM_ODT0 <24>
M_DA50 C7 K16 VRAM_ODT1
DQA1_18 ADBIA1/ODTA1 VRAM_ODT1 <25>
M_DA51 F7
DQA1_19
1
M_DA52 A5 H26 M_CLK0

DQA1_20 CLKA0 M_CLK0 <24>
DIS@ M_DA53 E5 H25 M_CLK#0
DQA1_21 CLKA0B M_CLK#0 <24>
RV45 M_DA54 C3
40.2_0402_1% M_DA55 E1 DQA1_22 G9 M_CLK1
DQA1_23 CLKA1 M_CLK1 <25>
M_DA56 G7 H9 M_CLK#1
M_CLK#1 <25>
2
M_DA57 G6 DQA1_24 CLKA1B

C M_DA58 G1 DQA1_25 G22 M_RAS#0 C
DQA1_26 RASA0B M_RAS#0 <24>
M_DA59 G3 G17 M_RAS#1
DQA1_27 RASA1B M_RAS#1 <25>
M_DA60 J6
DQA1_28
1
1 M_DA61 J1 G19 M_CAS#0

DQA1_29 CASA0B M_CAS#0 <24>
DIS@ DIS@ M_DA62 J3 G16 M_CAS#1
DQA1_30 CASA1B M_CAS#1 <25>
RV47 CV66 M_DA63 J5
100_0402_1% 1U_0402_6.3V6K DQA1_31 H22 M_CS0B#0
2 CSA0B_0 M_CS0B#0 <24>
+MVREFDA K26 J22
2
+MVREFSA J26 MVREFDA CSA0B_1

MVREFSA G13 M_CS1B#0
CSA1B_0 M_CS1B#0 <25>
J25 K13
RV52 1 DIS@ 2 120_0402_1% K25 NC#J25 CSA1B_1
MEM_CALRP0 K20 M_CKE0
CKEA0 M_CKE0 <24>
DIS@ DIS@ J17 M_CKE1
CKEA1 M_CKE1 <25>
RV48 RV49
49.9_0402_1% 10_0402_1% G25 M_WE#0
WEA0B M_WE#0 <24>
1 2 2 1 DRST L10 H10 M_WE#1
<24,25> DRAM_RST DRAM_RST WEA1B M_WE#1 <25>
1 RV54 @ 1 2 51.1_0402_1% CV69 @1 2 0.1U_0201_10V7K K8
CLKTESTA
1
1 @ RV55 @ 1 2 51.1_0402_1% CV70 @1 2 L7

DIS@ DIS@ CV67 0.1U_0201_10V7K CLKTESTB
CV68 RV50 68P_0402_50V8J
120P_0402_50V8J 5.1K_0402_1% 2 Route 50ohms single-ended/100ohm diff and keep short
2 debug only, for clock observation,if not need, DNI. 216-0841018 A0 SUN PRO S3
?
2
D D
Place close to GPU (within 25mm)

and place componment close to each other Issued Date 2016/04/07 Deciphered Date 2017/02/16 Title
EXO/MESO(5/5)_MEM
Custom 1.0
1 2 3 4 5
1 2 3 4 5
DDR3 Memory Channel Rank 0:A0

M_DA[63..0]
<23,25> M_DA[63..0]
M_MA[15..0]
<23,25> M_MA[15..0]
M_DQM[7..0] +1.5VGS +1.5VGS
<23,25> M_DQM[7..0]
M_DQS[7..0]
<23,25> M_DQS[7..0]
1
M_DQS#[7..0] DIS@ DIS@
A <23,25> M_DQS#[7..0] A
RV63 RV62
4.99K_0402_1% UV5 4.99K_0402_1% UV6
2
+FBA_VREF0 M8 E3 M_DA8 +FBA_VREF1 M8 E3 M_DA19
H1 VREFCA DQL0 F7 M_DA14 H1 VREFCA DQL0 F7 M_DA21
VREFDQ DQL1 F2 M_DA11 VREFDQ DQL1 F2 M_DA22
DQL2 DQL2
1
1 M_MA0 N3 F8 M_DA13 1 M_MA0 N3 F8 M_DA16
DIS@ DIS@ M_MA1 P7 A0 DQL3 H3 M_DA10 DIS@ DIS@ M_MA1 P7 A0 DQL3 H3 M_DA23
RV75 CV72 M_MA2 P3 A1 DQL4 H8 M_DA12 RV66 CV71 M_MA2 P3 A1 DQL4 H8 M_DA18
4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA9 4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA20
2 M_MA4 P8 A3 DQL6 H7 M_DA15 2 M_MA4 P8 A3 DQL6 H7 M_DA17
2
M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7
M_MA6 R8 A5 M_MA6 R8 A5
M_MA7 R2 A6 D7 M_DA6 M_MA7 R2 A6 D7 M_DA25
M_MA8 T8 A7 DQU0 C3 M_DA2 M_MA8 T8 A7 DQU0 C3 M_DA29
M_MA9 R3 A8 DQU1 C8 M_DA5 M_MA9 R3 A8 DQU1 C8 M_DA26
M_MA10 L7 A9 DQU2 C2 M_DA0 M_MA10 L7 A9 DQU2 C2 M_DA28
M_MA11 R7 A10/AP DQU3 A7 M_DA4 M_MA11 R7 A10/AP DQU3 A7 M_DA27
M_MA12 N7 A11 DQU4 A2 M_DA1 M_MA12 N7 A11 DQU4 A2 M_DA30
M_MA13 T3 A12 DQU5 B8 M_DA7 M_MA13 T3 A12 DQU5 B8 M_DA24
M_MA14 T7 A13 DQU6 A3 M_DA3 M_MA14 T7 A13 DQU6 A3 M_DA31
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS
M_BA0 M2 B2 M_BA0 M2 B2
<23,25> M_BA0 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9
<23,25> M_BA1 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7
<23,25> M_BA2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8
VDD N1 VDD N1
M_CLK0 M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9
M_CLK#0 <23> M_CLK0 M_CLK#0 K7 CK VDD R1 M_CLK#0 K7 CK VDD R1
B <23> M_CLK#0 M_CKE0 K9 CK VDD R9 M_CKE0 K9 CK VDD R9 B
<23> M_CKE0 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
1
DIS@ DIS@
RV102 RV103 VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1
<23> VRAM_ODT0 M_CS0B#0 L2 ODT/ODT0 VDDQ A8 M_CS0B#0 L2 ODT/ODT0 VDDQ A8
40.2_0402_1% 40.2_0402_1%
<23> M_CS0B#0 M_RAS#0 J3 CS/CS0 VDDQ C1 M_RAS#0 J3 CS/CS0 VDDQ C1
<23> M_RAS#0 M_CAS#0 K3 RAS VDDQ C9 M_CAS#0 K3 RAS VDDQ C9
2
<23> M_CAS#0 M_WE#0 L3 CAS VDDQ D2 M_WE#0 L3 CAS VDDQ D2

<23> M_WE#0 WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1
M_DQS1 F3 VDDQ H2 M_DQS2 F3 VDDQ H2
1 DQSL VDDQ DQSL VDDQ
DIS@ M_DQS0 C7 H9 M_DQS3 C7 H9
CV73 DQSU VDDQ DQSU VDDQ
0.01U_0402_16V7K
2 M_DQM1 E7 A9 M_DQM2 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM3 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
M_DQS#1 G3 VSS J2 M_DQS#2 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#3 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9
<23,25> DRAM_RST RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1
DIS@ L1 NC/ODT1 VSSQ B9 DIS@ L1 NC/ODT1 VSSQ B9
RV111 J9 NC/CS1 VSSQ D1 RV110 J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
C NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 C
SINGLE RANK:RV102,RV103 install 40.2 ohms
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
X76@ X76@
+1.5VGS +1.5VGS +1.5VGS
CV194_RF@
only for DIS
1U_0402_6.3V6K
CV106
1U_0402_6.3V6K
CV107
1U_0402_6.3V6K
CV108
1U_0402_6.3V6K
CV109
0.1U_0201_10V7K
CV125
10U_0603_6.3V6M
CV115
10U_0603_6.3V6M
CV116
1U_0402_6.3V6K
CV112
1U_0402_6.3V6K
CV117
1U_0402_6.3V6K
CV120
1U_0402_6.3V6K
CV121
1U_0402_6.3V6K
CV126
10U_0603_6.3V6M
CV105
1U_0402_6.3V6K
CV113
1U_0402_6.3V6K
CV123
1U_0402_6.3V6K
CV122
1U_0402_6.3V6K
CV124
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
RF_DIS@
CV194
D D
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
@
22P_0402_50V8J

EXO/MESO_DDR3L_A1 Rank 0
Custom 1.0
1 2 3 4 5
1 2 3 4 5
DDR3 Memory Channel Rank 0:A1

+1.5VGS
+1.5VGS
1
1
DIS@
DIS@ RV119
RV118 4.99K_0402_1% UV4
4.99K_0402_1% UV3
2
M_DA[63..0] +FBA_VREF3 M8 E3 M_DA35
<23,24> M_DA[63..0]
2
+FBA_VREF2 M8 E3 M_DA58 H1 VREFCA DQL0 F7 M_DA37
M_MA[15..0] H1 VREFCA DQL0 F7 M_DA61 VREFDQ DQL1 F2 M_DA34
<23,24> M_MA[15..0] VREFDQ DQL1 DQL2
1
A F2 M_DA57 M_MA0 N3 F8 M_DA36 A
DQL2 1 A0 DQL3
1
M_DQM[7..0] 1 M_MA0 N3 F8 M_DA62 DIS@ DIS@ M_MA1 P7 H3 M_DA32
<23,24> M_DQM[7..0] M_MA1 P7 A0 DQL3 H3 M_DA59 M_MA2 P3 A1 DQL4 H8 M_DA38
DIS@ DIS@ RV127 CV118
M_DQS[7..0] RV126 CV119 M_MA2 P3 A1 DQL4 H8 M_DA63 4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA33
<23,24> M_DQS[7..0] M_MA3 N2 A2 DQL5 G2 M_DA56 2 M_MA4 P8 A3 DQL6 H7 M_DA39
4.99K_0402_1% 0.1U_0201_10V7K
2
M_DQS#[7..0] 2 M_MA4 P8 A3 DQL6 H7 M_DA60 M_MA5 P2 A4 DQL7
<23,24> M_DQS#[7..0]
2
M_MA5 P2 A4 DQL7 M_MA6 R8 A5
M_MA6 R8 A5 M_MA7 R2 A6 D7 M_DA47
M_MA7 R2 A6 D7 M_DA52 M_MA8 T8 A7 DQU0 C3 M_DA43
M_MA8 T8 A7 DQU0 C3 M_DA50 M_MA9 R3 A8 DQU1 C8 M_DA46
M_MA9 R3 A8 DQU1 C8 M_DA55 M_MA10 L7 A9 DQU2 C2 M_DA42
M_MA10 L7 A9 DQU2 C2 M_DA49 M_MA11 R7 A10/AP DQU3 A7 M_DA44
M_MA11 R7 A10/AP DQU3 A7 M_DA54 M_MA12 N7 A11 DQU4 A2 M_DA41
M_MA12 N7 A11 DQU4 A2 M_DA51 M_MA13 T3 A12 DQU5 B8 M_DA45
M_MA13 T3 A12 DQU5 B8 M_DA53 M_MA14 T7 A13 DQU6 A3 M_DA40
M_MA14 T7 A13 DQU6 A3 M_DA48 M_MA15 M7 A14 DQU7
M_MA15 M7 A14 DQU7 A15/BA3 +1.5VGS
A15/BA3 +1.5VGS
M_BA0 M2 B2
M_BA0 M2 B2 M_BA1 N8 BA0 VDD D9
<23,24> M_BA0 M_BA1 N8 BA0 VDD D9 M_BA2 M3 BA1 VDD G7
<23,24> M_BA1 M_BA2 M3 BA1 VDD G7 BA2 VDD K2
M_CLK1 <23,24> M_BA2 BA2 VDD K2 VDD K8
M_CLK#1 VDD K8 VDD N1
VDD N1 M_CLK1 J7 VDD N9
M_CLK1 J7 VDD N9 M_CLK#1 K7 CK VDD R1
<23> M_CLK1 CK VDD CK VDD
1
DIS@ DIS@ M_CLK#1 K7 R1 M_CKE1 K9 R9

<23> M_CLK#1 M_CKE1 K9 CK VDD R9 CKE/CKE0 VDD +1.5VGS
RV139 RV140
<23> M_CKE1 CKE/CKE0 VDD +1.5VGS
40.2_0402_1% 40.2_0402_1%
VRAM_ODT1 K1 A1
VRAM_ODT1 K1 A1 M_CS1B#0 L2 ODT/ODT0 VDDQ A8
<23> VRAM_ODT1
2
M_CS1B#0 L2 ODT/ODT0 VDDQ A8 M_RAS#1 J3 CS/CS0 VDDQ C1

B <23> M_CS1B#0 M_RAS#1 J3 CS/CS0 VDDQ C1 M_CAS#1 K3 RAS VDDQ C9 B
<23> M_RAS#1 M_CAS#1 K3 RAS VDDQ C9 M_WE#1 L3 CAS VDDQ D2
<23> M_CAS#1 M_WE#1 L3 CAS VDDQ D2 WE VDDQ E9
1 <23> M_WE#1 WE VDDQ VDDQ
DIS@ E9 F1
CV154 VDDQ F1 M_DQS4 F3 VDDQ H2
0.01U_0402_16V7K M_DQS7 F3 VDDQ H2 M_DQS5 C7 DQSL VDDQ H9
2 M_DQS6 C7 DQSL VDDQ H9 DQSU VDDQ
DQSU VDDQ
M_DQM4 E7 A9
M_DQM7 E7 A9 M_DQM5 D3 DML VSS B3
M_DQM6 D3 DML VSS B3 DMU VSS E1
DMU VSS E1 VSS G8
VSS G8 M_DQS#4 G3 VSS J2
M_DQS#7 G3 VSS J2 M_DQS#5 B7 DQSL VSS J8
M_DQS#6 B7 DQSL VSS J8 DQSU VSS M1
DQSU VSS M1 VSS M9
VSS M9 VSS P1
VSS P1 DRAM_RST T2 VSS P9
DRAM_RST T2 VSS P9 RESET VSS T1
<23,24> DRAM_RST RESET VSS T1 L8 VSS T9
L8 VSS T9 ZQ/ZQ0 VSS
ZQ/ZQ0 VSS
1
J1 B1
NC/ODT1 VSSQ
1
J1 B1 DIS@ L1 B9
DIS@ L1 NC/ODT1 VSSQ B9 RV138 J9 NC/CS1 VSSQ D1
RV137 J9 NC/CS1 VSSQ D1 243_0402_1% L9 NC/CE1 VSSQ D8
243_0402_1% L9 NC/CE1 VSSQ D8 NCZQ1 VSSQ E2
2
NCZQ1 VSSQ E2 VSSQ E8
SINGLE RANK:RV139,RV140 install 40.2 ohms
2
VSSQ E8 VSSQ F9
VSSQ F9 VSSQ G1
VSSQ G1 VSSQ G9
VSSQ G9 VSSQ
C VSSQ 96-BALL C
96-BALL SDRAM DDR3
SDRAM DDR3 H5TC2G63FFR-11C_FBGA96
H5TC2G63FFR-11C_FBGA96 X76@
X76@
+1.5VGS +1.5VGS +1.5VGS

10U_0603_6.3V6M
CV128
1U_0402_6.3V6K
CV152
1U_0402_6.3V6K
CV158
1U_0402_6.3V6K
CV132
1U_0402_6.3V6K
CV164
0.1U_0201_10V7K
CV134
1U_0402_6.3V6K
CV136
10U_0603_6.3V6M
CV138
10U_0603_6.3V6M
CV139
1U_0402_6.3V6K
CV141
1U_0402_6.3V6K
CV144
1U_0402_6.3V6K
CV146
0.1U_0201_10V7K
CV147
1U_0402_6.3V6K
CV193
1U_0402_6.3V6K
CV148
1U_0402_6.3V6K
CV135
1U_0402_6.3V6K
CV145
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
D D

EXO/MESO_DDR3L_A2 Rank 0
Custom 1.0
1 2 3 4 5
5 4 3 2 1
W=60mils
+3VS
LCD Power Circuit +LCDVDD_CONN
+3VS Camera +3VS_CMOS
W=60mils U5
5 1 +LCDVDD R311 1 2 0_0805_5%
4.7U_0603_6.3V6K
IN OUT
C128
2
GND 1 W=20mils R318 1 @ 2 0_0603_5%
W=20mils
1
C1220 4 3 1 1
1U_0402_6.3V6K EN OC
EM5203AJ-20 SOT23 5P 2 Q4 C129 C130
2 SA00008R900 ME2301DC-G_SOT23-3 0.1U_0201_10V K X5R 10U_0603_6.3V6M
2 2
D <6> PCH_ENVDD D
D
3 1
G
2
R120
100K_0402_5% R119
150K_0402_5%
2
CMOS_ON#_R
<34> CMOS_ON#
1
C132
0.1U_0201_10V K X5R
2
+3VS
5
U15
2
From PCH
P
<6,34> ENBKL B 4 DISPOFF#
1 Y
From EC <34> BKOFF# A
eDP CONN.
2
+LEDVDD
3
2 R124 W=100mils B+
R211 TC7SH08FUF_SSOP5 100K_0402_5%
100K_0402_5% R121 2 1 0_0805_5%
1
1
C C
1
C133
R123 1 2 0_0402_5% 4.7U_0805_25V6-K
2
JEDP1
1
2 1
3 2
4 3
5 4
<6> INVPWM 5
<6> EDP_HPD R126 1 2 0_0402_5% EDP_HPD_R DISPOFF# 6
EDP_HPD_R 7 6
W=60mils 7
1
+LCDVDD_CONN 8
9 8
R128 C134 1 2 0.1U_0201_10V K X5R EDP_AUXN_C 10 9
100K_0402_5%
eDP <6> EDP_AUXN
C135 1 2 0.1U_0201_10V K X5R EDP_AUXP_C 11 10
<6> EDP_AUXP 11
12
2
C136 1 2 0.1U_0201_10V K X5R EDP_TXP0_C 13 12

<6> EDP_TXP0 13
C137 1 2 0.1U_0201_10V K X5R EDP_TXN0_C 14
<6> EDP_TXN0 14
15
C138 1 2 0.1U_0201_10V K X5R EDP_TXP1_C 16 15
<6> EDP_TXP1 16
C139 1 2 0.1U_0201_10V K X5R EDP_TXN1_C 17
EMI <6> EDP_TXN1

18
19
17
18
EMI
+3VS 19
@EMI@ +3VS_CMOS 20
R125 1 2 0_0402_5% C1211 1 2 10P_0402_50V8J USB20_N5_R 21 20
W=20mils USB20_P5_R 22 21
Camera 23 22
DMIC 24 23
<28> DMIC_CLK 24
USB20_N5_R 25
<12> USB20_N5 <28> DMIC_DAT 25
+3VS 26
R122 1 2 0_0402_5% TS_DISABLE#_R 27 26
Camera USB20_P5_R
<34> TS_DISABLE#
28 27
B <12> USB20_P5 28 B
Touch R1643 1 @ 2 0_0402_5% USB20_N1_R 29
<12> USB20_N1 29
R130 1 2 0_0402_5% 30
<6> TS_I2C_RST# <12> USB20_P1 30
31
1 2 32 31
<11> I2C1_SCL_TS 32
R127 0_0402_5% 33
<11> I2C1_SDA_TS 33
34
<6> TS_INT# 34
+3VS 35
36 35 41
<29,34> EC_SMB_DA4 36 G1
37 42
<29,34> EC_SMB_CK4 37 G2
38 43
R133 1 2 0_0402_5% TAB_SW#_SB 39 38 G3 44
G sensor /Hall sensor <34> TAB_SW#
@ 40 39 G4 45
+3VALW 40 G5
R132 1 2 0_0402_5% ACES_50398-04041-001
SP010013I00
RHS280 ME@
+3VALW 1 2
100K_0402_5%
2
1
VDD
YOGA@
CHS250
0.1U_0201_10V K X5R 3 TAB_SW#_MB
2 OUTPUT
GND
2
YOGA@
UHS17 CHS251
1
APX8132 SOT-23F 3P 10P_0402_50V8J

SA00008K800 1
A YOGA@ A

eDP / Camera
Custom 1.0
5 4 3 2 1
5 4 3 2 1
EMI change to 8.2 from 10

Near JHDMI1 chage to EMI@ from @
EMI
<6> HDMI_CLK+_CK CH229 1 2 0.1U_0201_10V K X5R HDMI_CLK+_CK_C R326 1 2 8.2_0402_1% HDMI_CLK+_CONN HDMI_CLK+_CONN R327 1 2 HDMI_CLK-_CONN
150_0402_5%
EMI@ EMI@
<6> HDMI_CLK-_CK CH230 1 2 0.1U_0201_10V K X5R HDMI_CLK-_CK_C R330 1 2 8.2_0402_1% HDMI_CLK-_CONN HDMI_TX0+_CONN R328 1 2 HDMI_TX0-_CONN
150_0402_5%
EMI@ EMI@
HDMI_TX1+_CONN R329 1 2 HDMI_TX1-_CONN
150_0402_5%
D D
EMI@
HDMI_TX2+_CONN R331 1 2 HDMI_TX2-_CONN
150_0402_5% +5V_Display
EMI@ UH6
CH231 1 2 0.1U_0201_10V K X5R HDMI_TX0+_CK_C R332 1 2 8.2_0402_1% HDMI_TX0+_CONN +5VS 3

<6> HDMI_TX0+_CK OUT W=40mils
1
EMI@ 1
CH232 1 2 0.1U_0201_10V K X5R HDMI_TX0-_CK_C R333 1 2 8.2_0402_1% HDMI_TX0-_CONN IN CH140
<6> HDMI_TX0-_CK 1
2 0.1U_0201_10V K X5R
+3VS CH141 GND 2
EMI@
0.1U_0201_10V K X5R
2 G5250Q1T73U_SC59-3
2
RH133 For HDMI
1M_0402_5%
QH5
2
G
CH233 1 2 0.1U_0201_10V K X5R HDMI_TX1+_CK_C R334 1 2 8.2_0402_1% HDMI_TX1+_CONN 2N7002K_SOT23-3 ME@
<6> HDMI_TX1+_CK
1
JHDMI1
EMI@ 3 1 HDMI_DET 19
<6> TMDS_B_HPD HP_DET
CH234 1 2 0.1U_0201_10V K X5R HDMI_TX1-_CK_C R335 1 2 8.2_0402_1% HDMI_TX1-_CONN 18
D
<6> HDMI_TX1-_CK +5V_Display +5V
2
17
RH137 HDMIDAT_R 16 DDC/CEC_GND
EMI@ SDA
20K_0402_5% HDMICLK_R 15
14 SCL
13 Utility
1
HDMI_CLK-_CONN 12 CEC
11 CK-
HDMI_CLK+_CONN 10 CK_shield
HDMI_TX0-_CONN 9 CK+
CH235 1 2 0.1U_0201_10V K X5R HDMI_TX2+_CK_C R336 1 2 8.2_0402_1% HDMI_TX2+_CONN 8 D0-
<6> HDMI_TX2+_CK D0_shield
HDMI_TX0+_CONN 7
C HDMI_TX1-_CONN 6 D0+ C
EMI@ D1-
CH236 1 2 0.1U_0201_10V K X5R HDMI_TX2-_CK_C R337 1 2 8.2_0402_1% HDMI_TX2-_CONN 5
<6> HDMI_TX2-_CK D1_shield
HDMI_TX1+_CONN 4 23
HDMI_TX2-_CONN 3 D1+ GND1 22
EMI@ D2- GND2
2 21
HDMI_TX2+_CONN 1 D2_shield GND3 20
D2+ GND4
ACON_HMRBL-AK120D
DC232004700
RPH29
5 4
6 3
7 2
8 1
470 +-5% 8P4R
RPH30
5 4
6 3
7 2
8 1
470 +-5% 8P4R +3VS

1
D
2
G
S QH7
3
2N7002K_SOT23-3
B B
+3VS +3VS +5V_Display

2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2
QH6A
RH144
RH143
RH146
RH145
2
2N7002KDW 2N SC88-6 @ESD@ DH1 @ESD@ DH2 @ESD@ DH3

HDMICLK_R 9 10 1 1 HDMICLK_R HDMI_TX1-_CONN 9 10 1 1 HDMI_TX1-_CONN HDMI_TX0-_CONN 9 10 1 1 HDMI_TX0-_CONN
1
1
1
<6> HDMICLK_NB
1 6 HDMICLK_R
HDMIDAT_R 8 9 2 2 HDMIDAT_R HDMI_TX1+_CONN 8 9 2 2 HDMI_TX1+_CONN HDMI_TX0+_CONN 8 9 2 2 HDMI_TX0+_CONN
5
HDMI_DET 7 7 4 4 HDMI_DET HDMI_TX2-_CONN 7 7 4 4 HDMI_TX2-_CONN HDMI_CLK-_CONN 7 7 4 4 HDMI_CLK-_CONN

<6> HDMIDAT_NB
4 3 HDMIDAT_R
+5V_Display 6 6 5 5 +5V_Display HDMI_TX2+_CONN 6 6 5 5 HDMI_TX2+_CONN HDMI_CLK+_CONN 6 6 5 5 HDMI_CLK+_CONN
QH6B
2N7002KDW 2N SC88-6 3 3 3 3 3 3
8 8 8
L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD
A A

HDMI
Custom 1.0
5 4 3 2 1
A B C D E
+5VS
ALC3240 +5VS_PVDD RA1 1 2 0_0805_5% Input
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
+3VDD_CODEC
2 1 2 1
+1.8VS
CA3
CA1
CA2
CA32
4.7U_0402_4V6M 1 2 1 2
2 place close audio codec
CA17
@
+3VDD_CODEC
1
Combo Jack
2
29
34
39
1
UA1
RA38 (Normal Open)
PVDD1
PVDD2
CPVDD
DVDD
<9> HDA_SDIN0 33_0402_5% 2 1 RA12 HDA_SDIN0_AUDIO 7 100K_0402_5%
1
4 SDATA-IN 25 HP_OUTL 1
<9> HDA_SDOUT_AUDIO Headphone
1
SDATA-OUT HPOUT-L(PORT-I-L) 26 HP_OUTR PLUG_IN_R RA13 1 2 200K_0402_1%~N
HPOUT-R(PORT-I-R) PLUG_IN <33>
EMI PC_BEEP 11
5
PCBEEP
VREF
22
27 CPVEE
CA27 1
2
2 1U_0402_6.3V6K
1
AGND
Place RA10 & CA12 on AGND moat <9> SM010016720
22P_0402_50V8J @EMI@ CA12

HDA_BITCLK_AUDIO
33_0402_5% 2 @EMI@ 1 RA10
BCLK CPVEE
CA20 1U_0402_6.3V6K EXT_MIC_SLEEVE EMI@
SM010016720
RA19 2 1 FBMA-L11-160808-121LMT 0603
EMI HGNDB
W=40mils HGNDB <33>
W=40mils EXT_MIC_RING2 EMI@ RA20 2 1 FBMA-L11-160808-121LMT 0603 HGNDA HGNDA <33>
RA6 1 2 2.2K_0402_5% EXT_MIC_RING2 13 17 LINE1-R HP_OUTL EMI@ RA22 1 2 47_0402_5% HPOUT_L
wide 40MIL 1 2 2.2K_0402_5% EXT_MIC_SLEEVE 14 MIC2-L(PORT-F-L)/RING
MIC2-R(PORT-F-R)/SLEEVE
LINE1-R(PORT-C-R)
LINE1-L(PORT-C-L)
18 LINE1-L
EMI HP_OUTR EMI@ RA23 1 2 47_0402_5% HPOUT_R
HPOUT_L <33>
HPOUT_R <33>
AGND
RA7 CA19 2 1 2.2U_0402_6.3V6M 15 24

+LINE1-VREFO-R SD028470A80
23 MIC2-CAP LINE1-VREFO-L 12 PLUG_IN_R SD028470A80
+MIC2-VREFO MIC2-VREFO HP/ LINE1-JD(JD1) SM01000NY00
SPK_L2+ 35 2
External DMIC
For Universal Audio Jack
470P_0402_50V7K
470P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
SPK-OUT-LP GPIO0/DMIC-DATA12
2
SPK_L1- 36 3 DMIC_CLK_R 220_0402_5% 2 1 LA1 DMIC_DAT <26>
SPK-OUT-LN GPIO1/DMIC-CLK 1 1
2
SPK_R1- 37 EMI@ DMIC_CLK <26> LINE1-L CA21 2 1 1U_0402_6.3V6K
RA26
RA27
CA35
CA36
10K_0402_5%
10K_0402_5%
SPK_R2+ 38 SPK-OUT-RN 8 @ @
CA33
CA34
SPK-OUT-RP DVDD-IO +IOVDD_CODEC
AGND AGND
LINE1-R CA22 2 1 1U_0402_6.3V6K
1
2.2U_0402_6.3V6M 1 2 CA26 2 2
1
1
LDO1 21 28
2.2U_0402_6.3V6M 1 2 CA16 LDO2 32 LDO1-CAP CBN 30 CA15
LDO3 6 LDO2-CAP CBP RA29 1 2 4.7K_0402_5% AGND AGND AGND AGND AGND AGND
LDO3-CAP 1U_0402_6.3V6K
2.2U_0402_6.3V6M 1 2 CA13 2 @ @ @ @
40 PDB 1 2 EC_MUTE# <34> +LINE1-VREFO-R RA32 1 2 4.7K_0402_5%
10 PDB 0_0402_5% RA11 2 1
VD33STB
9 DC DET 41
AVDD1
AVDD2
AVSS1
AVSS2
<9> HDA_SYNC_AUDIO SYNC THERMAL PAD RA8 10K_0402_5%
@
ALC3240-VA3-CG_MQFN40_5X5
20
33
19
31
16
2
Output 2
+5VDDA_CODEC
AGND +3VALW
+1.8VS EMI
RA5 1 2
SPEAK 4 ohm 40MIL
0_0402_5% SPEAK 8 ohm 20MIL ME@
Place RA5 on AGND moat JSPK1
SPK_R1- LA5 1 2 0_0603_5% SPK_R1-_CONN 1
CA8 1 2 1U_0402_6.3V6K SPK_R2+ LA6 1 2 0_0603_5% SPK_R2+_CONN 2 1
AGND 2
SPK_L1- LA7 1 2 0_0603_5% SPK_L1-_CONN 3
SPK_L2+ LA8 1 2 0_0603_5% SPK_L2+_CONN 4 3
Place near Pin33 5 4
6 G1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
G2
1 1 1 1 ACES_50278-00401-001
SP02000RR00
EMI@ CA31
EMI@ CA28
EMI@ CA29
EMI@ CA30
+5VS +5VDDA_CODEC Each Plalorm Power Net Support List
2 2 2 2
+5VS +5VDDA_CODEC
+1.5VS +1.8VS +3VS +5VS +3VALW
RA4 2 1 0_0603_5% 1.5V(S0) 1.8V(S0) 3.3V(S0) 5V(S0) 3.3V(S0~S5) ESD protection needs to be placed near connector side
Intel Broadwell V X V V V ESD
0.1U_0201_10V K X5R
1 1
1U_0402_6.3V6K
CA7
Intel Skylake X V V V V
CA11
Place RA4 on AGND moat +5VS

2 2 @ESD@ DA3
SPK_R1-_CONN 6 3 SPK_L2+_CONN
I/O4 I/O2
3 3
5 2
AGND VDD GND
Place near Pin20

SPK_R2+_CONN 4 1 SPK_L1-_CONN
I/O3 I/O1
Each Pla(orm HDA Link Voltage Support (Pin 8) AZC099-04S.R7G_SOT23-6
3.3V 1.5V
Intel Broadwell V (default) V
Intel Skylake V (default) V
+3VS +IOVDD_CODEC +3VS +3VDD_CODEC PC Beep EMI

+3VS +IOVDD_CODEC +3VS +3VDD_CODEC
place close audio codec
RA40 1 2 47K_0402_5% BEEP_N CA37 2 1 1U_0402_6.3V6K PC_BEEP EMI@ CA38 1 2 0.1U_0201_10V K X5R
EC Beep <34> BEEP#
RA3 2 1 0_0603_5% RA2 2 1 0_0603_5% RA41 1 2 47K_0402_5%
APU Beep <9> HDA_SPKR
RA42 1 2 0_0402_5%
1U_0402_6.3V6K
0.1U_0201_10V K X5R
100P_0402_50V8J
CA40 @ESD@
1 1
0.1U_0201_10V K X5R
1
CA4
CA5
1
RA39 RA43 1 2 0_0402_5%
CA6
4 4
27K_0402_5%
2
2 2
Place near Pin8 2 EMI@ CA42 1 2 0.1U_0201_10V K X5R
2
update from 4K7 to 27K

Place near Pin1
GND AGND
AGND

HD Audio Codec_ALC3240
C 1.0
A B C D E
A B C D E F G H
HDD SATA HDD Conn. (G-Sensor for 360-degree reverse)

Near Connector JHDD1
1
CH142 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2 GND
<12> SATA_PTX_DRX_P0 A+
<12> SATA_PTX_DRX_N0 CH143 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3
1 4 A- 1
CH144 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5 GND
<12> SATA_PRX_DTX_N0 CH145 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 6 B-
<12> SATA_PRX_DTX_P0 7 B+
GND
RH1411 @ 2 0_0805_5% +3V_HDD 8 +3VS

+3VS V33 +3VS
9
10 V33 UGS2 YOGA@
11 V33 RGS2 1 2 0_0402_5% +3VS_GS_R 7 3
GND VDD VDDIO
0.1U_0201_10V K X5R
12 10 11
13 GND CSB PS
RH142 1 2 0_0805_5% +5V_HDD 14 GND 5 4
+5VS V5 2 INT1 NC
YOGA@
15 6
V5 INT2
CGS3
16 1
Near HDD 17 V5 2 SDO 9
GND 1 <26,34> EC_SMB_DA4 SDx GND
18 12 8
+5V_HDD Reserved <26,34> EC_SMB_CK4 SCx GNDIO
19
20 GND BMA250E_LGA12
1 V12
@ESD@ 21 24
CH199 22 V12 GND 23
1
@
1 1
0.1U_0201_10V K X5R V12 GND SMB Address: 0001 1000
CH146 CH147 CH148 2
1000P_0402_50V7K 0.1U_0201_10V K X5R 10U_0603_6.3V6M SDAN_603006-022041
2
2 2 2
ESD ME@
DC01000CE00
2
NFC +5VS
+3VS
Finger Printer
2
RN2 RN1 +VDD_MOD JFP1

0_0402_5% 0_0402_5% +VDD_MOD ME@
250mA E-T_6705K-Y08N-40L
10
CLOSE to JNFC PIN 4 GND2
1
+VDD_MOD 9
GND1
CLOSE to JNFC PIN 1 8
8
0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
1U_0402_6.3V6K
USB20_N6 7
<12> USB20_N6 7
1 1 1 USB20_P6 6
<12> USB20_P6 6
NFC@
CN4 NFC@
CN35
NFC@
5
5
CN5
4
3 3 4 3
2 2 2 2 3
JNFC1 1 2
1 1
2 1
150mA 2
3
VCC_BOOST 4 3
5 4 D25 FP_ESD@
<12> NFC_IRQ 5
6 6 3 USB20_P6
SOC_SML0DATA 7 6 I/O4 I/O2
<8> SOC_SML0DATA 7
RN3 <8> SOC_SML0CLK SOC_SML0CLK 8
0_0402_5% 9 8
2 1 NFC_RST_CONN 10 9 5 2
<11> NFC_RST 10 +USB3_VCCA VDD GND
<11> NFC_DWL 11
12 11
13 12
RN4 1 @ 2 14 13 USB20_N6 4 1
<12> NFC_RST_KBL 14 I/O3 I/O1
15
0_0402_5% 15
16 AZC099-04S.R7G_SOT23-6
17 GND
GND
E-T_6705K-Y15N-00L
ME@
4 SMB Address: 0010 1000

SP01001S200
ESD 4

HDD/TPM/APS/NFC
Custom 1.0
A B C D E F G H
A B C D E
+3VS +3VS_WLAN
1 NGFF for WLAN / BT(Key E) 1
RWL153 1 2 0_0805_5%
+3VS_WLAN
JWLAN1
1 2 1 1
3 GND 3.3VAUX 4 CWL155 CWL156
<12> USB20_P7 USB_D+ 3.3VAUX
BT 5 6
<12> USB20_N7 USB_D- LED1#
7 8 4.7U_0603_6.3V6K 0.1U_0201_10V K X5R
9 GND PCM_CLK 10 2 2
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDO_DAT0 PCM_OUT 16
17 SDO_DAT1 LED2# 18
19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_W AKE# 22 WL_UART_RX
23 SDIO_W AKE# UART_RX RPWL1 @
SDIO_RESET# 0_0804_8P4R_5%
UART for intel debugging in WIN7
1 8
UART0_TX <11>
2 7
UART0_RX <11>
24 WL_UART_TX 3 6
UART_TX UART0_RTS <11>
25 26 WL_UART_CTS 4 5
GND UART_CTS UART0_CTS <11>
27 28 WL_UART_RTS
2 <12> PCIE_PTX_C_DRX_P6 PETP0 UART_RTS 2
29 30 RWL155 1 2 0_0402_5%
<12> PCIE_PTX_C_DRX_N6 PETN0 RESERVED EC_TX <32,34>
31 32 RWL156 1 2 0_0402_5%
GND RESERVED EC_RX <32,34>
33 34
<12> PCIE_PRX_DTX_P6 PERP0 RESERVED
WLAN 35 36
<12> PCIE_PRX_DTX_N6 PERN0 COEX3
37 38
39 GND COEX2 40
<10> CLK_PCIE_WLAN REFCLKP0 COEX1
41 42 SUSCLK_R RWL157 1 2 0_0402_5%
<10> CLK_PCIE_WLAN# REFCLKN0 SUSCLK SUSCLK <10>
43 44 WL_RST#
RWL158 1 2 0_0402_5% WLANCLK_REQ#_R 45 GND PERST0# 46 BT_DISABLE_R RWL159 1 2 0_0402_5%
<10> WLANCLK_REQ# CLKEQ0# W _DISABLE2# WLBT_OFF# <11>
<34,35> PCIE_WAKE# RWL162 1 @ 2 0_0402_5% WAKE#_R 47 48 RWL161 1 2 0_0402_5%
PEW AKE0# W _DISABLE1# WL_OFF# <12>
49 50
51 GND I2C_DATA 52
53 RSRVD/PETP1 I2C_CLK 54
55 RSRVD/PETN1 ALERT 56
Note: The real behavior of BT_DISABLE are
57 GND RESERVED 58 BT_DISABLE=LOW, BT=OFF
59 RSRVD/PERP1 RESERVED 60 BT_DISABLE=HIGH, BT=ON
61 RSRVD/PERN1 RESERVED 62
63 GND RESERVED 64
CLK_PCIE_WLAN 65 RESERVED 3.3VAUX 66
CLK_PCIE_WLAN# 67 RESERVED 3.3VAUX
GND
1 1
CRF5 CRF6 69 68
10P_0402_50V8J 10P_0402_50V8J MTG77 MTG76
3 @RF@ @RF@ 3
2 2 BELLW_80152-3221
ME@
SP070013E00
RF
2
@
RWL507 RWL508 WL_RST# RWL164 1 2 0_0402_5% PCI_RST# <10,19,33,34,35>
100K_0402_5% 100K_0402_5%
1
4 4

NGFF WLAN / BT
1.0
A B C D E
5 4 3 2 1
+3VGS +3VS
2
2
Thermal Sensor EX_THM@
R186
R176
0_0402_5%
@
0_0402_5%
1
DDR VRAM
1
D D
+3V_Thermal
Close to UTS17 GPU +EC_VCCA +EC_VCCA
UTS17 EX_THM@
16.5K_0402_1%
16.5K_0402_1%
<20> REMOTE1+
1
1 1 8 EC_SMB_CK2
VDD SCL EC_SMB_CK2 <8,20,34>
RTS336
RTS337
EX_THM@
CTS587 REMOTE1+ 2 7 EC_SMB_DA2 DIS@
D+ SDA EC_SMB_DA2 <8,20,34>
2200P_0402_50V7K
2 REMOTE1- 3 6 THM_ALERT#
<20> REMOTE1- THM_ALERT# <20>
2
D- ALERT#
+3V_Thermal RTS335 1 2 4.7K_0402_5% 4 5
EX_THM@ T_CRIT# GND
<34> DDR_TEMP <34> VRAM_TEMP
NCT7718W_MSOP8
1
RTS338 RTS339
SMB Address: 1001100x 100K +-1% 0402 B25/50 4250K DIS@ 100K +-1% 0402 B25/50 4250K
REMOTE1+/-:
Trace width/space:10/10 mil SL200002H00 SL200002H00
2
Trace length:<8"
ECAGND ECAGND
C C
REMOTE1+ Close to CPU
1
1
C
@ CTS588 2 QTS1 @
100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 E
3
REMOTE1-
CPU VGA LAN NGFF Shielding Clip

H1 H2 H3 H14 H18 H15 H16
Larger
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA CLIP1 CLIP10 CLIP11
HOLEA HOLEA HOLEA
1
1
1
H17 @ @ @
1
HOLEA
B LANGAN LANGAN B
+3VS H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 H_2P5
1
Smaller
1
H4 H5 H6 H7 H8 H19 H20
R235 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H_3P2 CLIP2 CLIP3 CLIP4 CLIP5 CLIP6 CLIP7 CLIP8 CLIP9 CLIP12 CLIP14
+5VS 10K_0402_5% ACES_87213-0500G HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
SP011308190
1
1
2
1
R168 2 1 0_0603_5% +5VS_FAN 5 7 @ @ @ @ @ @ @ @ @ @
1
1
1
1
1
4 5 G2 6
<34> EC_FAN_SPEED1 4 G1
<34> EC_FAN_PWM1 3
2 3
1 2
2 <34> EC_FAN_REVERSE 1 H_5P9X4P6-G H_5P9X4P6-G H_2P5-G H_6P0-G H_2P5-G H_4P6-G H_2P5-G
C162 JFAN1
10U_0603_6.3V6M ME@
1
H9 H10 H11 H12 H13 H21
FD1 FD2 FD3 FD4 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
1
1
1
1
H_3P5X2P5N H_1P5N H_1P5N H_2P5N H_3P5X2P5N
H_2P5
A A

FAN / Thermal Senser
Custom 1.0
5 4 3 2 1
Power Button LED +3VLP +VL
Keyboard +3VS
JKB2
R263 2 1 470_0402_5% CAPS_LED#_R 1

2 1
<34> CAPS_LED# 2
1
S15@ LED4 S15@ R177 YOGA@ S15@ KSI[0..7] KSO15 3
KSI[0..7] <34> 4 3
SC500004Y20 SD034374080 R1668 R1669 KSO10
S LED LTW-110DC5-C 3.2X1 WHITE S RES 1/16W 374 +-1% 0402 KSO[0..17] KSO11 5 4
0_0402_5% 0_0402_5% KSO[0..17] <34> 5
0.1U_0201_10V K X5R
1 KSO14 6
KSO13 7 6
Power (White)
2
C201 KSO12 8 7
S14@ LED3 S14@ KSO3 9 8
ESD@ 9
R175 2 KSO6 10
PWR_LED# 1 2 1 2 +VL_+3VLP_PWR_LED# KSO8 11 10
<34> PWR_LED# 11
KSO7 12
301_0402_1% KSO4 13 12
S LED 19-217/T1D-DP2R1QY/3T(PRE) WHITE KSO2 14 13
KSI0 15 14
SC50000GR00 15
S14@ R1668 KSO1 16
SD028000080 KSO5 17 16
17
3
S RES 1/16W 0 +-1% 0402 KSI3 18
R177 19 18
KSI2
1 2 1 2 KSO0 20 19
KSI5 21 20
+3VS KSI4 22 21
YOGA@ 160_0402_1% KSO9 23 22
LED4 YOGA@ KSI6 24 23
LTW-110DC5-C_WHITE KSI7 25 24
KSI1 26 25
SC500004Y20
15_NUM@ KSO16 27 26
KSO17 28 27
R264 2 1 470_0402_5% NUM_LED#_R 29 28
30 29
<34> NUM_LED# 31 30
<34> EC_GPIO72 31
1 32
32
Touch Pad
C1379 @ESD@ 33
0.1U_0201_10V K X5R GND 34
2 GND
ACES_51510-0320N-P01
ME@
+3VS RTP258 1 2 0_0402_5%
@
CTP163
0.1U_0201_10V K X5R
JTP1
8
7 GND
GND
TP_VCC 6
6
Hall Senser & Button

TP_CLK 5
<34> TP_CLK 5
TP_DATA 4
<34> TP_DATA 3 4
RTP260 1 2 0_0402_5% TP_SMB_CLK 2 3
<8,18> PCH_SMB_CLK 2
RTP261 1 2 0_0402_5% TP_SMB_DATA 1
<8,18> PCH_SMB_DATA 1
ACES_88514-00601-071 RHS279
ME@ 1 2
+3VALW
SP010014M00 100K_0402_5%
2
3
1 1 1
VDD
@ @ @ESD@
CTP164 CTP165 DTP5 CHS248
100P_0402_50V8J 100P_0402_50V8J PSOT24C_SOT23-3 0.1U_0201_10V K X5R 3
2 2 2 OUTPUT LID_SW# <34>
1
GND
2
UHS16 CHS249
1
APX8132 SOT-23F 3P 10P_0402_50V8J
ESD SA00008K800 1
For Debug
Keyboard Backlight +3VALW 1
2
JP3
1
<30,34> EC_TX 3 2
<30,34> EC_RX 3
4
4
ACES_85205-0400
ME@
+5VALW +5VS +VCC_KB_LED

+5VS
KBL@
QKBL121 ACES_51512-0040N-P01
1
KBL@ @ 3 1 4 6
RKBL1
10K_0402_5%
RKBL2
10K_0402_5% ME2301DC-G_SOT23-3
3
2
4 G2
3 G1
5
Power Botton +3VLP
Power Botton
@ CKBL906
KBL@ CKBL908
10U_0603_6.3V6M
2
0.1U_0201_10V K X5R
1
For S Series For YOGA
G
1 2
2
2
RKBL3 1 2 0_0402_5% JKBL1
ME@ ON/OFF#
2 1 R170
1
KBL@ SW6 100K_0402_5%
3
RKBL4 1 2 0_0402_5% CKBL907 SMT1-05_4P SW8
5
6
1
0.01U_0402_16V7K G 7
2 4 2 6 TSS31-EG2-160-T18-S017_3P
G
1
ON/OFF# 5
3 1 ON/OFF# <34> G
4
OUT
G
S14@
2
<34> KB_BL_PWM 2 YOGA@
IN
GND
@
QKBL122
ESD
3
2
DTC124EKAT146_SC59-3 SW7
3
SMT1-05_4P
5
6
D24
4 2 MESC5V02BD03 3P C/A SOT23 ESD
ESD@
3 1
1
S15@

2016/04/07 2017/02/16 Title
Issued Date Deciphered Date KBL/KBD/LED/TP/HS Conn.
C 1.0
Date: Wednesday, July 13, 2016 Sheet 32 of 50
5 4 3 2 1
+5VALWP ESD
ESD@ D6 ESD@ D7 ESD@ D8 ESD@ D9
C2145
C2146
C2147
C2148
C2149
C2150
U3RXDN3 9 10 1 1U3RXDN3 U3RXDN2 9 10 1 1 U3RXDN2 U2DP3 3 6 U2DP2 3 6
USB Charge
I/O2 I/O4 I/O2 I/O4
1 1 1 1 1 1
U3RXDP3 8 9 2 2U3RXDP3 U3RXDP2 8 9 2 2 U3RXDP2
@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
47U_0805_6.3V6M
U3TXDN3 7 7 4 4U3TXDN3 U3TXDN2 7 7 4 4 U3TXDN2 2 5 +USB3_VCCA 2 5 +USB3_VCCA
2 2 2 2 2 2 GND VDD GND VDD
U3TXDP3 6 6 5 5U3TXDP3 U3TXDP2 6 6 5 5 U3TXDP2
3 3 3 3 1 4 U2DN3 1 4 U2DN2
I/O1 I/O3 I/O1 I/O3
8 8
+5VALW_CHG AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6
D
+3VLP
For USB Charger to improve +5VALWP power ripple USB Charge switch L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD
D
+VL +5VALW_CHG +5VALW

R220 @
10K_0402_5%
2 1
2
+5V_CHGUSB 0_0603_5%
USB3.0_Port EMI
R1646
10K_0402_5%
2
1 R221 2 3 1
D
@ 1
R1647
1 0_0603_5% Q31
Add resistor
1
ME2301DC-G_SOT23-3
C455
C456 4.7U_0603_6.3V6K
G
2
4.7U_0603_6.3V6K 2
1
2 Intel_PCH_USB2.0
U9 SA000064O00 80mil L12 EMI@
1 12 1 4 U2DN2
IN OUT +VL <12> USB20_N2 1 4
USB_CHG_STATUS# 9 10 USB20_P4_C
<34> USB_CHG_STATUS# STATUS# DP_IN
R181 2 @ 1 0_0402_5% USB_OC1#_U9 13 11 USB20_N4_C R131
<12> USB_OC1# FAULT# DM_IN
4 2 USB20_N4 1 2 2 3 U2DP2
ILIM_SEL DM_OUT USB20_N4 <12> <12> USB20_P2 2 3
USB_CHG_EN 5 3 USB20_P4
<34> USB_CHG_EN EN DP_OUT USB20_P4 <12> EXC24CQ900U
USB_CHG_CTL1 6 15 R182 1 @ 2 20K_0402_1% 100K_0402_5%
<34> USB_CHG_CTL1 CTL1 ILIM_LO
USB_CHG_CTL2 7 16 R184 1 2 20K_0402_1% 1
<34> USB_CHG_CTL2 CTL2 ILIM_HI
USB_CHG_CTL3 8 14 @
<34> USB_CHG_CTL3 CTL3 GND
1
17 @ R338 D C101
1 T-PAD
10K_0402_5%
1 1 2 EC_ON_R 2 0.1U_0201_10V K X5R

<34,40> EC_ON
2
C174 S IC TPS2546RTER QFN 16P PWR SW @ G Q30 2

R1659
C176 470K_0402_1% S 2N7002K_SOT23-3

Intel_PCH_USB3.0 R223 2 1 0_0402_5%
3
2 0.1U_0201_10V K X5R
2
470P_0402_50V7K W=80mils
R1658 2 1 0_0402_5% U3RXDN2 +USB3_VCCA
<40> 5V_PGD <12> USB3_RX2_N
USB3.0 CONN
1
2
@ U3RXDP2 JUSB1
<12> USB3_RX2_P
C457 U3TXDP2 9
1 SSTX+
0.1U_0201_10V K X5R
1 U3TXDN2 8 VBUS
R224 2 1 0_0402_5% U2DP2 3 SSTX-
C D+ C
7
U2DN2 2 GND 10
R225 2 1 0_0402_5% U3RXDP2 6 D- GND 11
C168 4 SSRX+ GND 12
EMI <12> USB3_TX2_N

0.1U_0201_10V K X5R
C169
1 2U3TXDN2_L U3TXDN2
U3RXDN2 5 GND
SSRX-
GND 13
GND
ACON_TARA4-9K1311
L19 EMI@ 0.1U_0201_10V K X5R ME@
USB20_P4_C 2 3 USB20_P4_R 1 2U3TXDP2_L U3TXDP2
2 3 <12> USB3_TX2_P DC233007O10
USB20_N4_C 1 4 USB20_N4_R
1 4 R226 2 1 0_0402_5%
EXC24CQ900U
+USB3_VCCA
W=80mils
Intel_PCH_USB2.0
Layout JUSB2 close end user
L16 EMI@
1 4 U2DN3 JUSB2
<12> USB20_N3 1
IO CONN
4 U3TXDP3 9
1 SSTX+
2 3 U2DP3 U3TXDN3 8 VBUS
<12> USB20_P3 2 3 SSTX-
U2DP3 3
+3VLP +3VS +5V_CHGUSB EXC24CQ900U 7 D+
U2DN3 2 GND 10
U3RXDP3 6 D- GND 11
W=100mils 4 SSRX+ GND 12
JIO1 U3RXDN3 5 GND GND 13
1 R231 2 1 0_0402_5% SSRX- GND
2 1 Intel_PCH_USB3.0 ACON_TARA4-9K1311
3 2
3 ME@
4 U3RXDN3
4 <12> USB3_RX3_N DC233007O10
B
5 B
6 5
7 6 U3RXDP3
7 <12> USB3_RX3_P
BATT LED <34> BATT_LOW_LED# BATT_LOW_LED# 8
BATT_CHG_LED# 9 8
<34> BATT_CHG_LED# 9
10
PCIE_PRX_DTX_N9 11 10 R232 2 1 0_0402_5%
<12> PCIE_PRX_DTX_N9 11
PCIE_PRX_DTX_P9 12
<12> PCIE_PRX_DTX_P9 12
13
CLK_PCIE_CR# 14 13 R233 2 1 0_0402_5%
<10> CLK_PCIE_CR# 14
<10> CLK_PCIE_CR CLK_PCIE_CR 15 C172
16 15 0.1U_0201_10V K X5R
Card Reader PCIE_PTX_C_DRX_N9 17 16 1 2 U3TXDN3_L U3TXDN3
<12> PCIE_PTX_C_DRX_N9 17 <12> USB3_TX3_N
<12> PCIE_PTX_C_DRX_P9 PCIE_PTX_C_DRX_P9 18 C173
PCI_RST# 19 18 0.1U_0201_10V K X5R
<10,19,30,34,35> PCI_RST# 19
CR_CLKREQ# 20 1 2 U3TXDP3_L U3TXDP3
<10> CR_CLKREQ# 20 <12> USB3_TX3_P
USB20_N4_R 21
CR_CLKREQ# USB20_P4_R 22 21
USB2 For Charge NOVO# 23 22
<34> NOVO# 23
HGNDB 24 R234 2 1 0_0402_5%
<28> HGNDB 24
1
@ 25 Place TX AC coupling Cap (C168,169~171& 173). Close to connector

R1667 HGNDA 26 25
<28> HGNDA 26
0_0402_5% 27
HPOUT_L 28 27
<28> HPOUT_L 28
29
MIC/HP
2
30 29 +USB3_VCCA
HPOUT_R 31 30 33
<28> HPOUT_R 31 GND 34 +5VALW
2A/Active Low
PLUG_IN 32
<28> PLUG_IN 32 GND
W=80mils U10 W=80mils
ME@ 1
SP01001PC00 5 OUT
Close to CPU RPC6 ACES_51547-03201-P01 IN 2 R185
USB_EN# 4 GND 0_0402_5%
<34> USB_EN# EN 3 USB_OC0#_U10 1 @ 2
OCB USB_OC0# <12>
1
AGND C196 SY6288D20AAC_SOT23-5
0.1U_0201_10V K X5R 1
A
2 1 A
C178 + @
220U_6.3V_M C177
SF000006R00 470P_0402_50V7K
2 2

2016/04/07 2017/02/16 Title
USB2 / USB3 / FP / IO Board
5 4 3 2 1
+3VLP +3VLP +5VALW
L20
FBM-11-160808-601-T_0603 USB_EN# R194 1 2 10K_0402_5%
1 2 R189 1 2 0_0603_5% 1@
+3VALW_EC +EC_VCCA
SM010016810 1 1 C179
C185 @ +3VALW_EC 100P_0402_50V8J
C184 +3VS
1 1 1 1 2
0.1U_0201_10V K X5R
C180
0.1U_0201_10V K X5R
C181
1000P_0402_50V7K
C182
1000P_0402_50V7K
C183
0.1U_0201_10V K X5R 1000P_0402_50V7K
1 2 2 ECAGND 2
L21
FBM-11-160808-601-T_0603 2 2 @ 2 @ 2 +EC_VCCA
SM010016810
ECAGND TP_CLK R1648 1 2 4.7K_0402_5%
111
125
22
33
96
67
9
U11
+3VLP TP_DATA R261 1 2 4.7K_0402_5%
VSBY
VCC1/LPC
VCC5/SPI
AVCC
VCC2
VCC3
VCC4
R1655 2 1 100K_0402_5%
1 21 VCIN1_BATT_TEMP 1 2
<33> NOVO# 2 GPIO85/GA20 GPIO15/A_PWM 23 VCCST_PWRGD <10>
BEEP# C189 100P_0402_50V8J
<8> KB_RST# GPIO86/KBRST# GPIO21/B_PWM BEEP# <28>
100P_0402_50V8J
CA48 @ESD@
3 PWM Output 26 1 VCIN1_AC_IN 1 2
<8> SERIRQ 4 SERIRQ/GPIOF0 GPIO32/D_PWM 27 EC_FAN_PWM1 <31>
EC_VCIN1_AC_BYPASS C190 100P_0402_50V8J
<8> LPC_FRAME# LFRAME#/GPIOF6 GPIO45/E_PWM
5 1 2
EMI
@EMI@ @EMI@
<8> LPC_AD3
<8> LPC_AD2
<8> LPC_AD1
7
8
10
LAD3/GPIOF4
LAD2/GPIOF3
LAD1/GPIOF2 GPIO90/AD0
63
64 VCIN1_BATT_TEMP <38,39>
2
R203 @ 4.7K_0402_5%
2 1 R190 2 1 10_0402_1% <8> LPC_AD0 LAD0/GPIOF1 LPC & MISC GPIO91/AD1 65 VCIN1_BATT_DROP <40>
GPIO92/AD2 ADP_I <39>
C186 22P_0402_50V8J 12 AD Input 66
<8> CLK_LPC_EC LCLK/GPIOF5 GPIO93/AD3 DCHG_I <39>
13 75
1 2 <10,19,30,33,35> PCI_RST# 37 LRESET#/GPIOF7 GPIO05/AD4 76 AC_BATT <20>
EC_RST#
+3VALW_EC R192 47K_0402_5% EC_SCI# 20 ECRST# GPIO04/AD5 VRAM_TEMP <31>
<6,10> EC_SCI# 38 GPIO54/ECSCI#
2 <11> SENSOR_EC_INT GPIO11/CLKRUN# 68
YOGA only GPIO94/DA0 TAB_SW# <26>
0.1U_0402_16V7K
ESD@
C187 70
0.1U_0201_10V K X5R
1
GPIO95/DA1 71 TS_DISABLE# <26> YOGA only
1 DA Output GPIO96/DA2 DGPU_PWR_EN <11,21,48>
KSI0 55 72
56 KBSIN0/GPIOA0 GPIO97/DA3 USB_EN# <33>
KSI1
2
KBSIN1/GPIOA1
C188
KSI2 57
<32> KSO[0..17]
KSO[0..17]
KSI[0..7]
KSI3
KSI4
KSI5
58
59
60
KBSIN2/GPIOA2
KBSIN3/GPIOA3
KBSIN4/GPIOA4/N2TCK
GPIO31/SCL3/PSCLK1
GPIO23/SDA3/PSDAT1
83
84
85 EC_SMB_CK4_R
I2C0_SCL_SEN <11>
I2C0_SDA_SEN <11>
R1651 1
YOGA only
2 @ 0_0402_5%
KeyBoard BL_SELECT
<32> KSI[0..7] KSI6 61 KBSIN5/GPIOA5/N2TMS GPIO47/SCL4/PSCLK2 86 EC_SMB_DA4_R R1652 1 2 @ 0_0402_5%
EC_SMB_CK4 <26,29> Function KBL_ID
KBSIN6/GPIOA6 PS2 InterfaceGPIO53/SDA4/PSDAT2 EC_SMB_DA4 <26,29> YOGA only
KSI7 62 87 TP_CLK KBL 1
+3VALW_EC ESD KSO0
KSO1
KSO2
39
40
41
KBSIN7/GPIOA7
KBSOUT0/GPIOB0/SOUT_CR/JENK#
KBSOUT1/GPIOB1/TEST#
GPIO50/PSCLK3
GPIO52/PSDAT3
88 TP_DATA
TP_CLK <32>
TP_DATA <32>
+3VS NO KBL
0
R201 KSO3 42 KBSOUT2/GP(I)OB2/TRIST# 97

KBSOUT3/GP(I)OB3/XORTR# GPIO02 ENBKL <6,26>
1 2 EC_SMB_CK1 KSO4 43 98 1K_0804_8P4R_5% +3VALW
44 KBSOUT4/GPIOB4/SDP_VIS# GPIO75 99 SYS_PWROK <10,44> 4 5 +3VS
2.2K_0402_5% KSO5 GPIO I2C0_SCL_SEN
45 KBSOUT5/GPIOB5/TDO GPIO76 109 ME_EN <9> 3 6
R202 KSO6 I2C0_SDA_SEN
1 2 46 KBSOUT6/GPIOB6/RDY# VCIN1/GPIO16 VCIN0_PH1 <38> 2 7
EC_SMB_DA1 KSO7 Int. K/B EC_SMB_CK4
2.2K_0402_5% KSO8 47 KBSOUT7/GPIOB7 EC_SMB_DA4 1 8
KSO9 48 KBSOUT8/GPIOC0 Matrix 119
49 KBSOUT9/GPIOC1 F_SDI&F_SDIO1/GPO80 120 EC_SPI_MISO <8> RP1
KSO10
KBSOUT10&P80_CLK/GPIOC2 F_SDIO&F_SDIO0/GPIOC6 EC_SPI_MOSI <8>
1
KSO11 50 126 YOGA@ @
51 KBSOUT11&P80_DAT/GPIOC3 F_CLK/GPIOC4 128 EC_SPI_CLK <8>
KSO12 SPI Flash ROM R1665 R324
52 KBSOUT12/GPIO64/TCK F_CS0#/GPIOC5 EC_SPI_CS0# <8>
KSO13 +3VALW 1K_0402_5% @ 1K_0402_5%
KSO14 53 KBSOUT13/GPIO63/TMS
KSO15 54 KBSOUT14/GPIO62/TDI 73 +3VALW +3VLP
DDR_TEMP <31>
2
KSO16 81 KBSOUT15/GPIO61/XOR_OUT GPIO03/AD6/CIRRXM 74 R198 1 @ 2 10K_0402_5%
82 GPIO60/KBSOUT16 GPIO07/AD7/CIRTX1 89 CMOS_ON# <26>
KSO17
GPIO57/KBSOUT17 GPIO67/N2TMS 90 EC_MUTE# <28>
GPIO51/N2TCK BATT_CHG_LED# <33>
91
77 GPIO36 92 CAPS_LED# <32>
EC_SMB_CK1 GPIO
<38,39> EC_SMB_CK1 78 GPIO17/SCL1/N2TCK GPIO40/F_PWM 93 PWR_LED# <32>
EC_SMB_DA1 KB_BL_PWM
<38,39> EC_SMB_DA1 GPIO22/SDA1/N2TMS GPIO35 BATT_LOW_LED# <33>
1
100P_0402_50V8J
C2143 @ESD@
100P_0402_50V8J
C2144 @ESD@
EC_SMB_CK2 79 95 SYSON 1 1 @
<8,20,31> EC_SMB_CK2 80 GPIO73/SCL2 GPIO06/IOX_DOUT 121 SYSON <13,41>
EC_SMB_DA2 SM Bus R1657 R1666
<8,20,31> EC_SMB_DA2 GPIO74/SDA2 GPIO81/F_WP# 2.5V_EN <41>
1
127 EC_FAN_REVERSE 10K_0402_5% 10K_0402_5%
GPIO84/IOX_SCLK EC_FAN_REVERSE <31>
R325
2 2
10K_0402_5% NOKBL@
2
6 100
<33> USB_CHG_STATUS# 14 GPIO24 GPIO26/RSMRST# 101 EC_RSMRST# <10>
<33> USB_CHG_CTL1
2
15 GPIO10/LPCPD# GPIO20/TA2/IOX_DIO 102
<10> EC_CLEAR_CMOS 16 GPIO65/SMI# VC_IN2/GPIO72 103 EC_GPIO72 <32>
VCOUT1_PROCHOT#
<33> USB_CHG_CTL3 17 GPIO34/1_WIRE/CIRRXL VC_OUT2/GPIO37 104 VCOUT1_PROCHOT# <39>
<33> USB_CHG_EN 18 GPIO01/TB2 VC_OUT1/GPIO25 105 VCOUT0_MAIN_PWR_ON <40>
R179 GPIO BKOFF#
1 2 <33> USB_CHG_CTL2 19 GPIO43 GPIO77 106 BKOFF# <26>
EC_PCIE_WAKE# GPIO
<30,35> PCIE_WAKE# GPIO42/CIRTX2 GPIO44 PM_SLP_S3# <10>
0_0402_5% 25 107
<32> KB_BL_PWM 28 GPIO13/C_PWM GPIO12 108 VR_PWRGD <45>
<31> EC_FAN_SPEED1 GPIO56/TA1 GPIO30/F_WP# VR_ON <45>
100P_0402_50V8J
CA46 @ESD@
29 1
<10,20,39> VCIN1_AC_IN 30 GPIO14/TB1
EC_TX
<30,32> EC_TX GPIO83/SOUT_CR/P80_DATA 110 R1664
EC_RX 31 EC_VCIN1_AC_BYPASS R1656 1 @ 2 0_0402_5% VCIN1_AC_IN
<30,32> EC_RX GPIO87/SIN_CR/P80_CLK AC_IN/GPIO41/F_WP#
PCH_PWROK 32 112 EC_ON SUSP# 1 2
<10,44> PCH_PWROK 34 GPIO27/RSMRST# EC_ON/GPIO71 114 EC_ON <33,40> 2
GPIO66/G_PWM GPIO ON_OFFBTN#/GPIO70 ON/OFF# <32>
100P_0402_50V8J
CA49 @ESD@
1 36 115 LID_SW#
1 <32> NUM_LED# GPIO33/H_PWM GPO82/IOX_LDSH/LIDIN LID_SW# <32> 100K_0402_5%
R207 2 116 SUSP#
GPIO46/CIRRXM/PLCIN 117 SUSP# <13,36,41>
10K_0402_5% NUVOTON_VTT
@ VTT 118 PECI 1 2
2 PECI PECI H_PECI <6>
122 R208 43_0402_1%
<10> PBTN_OUT# 123 GPIO00/EXTCLK 124
Share ROM +V18R R209 1 @ 2 0_0402_5% +3VALW_EC
<10,39,41> PM_SLP_S4# GPIO55/CLKOUT/IOX_DIO VCORF
1
AGND
GND4
GND5
GND1
GND2
GND3
4.7U_0402_6.3V6M
C192
+1.0V_VCCST
VCOUT1_PROCHOT# R204 1 2 0_0402_5%
2
94
113
69
11
24
35
NPCE388NA1DX LQFP 128P KBC

+3VALW NUVOTON_VTT R210 1 2 0_0402_5% R205 1 2 0_0402_5% H_PROCHOT# <6>
<45> VR_HOT#
ECAGND
R212 1
1 2 PCIE_WAKE# ESD@
1K_0402_5%
R195
ESD 2
C191
100P_0402_50V8J
1 2 PBTN_OUT# SYSON
ESD 10K_0402_5%
C193
0.1U_0201_10V K X5R
1 @ESD@
@ESD@ 1
C197
0.1U_0201_10V K X5R
2
2
+3VS
1 2 EC_FAN_SPEED1
R214 10K_0402_5%
EC NPCE388
Custom 1.0
5 4 3 2 1
+3VALW +3V_LAN
RL18 1 2 0_0603_5%
60mil W=60mil 1.0V

+LAN_VDD
Source RL11 CL15
W=60mils
2 +LAN_SROUT1.05 1 2 0_0603_5%
RL11 RTL8111H LDO O O
CL1 1
1U_0402_6.3V6K
1 CL15 RTL8107E LDO O O
0.1U_0201_10V K X5R
2 Please refer to the table above when using different 1.0V supply source.
D D
LL1, CL16, and CL17 close to Pin24

( Should be place within 200 mils )
+3VS
RJ-45 CONN.
Rising time (10%~90%) 0.5ms => +3V_LAN <=100ms W=40mils +LAN_VDD JLAN2
1
+3V_LAN RL1
1 2 +LAN_VDDREG RL8 12
+3V_LAN 1K_0402_5% RJ45_TX3- 8 GND
W=60mils
4.7U_0603_6.3V6K
0.1U_0201_10V K X5R
0_0603_5% PR4- 11
1 1
1U_0402_6.3V6K
GND
0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
CL9 CL10 1 1 1 1 1 RJ45_TX3+ 7
2
PR4+
@
@ CL4 CL5 CL6 CL7 CL8 ISOLATE#
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1 1 RJ45_RX1- 6
PR2-
0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
@ @ 2 2
CL2 CL3 CL20 CL21 2 2 2 2 2 RJ45_TX2- 5
RL10 PR3-
2 2 2 2 15K_0402_5% RJ45_TX2+ 4
PR3+
RJ45_RX1+ 3
PR2+
Close to Pin23 RJ45_TX0- 2
Pin3 Pin8 Pin22 Pin30 Pin22 PR1- 10
Pin20 RJ45_TX0+ 1 GND
PR1+ 9
GND
CL2 close to Pin 11, only 8107E LDO mode unpop PS_601012-008041
CL3 close to Pin 32
ME@
C DC234007L00 LANGAN C
+LAN_VDD +LAN_VDD
UL2 @ Close to Pin17 Pin18
LAN_MDIP0 1 17 PCIE_PRX_C_DTX_P5 CL11 1 2 0.1U_0201_10V K X5R
MDIP0 HSOP PCIE_PRX_DTX_P5 <12>
LAN_MDIN0 2 18 PCIE_PRX_C_DTX_N5 CL12 1 2 0.1U_0201_10V K X5R
MDIN0 HSON PCIE_PRX_DTX_N5 <12>
3 19
LAN_MDIP1 4 AVDD10 PERSTB 20 ISOLATE# PCI_RST# <10,19,30,33,34>
LAN_MDIN1 5 MDIP1 ISOLATEB 21
MDIN1 LANWAKEB PCIE_WAKE# <30,34>
LAN_MDIP2 6 22
LAN_MDIN2 7 MDIP2 DVDD10 23 +LAN_VDDREG
8 MDIN2 VDDREG 24 +LAN_SROUT1.05 +3V_LAN
LAN_MDIP3 9 AVDD10 REGOUT 25 LED2 TPL1
LAN_MDIN3 10 MDIP3 LED2 26 LED1_GPIO 1 @ 2
11 MDIN3 LED1/GPO 27 LED0 RL17 10K_0402_5%
+3V_LAN AVDD33 LED0
12 28 XTLO TPL2
EMI <10> LANCLK_REQ#
<12> PCIE_PTX_C_DRX_P5
<12> PCIE_PTX_C_DRX_N5
13
14
15
CLKREQB
HSIP
HSIN
CKXTAL1
CKXTAL2
AVDD10
29
30
31
XTLI
2.49K_0402_1% 2 1 RL9
reserved GPIO pin
RL20 1 2 0_0402_5% <10> CLK_PCIE_LAN 16 REFCLK_P RSET 32
<10> CLK_PCIE_LAN# REFCLK_N AVDD33 +3V_LAN
33
RL21 1 2 0_0402_5% GND
RTL8111H-CG_QFN32_4X4
LANGAN
UL2
SA000086300
@EMI@ CL32 1 2 0.1U_0201_10V K X5R S IC RTL8107E-CG QFN 32P E-LAN CTRL
B B
8107E@
@EMI@ CL33 1 2 0.1U_0201_10V K X5R
UL2
SA000080P00
S IC RTL8111H-CG QFN 32P E-LAN CTRL
LANGAN 8111H@
+V_DAC 1
TL1
24 MCT
EMI
CL13
ESD EMI LAN_MDIP3 2
TCT1
TD1+
MCT1
MX1+
23 RJ45_TX3+ 1
RL19
2
CL19
1 2
1 2 XTLO SC300001G00 LAN_MDIN3 3 22 RJ45_TX3- 75_0805_5% 10P_0603_50V

AZC099-04S.R7G_SOT23-6 EMI@ CL18 TD1- MX1- EMI@ EMI@
10P_0402_50V8J LAN_MDIN3 3 6 LAN_MDIP2 1 2 +V_DAC 4 21
I/O2 I/O4 TCT2 MCT2 LANGAN
0.01U_0402_16V7K LAN_MDIP2 5 20 RJ45_TX2+
1
TD2 MX2+
YL1 2 5 LAN_MDIN2 6 19 RJ45_TX2-
OSC
NC
25MHZ_10PF_5YEA25000102IF50Q3 GND VDD TD2- MX2-

+V_DAC 7 18 2 1
SJ10000E500 TCT3 MCT3
OSC
LAN_MDIP3 1 4 LAN_MDIN2 LAN_MDIP1 8 17 RJ45_RX1+ DL3

NC
I/O1 I/O3 TD3+ MX3+ S SURGE_A MP340SB SMB

DL1 @ESD@ LAN_MDIN1 9 16 RJ45_RX1-
DL1 Only For GIGA EMI@
2
TD3- MX3-
CL14
+V_DAC 10 15
1
10P_0402_50V8J
2 XTLI
SC300001G00
AZC099-04S.R7G_SOT23-6
LAN_MDIP0 11
TCT4
TD4+
MCT4
MX4+
14 RJ45_TX0+ EMI
LAN_MDIN1 3 6 LAN_MDIP0 LAN_MDIN0 12 13 RJ45_TX0-
I/O2 I/O4 TD4- MX4-
NS892407
2 5 TL1 GIGA@
GND VDD S X'FORM_ NS892404 ETHERNET 10/100
A 100@ A
LAN_MDIP1 1 4 LAN_MDIN0 FOR 10/100 data transferring 2013/08/27

I/O1 I/O3
DL2 @ESD@

LAN_RTL8111H / RTL8107E
Custom 1.0
5 4 3 2 1
A B C D E
+3VS
J4
+3VALW 2 1
+VL 2 1
10U_0603_6.3V6M
JUMP_43X79
1 1
0.1U_0201_10V K X5R
1 1
+3VALW to +3VS
10U_0603_6.3V6M
C211
C212
0.1U_0201_10V K X5R
1
C205
1 @
C206
@ 2 2
U13
2 2 1
2 VIN1
VIN1
VOUT1
VOUT1
14
13
+3VALW_3VS
RF
3 12 C207 1 2
ON1 CT1 470P_0402_50V7K
4 11
<13,34,41> SUSP# VBIAS GND +5VS
5 10 1 2 220P_0402_50V7K +3VALW +5VALW
+5VALW ON2 CT2 C213 J5 +5VALW
CRF2
6 9 +5VALW_5VS 2 1 CRF1
VIN2 VOUT2 2 1
10U_0603_6.3V6M
7 8 1 2 1 2
VIN2 VOUT2
10U_0603_6.3V6M
0.1U_0201_10V K X5R
JUMP_43X79 1 1
0.1U_0201_10V K X5R
C217
C218
1 1 15 0.1U_0201_10V7K 0.1U_0201_10V7K
GPAD
C214
C215
@
@ EM5209VF_DFN14_3X2 @RF@ @RF@
SA00007PM00 2 2
2 2
2
+5VALW to +5VS 2
+3VALW +1.8VALW
+1.0VS_VCCIO +1.8VALW
CRF4
CRF3 1 2
1 2
0.1U_0201_10V7K
0.1U_0201_10V7K @RF@
@RF@
For +1.8VALW Discharge For +0.6VS Discharge

+5VALW +1.8VALW
1
+0.6VS
3 3
R1649 R1650
100K_0402_1% 22_0603_1% +5VALW
1
2
1 R228
@
3
D R230 470_0402_5%
1.8VALW_PWR_EN# 5 @
1 2
G 100K_0402_5%
2
S D
4
Q143B SUSP 2 Q21

2N7002KDW_SOT363-6 G 2N7002K_SOT23-3
1
S @
D
3
SUSP# 2 Q23
6
D G 2N7002K_SOT23-3
2 S @
<40,42> 3V/5VALW_PG G
3
S
1
Q143A
2N7002KDW_SOT363-6
4 4

DC to DC
Custom 1.0
A B C D E
5 4 3 2 1
JDCIN1
1
2 1
3 2
4 3
5 4
6 5
7 GND
GND CONN@
D D
ACES_50278-00501-001
EMI@ PL101
PF101
5A_Z120_25M_0805_2P
1 2
+19V_VIN
APDIN 7A_32VDC_0437007.WRML
1 2 +19V_APDIN
EMI@
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
1 2
PL102
1
EMI@ PC101
EMI@ PC102
EMI@ PC103
EMI@ PC104
5A_Z120_25M_0805_2P
2
C C
2
PR107
+CHGRTC
45.3K_0603_1%
PR108
1.5K_0603_5%
1
1 2
PD101
+3VLP
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCBATT 1
3 PR109
1K_0603_5% JRTC1 @
1 2 1
2 1
3 2
4 GND
GND
ACES_50271-0020N-001
B B
A A

PWR- DCIN / Vin Detector
5 4 3 2 1
5 4 3 2 1
EMI@
VMB2 +8.4V_VMB PL201 5A_Z120_25M_0805_2P

PF201 1 2
JBAT1 F1206HB12V024TM 12A 24V UL FAST
1 1 2
1 2 +12.6V_BATT+
EMI@
2 3 EC_SMCA PL202
3 4 EC_SMDA 1 2
4 5
5 6 5A_Z120_25M_0805_2P
6
1
7
7
1
100_0402_1%
100_0402_1%
8
8 9 PC201 EMI@ PC202 EMI@
D GND 10 1000P_0402_50V7K 0.01U_0402_25V7K D
2
GND
PR201
PR202
11
2
GND 12
GND
SUYIN_125022HB008M200ZL
CONN@
EC_SMB_CK1 <34,39>
EC_SMB_DA1 <34,39>
1 2
+3VLP
PR203
1 2 200K_0402_1% +3VALW
PR204
@ 200K_0402_1%
1 2
PR205
VCIN1_BATT_TEMP <34,39> PH201 under CPU botten side :
10K_0402_5%
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
+EC_VCCA
16.5K_0402_1%
1
PR206
C C
2
<34> VCIN0_PH1
1
PH201
100K +-1% 0402 B25/50 4250K
2
ECAGND
B B
A A

PWR- BATTERY CONN/OTP
5 4 3 2 1
A B C D
0x3CH <BIT9> PSYS current gain **Design Notes**

Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 10mΩ and Rs2 = 10mΩ For 45W/65W /90W system, 2S/3S/4S battery
BIT0 = 1.14uA/W Maximum Charging current 3.5A
BIT1 = 0.285uA/W
========================================================= Maximum Battery discharge power 55W
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ #Register Setting
BIT0 = 2.28uA/W 1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function
BIT1 = 0.57uA/W 2. Disable turbo when AC only
#Circuit Design
1. ACLIM and CCLIM are devider voltage control.
Ipsys = KPSYS x ( VADP x IADP + VBAT x IBAT ) 2. Use 7X7 choke and 3X3 H/L side MOSFET
R_Psys = 1.2V / Ipsys Protection for reverse input Charge current 3A
KPSYS = 1.14uA/W Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W)
adapter wattage = 45W Power density : 0.61 (23X16)
Battery wattage = 40Wh #Protect function
Ipsys = 1.14 x (45+40) = 96.9uA 1. ACOVP : VCC voltage > 24V
1
R_Psys = 1.2V / 96.9uA = 12.3K-ohm. Vgs = 20V 1
===================================== Vds = 60V 2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default).
adapter wattage = 65W Id = 250mA 3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).
4. CHGOCP : based on charge current setting
1
Battery wattage = 40Wh D
Ipsys = 1.14 x (65+40) = 119.7uA 2 PQ301 5. BATOVP : 4.6V/Cell
R_Psys = 1.2V / 96.9uA = 10K-ohm. G L2N7002WT1G_SC70-3 6. BATLOWV : No.
S max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W 7. TSHUT : 150C
3
Rds(on) = 15.8mohm max CSR rating: 1W
1 2 1 2
Vgs = 20V VCSIP-VCSIN spec < 81mV
PR301 PR302 Vds = 30V
1M_0402_1% 3M_0402_5% ID = 10.5A (Ta=70C) B+
PQ302 +19V_P1 PQ303
Need check the SOA for inrush MDU1512RH_POWERDFN56-8-5 AON7506_DFN33-8-5 PR303
1 1 +19V_P2 0.01_1206_1% EMI@ +19VB_CHG
2 2 PL301
5 3 3 5 1 4 1 2
+19V_VIN
EMI@
EMI@
2 3 1UH_2.8A_30%_4X4X2_F Module model information
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V7K
4
1
PC203
PC204
CSIN_CHG_R
CSIP_CHG_R
ISL95520_Hybrid_Boost_V2.mdd
PC205
PC206
2
2
1
2_0402_5%
Co-lay jump and ISN choke.
PR305
1 @ PR304
0_0402_5%
PR306
2
392K_0402_1% ASGATE_CHG_R
2
PC207
2
1 2 PQ304
4.02K_0402_1%
4.02K_0402_1%
2 2
AON7506_DFN33-8-5
1
0.1U_0402_25V6
1
2
5 3
PR309
PR729 and PR732 are ACDET setting base on your project to set. 100_0402_1%
4
PR307
PR308
1 2 +12.6V_BATT+ Rds(on) = 32mohm max
Vgs = 20V
0.22U_0402_16V7K Vds = 30V
1
CMSRC_CHG PC209 ID = 8A (Ta=70C) @ PC210

2200P_0402_50V7K
49.9K_0402_1%
1
PR310
PC208
1
ASGATE_CHG 1 2
2
BGATE_CHG
2
OPCN_CHG 2
0.1U_0402_25V7K
CSIN_CHG
CSIP_CHG
OPCP_CHG
VBAT_CHG
Rds(on) = 32mohm max
1 VDD_CHG
Vgs = 20V
Vds = 30V
5
PU301
ID = 8A (Ta=70C) PQ305
100K_0402_1%
support Turbo boost : 2200P Support max charge 3.5A
32
31
30
29
28
27
26
25
no support Turbo boost : 0.1u IC_ISL88739HRZ-T_QFN_32P_CHARGER
AON7408L_DFN8-5 Power loss: 0.245W
PR311
7X7X3
CSIN
CMSRC
OPCN
VBAT
CSIP
ASGATE
QPCP
BGATE
PR312 PC211 4 CSR rating: 1W
2.2_0603_5% 0.22U_0603_25V7K
Isat: 6.5A VCSPP-VCSON spec < 81mV
ACIN_CHG 1 24 BST_CHG 1 2 BST_CHG_R 1 2 DCR: 28mohm
2
ACIN BOOT PR315

PL302
2 23 UG_CHG 0.01_1206_1%
3
2
1
<10,20,34> VCIN1_AC_IN ACOK UGATE 4.7UH_5.5A_20%_7X7X3_M +12.6V_BATT+
1
1 2 0_0402_5% 3 22 LX_CHG 1 2 +12.6V_BATT_CHG 1 4

158K_0402_1%
PR313
<34,38> EC_SMB_DA1 SDA PHASE
PR314
PQ306
PR320 1 2 0_0402_5% 4 21 LG_CHG 2 3
680P_0603_50V7K 4.7_1206_5%
<34,38> EC_SMB_CK1 SCL LGATE
1
5
RF@ PR317
AON7752_DFN3X3EP8-5
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
3
5 20 VDDP_CHG 3
2
@ PR318 0_0402_5% PROCHOT# VDDP
1
PC212
19
PC213
PC214
1 2 AMON_ISL95520 6 VDD_CHG 1 2
<34> ADP_I AMON VDD
2
@ PR321 1 2 0_0402_5% BMON_ISL95520 7 18 PR319 4.7_0402_5% 4
2
<34> DCHG_I BMON DCIN
1
8 17
BATGONE
PC215 PC216
<45> PMON_SKYLAKE PSYS NTC
RF@ PC217
1U_0402_16V6K 1U_0402_16V6K
2
CCLIM
ACLIM
COMP
PROG
AGND
CSON
CSOP
FSET PR323
3
2
1
1
10K_0402_1%
PC219 100K_0402_1%
2
1
1
PR322
PC218 1000P_0402_25V8J
PD102
33
10
11
12
13
14
15
16
1000P_0402_25V8J Follow adapter and PR324 10_1206_5% 3
+19V_VIN
2
battery wattage in @ 1 2 1
3
Close to Vsys current source. 2 PQ307
2
2
1
EC.
FSET_CHG
PC220
VF = 0.38V
1U_0603_25V6
Base on CPU Core VR design.
PR326 LRB715FT1G_SOT323-3 LMUN5113T1G_SOT323-3
The resistor is pop on CPU VR schematic.
1
0_0402_5% PR316 2
1
@ PR325 @ 0_0603_5%
10K_0402_1% 1 2
+12.6V_BATT+
2
1
VDD=5V VDD_CHG
@ PR339
2
1 2
BA
1
CCLIM_CHG
2
200K_0402_1%
0_0603_5%
1
<34> VCOUT1_PROCHOT# ACLIM_CHG <10,34,41> PM_SLP_S4#

A31 connect to BA
PR328
PR329
200K_0402_1% PROG_CHG CSOP_CHG 1 2 CSOP_CHG_R Other team connect to batt conn PQ308
BA
3
COMP_CHG PR331 2_0402_5% LTC015EUBFS8TL_UMT3F
2
1
PR333
100_0402_1%
@ PR332 Fs=729KHZ ~ +/- 15% PC221

38.3K_0402_1%
BA
2 PR334 1
1
76.8K_0402_1% 0.1U_0402_25V6
2
1 2
1
CSON_CHG 1 2 CSON_CHG_R
182K_0402_1%
560P_0402_50V7K
1
PR335
PC222
@ PQ310 @ PR336
76.8K_0402_1%
2
1
1
4
D 0_0402_5% 4
2
1
2
VCIN1_AC_IN PR338 For A31 only.
0.015U_0402_25V7K
2
PR337
G 154K_0402_1% @ Turn off Charger IC on battery only.

1
VCIN1_BATT_TEMP <34,38>
PC223
S Depend on customer design for

3
L2N7002WT1G_SC70-3 BATGONE(BATT_TEMP) system power consumption.

2
logic high: above 2.4V

2
(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 20mΩ and Rs2 = 10mΩ). Hybrid boost power mode logic low: under 0.8V
2
CC_LIM = VccLIM / 64 x Rs2 Cell = 3s

============================================================= PC224
10P_0402_25V8J
(Rs1 = 10mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ).
1
CC_LIM = VccLIM / 32 x Rs2

=============================================================
2015/07/27 2016/07/27 Title
AC_LIM = Vac_LIM / 32 x Rs1 Adapter current limimed:
For U22(45W)_adp: Battery current limimed by CCLIm ~ 3.89A.
PWR_CHARGER
PR337=53.6k Adapter current limimed by ACLIm ~ 4.33A. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
For U23e(65W) and DIS_adp: (PR779 and PQ741 are for change ACLIm when AC in) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
PR337=76.8k Date: Tuesday, June 28, 2016 Sheet 39 of 50
A B C D
A B C D E
Module model information

SY8286B_V1.mdd
1 1
PU401
B+ EMI@ SY8286BRAC_QFN20_3X3 @ PR402
PL401
0_0603_5% PC402
2200P_0402_50V7K
1 2 +19VB_3V BST_3V 1 2 1 2
10U_0805_25V6K
10U_0805_25V6K
@EMI@ PC401
EMI@ PC403
0.1U_0402_25V6
5A_Z120_25M_0805_2P 0.1U_0603_25V7K
1
1
PC429
PC404
BS
IN
IN
IN
IN
PL402
@RF@
2
PC1473 LX_3V6 20 LX_3V 1 2
+3VALWP
2
22P_0402_50V8J @ LX LX
PR403
7 19 1.5UH_6A_20%_5X5X3_M
GND LX
22P_0402_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
@RF@ PC1474
680P_0603_50V7K 4.7_1206_5%
RF@
1
8 18
+3VLP GND GND
PC405
PC406
PC407
PC408
9 17
+3VL
2
PG LDO
1 3V_SN
2
1
10 16
NC NC
1
Check pull up resistor of SPOK at HW side PC409
OUT
EN2
EN1
21
NC
4.7U_0603_6.3V6M
FF
2
PR401 GND
PC410
RF@
100K_0402_5%
11
12
13
14
15
2
3.3V LDO 150mA~300mA
2
Vout is 3.234V~3.366V Ipeak=4.65A
2
<36,42> 3V/5VALW_PG Imax=3.25A 2
ENLDO_3V5V PC411 PR404
1000P_0402_25V8J 1K_0402_1%
TDC=6A Iocp=10A
5V_3V_EN 3V_FB 1 2 3V_FB_1 1 2
EN :H>0.8V ; L<0.4V
EN1 and EN2 dont't be floating @ PJ401
1 2
+3VALWP 1 2 +3VALW
JUMP_43X118
Module model information @ PJP402

SY8286C_V1.mdd JUMP_43X39
1 2
+3VL 1 2 +3VLP
B+ +19VB_5V
EMI@ @ PR405
PL403 PC412
PR407 PU402 SY8286CRAC_QFN20_3X3 0_0603_5%
499K_0402_1% 1 2 +19VB_5V BST_5V1 2 BST_5V_R 1 2
1 2 ENLDO_3V5V
B+ 5
1
5A_Z120_25M_0805_2P
1
150K_0402_1%
0.1U_0603_25V7K
BS
IN
IN
IN
IN
1
PR408
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PC431 LX_5V 6 20 PL404 +5VALWP

1U_0402_16V6K LX LX 3.3UH_+-20%_6.3A_7X7X3
2
PC430
7 19 LX_5V 1 4
2
GND LX
1
1
PC413
PC414
EMI@ PC415
@EMI@ PC416
8 18 2 3
GND GND
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
3 @ PC417 4.7U_0603_6.3V6M 3
2
1
9 17 VCC_5V 1 2
PG VCC
1
PR406
PC418
PC419
PC420
PC421
4.7_1206_5%
@
RF@
10 16
2
PR410 NC NC
OUT
LDO
EN2
EN1
2.2K_0402_5% 21
FF
1 2 GND
<33,34> EC_ON
2
@ PR411
11
12
13
14
15
0_0402_5%
+5VLP
15V_SN
4.7U_0603_6.3V6M
1 2
<34> VCOUT0_MAIN_PWR_ON <33> 5V_PGD 5V LDO 150mA~300mA
1
680P_0603_50V7K
PC424
For HW USB Charge
PC425
RF@
ENLDO_3V5V
2
5V_3V_EN
2
5V_3V_EN
Vout is 4.998V~5.202V
1
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR413
PC427
PR409 TDC=6A Ipeak=9A

100K_0402_5% PC426 PR412
1000P_0402_25V8J 1K_0402_1% Imax=6.25A
2
5V_FB 1 2 5V_FB_1 1 2
Iocp=10A
2
+19VB_5V
+VL
@ PJ403
1
1 2
PR341 EN :H>0.8V ; L<0.4V +5VALWP 1 2 +5VALW
JUMP_43X118
560K_0402_5% EN1 and EN2 dont't be floating
4 @ PJP404 4
2
JUMP_43X39
VCIN1_BATT_DROP <34> 1 2
+5VLP 1 2 +VL
1
PR342 PC327
1000P_0402_25V8J
2
105K_0402_1%
2
PWR- 3VALW/5VALW-SY8286B&C
A B C D E
A B C D E
Pin19 need pull separate from +1.35VP. 0.675Volt +/- 5%

If you have +1.35V and +0.675V sequence question, TDC 0.7A
EMI@ you can change from +1.35VP to +1.35VS.
B+ PL501 Peak Current 1A
1 2 +12.6VB_DDR PR501
2.2_0603_5%
5A_Z120_25M_0805_2P BST_DDR_R 1 2 BST_DDR
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.2VP
1
@EMI@ PC501
EMI@ PC502
PC503
PC504
UG_DDR +0.6VSP
2
1 1
5
LX_DDR
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
PC505
0.1U_0603_25V7K
PC506
PC507
16
17
18
19
20
2
PU501
2
PQ501 4
BOOT
VTT
VLDOIN
PHASE
UGATE
21
AON7408L_DFN8-5 PAD
LG_DDR 15 1
LGATE VTTGND
1
2
3
14 2
PL502 PR502 PGND VTTSNS
1UH_11A_20%_7X7X3_M 13K_0402_1%
1 2 1 2 CS_DDR 13 3
+1.2VP PC508 CS RT8207PGQW_WQFN20_3X3 GND
1
1U_0402_10V6K
PQ502 1 2 12 4 VTTREF_DDR
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
VDDP VTTREF
5
RF@ PR503 AON7506_DFN33-8-5 PR504
1
4.7_1206_5% 5.1_0603_5%
PC509
PC510
PC511
PC512
PC513
PC514
1 2 VDD_DDR 11 5
+5VALW +1.2VP
1 2
VDD VDDQ
1
PGOOD
2
PC516
+5VALW PR505
TON
1
RF@ PC515 4 0.033U_0402_16V7K
FB
S5
S3
2
680P_0402_50V7K PC517 1 2
2
1U_0402_10V6K 5.1_0603_5%
10
6
1
2
3
FB_DDR
EN_DDR
TON_DDR
EN_0.6VSP
PR507
1 2 +1.2VP
PR508 470K_0402_1%
+12.6VB_DDR 1 2
6.04K_0402_1%
1
@ PR510 0_0402_1% PR509
10K_0402_1%
1 2
<13,34> SYSON
2
MOSFET: 3x3 DFN
1
@ PC518
2 H/S Rds(on): 27mohm(Typ), 34mohm(Max) 0.1U_0402_10V7K 2
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C
2
L/S Rds(on): 19mohm(Typ), 23.5mohm(Max) @ PR511
Mode Level +0.675VSP VTTREF_1.35V Idsm: 11A@Ta=25C, 8.8A@Ta=70C 0_0402_1%
S5 L off off 1 2 @ PJ501
S3 L off on Choke: 7x7x3 <13,34,36> SUSP# +1.2VP 1 2 +1.2V
1 2
S0 H on on Rdc=6.7mohm(Typ), 7.4mohm(Max) @ PR518 0_0402_1% JUMP_43X118
Note: S3 - sleep ; S5 - power off Switching Frequency:540kHz 1 2
<7> DDR_VTT_PG_CTRL
Ipeak=8A
1
Iocp~9.6A @ PC519
OVP: 113%~120% 0.1U_0402_10V7K PJ503 @
2
1 2
VFB=0.75V, Vout=1.3545V +0.6VSP 1 2 +0.6VS
JUMP_43X39
3 3

SY8003A_V1.mdd
@ PR513
0_0402_5%
1 2 2.5V_EN <34>
PR512
@ 0_0402_5%
+2.5VSP_ON 1 2 PM_SLP_S4# <10,34,39>
0.1U_0402_16V7K
1
PC520
1
PR514
@ 1M_0402_5%
Note:Iload(max)=2.5A
2
PU502
2
9 @
PGND PJ504
1 8
FB SGND 1 2
PJ505 @ 2 7 +2.5VP 1 2 +2.5V
PG EN PL503
+3VALW 1 2 3 6 LX_2.5V 1 2 JUMP_43X79
1 2 IN LX 1UH_2.8A_30%_4X4X2_F +2.5VP
1
4 5
68P_0402_50V8J
JUMP_43X79 PGND NC
1
PC521 PR516
4.7_0603_5%
1
PR515
PC522
22U_0603_6.3V6M
36.5K_0402_1%
Rup
RF@
22U_0603_6.3V6M
22U_0603_6.3V6M
SY8003ADFC_DFN8_2X2
PC523
PC524
2
2
2
FB_2.5V
1
1
FB=0.6V PR517
680P_0402_50V7K
Note:Iload(max)=3A Rdown
RF@ PC525
11.5K_0402_1%
2
4 4
Vout=0.6V* (1+Rup/Rdown)
Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
2015/07/27
Compal Secret Data
2016/07/27 Title
+1.2VP/+0.6VSP/+2.5VP
Custom
LA-E221P 1.0

A B C D E
A B C D
1 1

APL5930_V2.mdd
+3VALW +5VALW
2
1
Ultra Low Dropout 0.23V(typical) at 3A Output Current 2
1
1 PC601
1U_0402_6.3V6K
JUMP_43X79
2
@ PJ601
2
2
PU601
APL5930KAI-TRG_SO8
1
PC602 6
4.7U_0603_6.3V6K 5 VCNTL 3
@ PR601 9 VIN VOUT 4
2
0_0402_5% VIN VOUT

+1.8VALWP
1
1 2 8
0.01U_0402_25V7K
<36,40> 3V/5VALW_PG EN
1
7 2 PR603
POK GND FB
PC604
12.7K_0402_1%
22U_0603_6.3V6M
1
Rup
0.1U_0402_16V7K
1
PC603
PC605
PR604
2
1M_0402_5%
2
2
@
2
PR606
PJ602
1
100K_0402_5% @
PR605 +1.8VALWP 1 2 +1.8VALW
10K_0402_1% 1 2
1
JUMP_43X79
Rdown
2
<43> PGOOD
3 3
+3VALW Vout=0.8V* (1+Rup/Rdown)
4 4

+1.8V_PRIM
A B C D
5 4 3 2 1
D D
C C

SY8288_V1.mdd
Confirm HW side
+19VB_1V RF@ PR703 RF@ PC702
4.7_1206_5% 680P_0603_50V7K
PR710 +3VALW 1 2 SNUB_1V 1 2
EMI@ @ 10K_0402_5%
PL701
PU701
B+ 1 2 +19VB_1V 2
IN PG
9 1 2 @ PR704
0_0402_5%
PC704
0.1U_0201_10V6K
(Common Part SH00000YE00)
10U_0805_25V6K
0.1U_0402_25V6
5A_Z120_25M_0805_2P 3 1 BST_1V 1 2 BST_1V_R 1 2 PL504

2200P_0402_50V7K
1
IN BS
1
1UH_11A_20%_7X7X3_M
EMI@ PC701
PC705
@EMI@ PC703
4
IN LX
6 LX_1V 1 2
+1.0VALW
2
2
2
5 19
14K_0402_1%
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
1
1
1
7 20
PR705
PC706
PC709
PC710
PC708
PC707
PC714
PC715
GND LX
8 14 FB_1V
R1
2
2
2
PR701 GND FB
2
@ 0_0402_5% 18 17 LDO_3V_1V
GND VCC
1 2 EN_1V 11 10 1 @ @
<42> PGOOD EN NC PC711 FB=0.6V
1
@ PC712 ILMT_1V 13 12 2.2U_0402_6.3V6M
2
ILMT
1
NC
1
B B
0.22U_0402_10V6K
PR706 15 16 PR707
1M_0402_1% +3VALW BYP NC Vout=0.6V* (1+R1/R2) R2 20K_0402_1%
+3VALW
2
21 =0.6*(1+(14/20))
2
PAD
2
SY8286RAC_QFN20_3X3
Vout=1.02V
1
PC713
1
EN :H>0.8V ; L<0.4V 1U_0402_6.3V6K

2
@ PR708
0_0402_5%
EN pin don't floating
If have pull down resistor at HW side,
2
please delete PR601.
The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high.
A A

+1.0VS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
5 4 3 2 1
A B C D
1
Module model information 1
NB681_V1.mdd
2 2
U23E@ PR802
100K_0402_1%
MODE_+1.0VS_VCCIOP 1 2
U23E@ PR801 U23E_RF@ U23E_RF@
0_0402_5% U23E@ PR803 U23E@ PC802 PR804 PC803
1 2LPM#_+VCCIOP 2.2_0402_5% 0.1U_0402_25V6 4.7_1206_5% 680P_0402_50V7K
<17> LPM_ZVM#
BST_+1.0VS_VCCIOP 1 2 BST_R_+1.0VS_VCCIOP 1 2 1 2SNUB_+1.0VS_VCCIOP 1 2
Note:Iload(max)=5.5A
U23E@
U23E_EMI@ PU801
IOCP=7A~8A(typ)
9
PL801 U23E@ PL802
5A_Z120_25M_0805_2P 0.68UH_7.9A_20%_5X5X3_M
MODE
LP#
BST
B+ 1 2 +19VB_+1.0VS_VCCIOP 1
VIN SW
8 LX_+1.0VS_VCCIOP 1 2
+1.0VS_VCCOPCP
U23E@PR805 EN_+1.0VS_VCCIOP 5 12
0.1U_0402_25V6
20K_0402_1% EN VOUT 3
2200P_0402_50V7K
10U_0805_25V6K
1
3
PC801
2
@U23E_EMI@ PC806
U23E@ PC808
1 2C1_+1.0VS_VCCIOP
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
C1 PGND U23E@ PR811
1
4 11
PC804
PC805
PC807
PC814
+3VALW C0_+1.0VS_VCCIOP 10_0402_5%
2
C0 AGND
3V3
1 2 +1.0VS_VCCOPCP
PG
1
U23E_EMI@
2
PR806 U23E@ NB681GD-Z_QFN13_2X3
13
10 U23E@ PR808
EN pin don't floating 20K_0402_1% 0_0402_5%
1 2 +1.0VS_VCCOPC U23E@
If have pull down resistor at HW side, pls delete PR606
2
U23E@ U23E@ @U23E@

PR807
0_0402_5% @ PJ801
1 2 PR809 @U23E@ JUMP_43X118
<10,34> PCH_PWROK
U23E@ <10,34> SYS_PW ROK
0_0402_5%
1 2 +3VALW +1.0VS_VCCOPCP
1
1 2
2
+1.0VS_VCCOPC
1
PC810 @U23E@
1
PC809 U23E@
0.1U_0402_25V6 PR810 @U23E@
2
100K_0402_1% 1U_0402_6.3V6K
2
1 2
EN Mode Voltage on EN
Ultra Sonic Mode 1.3v<EN<1.7v
Normal Mode 2.3v<EN<3.3v Switching frequency is 650KHz
4 4
Security Classification Compal Secret Data

+1.0VS_VCCOPC
A B C D
1 2 3 4 5
CPU Due to U23e VCC_GT and GTX merged current spec is TBD in PDDG. IccMAX@SA= 5A
CORE Please confirm FAE the setting of PRI23, PRI39 PRI63 for U23e GT and GTX merged. RIccMAX@SA= 15.8K --->PRI65
RIccMAX@SA= IccMAX*2V/10uA/64A
IOUTSP@SA= 5A
NCP81208_U2223E_COLAY_V1A.mdd for IC portion RIOUTSP@SA=69.8K --->PRI14
NCP81208_U2223E_COLAY_V1B.mdd for SW portion RIOUTSP= 2V/(gm*(Rth+RCSSP)*ICCMAX*DCR

/(RPHSP+Rth+RCSSP))
PSYS:
Copy the schematic to new page, PMON_SKYLAKE <39> Please confirm charger pull low resistance. OCP@SA= 9.5A
A
the co-lay location maybe changed. Charger side should be unpop. RLIMSP@SA=24K --->PRI5 A
RLIMSP= 1.3V/(gm*(Rth+RCSSP)*IoutLIMIT*DCR
PCI902 PRI902 /(RPHSP+Rth+RCSSP))
8200P 25V K X7R 0402 1.5K_0402_1%
OCP for VCCSA 1 2 1 2
PRI2, PRI8 place near CPU side. Load line@SA= 10.3m
If the resisters are at HW side and POP. PRI2, PRI8 can be canceled. RDRPSP@SA=1.78K --->PRI4
PCI901 COMP_1b_CPU 1 2 PCI903
1000P_0402_50V7K 15P_0402_50V8J
+VCCSA PRI901 1 2 RDRPSP= Load line*(RPHSP+Rth+RCSSP)
1000P_0402_50V7K
100_0402_1% /(gm * DCR) /(Rth+RCSSP)
1 2 @ PRI903 PRI904
1
0_0402_5% 1.78K_0402_1% CSN_1b_VCCSA <46>
24K_0402_1%
1
1 2 VSPP_1b_CPU_R 1 2 VSP_1b_CPU
PRI905
<13> VCCSA_SENSE
PHI902 Close to SA choke
PCI904
1200P_0402_50V7K
2
1
RDRPSP 100K_0402_1%_NCP15WF104F03RC
0.01U_0402_25V7K
PCI905 PRI907
2
@ PRI906 1000P_0402_50V7K 1K_0402_5%
PCI908
1 2
2
1
1 2
0_0402_5% VSNN_1b_CPU_R 1 2 VSN_1b_CPU CSN_1b_VCCSA_NTC
PCI907
<13> VSSSA_SENSE
1 2 1 2 PCI906 PRI909
2
PRI908 100_0402_1% 2200P_0402_50V7K 12K_0402_1%
+VCCGT PRI910 CSP_1b_VCCSA +3VS
1 2 CSP_1b_VCCSA_R <46>
2
1 2 20K_0402_1% PRI914 1 2
1
PRI911 100_0402_1% @ 0_0402_5% 64.9K_0402_1% 7.5K_0402_1%
<15> VCCGT_SENSE 1 2 PRI913 VSP_2ph_CPU 1 2 PRI912 PRI915
10K_0402_1%
1
1 2
<15> VSSGT_SENSE PCI910 PRI918 PCI909 470P_0402_50V7K
2
@ PRI917 1000P_0402_50V7K 1K_0402_1% VR_PWRGD <34>
2
1 2 1 2 VSN_2ph_CPU_R 1 2 VSN_2ph_CPU
1
RIOUT@GT: PRI916 100_0402_1%
0_0402_5% 1 2 PCI911 IMVP8_EN confirm with power sequence, PCI935
U23e = 22.1K PRI23 3300P_0402_50V7-K +1.0V_VCCST 10P_0402_25V8J
U22 = 25.5K PRI23 Upper Threshold > 0.8V it need behind +5VS.
2
Lower Threshold < 0.3V
1
B U23E@ PRI923 B
23.2K_0402_1% PRI919
604_0402_1%
1
PRI11, PRI16 place near CPU side. 49.9_0402_1% PRI922
@ 0_0402_5%
PRI921
If the resisters are at HW side and POP. PRI11, PRI16 can be canceled.
1 2
100_0402_1%
110_0402_1%
45.3_0402_1%
1 2
RIOUT@GT VR_ON <34>
IOUT_1b_CPU
PRI26 and PRI33 pull high resistor are pop at the end of VR SVID.
ILIM_1b_CPU
RPH@GT: Other VR is unpop.
470P_0402_50V7K
2
PCI912
EN_CPU
U23e = 130K PRI929,PRI938 PWM_1b_CPU <46>
1
470P_0402_50V7K
U22 =84.5K PRI929
2
CSCOMP_2ph_CPU_R
Close to VGT1 choke DRVON <46>
1
1
1
U23E@ PRI923 U22@ PRI924 @
PCI913
PRI929 PRI939 U23E@ 25.5K_0402_1% PCI915 110_0402_1% PRI935
1
1
4.75K_0402_1%
110K_0603_1% PHI901 14K_0402_1% 7.5K_0402_1%
49
48
47
46
45
44
43
42
41
40
39
38
37
0.1U_0402_25V6
2
2
THERM_ 220K 5% 0402 @ 1 2
CSP_1a_VCORE_R <46>
PRI927
1
1
1 2 U22/U23e is the same
VSN_2ph
VSP_2ph
VSP_1b
VSN_1b
COMP_1b
ILIM_1b
CSN_1b
CSP_1b
IOUT_1b
EN
TAB
PSYS
VR_RDY
2
2
2
PCI914 PUI901 VR_HOT# <34> PRI928
PRI934
PRI932
PRI933
but OCP is different. 15P_0402_50V8J NCP81208-MNTXG_QFN48_6X6 12K_0402_1%
OCP for VGT 2
1 2
PRI930 PRI931 IOUT_2ph_CPU 1 36 PCI917 1 2
165K_0402_1% 75K_0402_1% DIFFOUT_2ph_CPU 2 IOUT_2ph PWM_1b 35 PRI936 49.9_0402_1% 470P_0402_50V7K CSN_1a_VCORE_NTC
0.022U_0402_16V7K
1 2 1 2 1 2 U22@ PRI939 PCI916 FB_2ph_CPU 3 DIFFOUT_2ph DRVON 34 SCLK_CPU 1 2 1 2
<46> CSP1_VGT1 FB_2ph SCLK VR_SVID_CLK <15>
1
1
1
PRI929 U22@ 71.5K_0603_1% 12.4K_0402_1% 2200P_0402_50V7K COMP_2ph_CPU 4 33 1

ALERT#_CPU @ PRI937 2 Close to VCORE choke
PCI920
2
COMP_2ph ALERT# VR_ALERT# <15>
1 2 PCI918 PCI919 @ 1 2 ILIM_2ph_CPU 5 32 SDIO_CPU PRI9401 2 10_0402_1%
0_0402_5% PRI942 PHI903
<46> CSP2_VGT2 ILIM_2ph SDIO VR_SVID_DATA <15>
1
PRI938 U23E@ 110K_0603_1% 1000P_0402_50V7K 1000P_0402_50V7K CSCOMP_2ph_CPU 6 31 VR_HOTL# PRI9411 2 100_0402_1% 66.5K_0402_1% 100K_0402_1%_NCP15WF104F03RC
2
CSSUM_2ph_CPU 7 CSCOMP_2ph VR_HOT# 30 IOUT_1a_CPU 1 2 PCI921

1 2 CSREF_2ph_CPU 8 CSSUM_2ph IOUT_1a 29 CSP_1a_VCORE 0.01U_0402_25V7K
<46> CSN2_VGT2
2
2
2
PRI943 U23E@ 10_0402_1% CSP2_2ph_CPU 9 CSREF_2ph CSP_1a 28 CSN_1a_VCORE <46>
1
1 2 CSP1_2ph_CPU 10 CSP2_2ph CSN_1a 27 ILIM_1a_CPU
ROSC_COREGT
<46> CSN1_VGT1
0.1U_0402_25V6
0.1U_0402_25V6
PRI944 10_0402_1% TSENSE_2ph_CPU_R 1 2 TSENSE_2ph_CPU 11 CSP1_2ph ILIM_1a 26 COMP_1a_CPU
ADDR_VBOOT
1
TSENSE_2ph COMP_1a
1
TSENSE_1ph
RSOC_SAUS
ICCMAX_2ph
1 2 12 25
PCI922
U23E@ PCI923
ICCMAX_1a
ICCMAX_1b
PCI926
2
VRMP VSN_1a
1
PWM1_2ph
PWM2_2ph
PCI924 @ PRI945 PRI946 3300P_0402_50V7-K PCI925
VRMP_CPU
100K_0402_1%_NCP15WF104F03RC
+19VB_CPU 1K_0402_1%
PWM_1a
1
0_0402_5% 1 2 VSN_1a_CPU_R PCI927 PCI928 1000P_0402_50V7K
VSP_1a
2
2
0.1U_0402_25V6 PHI904 PRI948 15P_0402_50V8J 1500P_0402_50V7K
VCC
1 2
1
For U22: 61.9K_0402_1% PRI949 PRI950 PRI951
1
PRI943=De-pop PCI929 499_0402_1% @ 0_0402_5% 100_0402_1%
1
CSP1_VGT1 1 2 0.1U_0402_25V6 PCI930 1
VSN_1a_CPU 2 1 2 1 2 PRI952 PRI953
For U23e:
2
2
2
13
14
1ROSC_SAUS_CPU 15
16
17
18
19
20
21
22
23
24
PRI947 2.15K_0402_1% 0.01U_0402_50V7K 2.49K_0402_1% 40.2K_0402_1%
PRI943,PRI944=Pop
1
CSP2_VGT2 1 2 PCI931 VSSCORE_SENSE <15>
2
PRI954 2.15K_0402_1% 1000P_0402_50V7K
ICCMAX_2ph_CPU
2
VCC_CPU
ADDR_VBOOT_CPU
C C
ICCMAX_1a_CPU
ICCMAX_1b_CPU
U23E@ Close to VGT1 MOS RDRPSP
2
+5VS PRI955 PRI956 OCP for VCORE
1 2 2_0402_1% 2.61K_0402_1% @ PRI957
For U22: +5VS U22@ PRI958 1 2 1 2VSP_1a_CPU_R 1 2 +VCCCORE
VCCCORE_SENSE <15>
1K_0402_1%
PRI947=2K, PRI954=De-pop
1ROSC_COREGT_CPU
VSP_1a_CPU 1 2 1 2 0_0402_5% 1 2 PRI51, PRI58 place near CPU side.
24K_0402_1%
For U23e: 2.61K_0402_1% PRI961 100_0402_1%
PRI947=2K, PRI954=2K For U22: If the resisters are at HW side and POP. PRI51, PRI58 can be canceled.
1
472mV/120uA=3.933K PCI932 PRI960
PRI962
PCI923=De-pop PCI933 1000P_0402_50V7K
For U23e: Active Point110 degreeC = 4.206K 1U_0603_10V6K @ PRI963 For U22:
2
PCI923=0.1u TSENSE_1ph_CPU 1 2 TSENSE_1ph_CPU_R U22 Load line@VCORE= 2.35m
2
For U23e: RDRPSP@VCORE=2.1K --->PRI56
1
U22 OCP@GT= 40A 0_0402_5%
1000P_0402_50V7K
U23e Load line@VCORE= 2.1m
RLIM@GT=12.4K --->PRI39
33.2K_0402_1%
61.9K_0402_1%
1
1
Fsw for SA RDRPSP@VCORE=1.87K --->PRI56
2
U23e OCP@GT= 62A PWM_1a_CPU <46> PHI905
PCI934
PRI965
RLIM@GT=12.4K --->PRI39 100K_0402_1%_NCP15WF104F03RC

RDRPSP= Load line*(RPHSP+Rth+RCSSP)
PRI966
10K_0402_1%
100K_0402_1%
15.8K_0402_1%
48.7K_0402_1%
Fsw for CORE & GT /(gm * DCR) /(Rth+RCSSP)
RLIM= IoutLIMIT * Load line/10
2
2
2
Close to VCORE MOS
U22 IccMAX@GT= 31A NCP81208 Operating Frequency Rosc=24K
RIccMAX2ph= 48.7K --->PRI63 I/A and GT are 450KHz and SA is 450KHz
1
1
1
1
U23e IccMAX@GT= 56A IccMAX@VCORE= 28A
472mV/120uA=3.933K RIccMAX@VCORE= 87.6K --->PRI64
RIccMAX2ph= 87.6k --->PRI63 RIccMAX2ph: Active Point110 degreeC = 4.206K
PRI967 U23E@ RIccMAX@VCORE= IccMAX*2V/10uA/64A
U22@
PRI968
PRI969
PRI967
PRI970
RIccMAX2ph= (IccMAX2Ph+32)*200K Ohn/ 127
2
2
2
100K_0402_1%
U22 Iout@GT= 31A IOUTSP@VCORE= 28A

RIOUT@GT=25.5K --->PRI23 RIOUTSP@VCORE=64.9K --->PRI42
U23e Iout@GT= 56A VBOOT:
RIOUT@GT=22.1K --->PRI23 22.1K for debuge setting. RIOUTSP= 2V/(gm*(Rth+RCSSP)*ICCMAX*DCR
/(RPHSP+Rth+RCSSP))
D
RIOUT= 2* RLIM /(10 *IOUTICCMAX * Load line) D
PWM2_2ph_CPU <46> OCP@VCORE= 35A
U22 Load line@GT= 3.1m PWM1_2ph_CPU <46> RLIMSP@VCORE=33.4K --->PRI53
RPH@GT=84.5K --->PRI30,PRI38
U23e Load line@GT= 2m RLIMSP= 1.3V/(gm*(Rth+RCSSP)*IoutLIMIT*DCR
RPH@VGT=130K --->PRI30,PRI38 /(RPHSP+Rth+RCSSP))
Load line= (RCS2+(RCS1*Rth/(RCS1+Rth)))
*IOUTTOTAL * DCR/RPH Security Classification Compal Secret Data Compal Electronics, Inc.
Title
PWR-PROCESSOR_DECOUPLING
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
1 2 3 4 5
1 2 3 4 5
EMI@ PLI1001
CPU POWER STAGES 5A_Z120_25M_0805_2P
1 2
InputCapacitor:
EMI@ PLI1002
+19VB_CPU 10uF_0805_X5R_25V 5A_Z120_25M_0805_2P B+
1 2
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PCI1006
1 1
33U_25V_NC_6.3X4.5
33U_25V_NC_6.3X4.5
1
1
+ +
PCI1002
PCI1003
@EMI@
PC811
PC813
2
2
2 2
5
PRI1001 PCI1001
2.2_0603_5% 0.22U_0603_16V7K PQI1001
1 2 BST_VCORE_R 1 2
A A
BST_VCORE UG_VCORE 4
AON6428L_DFN8-5
PUI1001 VCC_CORE
3
2
1
NCP81253MNTBG_DFN8_2X2 FSW=450kHz
PLI1003
1 8 0.22UH +-20% 24A 7X7X4 +VCCCORE DCR = 1.19 mohm +/- 5%
BST DRVH
2 7 LX_VCORE 1 4
TYP MAX
<45> PWM_1a_CPU PWM SW H/S Rds(on) :11.7mohm , 14mohm
DRVON 3 6 2 3
+5VS EN GND L/S Rds(on) :2.7mohm , 3.3mohm
5
4 5
PAD
VCC DRVL
1
PQI1002 RF@
1
PRI1003 CSN_1a_VCORE <45>

9
PCI1008 AON6794_DFN5X6-8-5 4.7_1206_5%

2.2U_0603_16V6K 4
2
2
SNB_VCORE CSP_1a_VCORE_R <45>
3
2
1
1
RF@
PCI1010
680P_0603_50V7K
2
VCCGT(2 phase)
FSW=450kHz +19VB_CPU
B
DCR = 1.19 mohm +/- 5% B
TYP MAX
H/S Rds(on) :11.7mohm , 14mohm
10U_0805_25V6K
10U_0805_25V6K
PCI1013 U23E@
PCI1014 U23E@
L/S Rds(on) :2.7mohm , 3.3mohm
+19VB_CPU
1
2
2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
U23E@
0.1U_0402_25V6
PCI1021
EMI@ PCI1022
1 PRI1005
33U_25V_NC_6.3X4.5
PRI1004 2.2_0603_5%
1
1
1
+
PCI1018
PCI1019
2.2_0603_5% BST2_VGT2 1 2 BST2_VGT2_R
@EMI@
PC812
BST1_VGT1 1 2 BST1_VGT1_R
2
2
1
PCI1023 U23E@
1
0.22U_0603_16V7K
2
PCI1024 U23E@
0.22U_0603_16V7K PQI1003 PUI1003
2
PUI1002 NCP81151MNTBG_DFN8_2X2 U23E@
1
NCP81151MNTBG_DFN8_2X2 1 9 PQI1004 AON6992_DFN5X6D-8-7
BST FLAG
2
1 9 U23E@PLI1005
D1
G1
<45> PWM1_2ph_CPU BST FLAG <45> PWM2_2ph_CPU
PLI1004 2 8 UG_VGT2 0.22UH +-20% 24A 7X7X4
D1
G1
2 8 UG_VGT1 0.22UH +-20% 24A 7X7X4 +VCCGT PWM DRVH +VCCGT

PWM DRVH DRVON 3 7 LX_VGT2 7 LX_VGT2 1 4
3 7 LX_VGT1 7 LX_VGT1 1 4 EN SW D2/S1
<45> DRVON EN SW D2/S1
+5VS 4 6 2 3
VCC GND
4.7_1206_5%
U23E_RF@ PRI1008
4 6 2 3
RF@
330U_D1_2VY_R9M
G2
S2
S2
S2
VCC GND 5 LG_VGT2 U23E@
G2
S2
S2
S2
DRVL 1 1
1
4.7_1206_5%
330U_D1_2VY_R9M
+5VS LG_VGT1 PCI1026
6
DRVL
1
AON6992_DFN5X6D-8-7 U23E@ + PCI1025 +
3
6
1
PRI1009
PCI1028
SNUB_VGT2 2
PCI1027 2.2U_0603_16V6K
2
2.2U_0603_16V6K CSN2_VGT2 <45> 2 2
2
SNUB_VGT1 2
CSN1_VGT1 <45> LG_VGT2

C C
LG_VGT1
680P_0603_50V7K
CSP2_VGT2 <45>
RF@
CSP1_VGT1 <45>
For U22:
PCI92=De-pop
1
680P_0603_50V7K
U23E_RF@ PCI1030
For U23e:
1
PCI92=Pop
PCI1029
2
2
+19VB_CPU
10U_0805_25V6K
10U_0805_25V6K
1
1
PCI1031
PCI1032
PRI1010 PCI1035
2
2.2_0603_5% 0.22U_0603_16V7K
1 2 BST_VCCSA_R 1 2
VCCSA
BST_VCCSA
FSW=450kHz
UG_VCCSA
DCR 6.2mohm(TYP), 6.51mohm(Max)
TYP MAX
AON7934
PUI1004
Rds(on)=12.4~15.8m ohm H/S Rds(on) :12.4mohm , 15.8mohm
4
NCP81253MNTBG_DFN8_2X2 PQI1005
L/S Rds(on) :9.1mohm , 11.6mohm
D1
D1
D1
G1
1 8
PLI1006
+VCCSA
BST DRVH
<45> PWM_1b_CPU 2 7 10 9 1 4
D
PWM SW D1 D2/S1 D
RF@ PRI1011
DRVON 3 6 2 3
+5VS EN GND
4.7_1206_5%
G2
S2
S2
S2
4 5
PAD
VCC DRVL AON7934_DFN3X3A8-10 0.47UH_+-20%_12.2A_5X5X3

5
8
1
9
2.2U_0603_16V6K
PCI1036
CSN_1b_VCCSA <45>
2
SNB_VCCSA
680P_0603_50V7K
PCI1037

1
LX_VCCSA CSP_1b_VCCSA_R <45> Title

2
RF@
LG_VCCSA AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1 2 3 4 5
A
B
C
D
+VCCGT
+VCCCORE
2
1
U23E@
PC1236
5
5
22U_0603_6.3V6M
2
1
U23E@
PC1237 2 1 2 1 2 1 2 1
2
1
22U_0603_6.3V6M
@
PC1202 PC1189 PC1174 PC1137 PC1101
2
1
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
U23E@
PC1238 2 1 2 1 2 1 2 1
2
1
22U_0603_6.3V6M
@
PC1206 PC1190 PC1175 PC1138 PC1102
2
1
U23E@
PC1239 2 1 2 1 2 1 2 1
2
1
22U_0603_6.3V6M
@
PC1248 PC1191 PC1176 PC1139 PC1103
2
1
U23E@
PC1240 2 1 2 1 2 1 2 1
2
1
22U_0603_6.3V6M
@
PC1249 PC1192 PC1177 PC1140 PC1104
2
1
U23E@
PC1241 2 1 2 1 2 1 2 1
2
1
22U_0603_6.3V6M
@
PC1250 PC1193 PC1178 PC1141 PC1105
2
1
U23E@
PC1242 2 1 2 1 2 1 2 1
2
1
22U_0603_6.3V6M
@
PC1251 PC1194 PC1179 PC1142 PC1106
2
1
2.2U_0402_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
U23E@
PC1243 2 1 2 1 2 1 2 1
2
1
22U_0603_6.3V6M
@
PC1252 PC1195 PC1180 PC1143 PC1107
2
1
VCC_CORE Place on CPU Back Side @ V09
U23E@
PC1244 2 1 2 1 2 1 2 1
2
1
22U_0603_6.3V6M
@
PC1253 PC1196 PC1181 PC1144 PC1108
2
1
U23E@
PC1245 2 1 2 1 2 1
2
1
22U_0603_6.3V6M
PC1197 PC1182 PC1145 PC1109
2
1
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
U23E@
PC1246 2 1 2 1
4
4
2
1
22U_0603_6.3V6M
2 1 PC1183 PC1146 PC1110
2
1
22U_0603 * 33 pcs +1U_0201*35 pcs+2.2U_0402*3 pcs
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
@
U23E@
+VCCSA
PC1247 PC1198 2 1 2 1
22U_0603_6.3V6M PC1201 2.2U_0402_6.3V6M
22U_0603_6.3V6M PC1184 PC1147
2
1
2 1 1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 PC1111
@
PC1199 22U_0603_6.3V6M
2.2U_0402_6.3V6M PC1185 PC1148
2
1
1U_0201_6.3V6M 1U_0201_6.3V6M
2
1
2 1 2 1 2 1 PC1112
PC1203 @ 22U_0603_6.3V6M
22U_0603_6.3V6M PC1200 PC1186 PC1149
2
1
2.2U_0402_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M
2
1
PC1113
@
2 1 PC1204 22U_0603_6.3V6M
22U_0603_6.3V6M
2
1
PC1254
2
1
1U_0201_6.3V6M PC1114
@
2 1 PC1205 22U_0603_6.3V6M
22U_0603_6.3V6M
2
1
PC1255
2
1
1U_0201_6.3V6M PC1115
@
2 1 PC1150 22U_0603_6.3V6M
22U_0603_6.3V6M
2
1
PC1256
1
2
1
1U_0201_6.3V6M
PC1198 ,PC1199, PC1200
PC1116
@
2@
2 1 PC1207 PC1151 22U_0603_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
PC1257
1
2
1
1U_0201_6.3V6M PC1117
@
2@
EMI
2 1 PC1208 PC1152 22U_0603_6.3V6M

22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
PC1258
2
1
1U_0201_6.3V6M PC1118
@
2 1 PC1153 22U_0603_6.3V6M
22U_0603_6.3V6M
1
2
1
PC1259
2
1
2@
1U_0201_6.3V6M PC1209 PC1119
3
3
@
2 1 22U_0603_6.3V6M PC1154 22U_0603_6.3V6M
22U_0603_6.3V6M
1
2
1
PC1260
VCC_SA Place on CPU Back Side @ V09
2
1
2@
1U_0201_6.3V6M PC1210 PC1120
@
2 1 22U_0603_6.3V6M PC1155 22U_0603_6.3V6M
22U_0603_6.3V6M
2
1
PC1261
2
1
1U_0201_6.3V6M PC1211
@
2 1 22U_0603_6.3V6M PC1156
22U_0603_6.3V6M
2
1
PC1262
2
1
1U_0201_6.3V6M PC1212
Issued Date
@
2 1 22U_0603_6.3V6M PC1157
2 1 22U_0603_6.3V6M
PC1263
2
1
2
1
1U_0201_6.3V6M PC1213
1U_0201_6.3V6M PC1158 PC1121
22U_0603 * 9 (4 CPU back+8 outside)pcs + 1U_0201*7
2 1 22U_0603_6.3V6M 22U_0603_6.3V6M
For PI simulation
2
1
2
1
PC1214
1U_0201_6.3V6M PC1159 PC1122
2 1 22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
PC1215
1U_0201_6.3V6M PC1123
2 1 22U_0603_6.3V6M
PC1216
1U_0201_6.3V6M
2015/07/27
+VCCGT
2 1
PC1217 2 1
1U_0201_6.3V6M
2 1 PC1187
1U_0201_6.3V6M
PC1218 2 1 2 1
2
1
1U_0201_6.3V6M
2 1 PC1188 PC1160 PC1220
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
PC1219 2 1
2
2
2
1
1U_0201_6.3V6M
PC1161 PC1221
Compal Secret Data 1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
Deciphered Date
2 1
2
1
PC1124
PC1162 PC1222 22U_0603_6.3V6M
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1
2
1
PC1125
PC1163 PC1223 22U_0603_6.3V6M
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1
2
1
PC1126
PC1164 PC1224 22U_0603_6.3V6M
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1
2
1
PC1127
2016/07/27
PC1165 PC1225 22U_0603_6.3V6M

1U_0201_6.3V6M 22U_0603_6.3V6M 2 1
2 1
2
1
PC1128
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PC1166 PC1226 22U_0603_6.3V6M

1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1
C
2
1
PC1129
PC1167 PC1227 22U_0603_6.3V6M
Size
Title
Date:
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1 2 1
PC1130
PC1168 PC1228 22U_0603_6.3V6M
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1
2
1
PC1131
PC1169 PC1229 22U_0603_6.3V6M
Document Number
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2
1
2
1
PC1132
PC1170 PC1230 22U_0603_6.3V6M
Tuesday, June 28, 2016
22U_0603 * 29 pcs +1U_0201*12 pcs
22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
1
1
VCC_GT Place on CPU Back Side @ V09
2
1
2
1
PC1133
PC1171 PC1231 22U_0603_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
2
1
2
1
PC1134
PC1172 PC1232 22U_0603_6.3V6M
Sheet
22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
2
1
2
1
PC1135
47
PC1173 PC1233 22U_0603_6.3V6M

22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
of
2
1
PC1136
PC1234 22U_0603_6.3V6M
22U_0603_6.3V6M
50
2
1
PC1235
Rev
22U_0603_6.3V6M
1.0
A
B
C
D
5 4 3 2 1
VGA@ PR1403 10K_0402_1%
10K_0402_1%
VGA@ PR1402 41.2K_0402_1%
ISL62771_CZ_GFX35W_V1A.mdd for IC portion
2
ISL62771_CZ_GFX35W_V1B.mdd for SW portion
2
1
VGA@ PR1404
1
1
+5VS
+19VB_GFX VGA_EMI@ PL1401
VGA_M250=>Link +1.8VGS
D 1 2 B+ D
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
5A_Z120_25M_0805_2P
0.1U_0402_25V6K
VGA_M130=>Link +3VGS
PC1404
41
40
39
38
37
36
35
34
33
32
31
1
1
PC1405
VGA@ PC1402
PC1403
VGA@ PU1401
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
UG1_GFX
2
2
2
VR_ON
VGA@ PR1401 1100K_0402_1%
2 1 30
High > 1.6V BST2_GFX
@VGA_EMI@
NTC_NB BOOT2
VGA@
VGA_EMI@
Low < 1V VGA@ PR1405 1100K_0402_1%
2 2
IMON_NB UGATE2
29 UG2_GFX VGA@ PR1406 VGA@PC1406 VGA@
SH000010N00 (DCR:1.19mohm +/-5%)
1
2.2_0603_1% 0.22U_0603_25V7K PQ1401
3 28 LX2_GFX 1
BST1_GFX 2BST1_GFX_R 1 2 VGA@ PL1402
D1
G1
VGA@ <20> GPU_SVC SVC PHASE2 +5VS 0.22UH +-20%_35A_10X10X4
4 27 LG2_GFX
<20> GPU_PROCHOT# VR_HOT_L LGATE2
PR1407 LX1_GFX 7 LX1_GFX 1 4
VGA_M250@ PR1408
0_0402_5%
+3VS
1 2
100K_0402_1%
<20> GPU_SVD
5
SVD ISL62771HRTZ-T_TQFN40_5X5 VDDP
26 D2/S1
2 3
+VGA_CORE
1 2 VDDIO_GFX 6 25 1 PR1409 2 VGA_RF@
G2
S2
S2
S2
+1.8VGS
1
VDDIO VDD
VGA@ PC1408
PR1411 VGA@ PR1412
1U_0603_10V6K
1
7 24 LG1_GFX VGA_RF@ AON6992_DFN5X6D-8-7 4.7_1206_5% ISUMP_GFX1 2

<20> GPU_SVT
6
SVT LGATE1
1
1 2 VGA@ @VGA@ PR1413 1_0603_5% 3.65K_0603_1%
+3VGS
1 2ENABLE_GFX 8 23 LX1_GFX
<11,21,34> DGPU_PWR_EN
2
ENABLE PHASE1
VGA@ PC1407
VGA_M130@ PR1410 PC1401 VGA@ PR1414
1U_0603_10V6K
2
2
0.1U_0402_25V6K 0_0402_5% 9 22 UG1_GFX
<11> DGPU_PWROK PWROK UGATE1
LG1_GFX
0_0402_5% SNB_GFX ISEN1_GFX 1 2
1 2 IMON 10 21 BST1_GFX 10K_0402_1%
IMON BOOT1
1
+3VS
PR1415
PGOOD
133K_0402_1% VGA_RF@
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
VGA@ VGA@ PC1409 VGA@ PR1416
NTC
RTN
2
1 2 PC1410 680P_0603_50V7K ISUMN_GFX_R 1 2
FB
1
1000P_0402_50V7K 1_0402_1%
VGA@ PR1418 VGA@ PR1419
11
12
13
14
15
16
17
18
19
20
27.4K_0402_1% 20K_0402_1% @VGA@ PR1417
1 2 NTC_GFX_R 1 2 NTC_GFX 100K_0402_1%
+VGA_CORE
2
VGA@
GFX_core
ISUMN_GFX
COMP_GFX
PH1002 near APU_CORE H/S mos
ISEN2_GFX
ISEN1_GFX
PH1402
VSEN_GFX
DGPU_PWROK
FB_GFX
RTN_GFX
1 2 TDC 30(1H1L)
VRHOT Assert Threshold : 0.64V Peak Current 45A
470K_0402_5%_B25/50 4700K
C TSENSE Bias Current : 30uA C
PH1002=27.4K, 110C active ISUMN_GFX_R
VGA@ PC1411
1 2
1 1 1 OCP current > 45A
330U_D1_2VY_R9M
330U_D1_2VY_R9M
330U_D1_2VY_R9M
Reset Threshold: 0.66V, 98C active + + + Load line -2.1mV/A
VGA@ PC1414
PC1412
PC1413
.22U_0402_6.3V6K
110C Assert Threshold: PR1031=27.4K VGA@ PC1415 VGA_M250@ PC1417
FSW=400kHz
100C Assert Threshold: PR1031=16.9K 1 2 330P_0402_50V8J 2 2 2 DCR 1.19mohm +/-5%
.22U_0402_6.3V6K
TYP MAX
VGA@
VGA_M130@ PC1417
H/S Rds(on) :11.7mohm , 14mohm
VGA@
VGA@ PC1416 VGA@ PR1420 270P_0402_50V7K VGA_M250@ PR1421
1000P_0402_50V7K 301_0402_1% 73.2K_0402_1%
ISUMP_GFX 1 2 1 2 1 2 1 2 L/S Rds(on) :2.7mohm , 3.3mohm
1 2ISUMP_GFX_NTC
PR1423
11K_0402_1%
330P_0402_50V7K
@VGA@ PC1418
VGA@ PR1422
0.22U_0402_16V7K
1
2.61K_0402_1% VGA@ VGA@PR1425 VGA@ PC1419

PR1424
VGA@
VGA@ PC1421
137K_0402_1% 390P_0402_50V7K
.022U_0402_25V
1
1 2 1 2 1 2 +19VB_GFX
2
1
1
VGA@ PC1420
1.33K_0402_1%
VGA@PR1426 VGA@PC1422
10U_0805_25V6K
10U_0805_25V6K
2
VGA@ PH1401 2K_0402_1% 330P_0402_50V7K

2
PH1003 near GFX_CORE choke 1 2 1 2
1
VGA@ PC1423
10K_0402_5%_B25/50 4250K PR1058=3.65K, PR1040=2.1K and
PC1424
PR1046=604 to set loadline -2.1mV/A
2
549_0402_1% 10_0402_5%
2
ISUMN_GFX_R 1 2 1 2 UG2_GFX
+VGA_CORE
@VGA@ PR1429
1
VGA@
@VGA@PR1431 @VGA@ 0_0402_5% VGA@
VGA@ PC1425 100_0402_1% PC1426 1 2 VGA@ PR1430 VGA@PC1427
SH000010N00 (DCR:1.19mohm +/-5%)
1
0.1U_0402_25V6 1 2 1 2 GPU_VDD_SEN <20> 2.2_0603_1% 0.22U_0603_25V7K PQ1402
2
820P_0402_25V7 BST2_GFX 1 2BST2_GFX_R 1 2
D1
G1
VGA@ PL1403
PR1046 set 750 ohm to OCP 43.75A 1 2 0.22UH +-20%_35A_10X10X4
GPU_VDD_RUN_FB_L <20> 7 1 4
0.01U_0402_50V7K
PR1433 LX2_GFX LX2_GFX

VGA@ PR1444 0_0402_5% 10_0402_5% D2/S1
+VGA_CORE
1
VGA@ PC1428
100K_0402_5% PR1432 1 2 2 3
EN_1.5V 1 2 DGPU_PWR_EN @VGA@ VGA_RF@
G2
S2
S2
S2
1
2
AON6992_DFN5X6D-8-7 4.7_1206_5% ISUMP_GFX1 2
6
1
VGA@ PC1472 3.65K_0603_1%

VGA@ PR1445
B 0.22U_0402_10V6K B
2
2
1M_0402_1% VGA@ PR1436
LG2_GFX
SNB_GFX2 ISEN2_GFX 1 2
2
10K_0402_1%
1
PC1429 VGA@ PR1437
2
680P_0603_50V7K ISUMN_GFX_R 1 2
VGA_RF@ 1_0402_1%
EN pin don't floating PR1058=3.65K, PR1040=2.1K and
If have pull down resistor at HW side, pls delete PR702 PR1046=604 to set loadline -2.1mV/A
while PR1046=594 to set OCP 57.16A
for EDC 45A application.
+B_1.5V VGA_RF@ VGA_RF@ +VGA_CORE
PR1438 PC1430
4.7_1206_5% 680P_0603_50V7K
VGA_EMI@ PL1404 VGA@ 1 2 SNUB_1.5V 1 2
B+ HCB2012KF-121T50_0805
1 2 +B_1.5V 2
PU1402
IN PG
9 @VGA@ PR1439
VGA@
PC1434
(Common Part)
SH00000YE00
0_0603_5%
10U_0805_25V6K
0.1U_0402_25V6
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
3 1 BST_1.5V 1 2 BST_1.5V_R 1 2 VGA@ PL1405
2200P_0402_50V7K
1
IN BS
1
1
1
1
1
1
1
1
1
PC1432
@VGA_EMI@ PC1433
PC1435
VGA@ PC1431
PC1436
PC1444
PC1449
PC1438
PC1437
PC1439
PC1441
PC1442
PC1443
PC1440
PC1445
PC1446
PC1447
PC1448
PC1450
1UH_11A_20%_7X7X3_M
VGA_EMI@
LDO_3V_1.5V 4
IN LX
6 LX_1.5V
0.1U_0603_25V7K
1 2
+1.5VGSP
2
2
2
2
2
2
5 19
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
@VGA@ IN LX VGA@
1
1
1
VGA@
7 20
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@ PC1453
VGA@ PC1451
VGA@ PC1452
VGA@ PC1454
VGA@ PC1455
PR1440 PR1441
0_0402_5% GND LX
8 14 FB_1.5V
Rup
2
2
2
2
GND FB 30.1K_0402_1%
2
ILMT_1.5V 18 17 LDO_3V_1.5V
change PL601
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
GND VCC
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
SM01000C000 to comm EN_1.5V 11

NC
10 VGA@
1
EN
1
1
1
1
1
PC1461
PC1470
PC1457
PC1458
PC1466
PC1468
PC1469
PC1459
PC1460
PC1462
PC1464
PC1465
FB = 0.6V
PC1463
PC1467
PC1456
part SM01000P200
1
ILMT_1.5V 13 12 2.2U_0402_6.3V6M VGA@

2
ILMT NC PR1443
2
2
2
2
2
2
2
15 16
+3VALW BYP NC Rdown 20K_0402_1%
21
2
PAD
SY8286RAC_QFN20_3X3 Pin 7 BYP is for CS.
1
The current limit is set to 8A, 12A or 16A when this pin VGA@
Common NB can delete +3VALW and PC15
VGA@
VGA@
VGA@
VGA@
A A
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
PC1471
is pull low, floating or pull high 1U_0402_6.3V6K
2
Vout=0.6V* (1+Rup/Rdown)
=0.6*(1+(30.1/20))
Vout=1.503V
@ PJ1401
JUMP_43X118
1 2
+1.5VGSP 1 2 +1.5VGS
PWR-CPU_CORE/CPU_CORE_NB
Custom 1.0
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase
PC1198,PC1199,PC1200,PC1202,PC1206,PC1248
1 For PI cap un-pop PC1249,PC1250,PC1251,PC1252,PC1253,PC1254,PC1255,PC1256 2016.03.29 SIV
PC1257,PC1258, PC1259,PC1260,PC1261,PC1262,PC1263
D D
2 change PRI942 to 66.5k ohm CPU test result 2016.05.13 SIT
C C
9
10
11
12
13
14
B B
15
16
17
A A

PIR (PWR)
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z_BDW
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for HW
Item Reason for change PG# Modify List Date Phase
2
D D
C C
B B
A A

PIR (PWR)
5 4 3 2 1

Lenovo Yoga 510-14ikb Compal BIUS4S5 & CIUY0Y1 LA-E221P Rev 1.0 Схема PDF

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A B C D E

BIUS4/S5 & CIUY0/Y1

Intel KabyLake U Processor with DDR4

Security Classification Compal Secret Data Compal Electronics, Inc.

BOM Structure Table

+5VALW +1.5V +VCC_CORE For GPU M1 Chip M1@

For 2+3E power 23E@

Port USB 3.0 Port Table

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

BIVS3/ VE3 -PowerMap_SKL-U22_DDR3L_Volume_NON CS]

Security Classification Compal Secret Data Compal Electronics, Inc.

[AAX05-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]

G3->S0 S0->S3/DS3 S0/ DS3 ->S0 S0->S5

PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)

EXT_PWR_GATE# If EXT_PWR_GATE# Toffmin is too small, Pwr EXT_PWR_GATE#

Security Classification Compal Secret Data Compal Electronics, Inc.

< Compensation PU For eDP > SKL-U_BGA1356

Trace width=20 mils, Spacing=25mil, Max length=100mils

1 2 H_THERMTRIP# 1 2 H_PROCHOT#_R C65 PECI

KBL-U CPU SKL-U CPU

For EMC X4EJ BOM

DDR_VTT_CNTL to DDR +1.2V

Date: Tuesday, June 28, 2016 Sheet 7 of 50

SML0ALERT# (Internal Pull Down):

0 = LPC is selected for EC ==> Default

RPC1, RPC3 and RC30 are close to UC3

SOC_SPI_IO2 1 2 SOC_SPI_IO2_0_R RPC2

< SPI ROM - 8M >

Date: Tuesday, June 28, 2016 Sheet 8 of 50

Date: Tuesday, June 28, 2016 Sheet 9 of 50

RC39 1 2 1M_0402_5% SM_INTRUDER#

< PCH PLTRST Buffer >

RC53 1 2 60.4_0402_1% EC_VCCST_PG

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Tuesday, June 28, 2016 Sheet 10 of 50

GSPI0_MOSI (Internal Pull Down):

0 = Disable No Reboot mode. ==> Default

GSPI1_MOSI (Internal Pull Down):

Boot BIOS Strap Bit

0 = SPI Mode ==> Default

+3VS UC1F @ SKL-U

R74 1 DIS@ 2 10K_0402_5%

Date: Tuesday, June 28, 2016 Sheet 11 of 50

PCIE / USB3 / SATA SSIC / USB3

W L_OFF# RC139 1 @ 2 10K_0402_5%

Date: Tuesday, June 28, 2016 Sheet 12 of 50

Date: Tuesday, June 28, 2016 Sheet 13 of 50

+1.0V_AMPHYPLL K15 BB10 DCPRTC CC62 1 2 0.1U_0201_10V K X5R

+3VALW AD17 N20 +1.0V_CLK4_F100OC

MURATA BLM15EG221SN1D AN13

Close to AG15 Close to Y16 Close to T16 Close to AK17

Date: Tuesday, June 28, 2016 Sheet 14 of 50

+VCCCORE +VCCCORE +VCCGT +VCCGT

VSSGT_SENSE J69 AL61 VSSGTX_SENSE T162 TP@

SOC_SVID_ALERT# 1 2 (To VR) For CPU GT3 SKU

SVID DATA Place the PU

Date: Tuesday, June 28, 2016 Sheet 15 of 50

Date: Tuesday, June 28, 2016 Sheet 16 of 50

UC1S SKL-U UC1T SKL-U

E68 BB68 AW69 F6

Un-stuff 100k(RC99) for SkyLake-U

Display Port Presence Strap