Ain Shams University Total Marks: 25 Marks

Faculty of Engineering Duration: 1.5 hours

CHEP COMM Program – Fall 2014 Open-Book Exam
COMM 471: Digital Circuit Design Dr. Sameh A. Ibrahim

Make-up Mid-Term Exam

Model Answer

1. [8 M] For the resistor-load inverter shown in the

figure, VTHP = -0.5 V, µp = 400 cm2/Vs, Cox = 0.86
fF/µm2, CD = CG = CS = 10 fF/µm, λ = 0, and γ = 1.
a. Choose a value for RL such that VOH = 2.25 V.
b. What is the value of VOL?
c. Calculate tPHL and tPLH of the inverter.
d. Compare the inverter to a conventional CMOS
inverter in terms of power and noise margin.
e. Comment on the effect of the RL value on the noise
margin, delay, area and power consumption of the inverter.
Ain Shams University Total Marks: 25 Marks
Faculty of Engineering Duration: 1.5 hours
CHEP COMM Program – Fall 2014 Open-Book Exam
COMM 471: Digital Circuit Design Dr. Sameh A. Ibrahim
 Ain Shams University Total Marks: 25 Marks
Faculty of Engineering Duration: 1.5 hours
CHEP COMM Program – Fall 2014 Open-Book Exam
COMM 471: Digital Circuit Design Dr. Sameh A. Ibrahim

2. [12 M]
a. Implement the equation Y  ABC  D  E using complementary CMOS.
b. Size the devices so that the output resistance is the same as that of an inverter
with an NMOS W/L = 2 and PMOS W/L = 4.
c. Which input pattern(s) would give the worst and best equivalent pull-up or pull-
down resistance?
d. If P(A=1) = P(B=1) = P(C=1) = P(D=1) = P(E=1) = 0.5, determine the power
dissipation in the logic gate. Assume VDD=1.2 V, CL=15 fF and fclk=600 MHz.
Hint: P(L and M) = P(L).P(M) and P(L or M) = P(L)+P(M)-P(L).P(M)
e. What are the parasitic delay of the gate and the logical effort of the 5 inputs?
Ain Shams University Total Marks: 25 Marks
Faculty of Engineering Duration: 1.5 hours
CHEP COMM Program – Fall 2014 Open-Book Exam
COMM 471: Digital Circuit Design Dr. Sameh A. Ibrahim
 Ain Shams University Total Marks: 25 Marks
Faculty of Engineering Duration: 1.5 hours
CHEP COMM Program – Fall 2014 Open-Book Exam
COMM 471: Digital Circuit Design Dr. Sameh A. Ibrahim

3. [5 M] A pass-transistor network is shown.

Assume that inputs A and B are ideal voltage
sources. VDD=2.5V. VTN=-VTP=0.6V. The gate
capacitances are constant and equal to 4fF, and all
drain/source capacitances are equal to 2 fF (all
these capacitances can be considered as
capacitances to ground). The load capacitor
connected to the output is CL=10fF. The equivalent resistance of an NMOS
transistor with W/L=1 is 15kΩ, while the equivalent resistance of a PMOS with
W/L=1 equals 50 kΩ. The NMOS transistors have W/L=2 and the PMOS
transistors have W/L=4.
a. For all possible combinations of A and B find the output voltage level.
b. What is the logic function Y=f(A,B)?
c. Find the propagation delay when B=0, and A switches instantaneously from
VDD to 0.

a.
A B Y
0 0 VDD = 2.5 V
0 VDD 0
VDD 0 0
VDD VDD VDD - VTN = 1.9 V
b. Y=A XNOR B

c.