ADC AND RTC

Lecturer: Dr. Bui Ha Duc

Dept. of Mechatronics
Email: ducbh@hcmute.edu.vn

1
Outline
• ADC
• ADC process
• ADC initialization
• RTC
• Real-time clock structure
• RTC Initialization

2
3
Digital system

Interfacing a digital system to the analog world

4
ADC Process

Antialiasing
ADC
filter

Sampling Quantization

5
Aliasing

6
Nyquist – Shannon Sampling
• An analog signal can be in theory perfectly recovered as
long as the sampling rate is at least twice as large as the
highest-frequency component (Nyquist rate) of the
analog signal to be sampled.
𝑓𝑠 ≥ 2𝑓𝑚𝑎𝑥

• E.g. signal containing frequencies up to 1 Hz the

minimum sampling rate is 2 Hz ?

7
ADC Process

Antialiasing
ADC
filter

Sampling Quantization

8
Sampling
• Sampling converts a continuous variable to
discrete.
• Periodic sampling:
• for given sampling interval T
𝑥𝑛 = 𝑥 𝑛𝑇 , 𝑛 𝑖𝑠 𝑖𝑛𝑡𝑒𝑔𝑒𝑟
• Sample frequency
1
𝑓𝑠 = (𝐻𝑧)
𝑇

• The sampling process may cause aliasing or folding

distortion.

9
 SAMPLE-AND HOLD CIRCUIT

Unity-gain buffer amplifier:

makes a copy - at the output -
of the the input voltage

Capacitor charge time = tsampling

Simplified diagram of a sample-and hold circuit

10
Sampling

11
ADC Process

Antialiasing
ADC
filter

Sampling Quantization

12
Quantization
• Quantization is the process of converting analog input
amplitude to digital code.

Quantization error: Difference between the actual (analog) quantity

and the digital value assigned to it.
13
Quantization
Comparator output:
1: if VA > VAX
0: if VA < VAX

VAX = Step size x digital input

General diagram of ADC

tC = conversion time 14
Quantization
• Number of steps (quantization levels)
𝐿 = 2𝑛 (1)
n: number of bits used in ADC
• Quantization step size (Vmin; LSB)

𝑥𝑚𝑎𝑥 − 𝑥𝑚𝑖𝑛
∆= (2)
𝐿
𝑥𝑚𝑎𝑥 : maximum value of the analog input signal x
𝑥𝑚𝑖𝑛 : minimum value of the analog input signal x

15
Quantization
Example:
Assuming that a 8-bit ADC channel accepts analog input ranging from 0
to 5 volts, determine
a. the number of quantization levels?
b. the step size of the quantizer or resolution?
c. the quantization level when the analog voltage is 3.2 volts?
d. the binary code produced by the ADC?

16
HT32F5 ADC module
• 12 external analog input channels (12-bit)
• 2 internal analog input channels for reference voltage detection
• Programmable sampling time
• Up to 8 programmable conversion channel sequence
• Three conversion mode
• One shot conversion mode
• Continuous conversion mode
• Discontinuous conversion mode

• Various trigger start source for conversion modes

• Software trigger
• EXTI - external interrupt input pin
• GPTM0 / GPTM1 trigger
• BFTM0 / BFTM1 trigger
• …

17
 ADC Diagram
Trigger source

Clock source

Input
channels

Interrupt
control

18
ADC Clock
• ADC clock frequency is specified in APBCFGR register
• ADC clock is divided from AHB clock

APBCFGR

19
Input channel select
• Only 1 channel can be converted at a time
• Channels can be grouped to do conversion in sequence
• 1 group can have up to 8 channels
• Order of the sequence can be specified in the ADCLST0~ADCLST1
registers

20
ADC time
• ADC conversion time is specified by modifying the ADST[7:0] bits in
the ADCSTR register

• Total conversion time (Tconv) is:

𝑇𝑐𝑜𝑛𝑣 = 𝑇𝑠𝑎𝑚𝑝𝑙𝑖𝑛𝑔 + 𝑇𝑞𝑢𝑎𝑛𝑡𝑖𝑧𝑎𝑡𝑖𝑜𝑛
Where:
• Tsampling = 1.5 x T1 ADC clock x ADST
• Tquantization = 12.5 x T1 ADC clock

• Example:
With the ADC clock CK_ADC = 14 MHz and a sampling time =1.5 cycles:
Tconv = 1.5 + 12.5 = 14 cycles = 1 μs

21
Start ADC Conversion
• An A/D conversion can be initiated by
• software trigger
• General-Purpose Timer Module (GPTM) event,
• Motor Control Timer Module (MCTM) event,
• Basic Function Timer Module (BFTM) event
• External trigger (EXTI)
• Each trigger source can be enabled by
• setting the corresponding enable control bit in the ADCTCR register
• configuring the associated selection bits in the ADCTSR

22
Data Format
• The ADC conversion result can be read in the ADCDRy register
• ADC results is right aligned

23
ADC Registers

24
ADC Initialization
• Enable AFIO clock in APBCCR0 register
• AFIOEN – bit 14
• Enable ADC clock in APBCCR1 register
• ASCCEN – bit 24
• Specifies the APB clock prescaler for SPI in APBCFGR register
• ADCDIV – bit [18:16]

• Assign AF2 (ADC) to target pins in GPxCFGLR/GPxCFGHR registers

25
ADC Initialization
• Specifies the ADC operation in ADCCR register
• bit [18:16] – Subgroup length
• bit [10:8] – Conversion length
• bit [7] – ADCEN
• bit [1:0] – ADMODE

• Specifies the conversion sequence order in ADCLST0 and ADCLST1

registers
• Specifies ADC conversion time in ADCSTR register
• Select trigger source in ADCTCR and ADCTSR register

26
27
Real Time Clock
• 32-bit up-counter and compare register
• Programmable clock prescaler
• Division factor: 1, 2, 4, 8, …, 32768
• RTC clock source
• LSE oscillator clock
• LSI oscillator clock
• Three RTC Interrupt/wakeup
• RTC second clock interrupt/wakeup
• RTC compare match interrupt/wakeup
• RTC counter overflow interrupt/wakeup

28
Real Time Clock

29
RTC clock source
• The default RTC clock source can be derived from
• LSI oscillator (default)
• LSE

• Clock source is specified and enable in RTCCR register

• A prescaler is provided to divide the CK_RTC
• ranged from 20 to 215
• Determined by the RPRE [3:0] field

30
RTCOUT Output

31
RTC register

32