VLSI LAB Manual Digital Design Guide

S.G.
BALEKUNDRI INSTITUTE OF TECHNOLOGY

BELAGAVI
VLSI LAB MANUAL
SEMESTER: VII SUB CODE: 15ECL77
Compiled by:
1) Prof. Vinayak Honnungar
2) Prof. Mahadevappa Mugalihal
VLSI LAB Manual (PART-A) Digital Design
CONTENTS
SL.NO TITLE PAGE NO

1 Syllabus 2-3
2 Course objectives 4
3 Course outcome 5
4 Do’s and Don’ts 6
5 List of Experiments 7
6 Steps for Digital Design (Part –A) 8-13
S.G.Balekundri Institute of Technology Belagavi 1

1. SYLLABUS
Subject Code: 15ECL77 IA Marks: 20
No. of Practical Hrs. /Week: 03 Exam Hours: 03
Total no. of Practical Hrs: 42 Exam Marks: 80
---------------------------------------------------------------------------------------------------------------------
PART – A
DIGITAL DESIGN
1. Write Verilog Code for the following circuits and their Test Bench for verification, observe
the waveform and synthesize the code with the technological library, with the given
Constraints*. Do the initial timing verification with gate level simulation.
1. An inverter
2. A Buffer
3. Transmission Gate
4. Basic/universal gates
5. Flip flop - RS, D, JK, MS, T
6. Serial & Parallel adder
7. 4-bit counter [Synchronous and Asynchronous counter]
8. Successive approximation register [SAR]
* An appropriate constraint should be given
PART – B
ANALOG DESIGN
1. Design an Inverter with given specifications*, completing the design flow mentioned below:
a. Draw the schematic and verify the following: i) DC Analysis ii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design
e. Verify & Optimize for Time, Power and Area to the given constraint***
2. Design the following circuits with the given specifications*, completing the design flow
mentioned below:
a. Draw the schematic and verify the following: i) DC Analysis ii) AC Analysis
iii) Transient Analysis
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
i) A Single Stage differential amplifier

ii) Common source and Common Drain amplifier
3. Design an op-amp with the given specification* using given differential amplifier, Common
source and Common Drain amplifier in library** and completing the design flow as mentioned
below:


c. Check for LVS
4. Design a 4-bit R-2R based DAC for the given specification and completing the design flow
mentioned using given op-amp in the library**.
c. Check for LVS
5. For the SAR based ADC mentioned in the figure below, draw the mixed signal schematic and
verify the functionality by completing ASIC Design flow. [Specifications to GDS-II]
* Appropriate specification should be given.

** Applicable Library should be added & information should be given to the Designer.
*** An appropriate constraint should be given.

COURSE OBJECTIVES
 To educate students with the knowledge of Verilog HDL coding and test bench, to write
Verilog code for all logic gates, flip-flops, counters and adders etc.
 Students will be able to compile, simulate and synthesize the Verilog HDL code.
 The students will be able to draw the schematic diagram and layout for the inverter and
amplifiers and verify their functionality.

COURSE OUTCOMES
 Write Verilog Code for all the logic gate circuits and their Test Bench for verification,
observe the waveform and synthesize the code with the technological library, with the
given Constraints.
 Write Verilog Code for the SR, JK, D, T flip-flop circuits and their Test Bench for
verification, observe the waveform and synthesize the code with the technological
library, with the given Constraints
 Write Verilog Code for the counters adder circuits and their Test Bench for verification,
observe the waveform and synthesize the code with the technological library, with the
given Constraints
 Design an Inverter with given specifications, completing the design flow mentioned
below:
 Draw the schematic and verify the following: i) DC Analysis ii) Transient Analysis
 Draw the Layout and verify the DRC, ERC
 Check for LVS
 Extract RC and back annotate the same and verify the Design
 Verify & Optimize for Time, Power and Area to the given constraint
 Design the following circuits with the given specifications, completing the design flow
mentioned below:
 Draw the schematic and verify the following: i) DC Analysis ii) AC Analysis
 iii) Transient Analysis
 Draw the Layout and verify the DRC, ERC
 Check for LVS
 Extract RC and back annotate the same and verify the Design.
i. A Single Stage differential amplifier and op-amp
ii. Common source and Common Drain amplifier

DO’S AND DON’TS
DO’S
 Do log off the computer when you finish the work.
 Bring observation, manual, pen etc, with you.
 Do ask the staff for assistance if you need help.
 You should be in time in lab.
 Do keep your voice low when speaking to others in the lab.
 All users of the laboratory are to follow the directions of faculty.

 Before leaving lab, you should save your work, collect your belongings.
DON’TS
 Do not eat or drink in the laboratory
 Do not use pendrive or similar kind devices without permission.
 Do not take your baggages inside
 Do not change computer preference settings or endeavor to hack into unauthorized areas
 Do not install any programs without the faculty permission.
 Do not create any user accounts without faculty permission.
 Avoid stepping on electrical wires or any other computer cables.
 Do not touch, connect or disconnect any plug or cable without your lecturer/ laboratory
technician’s permission
 Do not misbehave in the computer laboratory.
 Don’t use chat rooms, online games or multiuser domains.

LIST OF EXPERIMENTS
EXPT.NO NAME OF THE EXPERIMENT PAGE NO
Part A: Digital Design

1 Inverter 14-15
2 Buffer 16-17
3 Transmission Gate 18-19
a. Basic gates 20-22
4
b. Universal gates 23-24
a)D-Flip Flop 25-27

b) SR Flip Flop 28-30
5 c) JK Flip Flop 31-33
d) T Flip Flop 34-36
e) MS Flip Flop 37-38
6 a. Parallel adder 39-44
b. Serial Adder 45-48
7 4-bit Counters a) Asynchronous counter 49-50
b) synchronous counter 51-53

STEPS FOR DIGITAL DESIGN (PART A)
STEPS FOR SIMULATION:
 Create a folder (ex: 2buxxecxxxpa) in Students home folder which is there on the
desktop.
 Create one more folder (Inverter) in the folder 2buxxecxxxpa.
 Right click on desktop → open terminal (terminal/ command window appears)
# csh /*configure shell

# source˽hep1.cshrc /* hep → higher education program
(MENTOR TOOL ENVIRONMENT)

-----------------------------------------------
-----------------------------------------------
-----------------------------------------------
$ qhsim /* Questa simulator*/

(Questa simulator window appears as shown in fig1)
(Close the dialogue box and click YES for close project)

Fig.1. Questa simulator window

 Go to File→New→Project
(Create project window appears as shown in fig.2)
Fig.2. Create project window

 Give project name…….Ex: inverter
 Browse the project location (Ex: /home/student/2buxxecxxxpa/inverter)
 Click OK
The following window appears automatically

 Click on create new file
 Give file name for main program (ex: invm) →choose file type as Verilog→click OK.
 Again click on create new file→ give file name for testbench program(ex: inv_tb)
→choose file type as Verilog→click OK →click close.
 Double click on main program file Ex: invm.v (we get space on right side of the
screen for the program).
 Type the program →save the program. (All keywords will be in red color).
 Similarly double click on the testbench file Ex: inv_tb → write the testbench
program → save.
 Go to compile→ compile all. Then we get × mark if there is any syntax error in the
program. Else we get mark.

 Go to simulate →start simulation (start simulation window appears).

 Click on + sign (work directory) and choose (always) testbench file Ex: inv_tb
→click OK.
 Right click on test bench file(highlighted) Ex: inv_tb → click on Add Wave
(wave window appears).
 Click on Run icon or press F9 key. (will get simulation results zoom it out →
check the output )→ Save the waveform (press PrtScr button and choose the desired
location to save the screenshot)

 close the wave window.

 Go to simulate→ End simulation.
 Close all windows (except terminal window).
 In terminal window type the command : exit
 Close the terminal window.
STEPS FOR SYNTHESIS:
 Right click on desktop → open terminal (terminal window appears).

Type the following commands in the terminal window.
# csh /* configure shell
# source˽hep2.cshrc /* hep higher education program
(MENTOR TOOL ENVIRONMENT)

-----------------------------------------------
-----------------------------------------------
-----------------------------------------------
[ ]$ spectrum
----------------------------------------------
----------------------------------------------
----------------------------------------------

leonardo{1}: load_library˽ /home /student/PDK/leonardo/tsmc025_typ.syn (to get

the underlined address path, go to file browser icon →PDK→leonardo, copy this path
and paste it in the terminal window and then type /tsmc025_typ.syn).
-------------------------------------------
-------------------------------------------
Load library finished successfully.
leonardo{2}: set˽input2output˽10
-----------------------------------------------
----------------------------------------------------
Setting input to output 10
leonardo{3}:read˽-format˽verilog˽ /home/student/2buxxecxxxpa/inverter/invm.v
(go to file browser and copy the underlined address path and paste it and then type
/invm.v i.e file name of the main program).
--------------------------------------------------
--------------------------------------------------
Command read finished successfully.

leonardo{4}: elaborate
-------------------------------elaboration finished successfully.
leonardo{5}:optimize
----------------------------optimization finished successfully.
leonardo{6}:report_area
----------------------- (note down the area details).
leonardo{7}: report_delay
---------------------( note down the delay details).
leonardo{8}: write˽-format˽verilog˽ /home/student/2buxxecxxxpa/inverter/inv_syn.v
(just paste the address path that copied while executing read command and then type
/inv_syn.v)
[ ] $ exit
******************************************************************************

Experiment No: 01
INVERTER
AIM:
To write Verilog code for an inverter circuit and its test bench for verification, observe the
waveform and synthesize the code.
TOOL REQUIRED:
Mentor Graphics Tool
THEORY:
Truth Table
The NOT gate or an inverter is an electronic circuit that produces an inverted version of the input
at its output. It is also known as an inverter. If the input variable is A, the inverted output is
known as NOT A. This is also shown as A', or A with a bar over the top, as shown at the outputs.
The diagrams below show two ways that the NAND logic gate can be configured to produce a
NOT gate. It can also be done using NOR logic gates in the same way.
Waveform:
PROGRAM:
module inv (a,b);

input a;
output b;
reg b;
always @(a)
begin
if(a)
b=1’b0;
else
b=1’b1;
end
endmodule

TEST BENCH:
module inv_tb;
reg a;
wire b;
inv dut (a, b);
initial
a=1’b0;
always #5 a=~a;
endmodule
SIMULATION RESULTS:
RESULT: Verilog code for the inverter circuit and its test bench for verification is written, the
waveform is observed and the code is synthesized with the technological library and is verified.

Experiment No: 02
BUFFER
AIM: To write Verilog code for a buffer circuit and its test bench for verification, observe the
waveform and synthesize the code with technological library with given Constraints.
TOOL REQUIRED: Mentor Graphics Tool
THEORY:
Logic Diagram
Truth Table
A B
0 0
1 1
A special logic gate called a buffer is manufactured to perform the same function as two
inverters. Its symbol is simply a triangle, with no inverting “bubble” on the output terminal.
Buffer gates merely serve the purpose of signal amplification: taking a “weak” signal source that
isn’t capable of sourcing or sinking much current, and boosting the current capacity of the signal
so as to be able to drive a load.
PROGRAM:
module buffer (a,b);

input a;
output b;
reg b;
always @(a)
begin
if(a)
b=1’b1;
else
b=1’b0;
end
endmodule

TEST BENCH:
module buffer_tb;
reg a;
wire b;
buffer dut (a, b);
initial
a=1’b0;
always #5 a=~a;
endmodule
SIMULATION RESULTS:
RESULT: Verilog code for the buffer circuit and its test bench for verification are written, the

Experiment No: 03
TRANSMISSION GATE
AIM: To write verilog code for an Transmission Gate circuit and its test bench for verification,
observe the waveform and synthesize the code with technological library with given Constraints.
THEORY: A transmission gate, or analog switch, is defined as an electronic element that will
selectively block or pass a signal level from the input to the output.
Basic Operation: This solid-state switch is comprised of a pMOS transistor and nMOS
transistor. The control gates are biased in a complementary manner so that both transistors are
either on or off. When the voltage on node A is a Logic 1, the complementary Logic 0 is applied
to node active-low A, allowing both transistors to conduct and pass the signal at IN to OUT.
When the voltage on node active-low A is a Logic 0, the complementary Logic 1 is applied to
node A, turning both transistors off and forcing a high-impedance condition on both the IN and
OUT nodes. This high-impedance condition represents the third "state" (high, low, or high-Z)
that the channel may reflect downstream. The schematic diagram (Figure 1) includes the
arbitrary labels for IN and OUT, as the circuit will operate in an identical manner if those labels
were reversed. This design provides true bidirectional connectivity without degradation of the
input signal.
Fig1: Schematic representation of a transmission gate
Truth Table:
Control IN OUT
0 X 0
1 0 0
1 1 1

PROGRAM:
Module transgate (in, control, out);

input in, control;
output out;
reg out;
always @(in)
begin
if(control)
out=in;
else
out=1’b0;
end
endmodule
TEST BENCH:
module transgate_tb;
reg in,control;
wire out;
transgate dut (in, control, out);
initial
begin
in=1’b1;
control=1’b1;
end
always #5 in=~in;
always #20 control=~control;
endmodule
SIMULATION RESULTS:
RESULT: Verilog code for the transmission gate circuit and its test bench for verification is
written, the waveform is observed and the code is synthesized with the technological library and
is verified.

Experiment No: 4.a
BASICS GATES
AIM: To write verilog code for a basic Gate circuit and its test bench for verification, observe
the waveform and synthesize the code with technological library with given Constraints.
THEORY: Digital systems are said to be constructed by using logic gates. These gates are the
AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates. The basic operations are described
below with the aid of truth tables.
NOT gate
The NOT gate is an electronic circuit that produces an inverted version of the input at its output.
It is also known as an inverter. If the input variable is A, the inverted output is known as NOT
A. This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams
below show two ways that the NAND logic gate can be configured to produce a NOT gate. It can
also be done using NOR logic gates in the same way.
AND gate:
The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high.
A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes
omitted i.e. AB
OR gate

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are
high. A plus (+) is used to show the OR operation.
EXOR gate
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its
two inputs are high. An encircled plus sign is used to show the EXOR operation.
EXNOR gate
The 'Exclusive-NOR' gate circuit does the opposite to the EXOR gate. It will give a low output if
either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle
on the output. The small circle represents inversion.
TRUTH TABLE:
INPUT NOT AND OR EXOR EXNOR

A B c= ~a d=a&b e=a|b f=a^b g=~(a^b)
0 0 1 0 0 0 1
0 1 1 0 1 1 0
1 0 0 0 1 1 0
1 1 0 1 1 0 1
PROGRAM:
module basicgates(a,b,c,d,e,f,g);
input a, b;
output c, d, e, f, g;
assign c=~a;
assign d=a&b;
assign e=a|b;
assign f= a^b;

assign g=~(a^b);
endmodule
TESTBENCH:
module basicgates_tb;
reg a,b;
wire c,d,e,f,g;
basicgates dut(a,b,c,d,e,f,g);
initial
begin
a=1’b0; b=1’b0;
#10 a=1’b0; b=1’b1;
#10 a=1’b1; b=1’b0;
#10 a=1’b1; b=1’b1;
end
endmodule
SIMULATION RESULTS:
RESULT: Verilog code for the basic gates circuit and its test bench for verification is written,
the waveform is observed and the code is synthesized with the technological library and is
verified.

Experiment No: 4.b
UNIVERSAL GATES
AIM: To write verilog code for an universal Gate circuit and its test bench for verification,
THEORY:
NAND gate
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs
of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small
circle on the output. The small circle represents inversion.
NOR gate
This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all
NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on
the output. The small circle represents inversion.
TRUTH TABLE:
INPUT NAND NOR

A B c= ~(a&b) d=~(a|b)
0 0 1 1
0 1 1 0
1 0 1 0
1 1 0 0
PROGRAM:
module unigates(a,b,c,d);
input a, b;

output c, d;
assign c=~(a&b);
assign d=~( a|b);
endmodule
TESTBENCH:
module unigates_tb;
reg a,b;
wire c,d;
unigates dut(a,b,c,d);
initial
begin
a=1’b0; b=1’b0;
#10 a=1’b0; b=1’b1;
#10 a=1’b1; b=1’b0;
#10 a=1’b1; b=1’b1;
end
endmodule
SIMULATION RESULTS:
RESULT: Verilog code for the universal gates circuit and its test bench for verification is
is verified.

Experiment No: 05a
D-FLIP FLOP
AIM : To write verilog code for an D flip flop circuit and its test bench for verification, observe
THEORY:
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to
store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change
state by signals applied to one or more control inputs and will have one or two outputs. It is the
basic storage element in sequential logic. Flip-flops and latches are fundamental building blocks
of digital electronics systems used in computers, communications, and many other types of
systems. Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit
(binary digit) of data; one of its two states represents a "one" and the other represents a "zero".
Such data storage can be used for storage of state, and such a circuit is described as sequential
logic.
The D ﬂip-ﬂop is widely used. It is also known as a "data" or "delay" flip-flop. The D
flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the
rising edge of the clock). That captured value becomes the Q output. At other times, the output Q
does not change. The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay
line.
Truth Table
reset clock d q qb
0 ꜛ 1 1 0
0 ꜛ 0 0 1
0 0 X X Hold
1 ꜛ X 0 1
('X' denotes a Don't care condition, meaning the signal is irrelevant & ‘Hold’ means
output follows the previous state).

PROGRAM :
module d_ff(d,clk,rst,q,qb);
input d,clk,rst;
output q,qb;
reg q;
wire qb;
always @ (posedge clk)
begin
if(rst)
q<=1’b0;
else
q<=d;
end
assign qb=~q;
endmodule
TEST BENCH :
module d_ff_tb;
reg d,clk,rst;
wire q,qb;
d_ff dut(d,clk,rst,q,qb);
initial
begin clk=1’b1;
rst= 1’b0;
d=1’b1;
end
always #5 clk=~clk;
always #40 rst= ~rst;

always #10 d=~d;

endmodule
SIMULATION RESULTS:
RESULT: Verilog code for the D flip-flop circuit and its test bench for verification is written,
verified.

Experiment No: 5b
SR FLIP FLOP
AIM : To write verilog code for an SR flip flop circuit and its test bench for verification, observe
THEORY:
Circuit Diagram:
Truth Table
Clk R S Q Qb comments
ꜛ 0 0 Hold No change
ꜛ 0 1 1 0 set
ꜛ 1 0 0 1 reset
ꜛ 1 1 z z indeterminate
0 x x Hold No change
Logic symbol:
Operation
S.N. Condition Operation
1 S = R = 0 : No change If S = R = 0 then output of NAND gates 3 and 4 are forced to become 1.
Hence R' and S' both will be equal to 1. Since S' and R' are the input of
the basic S-R latch using NAND gates, there will be no change in the
state of outputs.

2 S = 0, R = 1, clk = 1 Since S = 0, output of NAND-3 i.e. R' = 1 and clk = 1 the output of
NAND-4 i.e. S' = 0.
Hence Q =0 and Qbar = 1. This is reset condition.
3 S = 1, R = 0, clk = 1 Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1.
Hence output of S-R NAND latch is Q = 1 and Qbar = 0. This is the set
condition.
4 S = 1, R = 1, clk = 1 As S = 1, R = 1 and clk = 1, the output of NAND gates 3 and 4 both are
0 i.e. S' = R' = 0. Hence the Race condition will occur in the basic
NAND latch.
5 S=x, R=x, clk=0 If clk=0 then output of NAND gates 3 and 4 are forced to become 1.
Hence R' and S' both will be equal to 1. Since S' and R' are the input of
the basic S-R latch using NAND gates, there will be no change in the
state of outputs.
PROGRAM:
module rs_ff(rs,clk,q,qb);
input [1:0] rs;
input clk;
output q,qb;
reg q ,qb;
begin
case(rs)
2’b00: q=q;
2’b01: q=1’b1;
2’b10: q=1’b0;
2’b11: q=1’bz;
endcase
qb=~q;
end
endmodule
TESTBENCH:
module rs_ff_tb;
reg [1:0] rs;
reg clk;
wire q,qb;

rs_ff dut( rs,clk,q,qb);

initial
clk=1’b1;
always #5 clk=~clk;
initial
begin
rs=2’b01;
#20 rs=2’b00;
#20 rs=2’b10;
#20 rs=2’b11;
end
endmodule
SIMULATION RESULTS:
RESULT:
Verilog code for the SR flip-flop circuit and its test bench for verification is written, the waveform is
observed and the code is synthesized with the technological library and is verified.

Experiment No: 5c
JK FLIP FLOP
AIM : To write verilog code for an JK flip flop circuit and its test bench for verification,
TOOL REQUIRED : Mentor Graphics Tool
THEORY:
logic symbol Circuit Diagram

Truth Table:
Clk J K Q Qb Comments
ꜛ 0 0 Hold No change
Same as for SR ꜛ 0 1 0 1 Reset Q>>0
latch ꜛ 1 0 1 0 Set Q>>1
Toggle action 1 1 0 1 Toggle
ꜛ 1 0
The JK flip-flop is basically an SR flip flop with feedback which enables only one of its two
input terminals, either SET or RESET to be active at any one time thereby eliminating the
invalid condition seen previously in the SR flip flop circuit. Also when both the J and the K
inputs are at logic level “1” at the same time, and the clock input is pulsed either “HIGH”, the
circuit will “toggle” from its SET state to a RESET state, or visa-versa. This results in the JK flip
flop acting more like a T-type toggle flip-flop when both terminals are “HIGH”.
Although this circuit is an improvement on the clocked SR flip-flop it still suffers from timing
problems called “race” if the output Q changes state before the timing pulse of the clock input
has time to go “OFF”. To avoid this the timing pulse period ( T ) must be kept as short as
possible (high frequency). As this is sometimes not possible with modern TTL IC’s the much
improved MasterSlave JK Flip-flop was developed.

PROGRAM :
module jkff (jk,clk,q,qb);
input [1:0] jk;
input clk;
output q,qb;
reg q,qb;
begin
case(jk)
2’b00: q=q;
2’b01: q=1’b0;
2’b10: q=1’b1;
2’b11: q=~q;
endcase
qb=~q;
end
endmodule
TEST BENCH:
module jkff_tb;
reg [1:0] jk;
reg clk;
wire q,qb;
jkff dut(jk, clk, q.qb);
initial
clk=1’b1;
always #5 clk=~clk;
initial
begin

jk=2’b01;
#20 jk=2’b10;
#20 jk=2’b11;
#20 jk=2’b00;
end
endmodule
SIMULATION RESULTS:
RESULT: Verilog code for the JK flip-flop circuit and its test bench for verification is written,
verified.

Experiment No: 5d
T FLIP FLOP
AIM : To write verilog code for an T flip flop circuit and its test bench for verification, observe
THEORY:
Truth Table
Reset Clock T Qn-1 Q Qb

0 ꜛ 0 0 0 1
0 ꜛ 0 1 1 0
0 ꜛ 1 0 1 0
0 ꜛ 1 1 0 1
Logic symbol 1 ꜛ x x 0 1
If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is
strobed. If the T input is low, the flip-flop holds the previous value. This behavior is described by
the truth table.
When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock
frequency is 4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This
"divide by" feature has application in various types of digital counters. A T flip-flop can also be
built using a JK flip-flop (J & K pins are connected together and act as T) or a D flip-flop (T
input XOR Qprevious drives the D input).
PROGRAM :
module tff (T,clk,rst,q,qb);
input T,clk,rst;
output q,qb;
reg q;
wire qb;

begin
if(rst)
q<=1’b0;
else if(T)

q<=~q;
else
q<=q;
end
assign qb=~q;
endmodule
TEST BENCH :
module tff_tb;
reg clk,rst, T;
wire q,qb;
tff dut (rst,clk, T,q,qb);
initial
begin
clock=1’b1;
rst=1’b0;
T=1’b0;
end
always #5 clk=~clk;
always #40 rst=~rst;
always #10 T=~T;
endmodule

SIMULATION RESULTS:
RESULT: Verilog code for the T flip-flop circuit and its test bench for verification is written,
verified.

Experiment No: 5e
Master slave Flip-Flop (using D flip-flop)
AIM : To write verilog code for an Master Slave flip flop circuit and its test bench for
verification, observe the waveform and synthesize the code with technological library with given
Constraints.
THEORY:
THEORY:
The master slave flip-flop contains two clocked D -flipflops.The first is called master and the
second is called slave. When the clock is high the master is active. The D flip flop takes only a
single input, the D (data) input. When the clock is high, the D input is stored in the first latch, but
the second latch cannot change state. When the clock is low, the first latch's output is stored in
the second latch, but the first latch cannot change state. The result is that output can only change
state when the clock makes a transition from high to low. (The output of a master slave flip-flop
is available at the end of a clock pulse.
PROGRAM :
(i) D-Flip Flop:
module d_ff(reset,clock,d,q,qb);
input reset,clock,d;
output q,qb;
reg q;
wire qb;
always@(posedge clock)
begin
if(reset)
q<=1'b0;
else
q<=d;
end
assign qb=~q;
endmodule

(ii) Master Slave Flip Flop:
module ms_ff(reset,clock,d,q,qb);
input reset,clock,d;
output q,qb;
wire q,qb;
wire w1,w2;
d_ff master(.reset,clock,d,w1, w2);
d_ff slave( reset,(~clock),w1,q,qb);
endmodule
TESTBENCH:
module ms_ff_tb;
reg clock,reset,d;
wire q,qb;
ms_ff dut(reset,clock,d,q,qb);
initial
begin
clock=1'b1;
reset=1'b0;
d=1'b0;
end
always #5 clock=~clock;
always #40 reset=~reset;
always #10 d=~d;
endmodule
SIMULATION RESULTS:
RESULT: Verilog code for the Master Slave flip-flop circuit and its test bench for verification is
is verified.

Experiment No: 6a
PARALLEL ADDER (Ripple Carry Adder)
AIM: To write verilog code for parallel adder circuit and its test bench for verification, observe
THEORY: Addition is a fundamental operation for any digital system, digital signal processing
or control system. A fast and accurate operation of a digital system is greatly influenced by the
performance of the resident adders. Adders are also very important component in digital systems
because of their extensive use in other basic digital operations such as subtraction, multiplication
and division. Parallel adder is a combinatorial circuit (not clocked, does not have any memory
and feedback) adding every bit position of the operands in the same time. Thus it is requiring
number of bit-adders(full adders + 1 half adder) equal to the number of bits to be added. The
Parallel adder is constructed by cascading full adders (FA) blocks in series. One full adder is
responsible for the addition of two binary digits at any stage of the ripple carry. The carryout of
one stage is fed directly to the carry-in of the next stage.
Block Diagram of Parallel adder

PROGRAM:
module fa(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
assign s=a^b^cin;
assign cout=(a&b)|(b&cin)|(cin&a);
endmodule
module pa(a,b,cin,s,cout);
input [3:0]a,b;
input cin;

output [3:0]s;
output cout;
wire [3:1]w;
fa fa0(a[0],b[0],cin,s[0],w[1]);
fa fa1(a[1],b[1],w[1],s[1],w[2]);
fa fa2(a[2],b[2],w[2],s[2],w[3]);
fa fa3(a[3],b[3],w[3],s[3],cout);
endmodule
TESTBENCH:
module pa_tb;
reg [3:0]a,b;
reg cin;
wire[3:0]s;
wire cout;
pa dut(a,b,cin,s,cout);
initial
begin
a=4'b0111 ; b=4'b0100 ; cin=1'b0;
#10a=4'b1011 ; b=4'b0110 ; cin=1'b1;
end
endmodule
SIMULATION RESULTS:
RESULT: Verilog code for the parallel adder circuit and its test bench for verification is written,
verified.

PARALLEL ADDER ( Carry Look Ahead Adder)

AIM : To write verilog code for carry look ahead adder circuit and its test bench for
verification, observe the waveform and synthesize the code with technological library with given
Constraints.
THEORY:
Block diagram of Carry Look Ahead adder

Carry Look Ahead Adder (CLA Adder) (also known as Carry Look Ahead Generator) is one of
the digital circuits used to implement addition of binary numbers. It is an improvement over
'Ripple carry adder' circuit. In Ripple Carry adders, carry propagation time is the major speed
limiting factor as it works on the basic mechanism to generate carries as we generally do while
adding two numbers using pen and paper. A ripple carry adder may be supposed to be built of a
series of 1-bit adders (generally known as a full adder in digital electronics). Thus, the speed of
ripple carry adder is a direct function of number of bits. On the other hand, Carry Look Ahead
adder solves this problem by calculating carry signals in advance based upon input bits and does
not wait for the input signal to propagate through different adder stages. Hence, it implements
the adder with reduced delay at the cost of more area (as large combinational logic is required to
calculate the look ahead carry as compared to propagated carry).
Shown below is the truth table for a full adder (carry look ahead adder). Ai and Bi are two input
bits and Ci is the carry input from the previous stage. Si (Sum) and Ci+1 (Carry out for the next
stage) are the outputs for the next stage of the adder. As is evident, carry signal is generated if at
least two inputs of full adder are 1 i.e.
 When both bits Ai and Bi is 1 (regardless of Cin) OR

 When one of the two inputs (Ai or Bi) is 1 and carry-in (carry of previous stage) is 1.
The outputs of this full adder, when expressed in the form of a boolean expression can be written
as a function of inputs as follows:
Si = Ai^ Bi^ Ci
Ci+1 = Ci(Ai ^ Bi) + AiBi OR
Ci+1 = Ai&Bi+Bi&Ci+ Ci& Ai
Where Si is the sum bit calculated for nth adder stage and Ci+1 is the carry out from nth stage and
will act as input for n+1th stage. For an N stage ripple carry adder, there is overhead of
calculating the carry out of kth stage before carry out of k+1th stage can be calculated. If we go
deeper into analysis, it comes out that ck+1 is a function of c0 and is discussed below. Let the
intermediate outputs from a full adder stage be represented as Pi and Gi given as below:
Pi = Ai xor Bi
Gi = Ai.Bi
Si = Pi xor Ci
Ci+1 = Ci.Pi + Gi
 Gi is known as carry generate signal since carry (Ci+1)is generated whenever Gi= 1
regardless of Ci

 Pi is known as carry propagate signal since whenever Pi = 1, Ci+1 = Ci (when Pi=1, Gi =

0)
Thus, recursively replacing the values for Ci for each Ck, we can write the boolean expression of
carry outputs of various stages in terms of C0 and Pk's as follows:
C1 = C0P0 + G0,
C2 = C1P1 + G1 = (C0P0+G0)P1 + G1 = C0P0P1 + P1G0 + G1,
C3 = C2P2 + G2 = (C0P0P1 + P1G0 + G1)P2+G2 = C0P0P1P2 + P2P1G0 + P2G1 + G2,
C4 = C3P3 + G3 = (C0P0P1P2 + P2P1G0 + P2G1 + G2)P3 + G3 = C0P0P1P2P3 +
P3P2P1G0 + P3P2G1 + G2P3 + G3
Thus,
Ci = F(P,G,C0)
In other words, carry signal is a direct SOP (Sum of Products) expression of C0 (usually 0) and
input signals rather than its preceding carry signal. Let us illustrate taking a 4-bit adder as an
example. This expression can be used to construct a carry look-ahead adder of any number of
bits.
A 4 bit Carry Look Ahead (CLA) adder can be constructed with the help of following steps
(Assuming T as the delay of a single 2-Input gate):
1. Generate All P and G internal signals. These can be generated simultaneously as C0 and
all inputs are available.
2. Generate all carry output signals (C1, C2, C3, C4). These will be valid after 3T time
3. Generate Sum signals S = P xor C. It will be valid after 4T time.
Thus, Sum signals will be valid after a delay of 4T. On the other hand, delay expression in case
of ripple carry adder = (2n+2)T. Thus, for n =4, i.e. for 4 bit ripple carry adder, delay will be
10T.
For higher order addition, boolean expression of carry output becomes more complex. So, there
is tradeoff between area and speed. For larger number of bits, increase in area is more than speed
advantage obtained. Hence, Carry Look Ahead adders are usually implemented as 4-bit modules
that are used to build larger size adders.
PROGRAM:
module cla(x,y,cin,s,c);
input [2:0]x,y;
input cin;
output [2:0]s;
output c;
wire c0,c1;
wire [2:0]p,g;
assign g[0]=x[0]&y[0];

assign p[0]=x[0]|y[0];
assign c0=g[0]|(p[0]&cin);
assign c1=g[1]|(p[1]&g[0])|(p[1]&p[0]&cin);
assign c=(g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&cin));
assign s[0]=x[0]^y[0]^cin;
endmodule
TESTBENCH:
module cla_tb;
reg [2:0]x,y;
reg cin;
wire [2:0]s;
wire c;
cla dut(x,y,cin,s,c);
initial
begin
x=3'b111 ; y=3'b100 ; cin=3'b0;
#10x=3'b101 ; y=3'b110 ; cin=1'b1;
end
endmodule
SIMULATION RESULTS:
RESULT: Verilog code for the Carry look ahead adder circuit and its test bench for verification
is written, the waveform is observed and the code is synthesized with the technological library
and is verified.

Experiment No. 6.b

SERIAL ADDER
AIM: To write verilog code for serial adder circuit and its test bench for verification, observe
Block diagram of Serial adder

THEORY:
Serial adder is implemented using a 1 bit full adder. In this adder, there is a serial
computation of inputs i.e. only single least significant bit (LSB) is taken as input to the 1 bit full
adder along with the carry bit of previous computation and sum and carry out ( Cout) is obtained
for that bit position. Similarly the same process is carried out by shifting the input bits towards
right and then all the 8-bits of both the input signals are computed along with all the carry outs
generated and the sum is stored.
Program for Shift Register
module shift_reg(data,load,E,w,clock,q);
parameter n=8;
input [n-1:0] data;
input load,E,w,clock;
output [n-1:0] q;
reg [n-1:0] q;
integer k;

always @(posedge clock)

if (load)
q <= data;
else if (E)
begin
for (k=n-1;k>0;k=k-1)
q[k-1] <= q[k];
q[n-1] <= w;
end
endmodule
Program for Serial Adder [8 bit]
module serial_adder ( A, B, reset, clock, sum, cout);
input [7:0] A, B;
input reset, clock;
output [7:0] sum;
output cout;
reg [3:0] count;
reg s,y,Y;
wire [7:0] qa, qb, sum;
wire run;
parameter G=0, H=1;

shift_reg shift_A (.data(A), .load(reset), .E(1'b1), .w(1'b0), .clock(clock), .q( qa));
shift_reg shift_B (.data(B), .load(reset), .E(1'b1), .w(1'b0), .clock(clock), .q( qb));
shift_reg shift_sum (.data(8'd0), .load(reset), .E( run),.w(s), .clock)clock),.q( sum));
//adder fsm
//output and next state combinational circuit
always @(qa or qb or y)
case (y)
G: begin
s = qa[0]^qb[0];
if (qa[0] & qb[0])

Y = H;
else
Y = G;
end
H: begin
s = qa[0] ~^qb[0];
if (~qa[0] & ~qb[0])
Y =G;
else
Y = H;
end
default : Y = G;
endcase
//sequential block
if (reset)
y <= G;
else
y <= Y;
assign cout=y;
//control the shifting process
if (reset)
count = 8;
else if (run) count = count - 1;
assign run=|count;
Test Bench
module serial_adder_tb ;
reg [7:0] A,B;
reg reset,clock;
wire [7:0] sum ;

serial_adder s1 (A, B, reset, clock, sum);

initial
clock = 1'b1;
always #5 clock =~clock;
initial
begin
reset = 1'b0;A = 8'b10101010; B = 8'b11111111;
#20 reset = 1'b1;
#20 reset = 1'b0;
#80 $finish;
end
endmodule
SIMULATION RESULTS:
RESULT: Verilog code for the serial adder circuit and its test bench for verification is written,
verified.

Experiment No: 7a
SYNCHRONOUS COUNTER (4 BIT UP/DOWN COUNTER)
AIM : To write verilog code for synchronous counter circuit and its test bench for verification,
TOOL REQUIRED : Mentor Graphics Tool
THEORY: A synchronous counter, in contrast to an asynchronous counter, is the one whose
output bits change state simultaneously, with no ripple.
UP DOWN COMMENTS
0 0 COUNT
0 1 COUNT=COUNT-1
1 0 COUNT=COUNT+1
1 1 COUNT
PROGRAM:
module sync(clk,reset,up,down,count);
input clk,reset,up,down;
output [3:0]count;

reg [3:0]count;
always@(posedge clk)
begin
if(reset)
count=4'b0000;
else if(up&&~down)
count=count+1'b1;
else if(down&&~up)
count=count-1'b1;
else
count=count;
end
endmodule
TESTBENCH:
module sync_tb;
reg clk,reset,up,down;
wire [3:0]count;
sync dut (clk,reset,up,down,count);
initial
clk=1'b1;
always #5 clk=~clk;
initial
begin
reset=1'b1;up=1'b0;down=1'b1;
#10 reset=1'b0; up=1'b1;down=1'b0;
#150 up=1'b0;down=1'b1;
#310 up=1'b1;down=1'b1;
end
endmodule
SIMULATION RESULTS:
RESULT: Verilog code for synchronous counter and its test bench for verification is written, the

Experiment No: 7b
ASYNCHRONOUS COUNTER (4 BIT UP COUNTER)
AIM: To write verilog code for asynchronous counter circuit and its test bench for verification,
THEORY: A ripple counter is an asynchronous counter where only the first flip-flop is clocked
by an external clock (because all the flip-flops are not hooked to a same clock). All subsequent
flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also
called ripple-counters because of the way the clock pulse ripples through the flip-flops.
Four T flip-flops connected in such a way to always are in the “toggle” mode and we need to
determine how to connect the clock inputs in such a way so that each succeeding bit toggles
when the bit before it transitions from 1 to 0. The Q outputs of each flip-flop will serve as the
respective binary bits of the final, four-bit count.
PROGRAM:
(i) T_Flip Flop
module t_ff (clock, reset, T, q);
input clock, reset, T;
output q;
reg q;
always @ (posedge clock)
begin
if(reset)
q<=1'b0;
else if (T)
q<=~q;
else
q<=q;
end
endmodule

(ii) 4bit-counter
module asyn_counter (clock, reset, count);
input clock, reset;
output [3:0] count;

t_ff T1(.clock(clock), .reset(reset),.T(1'b1),.q( count[0]));
t_ff T2(.clock(~count[0]), .reset(reset),.T(1'b1),.q( count[1]));
endmodule
TESTBENCH:
module asyn_counter_tb;
reg clock, reset;
wire [3:0] count;
asyn_counter uut(clock, reset, count);

initial
clock=1'b0;
always #5 clock=~clock;
initial
begin
#5 reset=1'b1;
#10 reset=1'b0;
end
endmodule

SIMULATION RESULTS:
RESULT: Verilog code for asynchronous counter and its test bench for verification is written,
verified.
******************************************************************************

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S.G.

BALEKUNDRI INSTITUTE OF TECHNOLOGY

VLSI LAB MANUAL

SEMESTER: VII SUB CODE: 15ECL77

SL.NO TITLE PAGE NO

S.G.Balekundri Institute of Technology Belagavi 1

* An appropriate constraint should be given

i) A Single Stage differential amplifier

S.G.Balekundri Institute of Technology Belagavi 2

iii) Transient Analysis

* Appropriate specification should be given.

S.G.Balekundri Institute of Technology Belagavi 3

S.G.Balekundri Institute of Technology Belagavi 4

S.G.Balekundri Institute of Technology Belagavi 5

DO’S AND DON’TS

 All users of the laboratory are to follow the directions of faculty.

S.G.Balekundri Institute of Technology Belagavi 6

EXPT.NO NAME OF THE EXPERIMENT PAGE NO

Part A: Digital Design

a)D-Flip Flop 25-27

S.G.Balekundri Institute of Technology Belagavi 7

STEPS FOR DIGITAL DESIGN (PART A)

STEPS FOR SIMULATION:

# csh /*configure shell

(MENTOR TOOL ENVIRONMENT)

$ qhsim /* Questa simulator*/

S.G.Balekundri Institute of Technology Belagavi 8

Fig.1. Questa simulator window

Fig.2. Create project window

S.G.Balekundri Institute of Technology Belagavi 9

 Click on create new file

program. Else we get mark.

S.G.Balekundri Institute of Technology Belagavi 10

S.G.Balekundri Institute of Technology Belagavi 11

 close the wave window.

STEPS FOR SYNTHESIS:

 Right click on desktop → open terminal (terminal window appears).

(MENTOR TOOL ENVIRONMENT)

S.G.Balekundri Institute of Technology Belagavi 12

leonardo{1}: load_library˽ /home /student/PDK/leonardo/tsmc025_typ.syn (to get

Command read finished successfully.

S.G.Balekundri Institute of Technology Belagavi 13

module inv (a,b);

S.G.Balekundri Institute of Technology Belagavi 14

S.G.Balekundri Institute of Technology Belagavi 15

TOOL REQUIRED: Mentor Graphics Tool

module buffer (a,b);

S.G.Balekundri Institute of Technology Belagavi 16

S.G.Balekundri Institute of Technology Belagavi 17

TOOL REQUIRED: Mentor Graphics Tool

Fig1: Schematic representation of a transmission gate

S.G.Balekundri Institute of Technology Belagavi 18

Module transgate (in, control, out);

S.G.Balekundri Institute of Technology Belagavi 19

Experiment No: 4.a

TOOL REQUIRED: Mentor Graphics Tool

S.G.Balekundri Institute of Technology Belagavi 20

INPUT NOT AND OR EXOR EXNOR

S.G.Balekundri Institute of Technology Belagavi 21

S.G.Balekundri Institute of Technology Belagavi 22

Experiment No: 4.b

TOOL REQUIRED: Mentor Graphics Tool

INPUT NAND NOR