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Foundation Of VLSI Design

Module 1 : Digital Electronics

Digital basics (Revision of Engineering course work)

Binary System, Logic Levels, Different Logic States, Noise Margins
Combinational circuit & Sequential circuit,Frequency Divider/Multiplyer
Circuit,Sequence Detector
FSM (Meely and Moree Models)

Advance Digital (Implementation of Digital circuit in VLSI design)

Designing of Different Logic gates/Combinational Circuit/Sequential elements using
MUX
PAL, PLA concepts, Tristate Buffers / Tristate Inverter,Clock Gating Concepts
Standard Cell Library Concepts
Logic Optimization

Module 2: Semiconductor Electronics

1/15
Semiconductor Overview
Property & Parameter : (Doping/Impurities,Amount of Impurities, Different type of
Region (N+/N++, P+/P++),Energy Bands, Fermi Level,Drift Current, Mobility)
Semiconductor Devices : (Depletion region, Build In potential,Immobile Ions,Diffusion
Current, Recombination)

Module 3: CMOS Design

CMOS Fundamental
Basic : (Concepts of Vt in a MOS & Subthreshold Regions, MOS Electrical Parameters:
Inout output characteristics,How Source/Drain Terminals are defined,Cross Section of
NMOS,PMOS,CMOS,Finfet Vs Planner CMOS)
Advance CMOS : ("Different factors on which Vt has dependency, Body Biasing,
Channel Length Modulation", FInFet Concepts, W/L Ration Concepts (Parallel and
Series Connection),Parameter Varaition (Fast and Slow Transistor) FF/SS CMOS, HVT /
LVT / RVT Cells,Device Scalling)

CMOS Circuit Design

CMOS Pass Transistor : (Switching Theory,NMOS and PMOS pass Transistor,
Transmission Gate concepts, Pass transistor based problems)
CMOS Circuit Design : (Designing of all Logic Gates, Combinational & Sequential
Circuit)

CMOS Fabrication
Cross Section of CMOS,Single Tub/ Twin Tub, Single Well
Device Cap and Metal Cap / CMOS Fabrication Process (Step by Step)
Shallow Trench Isolation (STI layer), Latch Up Concepts

Module 4: CMOS Design in VLSI Design

Advance CMOS Design

CMOS Design : (Temperature Variation, Supply Voltage Variation, Process
Variation,PVT Corners,Tap Cells, 3 Terminal & 4 Terminal Devices)
Power Dissipations (Static , Dynamic Power, Transition Current, Short Circuit Power
Dissipations, CMOS Leakages: Leakage related short circuit current, static current)

Schematic & Simulation Concepts (Include Practical Labs)

2/15
 Schematic of Different Logic Gates : (BSIM Models, SPICE Netlist, Model Files)
Fan-In, Fan-out, Driving Strength
Introduction to Virtuoso/Tanner & different settings
Technology File and different Inputs files

Module 5: Standard Cell Layout Design

Layout Design (Theoritical Concepts)

Different layers Understanding, Metal Stack Concepts, Different DRC Rules & their
understanding
Layout drawing using Paper and Pen
Fingering concepts
TapCells , Nwell Cells Layout Concepts, Well Proximity Effect (WPE)
Latchup and it's preventions, Introduction of Guard Ring
Placement of Standard cell in Design(Concepts of SiteRows/Grids/Tracks/Flipping of
Standard Cells)
Antenna Effects (Concepts, Damage, Remedies),Jumpers, Antenna Diode,
Electromigration concepts and it's preventions, AC/DC EM, IR Analysis, Power planning
methods to reduce IR, Shielding Concepts

Layout Design (Practical Tool based)

Introduction to Virtuoso Layout window & different settings, Layout Pallets, GUI
Interface
Concepts of DRC, LVS, ERC and Basic Checks (Soft Check)
Metal Stack based Design (Like Use both M1, M2 for design)

Module 6: VLSI Automation Concepts and QOR

Unix
Overview of Unix platform & Different commands
Shell Scripting: bash cshell,awk,sed
VI editor concepts

TCL & Perl Scripting

TCL & Perl Introduction and it's industrial use,Concepts of Wrapper,
Procedure in TCL & regular expression
File Handling, Read/Write Operation, Flow Control (Foreach, while, switches, for etc)
Perl: List, Hash concepts

3/15
QOR and Reporting Concepts
Reporting concepts & different analysis concepts
Log file and different type of Messages in that ( ERROR Messages, INFO Messages,
WARNING Messages)
Regression Concepts,Version to Version Check , Accuracy Check, Golden Vs Test Result
Automation For Validation
How to create charts, read charts, Histrogram, Pi charts concepts

Module 7: Logic Synthesis

Logic Synthesis (basic)

Introduction to Synthesis, Basic Terminology
Netlist Overview with libraries introduction (Target Library, Link Library)
Concept of Synthesizable RTL, Mapping to Gatelevel Netlist
Different way of Modelling combinational or sequential elements

Logic Synthesis (Advance)

Timing constriant basic (Max Trans, Max Cap, Max Fanout, Min cap)
Commonly Faced Issues during Synthesis
CDC and LINT Concepts
DFT insertion basics inside synthesis tool

Module 8: Static Timing Analysis

Introduction to Static Timing Analysis & Timing Arc

Importance of Timing Analysis, VLSI Flow Introduction & different stages where Timing
analysis happen
Different component of Timing analysis (Timing Budgeting,Timing Constraint,Timing
Check,Timing Violations,Fixing of Timing Violations
Introduction about different input and output files for STA
Importance of Timing Arc & Timing Arc Representation in .LIB Files

Delay Introduction (Cell Delay and Net Delay)

Introduction of Delay Concepts
Combinational Path Delays,Sequential Path Delays
Net Delay basic (Metal Wire Concepts,Metal Stack concepts)
Gate Delay Concepts (Charging & Discharging concepts, Load related Concepts, Delay
dependency on current of Inverter,Internal Capacitance,Input Capacitance and Output
4/15
 Capacitance concepts

Delay Models & Understanding Delays Libraries

Gate Delay Models (How delay depends on Input Transition & Output Load,NLDM
Library & CCS Library)
Net Delay Models (Transmission Line Models,Elmore Model,Wire Load Model

STA Tool Delay Calculation Methodology

Delay Calculation by STA tools (Path based Analysis and Graph Based Analysis)
Pre-Layout Delay (using wire-load model) & Post layout Delay (using SPEF File)
calculation
Delay Calculation using Delay tables, Complexity across different corners.
Dependency of Delay on different parameters (PVT Corners,Manufacturing defects,RC
Corners)

Timing Paths, Timing Exceptions & Timing Constraints

Various Timing Paths (Data Path, Clock Path, Asynchronous Path,Clock Group
Introduction
Representation of Timing path within Timing report
Timing Exceptions (False path, Multicycle path)
Clock Constraints,Input and Output Delay constraints

Setup and Hold Time

Different Timing Terminology (launch/Capture path,Slew, Clock latency,Clock skew)
Setup and Hold Time
Setup and Hold Check and corresponding Equations
Basic Timing Report

Advance Timing Concepts

Gloabal Setup-hold time
Onchip Variations (OCV),Advance onchip Variation (AOCV),Setup and Hold Check in
case of OCV, AOCV
CRP & CRPR
Multi-Mode Multi-Corner timing analysis

Timing optimization & Timing Closure Methods

Pre-placement (After synthesis) optimization
Pre-CTS (during or after placement or floorplaning) optimization

5/15
 Fixing of Setup and Hold Violation at Logic Synthesis (front-end vlsi)

Post Layout STA (Backend) & Fixing Setup and Hold Violations Methods
Post CTS or Pre-Route (After CTS)Optimization
Signoff Timing or Post-Route (After Routing) Timing Closure

Module 9: Memory Circuit Design

SRAM
SRAM Basic Concepts & SRAM Vs DRAM
SRAM array architecture
SRAM - Basic Read and write operation

Module 10: DFT Concepts

Fundamental of DFT
DFT ? Why, What, Who, When?
Implementation of Digital Concepts in DFT & Different Terminology
Test Concepts & Automatic Testing
Timing Checks and Constraints, Timing concepts for DFT

DFT Basics
Introduction to BIST (Built-In Self Test)
Introduction to BIT (Built-In Test)
Scan Chain Concepts, Boundry scan chain
Introduction of ATPG (Automatic Test Pattern Generation)

Module 11: Low Power Methodology

Basic Concepts
Power Domain Concepts, Different Device powers (Leakage power,Static
Power,Transition power)
"Power Related Cells(Retention cell,Level shifter,Isolation Cell and other special cells)
Low power concepts - Why we need it, UPF / CPF concepts - Why we need it

Module 12: ASIC Flow and Physical Design

6/15
Flow and Design basics
Modular Approach / Hierarchical Approach,Top to bottom, Bottom to Top Approach
Overview of RTL to Gatelevel Netlist, Overview of Physical Design
Modes (Functional, Test and others),MCMM, Case Analysis,
Constraints (Physical Constraint,Design Constrainst,Power Constraints,Timing
Constraints)
Netlist,Pins/Ports/IO Pads /PG Pins,Design Corners (PVT and RC Corners)
Timing Analysis Vs Timing Optimization,Power Analysis Vs Power Optimization

Understanding of Different Input/Output files

LEF/DEF, Model Files
Timing Library (.lib),SDC,Wireload,
LVS Deck, DRC Deck, ERC Deck, Interconnect file, TLU+File/Captables, Parasitic Files
(SPEF)

Physical Design Flow

Floorplan
Placement
CTS
Routing
STA and Parasitic Extraction

Module 13: Verilog

Verilog Concepts
Verilog Deisgn Flow and Design Methodology
Defination of Verilog Codes (Diferent Syntax)
Different Type of Modelling (Gate level Modelling, Data Flow Modelling, Behavioral
Modelling)
Test Bench Writting concepts
System Task Function

Digital Design using Verilog and Protocols

Modeling of combinational and sequential circuits
Basic FIFO concepts,UART protocol theory

Module 14: Add-ons

7/15
To prepare for Written test
C basic and Aptitute Concepts
Analog Circuit and RC Circuits

Interview related
100+ Online Papers
25+ Mock Interviews

Fundamental Of STA

Introduction to Static Timing Analysis & Timing Arc

Importance of Timing Analysis, VLSI Flow Introduction & different stages where Timing
analysis happen
Different component of Timing analysis (Timing Budgeting,Timing Constraint,Timing
Check,Timing Violations,Fixing of Timing Violations
Introduction about different input and output files for STA
Importance of Timing Arc & Timing Arc Representation in .LIB Files

Delay Introduction (Cell Delay and Net Delay)

Introduction of Delay Concepts
Combinational Path Delays,Sequential Path Delays
Net Delay basic (Metal Wire Concepts,Metal Stack concepts)
Gate Delay Concepts (Charging & Discharging concepts, Load related Concepts, Delay
dependency on current of Inverter,Internal Capacitance,Input Capacitance and Output
Capacitance concepts

Delay Models & Understanding Delays Libraries

Gate Delay Models (How delay depends on Input Transition & Output Load,NLDM
Library & CCS Library)
Net Delay Models (Transmission Line Models,Elmore Model,Wire Load Model

STA Tool Delay Calculation Methodology

Delay Calculation by STA tools (Path based Analysis and Graph Based Analysis)
Pre-Layout Delay (using wire-load model) & Post layout Delay (using SPEF File)
calculation
Delay Calculation using Delay tables, Complexity across different corners.
Dependency of Delay on different parameters (PVT Corners,Manufacturing defects,RC
Corners)
8/15
Timing Paths, Timing Exceptions & Timing Constraints
Various Timing Paths (Data Path, Clock Path, Asynchronous Path,Clock Group
Introduction
Representation of Timing path within Timing report
Timing Exceptions (False path, Multicycle path)
Clock Constraints,Input and Output Delay constraints

Setup and Hold Time

Different Timing Terminology (launch/Capture path,Slew, Clock latency,Clock skew)
Setup and Hold Time
Setup and Hold Check and corresponding Equations
Basic Timing Report

Advance Timing Concepts

Gloabal Setup-hold time
Onchip Variations (OCV),Advance onchip Variation (AOCV),Setup and Hold Check in
case of OCV, AOCV
CRP & CRPR
Multi-Mode Multi-Corner timing analysis

Timing optimization & Timing Closure Methods

Pre-placement (After synthesis) optimization
Pre-CTS (during or after placement or floorplaning) optimization
Fixing of Setup and Hold Violation at Logic Synthesis (front-end vlsi)

Post Layout STA (Backend) & Fixing Setup and Hold Violations Methods
Post CTS or Pre-Route (After CTS)Optimization
Signoff Timing or Post-Route (After Routing) Timing Closure

Foundation of FrontendDesign

(Coustomized course)

Module 1 : Digital Electronics

Digital basics (Revision of Engineering course work)

Binary System, Logic Levels, Different Logic States, Noise Margins
9/15
 Combinational circuit & Sequential circuit,Frequency Divider/Multiplyer
Circuit,Sequence Detector
FSM (Meely and Moree Models)

Advance Digital (Implementation of Digital circuit in VLSI design)

Designing of Different Logic gates/Combinational Circuit/Sequential elements using
MUX
PAL, PLA concepts, Tristate Buffers / Tristate Inverter,Clock Gating Concepts
Standard Cell Library Concepts
Logic Optimization

Module 2: Semiconductor Electronics

Semiconductor Overview
Property & Parameter : (Doping/Impurities,Amount of Impurities, Different type of
Region (N+/N++, P+/P++),Energy Bands, Fermi Level,Drift Current, Mobility)
Semiconductor Devices : (Depletion region, Build In potential,Immobile Ions,Diffusion
Current, Recombination)

Module 3: CMOS Design

CMOS Fundamental
Basic : (Concepts of Vt in a MOS & Subthreshold Regions, MOS Electrical Parameters:
Inout output characteristics,How Source/Drain Terminals are defined,Cross Section of
NMOS,PMOS,CMOS,Finfet Vs Planner CMOS)
Advance CMOS : ("Different factors on which Vt has dependency, Body Biasing,
Channel Length Modulation", FInFet Concepts, W/L Ration Concepts (Parallel and
Series Connection),Parameter Varaition (Fast and Slow Transistor) FF/SS CMOS, HVT /
LVT / RVT Cells,Device Scalling)

CMOS Circuit Design

CMOS Pass Transistor : (Switching Theory,NMOS and PMOS pass Transistor,
Transmission Gate concepts, Pass transistor based problems)
CMOS Circuit Design : (Designing of all Logic Gates, Combinational & Sequential
Circuit)

CMOS Fabrication
Cross Section of CMOS,Single Tub/ Twin Tub, Single Well
10/15
 Device Cap and Metal Cap / CMOS Fabrication Process (Step by Step)
Shallow Trench Isolation (STI layer), Latch Up Concepts

Module 4: Linux

Linus Basic
Development, Architecture and Features of Linux OS, Shell Support, Disk Usage and
Login.
Managing Disk Files & Directories,Managing Documents using Find command,
filters,pipes & redirections
Shell Programming,Shell within shell, Parameter handling & command substitutions.
Functions – Recursion writing
Shell Scripting: bash cshell,awk,sed
VI editor concepts

Module 5: VLSI Automation and Scripting

TCL & Perl Scripting

TCL & Perl Introduction and it's industrial use,Concepts of Wrapper,
Procedure in TCL & regular expression
File Handling, Read/Write Operation, Flow Control (Foreach, while, switches, for etc)
Perl: List, Hash concepts

QOR and Reporting Concepts

Reporting concepts & different analysis concepts
Log file and different type of Messages in that ( ERROR Messages, INFO Messages,
WARNING Messages)
Regression Concepts,Version to Version Check , Accuracy Check, Golden Vs Test Result
Automation For Validation
How to create charts, read charts, Histrogram, Pi charts concepts

Module 6: C and C++

C language
Introduction and Overview of C.
Constant, Variables & Data Types,Operators & Expressions, Conditional, Multiway
Branching & Looping, Arrays and Strings
Input and Output Management.
11/15
 User Defined Functions, Structures and Unions.
Pointers,Dynamic Memory Allocation and Linked Lists

C++ Programing
Introduction & Overview of C++,Basics of Program writing.
Arrays, Qualifiers, Reading Numbers and Bit Operations,Decision & Control
Statements.
C++ Preprocessor, Variable Scope & Functions, Advance Programming Concepts (File
Input/Output, Debugging & Optimization, Operator Overloading, and Floating Point)
Advance Data Types, OOPs (Simple & Advance Classes),Basic & Advance Pointers

Module 7: Logic Synthesis

Logic Synthesis (basic)

Introduction to Synthesis, Basic Terminology
Netlist Overview with libraries introduction (Target Library, Link Library)
Concept of Synthesizable RTL, Mapping to Gatelevel Netlist
Different way of Modelling combinational or sequential elements

Logic Synthesis (Advance)

Timing constriant basic (Max Trans, Max Cap, Max Fanout, Min cap)
Commonly Faced Issues during Synthesis
CDC and LINT Concepts
DFT insertion basics inside synthesis tool

Module 9: Verilog HDL

Digital Design Using Verilog

VLSI Flow,Different Modeling Styles,Predefined Gate Primitives,Continuous Data
Assignments.
Hierarchy Creation, Module Instantiation and Mapping, Stimulus Creation.
Multiway Branching & Generate Blocks.Delays, Event Control and Timing Regions at
Higher Level of Abstraction.
Compiler Directives,System Tasks & Functions
Switch Level Modeling (Lowest Level Abstraction Level).
User Defined Primitives (UDPs).Variable Change Dump (VCD),Specify Block.

Module 10: System Verilog

12/15
Introduction to System verilog
Arrays, Structures and Data Types,Tasks and Functions New Features, Interfaces
Program Control & Hierarchy, Hierarchy & Connectivity of modules.
IPC (Inter Process Communication),Semaphore and Mailbox, Randomization,Programs
& Clocking Block
Functional Coverage,SVA (System Verilog Assertions),Verification Environment.
Labs

Module 11: UVM (Universal Verification Methodology)

Introduction to UVM
UVM Reporting,UVM Transaction, UVM Configuration,UVM Factory,UVM
Sequences,UVM Transaction Level Modeling (TLM),UVM Callback.
UVM Testbench (Testbench Top,UVM Test,UVM Environment,UVM Scoreboard,UVM
Agent,UVM Monitor,UVM Driver,UVM Phases,UVM Sequencer

Module 12: Static Timing Analysis

Introduction to Static Timing Analysis & Timing Arc

Importance of Timing Analysis, VLSI Flow Introduction & different stages where Timing
analysis happen
Different component of Timing analysis (Timing Budgeting,Timing Constraint,Timing
Check,Timing Violations,Fixing of Timing Violations
Introduction about different input and output files for STA
Importance of Timing Arc & Timing Arc Representation in .LIB Files

Delay Introduction (Cell Delay and Net Delay)

Introduction of Delay Concepts
Combinational Path Delays,Sequential Path Delays
Net Delay basic (Metal Wire Concepts,Metal Stack concepts)
Gate Delay Concepts (Charging & Discharging concepts, Load related Concepts, Delay
dependency on current of Inverter,Internal Capacitance,Input Capacitance and Output
Capacitance concepts

Delay Models & Understanding Delays Libraries

Gate Delay Models (How delay depends on Input Transition & Output Load,NLDM
Library & CCS Library)
Net Delay Models (Transmission Line Models,Elmore Model,Wire Load Model
13/15
STA Tool Delay Calculation Methodology
Delay Calculation by STA tools (Path based Analysis and Graph Based Analysis)
Pre-Layout Delay (using wire-load model) & Post layout Delay (using SPEF File)
calculation
Delay Calculation using Delay tables, Complexity across different corners.
Dependency of Delay on different parameters (PVT Corners,Manufacturing defects,RC
Corners)

Timing Paths, Timing Exceptions & Timing Constraints

Various Timing Paths (Data Path, Clock Path, Asynchronous Path,Clock Group
Introduction
Representation of Timing path within Timing report
Timing Exceptions (False path, Multicycle path)
Clock Constraints,Input and Output Delay constraints

Setup and Hold Time

Different Timing Terminology (launch/Capture path,Slew, Clock latency,Clock skew)
Setup and Hold Time
Setup and Hold Check and corresponding Equations
Basic Timing Report

Advance Timing Concepts

Gloabal Setup-hold time
Onchip Variations (OCV),Advance onchip Variation (AOCV),Setup and Hold Check in
case of OCV, AOCV
CRP & CRPR
Multi-Mode Multi-Corner timing analysis

Timing optimization & Timing Closure Methods

Pre-placement (After synthesis) optimization
Pre-CTS (during or after placement or floorplaning) optimization
Fixing of Setup and Hold Violation at Logic Synthesis (front-end vlsi)

Post Layout STA (Backend) & Fixing Setup and Hold Violations Methods
Post CTS or Pre-Route (After CTS)Optimization
Signoff Timing or Post-Route (After Routing) Timing Closure

Module 13: DFT Concepts

14/15
Fundamental of DFT
DFT ? Why, What, Who, When?
Implementation of Digital Concepts in DFT & Different Terminology
Test Concepts & Automatic Testing
Timing Checks and Constraints, Timing concepts for DFT

DFT Basics
Introduction to BIST (Built-In Self Test)
Introduction to BIT (Built-In Test)
Scan Chain Concepts, Boundry scan chain
Introduction of ATPG (Automatic Test Pattern Generation)

Module 14: Low Power Methodology

Basic Concepts
Power Domain Concepts, Different Device powers (Leakage power,Static
Power,Transition power)
"Power Related Cells(Retention cell,Level shifter,Isolation Cell and other special cells)
Low power concepts - Why we need it, UPF / CPF concepts - Why we need it

15/15