Digital Principles Notes (1) TCFL PDF

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INTRODUCTION TO DIGITAL TECHNIQUES
CONTENTS
1.1. DIFFERENCE BETWEEN ANALOGUE AND DIGITAL SIGNALS
1.2. ADVANTAGES OF DIGITAL TECHNIQUES
1.3. DIGITAL SYSTEMS
1.3.1. THE DIGITAL COMPUTER AND THE MICROPROCESSOR
1.3.2. VARIOUS DIGITAL EQUIPMENT
1.3.3. TELEPHONE TRANSMISSION SYSTEMS
1.4. EXERCISES
TelOne Centre for Learning

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1.1. DIFFERENCE BETWEEN ANALOGUE AND DIGITAL SIGNALS
A lot of present-day electronic and telecommunication equipment is still analogue in nature. This means
that the signals to be handled, processed or transmitted are represented by voltages whose amplitude
and/or frequency vary continuously with time thus, in a telephone system; the transmitted signals are
replicas of the speech waveforms. Digital signals are not continuous in nature but consist of discrete
pulses of voltage or current which represent the information to be processed. Fig. 1.1 shows some
examples of analogue and digital signals. Digital voltages can vary only in discrete steps; normally only
two voltage levels are used –often one of which is zero - so that two state devices can be employed. A

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two state device is one which has only two stable states; so it is either ON or it is OFF. Examples of two
state devices are : a lamp which is either glowing visibly or not; a :buzzer which is either producing an
audible sound or not or an electrical switch which either completes an electrical circuit or breaks it.
Further examples of two state devices that are used extensively in electronic circuitry are the
semiconductor diode and the transistor (junction and field effect).
1.2. ADVANTAGES OF DIGITAL TECHNIQUES
The advantages to be gained from the use of digital techniques instead of analogue methods arise
largely from the use of just the two voltage levels. Digital circuitry, mainly integrated in modern systems,
operates by switching transistors ON and OFF and does not need to produce or to detect: precise values
of voltage and/or current at particular points in an equipment or system. Because of this it is easier and
cheaper to mass produce digital circuitry. Digital circuitry are generally more reliable than analogue
circuits because faults will not often occur through variations in performance caused by changing values
of components, misaligned coils, and so on. Again, the effects of noise and interference are very much
reduced in a digital system since the digital pulses can always be regenerated and made like new
whenever their wave shape is becoming distorted to the point where errors are likely. This is not
possible in an analogue system where the effect of unwanted noise and interference is to permanently
degrade the signal.
1.3. DIGITAL SYSTEMS
1.3.1. THE DIGITAL COMPUTER AND THE MICROPROCESSOR
Nowadays the digital computer is an integral part of the day-to-day operations of many firms and
organizations. They are employed for the calculation of wages and salaries, taxes, pensions, bills and
accounts; for the storage of medical, scientific and engineering data and for the rapid booking of aircraft
seats, holidays etc. They are also used to carry out complex scientific and engineering calculations, to
control engineering processes in factories, to control the operations of telephone exchanges and for
many other purposes.
A digital computer is able to store large quantities of data in its memory which can be made available as
and when required. The task to be performed by the computer is detailed to the computer by means of
a set of instructions known as the programme. The programme is fed into the computer and stored in
another part of its memory.
The basic block diagram of a digital computer is shown in Fig. 1.2. The instructions contained in the
programme are taken sequentially (one after the other) from the memory under the direction of the
control unit. Each instruction causes the arithmetic unit to perform arithmetic and logic operations on
the data, also taken from the memory. The results of the calculations can be stored in the memory or
they can be held temporarily in a part of the arithmetic unit known as the accumulator. When a
calculation has been completed, the control unit will transfer the results to an output device, which

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will(probably) produce the results in printed form; alternatively the results may be transmitted over a
data link to a distant point where they are needed.
The input devices used to feed information into a computer are usually some kind of teleprinter, or a
paper tape or card reader, or a magnetic tape or disc reader.
Teleprinters and other similar printing apparatus, and paper tape/card punchers, can be used as output
devices but very much faster in operation are equipment known as line printers. Visual display units
(VDU) are also employed and these basically consist of a picture tube upon the screen of which data can
be displayed.
MICROPROCESSORS
The term microprocessor is generally applied to a form of computer that is able to control the operation
of a wide variety of equipment internally. A microprocessor occupies very little space since much of its
circuitry is contained within an integrated circuit. As a result, a microprocessor can be built into
theequipment whose operation it is to control. Fig 1.3 shows thebasic block diagram of a micro-
computer system. The microprocessor chip contains besides various registers the arithmetic unit and
the control circuitry very similar to a main computer. Often the memory is also integrated on the same
chip.

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1.3.2. VARIOUS DIGITAL EQUIPMENT
CALCULATORS
Hand-calculators are nowadays in common use and are an example of the use of digital circuitry. All
calculators are able to carry out the basic mathematical procedures while many are provided with
several more advanced mathematical facilities. Some models are programmable. The circuitry contained
within a calculator is complex and these devices have only become practical since the advent of
integrated circuits.
CASH REGISTERS
Many cash registers and weighing scales used in the shops are electronic and these provide a readout in
digital form of the total money to be paid and, once the money offered has been entered by the
operator, of the change to be given as well as a print-out of the purchases. The cash register also keeps
a record of the cash input and in some cases this is signaled to a central point where a complete record
for the shop or department can be maintained.
MEASURING INSTRUMENTS
In engineering, digital readouts of data are often more convenient andaccurate than analogue readings.
Digital voltmeters and frequency meters or counters are particularly suited to measurements
applications where a large number of repetitive readings are to be made. The advantage of digital
meters is most noticeable when relatively unskilled personnel are employed to carry out the tests. With
a digital instrument the operator can read at a glance the value of the displayed parameter, but very
often an analogue reading requires care if reasonable accuracy is to be obtained. This point is illustrated

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by Fig. 1.4. When the pointer is in-between two scale markings, some doubt exists as to the value
indicated. No such doubt is present with the digital instrument; its indicated value is easier to read.
1.3.3. TELEPHONE TRANSMISSION SYSTEMS
Telecommunication systems have traditionally been analogue in nature, with the exception of Morse
code telegraphy. Speech signals are transmitted over purely analogue circuits routed over a combination
of physical pairs in telephone cables and frequency division multiplex channels over line and/or radio
links.
Digital transmission using pulse code modulation (PCM) is increasingly used and much of the junction
networks throughout the world are being transferred to this technique. One advantage of digital
working is that it can be used for all kinds of signal, be it speech, music, television, telegraphy or data.
There are two main reasons why the application of digitaltechniques to telecommunications has been
fairly limited in scope until recent years. First, digital circuitry was, in the main, not economic until
integrated circuits became freely available, and secondly, the transmission of digital signals requires the
provision of circuits with a very wide bandwidth. Some digital circuits and equipment have, of course
been available since pre-integrated circuit days but their scope and application were very limited.
1.4. EXERCISES
1. Explain the difference between analogue and digital signals. Give examples.
2. State the advantages of digital techniques.
3. (a) Explain the operation of a digital computer with means of a block diagram.
(b) Give some examples of the use of digital computers.
4. Explain the term "microprocessor" and indicate its main application.
5. Mention some equipment which makes use of digital techniques.

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NUMBER SYSTEMS AND CODES
2.1 NUMBER SYSTEMS
There are four systems of arithmetic which are often used in digital circuits. These systems are:
1. Decimal -it has a base (or radix) of 10 i.e. it uses10 different symbols to represent numbers.
2. binary -it has a base of 2 i.e. it uses only two different symbols
3. Octal -it has a base of 8 i.e. uses eight different symbols.
4. hexadecimal -it has a base of 16 i.e. it uses sixteen different symbols.
All these systems use the same type of positional notation except that
-decimal system uses powers of 10
-binary system uses powers of 2
-octal system uses powers of 8
-hexadecimal system uses powers of 16
Decimal numbers are used to represent quantities which are outside the digital system. Binary system is
extensively used by digital systems like digital computers which operate on binary information. Octal
system has certain advantages in digital work because it requires less circuitry to get information into
and out of a digital system. Moreover, it is easier to read, record and print out octal numbers than
binary numbers. Hexadecimal number is particularly suited for microcomputers.
2.2 THE DECIMAL NUMBER SYSTEM
We will briefly recount some important characteristics of this more familiar system before taking up
other systems. This system has a base of 10 and is a position-value system (meaning that value of a
digital depends on its position). It has the following characteristics:
i. Base or radix
It is defined as the number of different, digits which can occur in each position in the
number system.
The decimal number system has a base of 10 meaning that it contains ten unique symbols
(or digits). These are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. Any one of these may be used in each position
of the number.
Incidentally it may be noted that we call it a decimal (10’s) system although it does not have
a distinct symbol of 10. As is well known, it expresses 10 and any number above 10 as a
combination of its ten unique symbols.

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ii. Position value

The absolute value of each digit is fixed but its position value (or place value or weight) is
determined by its position in the overall number. For example, position value of 3 in 3000 is
not the same as in 300. Also, position value of each 4 in the number 4444 is different as
shown in fig 2.1
Similarly, the number 2573 can be broken down as follows:
2573 = 2 𝑥 103 + 5 𝑥 102 + 7 𝑥 101 + 3 𝑥 100
It will be noted that in this number, 3 is the least significant digit (LSD) whereas 2 is the most significant
digit (MSD).
Again, the number 2573.469 can be written as
2573.469 = 2 𝑥 103 + 5 𝑥 102 + 7 𝑥 101 + 3 𝑥 100 + 4 𝑥 10-1+ 6 𝑥 10-2+ 9 𝑥 10-3
It is seen that position values are found by raising the base of the number system (i.e. 10 in this case) to
the power of the position. Also, powers are numbered to the left of the decimal point starting with 0
and to the right of the decimal point starting with -1.
2.3 BINARY SYSTEM
Like decimal (or denary) system, it has a. radix and it also uses the same type of position value system.
i. Radix
Its base or radix is two because it uses only two digits 0 and 1 (the word ‘binary digit' is
contracted to bit). All binary numbers consist of a string of 0s and 1s. Examples are 10, 101
and 1011 which are read as one-zero, one-zero-one and one-zero-one-one to avoid
confusion with decimal numbers. Another way to avoid confusion is to add a subscript of 10
for decimal numbers and of 2 for binary numbers as illustrated below.
1010, 10110, 574210 decimal numbers and 102, 1012, 1100012 -binary numbers.

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It is seen that the subscript itself is in decimal. It may be noted that binary numbers need
more places for counting because their base is small.
ii. Position Value

Like the decimal system, binary system is also positionally-weighted. However, in this case,
the position value of each bit corresponds to some power of 2. In each binary number, the
valueincreases in powers of 2 starting with 0 to the left of the binary point and decrease to
the right of thebinary point starting with power of -1. The position value (or weight) of each
bit along with a 7-bit binary number 1011.011 is shown in fig 2.2
As seen, the fourth bit to the left of binary point carries the maximum weight (i.e. has the highest value)
and is calledmost significant digit (MSD). Similarly, the third bit tothe right of the binary point is called
least significant digit (LSD). The decimal equivalent of the binary number maybe found as under
1101.0112 = (1𝑥23) + (1𝑥22) + (0𝑥21) + (1𝑥20) + (0𝑥2-1) + (1𝑥2-2) + (1𝑥2-3)
= 8 + 4 + 0 + 1 + 0 + 1/4 + 1/8 = 13.37510
As stated earlier, position value of different bits are given by ascending powers of 2 to the left of binary
point and by descending powers of 2 to the right of binary point. The different digit positions of a given
binary number have the following decimal weight (Fig. 2.3).
Binary numbers are used extensively by alldigital systems primarily due to the nature of electronics
itself. The bit 1 may be represented by a saturated (fully-conducting) transistor, a light turned ON, a
relay energized or a magnet magnetized in a particular direction. The bit 0, on the other hand, can be
represented as a cut-off transistor, a light turned OFF, a relay de-energized or a magnet magnetized in
the opposite direction. In such cases, there are only two values which a device can assume.

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2.3.1 BINARY TO DECIMAL CONVERSION
Following procedure should be adopted for converting a binary integer (whole number) into its
equivalent decimal number.
Step 1 Write the binary number i.e. its bit in a row
Step 2 Directly under the bits, write 1,2,4,8,16,starting from right to left.
Step 3 Cross out the decimal weights which lie under 0 bits
Step 4 Add the remaining weights to get the decimalequivalent
Example 2.1 Convert 110012 to its equivalent decimal number
Solution
The four steps involved in the conversion are as under:
Step 1 1 1 0 0 1
Step 2 16 8 4 2 1
Step 3 16 8 4 2 1
Step 4. 16+8+1= 25
110012 = 2510
It is seen that the number contains 1 sixteen, one eight, 0 four's, 0 two's and 1 one. Certain decimal and
binaryequivalent numbers are tabulated in Table No. 2.1

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Table 2.1
Decimal Binary Decimal Binary Decimal binary

1 1 11 1011 21 10101
2 10 12 1100 22 10110
3 11 13 1101 23 10111
4 100 14 1110 24 11000
5 101 15 1111 25 11001
6 110 16 10000 26 11010
7 111 17 10001 27 11011
8 1000 18 10010 28 11100
9 1001 18 10011 29 11101
10 1010 20 10100 30 11110
2.3.2 BINARY FRACTIONS
Here, procedure is the same as or binary integers except that the following weights are used for
different bit positions.
2-1 2-2 2-3 2-4

1 1 1 1
.2 4 8 16
BINARY POINT
Example 2.2 Convert the binary fraction 0.101 into decimal equivalent.
Solution
The following four steps will be used for this purpose.
step 1 0 1 0 1
Step 2 ½ ¼ 1/8
Step 3 ½ ¼ 1/8
Step 4 ½ + 1/8= 0.625
0.1012 = 0.62510
Example 2.3 Find the decimal equivalent of 6-bit binary number 101.1012

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Solution
1 0 1 1 0 1
4 2 1 ½ ¼ 1/8
4 2 1 ½ ¼ 1/8 = 5 + 1/2 +1/8 = 5.625
101.1012 =5.62510
2.3.3 DOUBLE-DADD METHOD
This method of converting binary integers into decimal equivalents is much simpler and quicker than the
method given in Art. 2.3.1 especially in the case of large numbers. Following three steps are involved:
1. Double the first bits to the extreme left and add this doubled value to the next bit on the right.
2. Double the sum obtained and add the doubled value to the next bit.
3. Continue step 2 until the last bit has been added tothe previously-doubled sum.
The conversion of 11001 is shown in Fig. 2.4. It is seen that 110012= 2510.
Using doub1e-dadd method, let us convert 1110102 into its binary equivalent.
1. 2x1 = 2 add next bit 1 sothat 2+1 = 3
2. 2x3 = 6 add next bit 1 sothat 6+1 = 7
3. 2x7 = 14 add next bit 0 so that 14+0 = 14

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4. 2x14 = 28 add next bit 1 so that 28+1 = 29
5. 2x29 = 58, add next bit 0 so that 58+0 = 58
1110102 = 5810
2.3.4 DECIMAL TO BINARY CONVERSION
(a) Integers
Such conversion can be achieved by using the so-calleddouble-dabble method. It is also shown as divide-
by-twomethod. In this method, we progressively divide the given decimal number by 2 and write down
the remainders after eachdivision. These remainders taken in the reverse order (i.e.from bottom-to-top)
form the required binary number. As anexample, let us convert 2510 into its binary equivalent.
2510 = 110012
The above process may be simplified as under:
Reading the remainders from bottom to top, we get 2510 =110012

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It may also be put in the following form:
(b) FRACTIONS
In this case, mu1tiply-by-two rule is used i.e. we multiply each bit by 2 and record the carry in the
integer position. These carries taken in the forward (top-to-bottom) directions give the required binary
fraction.
Let us convert 0.812510 into its binary equivalent.
Please note that we have to add the binary point from our side. Let us now convert 0.7710 into its binary
equivalent.
*It is so because there is 0 at the integer position i.e. to the left of the decimal point.

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We may stop here but the answer would be approximate.
0.7710 = 1100012
Example 2.4
Convert 25.62510 into its binary equivalent
Solution
We will do the conversion in two steps (i) first for the integer and (ii) then for the fraction.
..
2510 = 110012 0.62510 = 0.1012
Considering the complete number, we have 25.62510 = 11001.1012
Obviously binary system needs more bits to express the same number than decimal system.

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2.3.5 SHIFTING THE PLACE POINT
In a decimal number if the decimal point is moved one place to the right, the number is multiplied by 10.
For example, when decimal point in 7.86 is shifted one place to the right, it becomes 78.6 i.e. it
increases the value of the number 10 times. Moving the decimal point one place to the left reduces its
value to one-tenth.
In binary numbers, shifting the binary point by one place multiples or divides the number 2. For
example, 111.02 is equal to 710 but 1110.02 is 1410. As seen, 7 is doubled to 14 by moving the binary point
one place to the right.
Similarly, 11.12 is (2 + 1 + ½ ) = 3.510. Hence, 111.02is halved to 3.510 by moving its binary point one place
to the left.
2.3.6 BINARY OPERATIONS
We will now consider the following four binary operations
1. Addition 2. Subtraction
3. Multiplication 4. Division
Addition is the most important of these four operations. In fact, by using complements, subtraction can
be reduced to addition. Most digital computers subtract by complements. It leads to reduction in
hardware because only adding types of circuits are required. Similarly, multiplication is nothing but
repeated addition and, finally, division is nothing but repeated subtraction.
2.3.7 BINARY ADDITION
Addition is simply the manipulation of numbers for combining physical quantities. For example, in the
decimal number system, 2+3=5 means the combination of with to give a total a
Addition of binary numbers is similar to the decimal addition.
Fo11owing points will help in understanding the rules of binary addition.
1. When 'nothing' is combined with nothing, we getnothing.Binary representation of the above

statement is : 0+0=0
2. When nothing is combined with we get In binary languages 0 + 1 = 1
3. Combining with nothing, gives The binary equivalent is 1+0=1
4. When we combine with , we get The binary representation of the above is 1+1=10

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It should be noted that the above sum is not 'ten' but 'one-zero' i.e. it represents and not
In other words, it is 102 which represents decimal 2. It is not decimal ten.
The last rule is often written as 1+1 = 0 with a carry of 1
The above rules for binary addition can be summarized as under:
0+0 = 0
0+1 = 1
1+0 = 1
1+1 = 0 with a carry of 1 = 102
or
It is worth noting that 'carry-overs' are performed in the same manner as in decimalarithmetic. The rules
of binary addition could also be expressed in the form of a table as shown below.
0 1
0 0 1
1 1 102
As an illustration, let us add 101 and 110.
101 -first column 1+0 = 1

+ 110 second column 0+1 = 1
--------- Third column 1+1 = 10
1011 (i.e. 0 with carry 1)
Similarly,
1 carry

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1 1 1 -1st column, 1+0 = 1

+ 110 -2nd column 1+1 = 0 with carry 1
1 1 0 1 -3rd column 1+1+carryof 1 = 10+1=112
Let us consider one more example:
1 carry ←11 carry ←11 carry ←11 carry

1011 1011 1011 1011
+1001 +1001 +1001 +1001
0 00 100 10100
Hence, we find from the above examples that the only two possible combinations with a carry are:
(a) 1+1 = sum of 0 with a carry of 1.It is binary 10 i.e. 102 which equals decimal 2.
(b) 1+1 carry of 1 = a sum of 1 with a carry of 1. It equals binary 11 i.e. 112 of decimal 3.
Example 2.5
Add 1100112 to 1011012
Solution
110011
101101
1100000
1. First column: 1+1 = 0 with a carry of 1. Hence, we put down zero there and carry 1 to the second
column.
2. Second column: 1+0 = 1. But combined with 1 from first column, it gives 1+1 = 0 and a carry of 1.
Hence, we put 0 there and carry 1 further to the thirdcolumn.
3. Third column: 0+1 = 1. Again, when it is combined with carry of 1.. Hence, again, we put down 0 and
carry 1 to the fourth column. 1 from the second column, we get 1+1 = 0 with a carry of 1. Hence, again,
we put down 0 and carry 1 to the fourth column.
4. Fourth column: Here, 0+1 = 1. When combined with carry 1 from third column, we get 1+1 = 0 with a
carry of 1. Hence, we put down 0 there and carry 1 to the fifth column.
5. Fifth column: Here, 1+0 = 1. When combined with the carry 1 from fourth column, we get 1+1 = 0 with
a carry of 1. Hence, we put down 0 there and carry 1 to the sixth column.
6. sixth column: Here, it is a case of 1+1+carry of 1=112 as stated earlier in (b) above.

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2.3.8 BINARY SUBTRACTION
It is also performed in a manner similar to that used in decimal subtraction. Because binary system has
only two digits, binary subtraction requires more borrowing operationsthan decimal subtraction. The
four rules for binary subtraction are as under:
1. 0-0 = 0
2. 1-0 = 1
3. 1-1 = 0
4. 0-1 =1 with a borrow of 1 from the next columnof the minuend
Or 10-1 = 1
The last result represents - = which makes sense.
While using Rule 4, it should be borne in mind that borrow reduces the remaining minuend by 1. It
means that a borrow will cause a 1 in the next column to the left in the minuend to become 0. If the
next column also happens to contain 0, it is changed to a 1 and the succeeding 0s in the minuend are
changed to 1s until a 1 is found which is then changed to a 0.
Example 1
Let us subtract 01012 from 11102. The various steps are explained below :-
01 borrow 01 01 01
1110 1110 11101110
-0101-0101-0101-0101
1 01 001 1001
Explanation
1. In the first column, since we cannot subtract 1 from 0,we borrow 1 from the next column to the
left. Hence,we put down 1 in the answer and change the 1 of thenext left column to a 0.
2. We apply Rule 1 to the next column i.e. 0-0 = 0
3. We apply Rule 3 to the 3rd column i.e. 1-1 = 0
4. Finally, we apply Rule 2 to the last i.e. fourth columni.e. 1-0 = 1
As a check, it may be noted that talking in terms of decimal numbers, we have subtracted 5 from 14.
Obviously, the answer has to be 9 (10012).
Example 2

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Let us now try subtracting 00012 from 10002

Step 1 Step 2 Step 3 Step 4
1 11 011 011
1000 1001 1001 1001
-0001-0001-0001-0001
1 11 011 0111
Since there happened to be a 0 in the second column, it was changed to 1. Again, there was a 0 in the
third column, so it was also changed to a 1. Finally we meet a 1 in the fourth column which was changed
to a 0 and the final answer was written down as shown above.
Example 2.6
Subtract 01112 from 10012.
Solution
1001 1st column: 1-1 = 0

-0111 2nd column: 0:-1 = with a borrow of 1
0010 3rd column: 1 (after borrow) -1 = 0
4th column: 0 (after borrow) -0 = 0
Example 2.7
Subtract 010112 from 101102
Solution
Step-wise the solution is as under:
Step 1 Step 2 Step 3 Step 4 Step 5

0 00 00 0 00 0 00
1011010110 10110 10110 10110
-01011-01011-01011-01011-01011
1 11 011 1011 01011
2.3.9 COMPLEMENT OF A NUMBER
In digital work, two types of complements of a binary number are used for complementary subtraction.
(a) 1's complement
The 1's complement of a binary number is obtained by changing its each 0 into a 1 and each 1
into a 0. Itis also called radix-minus-one complement. For example, 1's complement of 1002 is
0112 and of 11102is00012.

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(b) 2's complement
The 2's complement of a binary number is obtained by adding 1 to its 1's complement.
2's complement = 1's complement + 1
It is also known as true complement. Suppose we areasked to find 2's complement of 10112. Its
1'scomplement is 01002. Next, add 1 to get 01012. Hence, 2's complement of 10112 is 01012.
The complement method of subtraction reduces subtraction to an addition process.
This method is popular in digital computers because
1. Only adder circuits are needed thus simplifying the circuitry
2. It is easy with digital circuits to get the complements.
2.3.10 1'S COMPLEMENTAL SUBTRACTION
In this method, instead of subtracting a number, we add its 1's complement to the minuend. The last
carry (whether 0 or 1) is then added to get the final answer. The rules for subtraction by 1's complement
are as under:
1. compute the 1's complement of the subtrahend by changing all its 1s to 0s and all its 0s to 1s
2. add this complement to the minuend
3. perform the end-around carry of the last 1 or 0
4. if there is no end-around carry (i.e. 0 carry), thenthe answer must be re-complemented and a
negative signattached to it.
5. if the end-around carry is 1, no re-complementing is necessary.
Suppose we want to subtract 1012 from 1112. The procedure is as under:
111
+ 0 1 0 ←1’s complement of 1001 subtrahend 101
1001
1 ←end-round carry
010
As seen, we have removed from the addition sum the 1 carry in the last position and added it onto the
remainder. It is called end-around carry.
Let us now subtract 11012 from 10102.
1010
+0 0 1 0 ←1's complement of 1101
1100 NO CARRY

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As seen, there is no end-around carry in this case. Hence, as per Rule 4 given above, answer must be re-
complemented to get 0011 and a negative sign attached to it. Therefore, the final answer becomes -
0011.
Finally, consider the complemental subtraction of 11102 from 01102.
0110
+ 0 0 0 1 ← 1's complement of 11102
0 1 1 1 NO CARRY
As seen, there is no carry. However, we may add an extra 0 from our side to make it a 0 carry as shown
below.
0110
+0 0 0 1 ← 1's complement
00111
0 ← end-around carry
0111
After re-complementing, it becomes 1000. When negative sign is attached, the final answer becomes -
1000.
Example 2.8
Using 1's complemental method, subtract 011012from 110112.
Solution
11011
+ 1 0 0 1 0 ← 1's complement of subtrahend
101 101
1 ←end-around carry
01110
Since end-around carry is 1, we take the final answer as it is (Rule 5).
Example 2.9
Use 1's complement to subtract 110112 from 011012.
Solution
0 1 101
+ 0 0 1 0 0 ←1's complement of 110112
1 0 0 0 1 →01110

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↑NO CARRY
Since there is no final carry, we re-complement the answer and attach a minus sign to get the final
answer -011102.
2.3.11 2'S COMPLEMENTAL SUBTRACTION
In this case, the procedure is as under:
1. find the 2's complement of the subtrahend

2. add this complement to the minuend
3. drop the final carry
4. if the carry is 1, the answer is positive and needs nore-complementing
5. if there is no carry, re-complement the answer andattach minus sign
Example 2-10
Using 2's complement, subtract 10102 from11012.
Solution
The 1's complement of 1010 is 0101. The 2's complement is 0101 + 1 = 0110. we will add it to
1101.
1101
+ 0 1 1 0 ← 2’s complement of 10102
10011
↑DROP
The final answer is 00112.
Example 2.11
Use 2's complement to subtract 11012 from10102.
Solution
The 1's complement of 1101 is 0010. The 2's complement is 0011:
1010
+ 0 0 1 1 ← 2's complement 11012
1101
↑NO CARRY
In this case, there is no carry. Hence, we have to re-complement the answer. For this purpose, we first
subtract 1 from it to get 1100. Next, we re-complement it to get 0011. After attaching the minus sign,
the final answer becomes-00112.

24
Talking in terms of decimal numbers, we have subtracted 13 from 10. Obviously the answer is -3.
2.3.12 BINARY MULTIPLICATION
The procedure for this multiplication is the same as for decimal multiplication though it is comparatively
much easier. The four simple rules are as under:
1. 0x0=0 2. 0x1=0 3. 1x0=0 4. 1x1=1
As in the decimal system, the procedure is
1. copy the multiplicand when multiplier digit is 1 but not when it is 0

2. Shift as in decimal multiplication
3. Add the resulting binary numbers according to the rules of binary addition.
Example 2.12
Multiply 1112 by 1012 using binarymultiplication method.
Solution
111
x101
111
0 0 0 -shift left, no add
111 -shift left and add
100011
Example 2.13
Multiply 11012 by 11002
Solution
1101
x1 1 0 0
0000
0000
1101
1 1 0 1.
10011100
Example 2.14
Multiply 11112 by 01112.
Solution
This example has been included for the specificpurpose, of explaining how to handle the
addition if multiplication results in columns with more than two 1s.

25
1. Result of the first column is 1.

2. In the second column, addition of 1+1=102.hence, weput down 0 there and carry 1 to the third
column.
3. In the third column, 1+1+1+1 = 1002 (decimal 4). Wekeep one 0 there, put the second 0 in fourth
column andpass on 1 to the fifth column.
4. In the fourth column, 1+1+1+0 = 11 (decimal 3). Hence,one 1 kept there and the other 1 is
passed on to thefifth column.
5. In the fifth column, 1+1+1+1 = 1002 (decimal 4).Again, one 0 is retained there, second 0 is
passed onto the sixth column and 1 to the seventh column.
6. In the sixth column, 1+0=1
7. The seventh column already has 1 given by the additionof the fifth column.
Hence 1111 x 0111 = 1101001
2.3.13 BINARY DIVISION
It is similar to the division in the decimal system. As in that system, here also division by 0 is
meaningless. Rules are:
0
1. 0 / 1 = 0 or 1 = 0
1
2. 1 / 1 = 1 or 1 = 1
Example 2.15
Carry out the binary division 11001 / 101
Solution
101
101√11001
101
10
101
101

26
000
After we bring down that next 0 bit, the number 10 so formed is not visible by 101. Hence, we put a 0 in
the quotient. Therefore, the answer is 1012 (decimal 5).
Incidentally, it may be noted that the dividend is 2510 and divisor is 510 so that the result of division, as
expected is 510.
Example 2-16
Divide 110112 by 1002
Solution
1 1 0.1 1
100√11011
100
101
100
11
110
100
100
100
000
2.3.14 Shifting a Number to Left of Right
Shifting binary numbers one step to the left or right corresponds respectively to multiplication or
division by decimal 2.
When binary number 1011002 (4410) is shifted one step to the Left, it becomes 10110002 which is 8810
i.e. it is doubled.If the given number is shifted one step to the right, it becomes 101102 which is 2210.
Obviously the number is halved.
2.3.15 Representation of Binary Numbers as electrical Signals
As seen from above, any binary number can be represented as a string of 0s and 1s. however, it is fine
for paper and pencil calculations only. Practical problem is how to apply the desired binary information
to logic circuits in digital computers. For that purpose, two types of electrical signals are selected to
represent 1 and 0. Since speed and accuracy are of primary importance in digital circuits, the two
electrical signals chosen to represent 1 and 0 must meet very rigid requirements.
1. they must be suitable for use in high-speed circuitry

2. the signals should be very easy to tell apart
3. They must be hard to confuse with each other.

27
The second and third statements may look alike but they, infact, are not so. It is found that all transistor
circuits distort, to some extent, the electrical signals that pass through. them. Sometime, these distorted
signals can look confusingly alike. Hence, this effect of distortion or degradation has to be kept in mind
while selecting the two signals.
In Fig. 2 are shown several signal pairs that meet the above requirements. It will be noted that it is
impossible to distort a positive pulse (representing) to look like the pulse or negative pulse
(representing).
Fig. 2 shows how signal pairs can be used to represent different binary numbers.
2.4 OCTAL NUMBER SYSTEM
(i) Radix or Base
It has a base of 8 which means that it has eight distinct counting digits:
0, 1, 2, 3, 4, 5, 6 and 7
These digits 0 through 7, have exactly the same physical meaning as in decimal system.
For counting beyond, 7, 2-digit combinations are formed taking the second digit followed by the first~
then thesecond followed by the second and so on., hence after 7, thenext octal number is 10 (second
digit followed by first),then 11 second digit followed by second) and so on. Hence, different octal
numbers are:
0, 1, 2, 3, 4, 5, 6, 7,
10, 11, 12, 13, 14, 15, 16, 17,
20, 21, 22, 23, 24, 25, 26, 27,
30,31,32, … … … … …
(ii) Position Value
The position value (or weight) for each digit is given bydifferent powers of 8 as shown below.
83 828180 .8-18-28-3
octal point
For example, decimal equivalent of octal 352 is
3 5 2
828180
64 8 1 = (3x64)+(5x8)+(2x1) = 23410 .
3528 = 3x82+5x81+2x80 = 192 + 40 + 2 = 23410

28
Similarly, decimal equivalent of octal 127.24 is
127.248 = 1 x 82 + 2 x 81 + 7 x 80 + 2 x 8-1 + 4 x 8-2

2 4
= 64 + 16 + 7 + 8 + 64 = 97.312510
2.4.1 OCTAL TO DECIMAL CONVERSION
Procedure is exactly the same as given in Art. 2-3-1 except that we will use digit 8 rather than 2.
Suppose, we want to convert octal 206.1048 into its decimal equivalent number,Procedure is as under:
2 0 6 1 0 4
82 81 80 8-1 8-2 8-3
206.1048 = 2 x 82 + 6 x 80 + 1x8-1 +4x 8-3

17
= 128 +6 + 1/8 +1/128 = (134 128
) 10
2.4.2 DECIMAL TO OCTAL CONVERSION
The double-dabble method (Art. 2.3.4) is used with 8 acting as the multiplying by for integers and the
dividing factor for fractions.
Let us see how we can convert 17510 into its octal equivalent.
175 / 8 = 21with 7 remainder
21 / 8 = 2 with 5 remainder
2/ 8 = 0 with 2 remainder
Taking the remainders in the reverse order, we get 2578.
17510 =2578
Let us now take decimal fraction 0.15 Its octal equivalent can be found as under:
0.15 x 8 = 1.20 = 0.20 with a carry of 1
0.20 x 8 = 1.60 = 0.60 with a carry of 1
0.60 x 8 = 4.80 = 0.80 with a carry of 4 etc
0.1510 = 0.1148
As seen, here carries have been taken in the forward direction i.e. from top to bottom.

29
Using positional notation, the first few octal numbers and their decimal equivalents are shown in Table
2.2
Table no 2.2
octal decimal octal decimal octal decimal

0 0 12 10 24 20
1 1 13 11 25 21
2 2 14 12 26 22
3 3 15 13 27 23
4 4 16 14 30 24
5 5 17 15 31 25
6 6 20 16 32 26
7 7 21 17 33 27
10 8 22 18 34 28
11 9 23 19 35 29
2.4.3 BINARY TO OCTAL CONVERSION
The simplest procedure is to use binary-triplet method. In this method, the given binary number is
arranged into groups of 3 bits starting from the octal point and then each group is converted to its
equivalent octal number. Of course where necessary extra 0s can be added in front (i.e. left end) of the
binary number to complete groups of three.
Suppose, we want to convert 1010112 into its octal equivalent,converting the bits into groups of three,
we have
101 011
Now, 1012 is 5 octal and 011 is 3 octal.
101 011
5 3 101 0112 = 538
Now, take 1111101112. We will split it into groups of three bits (space is left between the groups for
easy reading). Then, each group is given its octal number as shown below:
111 110 111
7 6 7 111 110 1112 = 7678
Finally, take the example of a mixed binary number 10101.112. Here, we will have to add one 0 in front
of the integral part as well as to the fractional part.

30
010 101 110
2 5 6 10101.112 = 25.68
The equivalence between binary triplets and octal numbers is given in Table 2.3
Table 2.3
binary octal binary octal

000 0 1010 12
001 1 1011 13
010 2 1100 14
011 3 1101 15
100 4 1110 16
101 5 1111 17
110 6 10000 20
111 7 10001 21
1000 10 10010 22
1001 11 10011 23
2.4.4 OCTAL TO BINARY CONVERSION
The procedure for this conversion is just the opposite of that given in Art 2.4.3. Here, each digit of the
given octal number is converted into its equivalent binary triplet. For example, to change 758 into its
binary equivalent, proceed as under:
7 5
111 101 758 = 111 1012
Similarly, 74.5628 can be converted into binary equivalent as under:
7 4 5 6 2
111 100 101 110 010 74.5628 = 111100.101 110 0102
Incidentally, it may be noted that number of digits in octal numbers is one-third of that in equivalent
binary numbers. In the present case, it is five versus fifteen.
2.4.5 ADVANTAGES OF OCTAL NUMBER SYSTEM
The chief advantage of this system is that its numbers are one-third in length as compared to binary
numbers. Hence, from the user's i.e. computer operator’s point of view, it would be comparatively much
easier to handle the input and output data of a digital computer in octal form. Moreover, the print-outs
are more compact and easy to read. Additionally, conversion from binary-to-octal and octal-to-binary is
quick and simple. In fact, octal numbersare used to represent binary numbers because of ease
ofconversion and compactness.

31
2.5 HEXADECIMAL NUMBER SYSTEM
The characteristics of this system are as under:
1. it has a base of 16. Hence, it uses sixteen distinct counting digits 0 through 9 and A through F as
detailedbelow:
0,1, 2, 3, 4, 5, 6, 7,8,9,A, B, C, D, E, F
2. place value (or weight) for each digit is in ascendingpowers of 16 for integers and descending
powers of 16for fractions.
The chief use of this system is in connection withbyte-organized machines. It is used for specifying
addressesof different binary numbers stored in computer memory.
2.5.1 HOW TO COUNT BEYOND F IN HEX NUMBER SYSTEM
As usual, we resort to 2-diqit combinations. After reaching F, we take the second digit followed by the
first digit, thensecond followed by second, then second followed by third asso on. The first few 'hex'
numbers and their decimalequivalents are given in Table 2.4.
Table No. 2.4
hexadecimal decimal hexadecimal decimal hexadecimal decimal

0 0 B 11 16 22
1 1 C 12 17 23
2 2 D 13 18 24
3 3 E 14 19 25
4 4 F 15 1A 26
5 5 10 16 1B 27
6 6 11 17 1C 28
7 7 12 18 1D 29
8 8 13 19 1E 30
9 9 14 20 1F 31
A 10 15 21 20 32
2.5.2 BINARY TO HEXADECIMAL CONVERSION
The simple method is to split the given binary number into 4-bit groups (supplying 0s from our own side
if necessary) and then give each group its 'hex' value as found from Table 2.5

32
Table No. 2.5
binary hex binary hex binary hex

0000 0 0110 6 1100 C
0001 1 0111 7 1101 D
0010 2 1000 8 1110 E
0011 3 1001 9 1111 F
0100 4 1010 A 10000 10
0101 5 1011 B 10001 11
Let us see how we would convert 100011002 into its hexadecimal equivalent number. We will first split
the given binary number into 4-bit groups and then give each group its proper value from Table 2.5.
1000 1100
8 C 100011002 = 8C16
Let us now consider 10110101112. Following the above procedure, we have
0010 1101 0111
2 D 7 10110101112 = 2D716
It is seen that two 0s have been added to complete the 4-bit groups.
2.5.3 HEXADECIMAL TO BINARY CONVERSION
Here, the procedure is just the reverse of that given in Art 2.5.2. Each hexadecimal digit is converted into
its equivalent 4-bit binary.
Suppose, we want to convert 23A16 into its binary equivalent. It can be done as given below :
2 3 A
0010 0011 1010 23A16 = 0010 0011 10102
Incidentally, hex numbers contain one-fourth the number of bits contained in the equivalent binary
number. Optionally, we could drop off the two 0s in front of the binary equivalent.
2.5.4 DECIMAL TO HEXADECIMAL CONVERSION
Two methods are available for such a conversion. One is to go from decimal to binary and then to
hexadecimal. The other method called hex-dabble method is similar to the double-dabble (or divide-by-
two) method of Art 2.3.4 except that we use 16 (instead of 2) for successive divisions. As an example, let
us convert decimal 1983 into hexadecimal by consulting Table No. 2.4 for remainders.

33
1983 / 16 = 123 + 15 → F
123 / 16 = 7 + 11 → B
7 / 16 = 0 + 7 →7
Hence 198310 = 7BF16
2.5.5 HEXADECIMAL TO DECIMAL CONVERSION
Two methods are available for such a conversion. One is to convert from hexadecimal to binary and then
to decimal. The other direct method is as follows:
Instead of using powers of 2, use powers of 16 for the weights. Then, sum up the products of
hexadecimal digits and their weights to get the decimal equivalent. As an example, let us convert F6D9
to decimal.
F6D9 = F(163) + 6(162 )+ D(161) + 9(160)
= 15 x 163 + 6 x 162 + 13 x 161 + 9 x 160
= 61,440 + 1536 + 208 + 9 = 63,19310
Example 2.17
Find the binary, octal and hexadecimal equivalents of the following decimal numbers
(i) 32 (ii) 256(iii) 51.
Solution
(i) Decimal number 32

As seen from Art: 2.3.4 32 16842 1
10000 0 3210 = 1000002
For octal conversion: 100 000
4 0 3210 = 408
For hexadecimal conversion 0010 0000
2 0 3210 = 2016
As will be seen, the binary number has been divided into two 4-bit groups for which purpose two 0s
have been added to the left.
(ii) In the same way, it can be found that 25610 =1000000008 = 10016

34
(iii) Also, 5110 = 1100112 = 638 = 3316
Example 2.18
Convert the following number to decimal
(i) (110101)2(ii) (AB60)16(iii) (777)8
Solution
(i) For binary to decimal conversion, we will followthe procedure given in 2.3.1.
11010
1684 2 1 110102 = 16 + 8 + 2 = 2610
(ii) Following the procedure given in Art. 2.2, we have,
AB6016 = A (163)+B(162)+ 6(161)+0(160)
= 10x163+11x162+6x161+0x160
= 4387210
(iii) As per the procedure given in Art 2.4.1,
7778 = 7(82) + 7(81) + 7(80)
= 51110
Example 2.19
A computer is transmitting the following groupsof bytes (each consisting of 8-bits) to some
output device. Give the equivalent octal and hexadecimal listings.
1000 1100 0011 1010
0010 1110 1001 0101
0101 1111 1011 0110
0111 1011 0101 1011
Solution
binary octal hexadecimal

1000 1100 10 001100 1000 1100
2 1 4 8 C
0010 1110 00 101110 0010 1110
0 5 6 2 E

35
0101 1111 01 011111 0101 1111

1 3 7 5 F
0111 1011 01 111 011 0111 1011
1 7 3 7 B
0011 1010 00 111 010 0011 1010
0 7 2 3 A
1001 0101 10 010 101 1001 0101
2 2 5 9 5
1011 0110 10 110 110 1011 0110
2 6 6 B 6
0101 1011 01 011 011 0101 1011
1 3 3 5 B
Hence, the groups of given memory bytes when expressed in different number systems becomes as
under:
binary octal hexadecimal

10001100 214 8C
00101110 056 2E
01011111 137 5F
01111011 173 7B
00111010 072 3A
10010101 225 95
10110110 266 B6
01011011 133 5B
It is clear from above that so far as the computer operator (or programmer) is concerned; it is much
easier to handle this data when expressed in octal or hexadecimal system than in the binary system. For
example, it is much easier and less error-prone to write the hexadecimal 8C than the binary 10001100 or
6AF than 011010101111. Of course, when the need arises, the operator can easily convert from octal or
hexadecimal to binary.
2.6 DIGITAL CODING
In digital logic circuits, each number or piece of information is defined by an equivalent combination of
binary digits. A complete group of these combinations which represents numbers, letters or symbols is
called a digital code.
Codes have been used for security reasons so that others may not be able to read the message even if it
is intercepted. In modern digital equipment, codes are used to represent and process numerical
information. The choice of a code depends on the function or purpose it has to serve. Some codes are

36
suitable where arithmetic operations are performed whereasothers have high efficiency i.e. they give
more information using fewer bits.
In certain applications, use of one code or the other simplifies and reduces the circuitry required to
process the information. By limiting the switching circuitry, reliability of the digital system is increased.
Of continuing importance are other codes which allow for error detection or correction. These codes
enable the computers to determine whether the information that was coded and transmitted is
received correctly and, if there is an error, to correct it. Since coding, itself is a detailed subject, only a
few of the more familiar codes will be discussed.
2.6.1 BINARY CODED DECIMAL (BCD) CODE
It is a binary code in which each decimal digit is represented by a group of four bits. Since the right-to-
left weighting of the 4-bit positions is 8-4-2-1, it is also called an 8421 code. It is a weighted numerical
code. As said above, here each decimal digit from 0 through 9 requires a 4-bit binary-coded number. For
example, the decimal number 35 in BCD code is 0011 0101. The coding of ten decimal digits is given in
Table No. 2-6. Lest you think that BCD code is the same thing as binary numbers, consider the following.
Table 2.6
decimal BCD
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
In the binary system, ten is represented by 1010 but in BCD code, it is 0001 0000. 17 in binary is 10001
but inBCD code it is 0001 0111. See the difference! Actually, theconfusion is due to the ,fact that the
first nine numbers in BCD and binary are exactly similar (Table No, 2.7). After -7that, they become quite
different (Table No. 2-7).
Table 2.7
decimal BCD
26 0010 0110
59 0101 1001
673 0110 0111 0011
2498 0010 0100 1001 1000

37
It should be realized that with four-bits, sixteen numbers(24) can be represented although in the BCD
code only ten ofthese are used. The following six combinations are invalid in the BCD code: 1010, 1011,
1100,1101,1110 and 1111.
The main advantage of BCD code is that it can be read and recognized easily although special address
are needed for arithmetic operations.
Any decimal number can be expressed in BCD code by replacing each decimal digit by the appropriate 4-
bit combination.Conversely, a BCD number can be easily converted into adecimal number by dividing
the coded number into groups of four bits (starting with LSB) and then writing down thedecimal digit
represented by each four-bit group.
Example 2-20
Write the decimal number 369 in BCD code.
Solution
For writing this 3-digit number in BCD, the valueof each digit must be replaced by its 4-bit
equivalent fromthe BCD code. From Table No. 2.6, we get
3 = 0011, 6 = 0110, 9 = 1001 36910 =001101l01001BCD
Example 2-21
Find the equivalent decimal value for the BCDcoded number 0001010001110101.
Solution
Starting from the LSB, the given number can bedivided into groups of four bits as 0001 0100
0111 0101. Asseen from Table No. 2.6,
0001 = 1, 0100 = 4, 0111 = 7 and 0101 = 5
Hence, 0001010001110101BCD = 147510
Example 2.22
(a) Convert the hexadecimal number F8E6 to thecorresponding decimal number.
(b) Convert the decimal number 2479 to the correspondinghexadecimal number
(c) Encode the following decimal numbers into 8421 BCDnumbers (i) 59 (ii) 39 and (iii) 584.
(d) Decode the following 8421 BCD numbers (i) 0101 (ii)0111.

38
Solution
(a) F8E6 = F(163) + 8(162) + E(161) + (160)

= 15 x 163 + 8 x 162 + 14 x 161 + 6 x 160 = 63,71810
(b) We would use the hex-dabble method explained in Art. 2.5.4
2479/ 16 = 154 + 15 → F
154 /16 = 9 + 10→ A
9 / 16 = 0+9→9
247910 = 9AF16
(c) As seen from Table No. 2.6
59 39 584
0101 1001 0011 1001 0101 1000 0100
(d) Again, consulting Table No. 2.6, we have
0101 0111
5 7
2.6.2 OCTAL CODING
It involves grouping the bits in three's. For example, (1756)8 = (001 111 101110)2 = (001111101110)2.
Similarly, the 24-bit number stored in the computer memory such as 101 010 011 100 010 111 000 110
can be read in the octal as
101 010 011 100 010 111000 110
52342706
Apart from ease of recognition and conversion to binary, one important feature of the octal code is that
its numbers are straight binary numbers which can be manipulated mathematically. For example, octal
25 expressed in octal is 010 101 which can be read as binary 010101
(25)8 = 2 x 81+ 5 x 80 = (21)10
(010101)2 = 0 x 25 + 1 x 24 + 0 x 23 + 1 x 22 +0 x21+1 x 20 = (21)10
You might recall that in BCD code, the resulting number is always a 4-bit group and a special adder is
needed to convert it into decimal.In octal coding, 3-bit grouping is used but the resulting binary number
can be considered a single numberin natural binary form.

39
2.6.3 HEXADECIMAL CODING
The advantage of this coding is that four hits are expressed by a single character. However, the
disadvantage is that new symbols have to be used to represent the values from 1010 to 1111 binary. As
seen from Table No. 2-3, the binary number 1010 0101 is hex number A5. Similarly, hexadecimal
number C7 is (11000111)2. To prove that the resulting binary number is the same as the hexadecimal
value, consider the following example:
(3D)16 = 3 x 161 + D x 160
= 3 x 16 + 13 x 1 = (61)10
(3D)16 = (00111101)2 = 1 x 25 + 1 x 24 + 1 x 23 + 1 x 22 + 0 x 21+ 1 x 20 = (61)10
2.6.4 EXCESS-3 CODE
It is an un-weighed code and is a modified form of BCD. It is widely used to represent numerical data in
digital equipment. It is abbreviated as XS-3. As its name implies, each coded number in XS-3 in three
larger than in BCD code. For example, six is written as 1001. As compared to BCD, the XS-3 has poorer
recognition but it is more desirable for arithmetic operations. A few numbers using Excess-3 code are
given in, Table 2-8.
Table No. 2.8
decimal XS-3
3 0110
26 0101 1001
629 1001 0101 1100
3274 0110 0101 1010 0111
2.6.5 GRAY CODE
It is an un-weighed code to number 0 through 9 and is largely used in mechanical switching systems. As
seen from Table No. 2.9, only a single bit changes between each successive word. Because of this, the
amount of switching is minimized and the reliability of the switching system is improved.
Table No. 2.9
binary gray XS-3 gray

0 0000 0010
1 0001 0110
2 0011 0111
3 0010 0101
4 0110 0100
5 0111 1100
6 0101 1101

40
7 0100 1111
8 1100 1110
9 1101 1010
2.6.6 EXCESS-3 GRAY CODE
It is shown in Table No. 2-9 and is the original gray code shifted by three binary combinations. It exhibits
the same properties as the Gray code.
Example 2.23
Express the number 4310 in XS-3 code.
Solution
Let us first represent each decimal digit by its4-bit XS-3 code.
4 = 0111, 3 = 0110 4310 = 01110110XS-3
Example 2.24
The number 0110 1001 is expressed in XS-3 code. What is its decimal value?
Solution
Starting from least significant bit (LSB), thegiven number is first separated into groups of four
and theneach group is replaced by its equivalent value i.e. actual value decreased by 3.
0110 = 6 -3 = 3; 1001 = 9 -3 = 6 01101001XS-3 = (36)10
2.6.7 OTHER CODES
Some of the other codes which are presently popular are given below:
(a) 4-bit codes
The different 4-bit weighted BCD codes for decimal numbers 0 through 9 in use are: 5421, 2*421, 7421,
7421 etc. and are tabulated below:
Table No. 2.10
decimal 5421 2*421 7421 7421

0 0000 0000 0000 0000
1 0001 0001 0001 0111
2 0010 0010 0010 0110
3 0011 0011 0011 0101
4 0100 0100 0100 0100
5 1000 1011 0101 1010

41
6 1001 1100 0110 1001

7 1010 1101 1000 1000
8 1011 1110 1001 1111
9 1100 1111 1010 1110
(b) 5-bit Codes
i) 2-out-of-5 code is an un-weighed BCD code andallows easy error detection. It has been used
in communications and telephone operation.
ii) 51111 Code is a weighted BCD code and is much easier to operate with electronic circuitry.
iii) Shift-counter (Johnson) Code is an un-weighed BCD and because of its pattern is
easilyoperated on with electronic circuitry.
(c) 7-bit Binary Code -it uses a group of seven bits to represent decimal pattern is easily operated on
withelectronic circuitry.
(d) Ring-counter Code -it is also called 10-bit code because it uses a group of 10 bits to represent a
decimal number. Though it requires as many as 10 positions, the ease of error detection with the
code and of operating electronic circuits to implement the code makes it quite attractive.
(e) Alphanumeric Codes -these binary codes are used to represent both alphabetic and numeric
characters.Different codes are used to represent alphanumeric data stored on paper tape, punched
card or magnetic tape for use by a line printer or typewriter. One of these is ASCII (American
Standard Code for Information Interchange) which is frequently used by input/output (I/O
equipment. Another similarly I/O-oriented code is EBCDIC (Extended Binary Coded Decimal
Interchange Code).
2.7 TUTORIA1 PROBLEMS
1. Find the decimal equivalents of the following binary numbers: (a) 101 (b) 1001 (c) 10-011
2. What are the decimal equivalents of the following binary numbers?
(a) 1111 (b) 10100 (c) 1101101(d) 10011001
3. Express the following binary numbers into theirequivalent decimal numbers:
(a) 11.01 (b) 101.11 (c) 110.01
4. Convert the following decimal numbers into their binaryequivalents:
(a) 25 (b) 125 (c) 0.85
5. What are the binary equivalents of the followingdecimal numbers?
(a) 27 (b) 92 (c) 64

42
6. Perform the, following binary additions:-
(a) 1011+1001 (b) 1011+110 (c) 101101+1101101(d) 1011.01+1001.11
(e) 0.0011+0.1110 (f) 1111+111+1111
7. Add the following binary numbers 1011 and 1001
8. Perform the following binary subtractions
(a) 1101-1011 (b) 111-101 (c) 1000-11 (d) 101011-10010
9. Carry out the following subtractions using binarynumber system:
(a) 6410-3210 (b) 12810-6410 (c) 93.510-42.7510(d) 710-1110
10. Subtract the following binary numbers: 100011-111010
11. Find the 1’s complements of the following binary numbers:
(a) 01101 (b) 1101 (c) 1001 (d) 1010
12. What are 2's complements of the following binary numbers?
(a) 1011 (b) 11011 (c) 11011.01 (d) 10011.11
13. Use the 1's and 2's complements to perform the following binary subtractions:-
(i) 1111-1011 (ii) 110011-100101 (iii) 100011-11101
14. Multiply the fol1owinq binary numbers:-
(a) 1100 x 101 (b) 10101x 101 (c) 10111x101 (d) 1110x111
15. Perform the following binary numbers:-
(a) 11011 100 (b) 1110011 101 (c) 1100010 111
16. Convert the following binary numbers into their octal equivalents:-
(a) 1001 (b) 11 011 (c) 10 101 111 (d) 1101.0110111 (e) 11 111 011 110 101
17. Convert the under given octal numbers into their binary equivalents:-
(a) 13 (b) 11 (c) 713 (d) 3614
18. Convert the following numbers:-
(a) 3578 to decimal (b) 64218 to decimal (c) 135910 to octal (d) 777710 to octal

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19. Convert the following real numbers to the binary numbers:-
(i) 12.0 (ii) 25.0 (iii) 0.125
20. Convert the following binary numbers into their equivalent hexadecimal numbers:-
(a) 1101 0111 (b) 1010 0110 (c) 1001 1110(d) 1100 1111
21. Convert the following decimal numbers to binarynumbers by converting them to octal, then
tobinary:-
(i) 850 (ii) 7563
21. Convert the following numbers to decimal :-
(i) (11010)2 (ii) (777)8
22. Convert the following numbers to decimal:
(i) (11010)2 (ii) (777)8

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BASIC LOGICAL CIRCUITS
CONTENTS
3.1. INTRODUCTION LOGIC
3 .1 .1 BOOLEAN ALGEBRA
3.2. KARNAUGH MAP METHOD
3.3. SIMPLIFICATION OF BOOLEAN FUNCTIONS
3.4. THE BASIC LOGIC GATES
3.5. THE USE OF NAND/NOR GATES TO GENERATE AND/OR FUNCTIONS
3.6. EXERCISES

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3.1. INTRODUCTION TO LOGIC
Logic circuits operate on signals which are binary in nature, i.e. signals which take one of two possible
voltage levels. Both signal levels are indicated by the binary digits 0 and 1. When the level that
corresponds with 1 is more positive than the level that corresponds with 0, then we talk about positive
logic. In the opposite case we talk about negative logic. See also Fig. 3.1 for explanation of this concept.
Throughout this chapter we will assume positive logic.
3.1.1. BOOLEAN ALGEBRA
All signal operations performed in digital circuitry can be reduced to combinations of three fundamental
operations. These three fundamental operations correspond with elementary so called logical
operations known in Boolean algebra. In this algebra only two numbers are known, coded by 0 and 1.
Each Boolean variable can only take either of these values and no other one.
LOGIC OPERATIONS
The three basic logical operations known in Boolean algebra are:-
i) AND, represented by a dot (•) (sometimes omitted).

ii) OR, represented by a plus sign (+) and,
iii) NOT, normally represented by a dash drawn on top of thesymbol but in this text
represented by an asterisk such as X* to represent NOT X.
The NOT operator is also known as the "negation" or "complement" operator.
The operations are defined as follows:-
AND OR NOT
0•0=0 0+0=0
0•1=0 0+1=1 0* =1
1•0=0 1+0=1 1* =0
1•1=1 1+1=1
Table 1.

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Now, logic functions of binary variables can be written down with the help of the three defined logical
operations. It is these Logical functions which form the base of digital circuitry.

47
Postulates of Boolean Algebra
1. Postulate [P1]
For every
2. Postulate [P2]
Substitution law
3. Postulate [P3]
Identity law 𝑎 + 0 = 𝑎 𝑎 • 1 = 𝑎
4. Postulate (P4)
Commutative Law
𝑎 + 𝑏 = 𝑏 + 𝑎
5. Postulate (P5)
Associative law
𝑎 + (𝑏 + 𝑐) = (𝑎 + 𝑏) + 𝑐
𝑎 • (𝑏 • 𝑐) = (𝑎 • 𝑏) • 𝑐
6. Postulate [P6] Distributive law
𝑎 + (𝑏 • 𝑐) = (𝑎 + 𝑏) • (𝑎 + 𝑐)
𝑎 • (𝑏 + 𝑐) = (𝑎 • 𝑏) + (𝑎 • 𝑐)
7. Postulate [P7] Complement law
𝑎 + 𝑎̅ = 1
𝑎 • 𝑎̅ = 0
THEOREMS OF BOOLEAN ALGEBRA
8. Theorem [T8] Idem potency
𝑎 + 𝑎 = 𝑎
𝑎 • 𝑎 = 𝑎
Proof 𝑎 + 𝑎 = 𝑎 + 𝑎
= (𝑎 + 𝑎)1 P3
= (𝑎 + 𝑎)(𝑎 + 𝑎̅) P7
= 𝑎 + 𝑎 𝑎̅ P6
= 𝑎 + 0 P7
= 𝑎 P3
9. Theorem [T9] Identity

𝑎 + 1 = 1
𝑎 • 0 = 0

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10. Theorem [T10] Absorption

𝑎 + 𝑎𝑏 = 𝑎
𝑎 • (𝑎 + 𝑏) = 𝑑
11. Theorem [T11]
𝑎 + 𝑎̅𝑏 = 𝑎 + 𝑏 Part (a)
𝑎 (𝑎̅ + 𝑏) = 𝑎𝑏 Part (b)
Proof Part (b)
𝑎(𝑎̅ + 𝑏) = 𝑎(𝑎̅ + 𝑏)
= 𝑎𝑎̅ + 𝑎𝑏 P6
= 0 + 𝑎𝑏 P7
= 𝑎𝑏 + 0 P4
= 𝑎𝑏 P3
12. Theorem [T12] Consensus
𝑎𝑏 + 𝑎̅𝑐 + 𝑏𝑐 = 𝑎𝑏 + 𝑎̅𝑐
(𝑎 + 𝑏)(𝑎̅ + 𝑐)(𝑏 + 𝑐) = (𝑎 + 𝑏) (𝑎̅ + 𝑐)
Proof
𝑎𝑏 + 𝑎̅𝑐 + 𝑏𝑐 = 𝑎𝑏 + 𝑎̅𝑐 + 𝑏𝑐
= 𝑎𝑏 + 𝑎̅𝑐 + 1 • 𝑏𝑐 P3
= 𝑎𝑏 + 𝑎̅𝑐 (𝑎 + 𝑎̅) 𝑏𝑐 P7
= 𝑎𝑏 + 𝑎̅𝑐 + 𝑎𝑏𝑐 + 𝑎̅𝑏𝑐 P6
= (𝑎𝑏 + 𝑎𝑏𝑐) + (𝑎̅𝑐 + 𝑎̅𝑏𝑐)
= 𝑎𝑏 + 𝑎̅c T10
13. Theorem [T13]
𝑎𝑏 + ̅̅̅
𝑎𝑏 = 𝑎
(𝑎 + 𝑏) ((𝑎 + 𝑏) ̅) = 𝑎
14. Theorem [T14]
𝑎𝑏 + 𝑎𝑏𝑐 = 𝑎𝑏 + 𝑎𝑐 (1)
(𝑎 + 𝑏) + (𝑎 + 𝑏 + 𝑐) = (𝑎 + 𝑏) + (𝑎 + 𝑐) (2)

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Proof (1)
𝑎𝑏+𝑎𝑏𝑐 = 𝑎𝑏 + 𝑎𝑏𝑐
= 𝑎(𝑏 + 𝑏𝑐) P6
= 𝑎(𝑏 + 𝑐) T11
= 𝑎𝑏 + 𝑎𝑐 P6
15. Theorem T14
𝑎𝑏 + 𝑎̅𝑐 = (𝑎 + 𝑐) (𝑎 + 𝑏)
(𝑎 + 𝑏) (𝑎̅ + 𝑐) = 𝑎𝑐 + ̅𝑎𝑏
Proof: this theorem is very useful for changingthe form of Boolean expression
𝑎𝑏 + 𝑎̅𝑐 = 𝑎𝑏 + 𝑎̅𝑐
= (𝑎𝑏 + 𝑎̅) (𝑎𝑏 + 𝑐) P6
= (𝑎 + 𝑎̅) (𝑏 + 𝑎̅) (𝑎 + 𝑐) (𝑏 + 𝑐) P6
= 1 • (𝑏 + 𝑎̅)(𝑎 + 𝑐)(𝑏 + 𝑐) P3
= (𝑏 + 𝑎̅) (𝑎 + 𝑐) T13
3 .2. KARNAUGH MAP METHOD
The Karnaugh map is a variation of the truth table. The technique provides a systematic method for
simplifying and manipulating Boolean expressions. Although the technique may be used for any number
of variables, it is seldom used for more than six, and four variables will be the maximum number
presented here.
1. TWO VARIABLE K-MAP
The cells represent all the unique combinations of the two variables A and B.

50
In a K-map it is usual to indicate only the logic '1' conditions,all other empty cells beingunderstood to
correspond to the Boolean functions being logic '0'.
example 1
(i) 𝑙𝑒𝑡 𝐹 = 𝐴𝐵̅ + 𝐴̅𝐵̅
K-map of the expression 𝐹 = 𝐴𝐵̅ + 𝐴̅𝐵̅
The two adjacent is on the map can be grouped together and expressed simply as the logical expression.
Map = B i.e. the variable does not change as we move from one cell to the other (adjacent 1s)
As verification
𝐹 = 𝐴𝐵̅ + 𝐴̅𝐵̅ = 𝐵̅(𝐴̅ + 𝐴)
Since𝐴 + 𝐴̅ = 1
= 𝐵̅
ii) 𝐿𝑒𝑡 𝑀 = 𝐴̅𝐵̅ + 𝐴𝐵̅ + 𝐴𝐵
K-map of the expression 𝑀 = 𝐴̅𝐵̅ + 𝐴𝐵̅ + 𝐴𝐵
If the adjacent 1s are combined, the map function becomes
𝑀 = 𝐴 + 𝐵̅
which is obviously simpler than the original expression.

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2. THREE-VARIABLE K-MAP
For three variables there are eight (23) possible combinations. AK-map for three variables is shown
below.
The rules for simplification usingthree-variables K-map are as follows:
1. A group of four adjacent cells can be combined to represent a single variable.

2. A group of two adjacent cells can be combined to representa two-variable term.
3. A single cell represents a three-variable term.
Example 2
(i) Use a K-map to simplify the Boolean expression
𝐷 = 𝐴𝐵𝐶̅ + 𝐴̅𝐵𝐶 + 𝐴𝐵̅𝐶̅ + 𝐴𝐵̅𝐶 + 𝐴𝐵𝐶
The map is obtained by plotting the 1s corresponding to each term of the given expression.
Grouping adjacent 1s in groups of four and groups of two a simplified expression is obtained
𝐷 = 𝐴 + 𝐵𝐶
ii) Plot a K-map for the following Boolean expression𝑌 = 𝐵 + 𝐴̅𝐶̅ + 𝐴𝐶

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The rules for operating with a four-variable K-map are as follows:
1. A grouping of eight adjacent cells represents a singlevariable term.

2. A grouping of four adjacent cells represents a two-variableterm.
3. A grouping of two adjacent cells represents athree-variable term.
4. Individual cells represent a four-variable term.
𝐹 = 𝐴̅ + 𝐶̅ + 𝐷
̅
HAZARDS
Hazards causing possible malfunction of a combination logic circuit can occur due to the non-ideal
nature of the devices used to implement the logic function. During transition times of a binary signal,
the conditions 𝑋 = 𝑋̅ = 1 or 𝑋 = 𝑋̅ = 0 may exist briefly. A hazard may thus exist when two signals
controlling a single gate both change as a result of a single variable change, but gate output signal is
required to remain unchanged.
Consider the function 𝐹 = 𝐴. 𝐵 + 𝐴̅. 𝐶the map of which is shown below

53
A hazard occurs when a change of value of a variable causes amovement between two states not in the
same group, e.g., between ABC = 011 and ABC = 111.
The hazard is eliminated by grouping the '1' squares between which the movement exists. Thus in this
case the hazard is eliminated by generating F as:
𝐹 = 𝐴. 𝐵 + 𝐴. 𝐶 + 𝐵. 𝐶
It is ironic that if F is mapped in order to reduce its implementation to 'minimum' form then the term
B.C would be eliminated as being 'redundant'.
Example 4
𝑓(𝑋, 𝑌, 𝑍) = 𝑋𝑌(𝑍 + 𝑌𝑋) + 𝑌𝑍
= 𝑋𝑌𝑍 + 𝑋𝑌𝑌𝑋 + 𝑌𝑍 [P6 (b)]
= 𝑋𝑌𝑍 + 0 + 𝑌𝑍 [P7(b)]
= 𝑋𝑌𝑍 + 0 + 𝑌𝑍 [P3(a)]
= 𝑋𝑌𝑍 + 𝑌𝑍 [T15(a)]
= 𝑋𝑍 + 𝑌𝑍 [P6(b)]
= (𝑋 + 𝑌)𝑍 [P6(b)]
= 𝑋𝑌𝑍 [T12(b)]
Either of the last two forms has three literals, the minimum number possible.
Example
Consider now a function of four variables with 13 literals:
𝑓(𝐴, 𝐵, 𝐶, 𝐷) = 𝐴𝐵𝐶 + 𝐴𝐵𝐷 + 𝐴𝐵𝐶 + 𝐶𝐷 + 𝐵𝐷
= 𝐴𝐵𝐶 + 𝐴𝐵 + 𝐴𝐵𝐶 + 𝐶𝐷 + 𝐵𝐷 [T15(a)]
= 𝐴𝐵𝐶 + 𝐴𝐵 + 𝐵𝐶 + 𝐶𝐷 + 𝐵𝐷 [15(a)]
= 𝐴𝐵 + 𝐵𝐶 + 𝐶𝐷 + 𝐵𝐷 [10(a)]
= 𝐴𝐵 + 𝐶𝐷 + 𝐵(𝐶 + 𝐷) [P6(b)]
= 𝐴𝐵 + 𝐶𝐷 + 𝐵𝐶𝐷 [T12(b)]
= 𝐴𝐵 + 𝐶𝐷 + 𝐵 [T11(a)]
= 𝐵 + 𝐶𝐷 [T10(a)]

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In this example we have reduced the number of literals from 13 to 3.
Example 5
𝑓(𝐴, 𝐵, 𝐶, 𝐷, 𝐸) = 𝐴𝐵 + 𝐴𝐶𝐷𝐸 + 𝐵𝐶𝐷
= 𝐴𝐵 + 𝐴𝐶𝐷𝐸 + 𝐵𝐶𝐷𝐸 + 𝐵𝐶𝐷 [T13(a)]
= 𝐴𝐵 + 𝐴𝐶𝐷𝐸 + 𝐶𝐷𝐸 + 𝐵𝐶𝐷 [T15(a)]
= 𝐴𝐵 + 𝐶𝐷𝐸 + 𝐵𝐶𝐷 [T10(a)]
In the last example we began with 9 literals, expanded to 13, and finally reduced the answer to 8 literals.
As a final example of expansion to achieve literal reduction, consider the following:
Example 6
𝑓(𝐴, 𝐵, 𝐶, 𝐷, 𝐸) = (𝐴 + 𝐵 + 𝐶) (𝐴 + 𝐵 + 𝐷 + 𝐸) (𝐶 + 𝐷)
= (𝐴 + 𝐵 + 𝐶) (𝐴 + 𝐵 + 𝐶 + 𝐷 + 𝐸) (𝐶 + 𝐷) [T15(b)]
= (𝐴 + 𝐵 + 𝐶) (𝐶 + 𝐷) [T10(b)]
In this example Theorem 15(b) is used to insert the variable C into the second term, which allows it to be
absorbed by the last term.
3.3 SIMPLIFICATION OF BOOLEAN FUNCTIONS
For any given Boolean function we may attempt to reduce or simplify the function to obtain some
desired goal or to satisfy some criteria. A common goal to seek is the reduction of the number of literals
in the expression representing a Boolean function. A literal is defined as each occurrence of a variable or
complemented variable in a Boolean expression. The concept of a literal is best described by example.
1. 𝑓(𝑋, 𝑌, 𝑍) = 𝑋𝑌(𝑍 + 𝑌𝑋) + 𝑌𝑍. This function has seven literals.
2. 𝑔(𝐴, 𝐵, 𝐶) = 𝐴𝐵 + 𝐴𝐵 + 𝐴𝐶. This function has six literals.
He may apply the postulates and theorems of Boolean algebra to these functions to try to eliminate
literal occurrences.
3.4. THE BASIC LOGIC GATES
The electronic logic circuit or gate is a circuit that is able to operate on a number of input binary signals
in order to perform a particular logical function the logic gate is one of the basic.
Building blocks from which many different kinds of logical system can be constructed. A number of
different types of gate exist, the most common of which are the AND, OR, NOT, NAND, NOR and the

55
exclusive OR gate. The circuit symbols of these gates together with the logical function they perform are
given in (3.2).
The AND GATE
The AND gate is a logic element having two or more input terminals and only one output Terminal. The
output logic state is 1 onlywhen all of the inputs are at logic 1. If anyone or more of the inputs is at logic
1. If anyone or more of the inputs is atlogic 0, the output state will also be at logic 0.
Using Boolean, algebra the output F of an AND gate with threeinputs A, Band C can be written down as
𝐹 = 𝐴. 𝐵. 𝐶. (1)
since in Boolean algebra the symbol for the AND logical function is the dot (•).
The operation of any logical element can be described by means oftruth table. This is a table which
shows the output state of thecircuit for all the possible combinations of input states. The truth table of a
3-input AND gate is given by table 2. It is clear from the table that the output is 1 only when A AND B
AND Cis 1.
A 0 1 0 1 0 1 0 1
B 0 0 1 1 0 0 1 1
C 0 0 0 0 1 1 1 1
f 0 0 0 0 0 0 0 1
TABLE 2. TRUTH TABLE OF 3 -INPUT AND GATE
The AND gate can be used to enable and inhibit a digital signal.since the output of a 2-input AND gate
will be 1 only if both itsinputs A and B are 1, a control signal applied to, say, input A can control the
passage of a signal applied to, say, input A can control the passage of a signal applied to input B. When
input A is at the logic 1 level, it will allow, or enable, the signal applied to B to pass to the output. Very
often the controlled signal is a regularly occurring pulse waveform derived from acircuit known as the
clock. An example of this technique is shownin Fig. 3.3.

56
THE OR-GATE
The OR gate has two or more input terminals and a single output terminal which will be at logic 1
Whenever anyone or more of its input terminals is at logic 1. The Boolean expression for the output of a
3-input OR gate is given by:-
𝐹 = 𝐴+𝐵+𝐶 (2)
the OR function being represented by the symbol +. The truthtable of a 3-input OR gate is given by Table
3.
A 0 1 0 1 0 1 0 1
B 0 0 1 1 0 0 1 1
C 0 0 0 0 1 1 1 1
F 0 1 1 1 1 1 1 1
TABLE 3. TRUTH TABLE OF 3-INPUT OR GATE
THE NOT-GATE
The NOT gate has just one input and a single output terminal and it is used in logical circuitry as an
invertor, i.e. the NOT logical function inverts its input. The Boolean expression describing a NOT function
is the bar over the input signal. For input A, output F equals:
𝐹 = 𝐴̅ (3)
THE NAND-GATE
A NAND gate performs the inverse of the AND logical function, so that its output is at logical 0 only when
all of its inputs are at logical 1. The truth table of a 3-input NAND gate is given by Table 4.
A 0 1 0 1 0 1 0 1
B 0 0 1 1 0 0 1 1
C 0 0 0 0 1 1 1 1
F 1 1 1 1 1 1 1 0
TABLE 4. TRUTH TABLE OF 3-INPUT NAND GATE
Clearly the output of a NAND gate is only at logical 0 when all three of its inputs are logical 1. This action
can be described by the Boolean expression:-
𝐹 = ̅̅̅̅̅̅̅̅̅̅̅
(𝐴. 𝐵. 𝐶) (4)
The NAND function can be produced by an AND gate followed by a NOT gate but it is most often
produced by a NAND gate (See Fig. 3.2).The NAND gate is readily available in integrated circuit form.

57
The NOT function can also be obtained using a NAND gate by connecting its input terminals together.
THE NOR-GATE
A NOR gate performs the same logical function as an OR gate that is followed by an inverter. This means
that its output is at logical 0 whenever anyone or more of its inputs is at logical 1. The truth table of a 3-
input NOR gate is given by Table 5.
A 0 1 0 1 0 1 0 1
B 0 0 1 1 0 0 1 1
C 0 0 0 0 1 1 1 1
F 1 0 0 0 0 0 0 0
TABLE 5. TRUTH TABLE OF 3-INPUT NOR GATE
The Boolean expression describing the function is:
̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐹 = (𝐴 + 𝐵 + 𝐶)
The NOR gate can also be used as an invertor or NOT gate by connecting its inputs together.
Example 7
The waveforms shown in Fig. 3.4(a) and (b) are applied to:-
a) a 2-input AND gate

b) a 2-input OR gate
c) a 2-input NOR gate, and
d) a 2-input NAND gate.
For each case draw the output waveform of the gate.

58
THE EXCLUSIVE-OR GATE
The exclusive-OR gate has just two input terminals and one output terminal and it performs the logical
function:-
𝐹 = 𝐴. 𝐵̅ + 𝐴̅. 𝐵 or ̅̅̅̅̅
(𝐴 + 𝐵)(𝐴. 𝐵) (6)
A 0 1 0 1
B 0 0 1 1
F 0 1 1 0
TABLE 6. TRUTH TABLE OF EXCLUSIVE-OR GATE
The output F of the gate is at logical 1 only when either one, but not both, of its inputs is also at logical
1. If both inputs are at logical 0 or at logical 1, the output of the gate will be at 0.
The exclusive-OR gate can be fabricated by suitably combining other types of gate it can also be
obtained in an integrated circuit package. Fig. 3.5 shows how an exclusive-OR gate can be made using a
mixture of AND and OR gates.
3.5. THE USE OF NAND/NOR GATES TO GENERATE AND / OR FUNCTIONS
The majority of integrated circuit gates employed in modern equipment belong to one or other of two
logic families, namely the TTL and the CMOS families. In both of these families, NAND and NOR gates are
the most commonly used since their cost is less than that of the other types of gate which are available.
Also, the NAND and NOR gates generally have a faster operating speed and a lower power dissipation.
Very often therefore, a digital circuit is made up using only NAND and/or NOR gates.
It is easy to see that the AND function can be obtained by cascading two NAND gates as shown by Fig.
3.6(a), the second gate being employed as an invertor. Similarly the OR function is easily obtained by the
cascade connection of two NOR gates as shown by Fig. 3.6(b).

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Implementation of the AND function using NOR gates, and the OR function using NAND gates, is not
quite as easy but the necessary connections can readily be deduced by the use of De Morgan's rules
from the theory of Boolean algebra. One rule is:
̅̅̅̅̅̅̅̅
a) 𝐴 • 𝐵 = 𝐴̅ + 𝐵̅
b) ̅̅̅̅̅̅̅̅̅
𝐴 + 𝐵 = 𝐴̅ • ̅𝐵
Proof. Let us prove the (a) part. If
𝑋 = 𝐴̅ + 𝐵̅ then 𝑋 = ̅̅̅̅̅̅̅̅
𝐴 • 𝐵. By Postulate 7
𝑋 • 𝑋̅ = 0 and 𝑋 + 𝑋̅ = 1
If 𝑋 • 𝑌̅ = 0 and 𝑋 + 𝑌̅ = 1 then 𝑌 = 𝑋 because the complement of X is unique. Therefore we let 𝑌 =

̅̅̅̅̅̅̅
𝐴 • 𝐵and test 𝑋 • 𝑌̅ and 𝑋 + 𝑌̅:
𝑋. 𝑌 = (𝐴̅ + ̅
𝐵) (𝐴 𝐵) (P2)
= (𝐴 𝐵) (𝐴̅ + ̅
𝐵) [P4(b)]
= (𝐴 𝐵)̅̅̅
𝐴 + (𝐴 𝐵) ̅
𝐵 [P6(b)]
= 𝐴̅ (𝐴 𝐵) + (𝐴 𝐵) ̅
𝐵 [P4(b)]
= (𝐴̅ 𝐴) 𝐵 + 𝐴 (𝐵 ̅𝐵) [P5(b)]
= 0 • 𝐵 + 𝐴 ( 𝐵 • 𝐵̅) [P7(b),4(b)]
= 𝐵 • 0 + 𝐴 • 0 [P4(b), 7(b)].
= 0 + 0 [T9(b)]
= 0 [P3(a)]

60
𝑋 + 𝑌 = (𝐴̅ + 𝐵̅) + 𝐴 𝐵 (P2)
= (𝐵̅ + 𝐴̅) + 𝐴 𝐵 [P4(a)]
= 𝐵̅ + (𝐴̅ + 𝐴 𝐵) [P5(a)]
= 𝐵̅ + (𝐴̅ + 𝐵) [T11(a)]
= (𝐴̅ + 𝐵̅) + 𝐵 [P4(a)]
= 𝐴̅ + (𝐵̅ + 𝐵) [P5(a)]
= 𝐴̅ + (𝐵̅ + 𝐵) [P4(a)]
= ̅𝐴 + 1 [P7(a)]
= 1 [T9(a)]
Therefore, by uniqueness of X and Y = 𝑋̅
̅̅̅̅̅
𝐴 𝐵 = 𝐴̅ + 𝐵̅
Theorem 12 may be generalized to include longer expressions as shown below:
a) 𝐴̅ + 𝐵̅ + ... + 𝑍̅ = ̅̅̅̅̅̅̅̅̅̅̅
𝐴 𝐵 ...𝑍
b) 𝐴 𝐵 . . . 𝑍 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅𝐴 + 𝐵̅ + . . . + 𝑍̅
After negating both sides of equation (9), the right-hand side of (10) can be implemented using NAND
gates as shown in fig. 3.7(b).
Clearly, more gates are needed to implement the AND/OR functions with NAND/NOR gates, but very
often the apparent increase in the number of gates required is not as great as at first anticipated since
consecutive stages of inversion need not be provided. This point is illustrated in the following examp1e:-

61
Example 8
Implement the exclusive-OR function 𝐹 = 𝐴. 𝐵̅ + 𝐴̅. 𝐵 using
i. NAND gates only, and

ii. NOR gates only.
Solution
The first step is to draw the logic diagram using AND, OR and NOTgates. When this has been
done, replace each gate with its NANDor NOR equivalent circuit. Finally, if possible simplify the
resulting network by eliminating any redundant gates.
i. Fig. 3.5 shows the exclusive-OR gate built with AND and ORgates. Replacing
each gate with the equivalent NAND logicnetwork gives the circuit of Fig. 3.8(a).
It can be seenthat this network includes two sets of two NAND gates incascade.
These are redundant. Fig. 3.8(b) shows thesimplified network which does not
include the fourredundant gates. It will be noticed that the number ofNAND
gates required (i.e. 5) to implement the exclusive-ORgate is the same as the
number of NAND gates required (i.e.5) to implement the exclusive-OR gate is
the same as thenumber of AND and OR gates which are necessary.
ii. Replacing each AND and each OR gate with the corresponding NOR gate version
results in the circuit of fig. 3.9(a) and this can be simplified by eliminating
redundant gates to produce the final version given in fig. 3.9(b).
In general, Boolean equations in the product-of-sums form, e.g. (A + B) • (C + D), are best implemented
using NOR gates, and sum-of-products equations, e.g. (A • B) + (C • D) are more easily implemented
using NAND gates.

62
EXERCISES
1. Explain what is meant by the terms positive logic and negative logic
2. Explain what is meant by the term enable and inhibit when applied to logic gates
3. Give the advantages of using only one type of gate in logic circuit.
4. Show how the NOR logical function can be implemented using NAND gates
5. Show how the NOR logical function can be implemented using NAND gates
6. Show, with the help of truth tables, the correctness of the so called De Morgan’s rules.
(equations (7) and (9))

63
PRACTICAL ELECTRONIC GATES

CONTENTS
4.1 INTRODUCTION TO LOGIC FAMILIES
4.2 POSITIVE AND NEGATIVE LOGIC
4.3 TWO STATE DEVICES
4.4 ELECTRONIC GATES
4.5 LOGIC FAMILIES
1. DIODE RESISTOR LOGIC (DRL)
2. DIODE TRANSISTOR LOGIC (DTL)
3. TRANSISTOR TRANSISTOR LOGIC
4. CMOS LOGIC
5. EMITTER-COUPLED LOGIC (ECL)
4.6 COMPARISON BETWEEN INTEGRATED LOGIC FAMILIES
4.7 EXERCISES
INTRODUCTION TO LOGIC FAMILIES
The various kinds of basic logic circuits described in the previous chapter are manufactured in a number
of standard types. Some of the methods of making an electronic gate circuit are only suitable,for use
with discrete circuitry and so are rarely employed in modern equipment, whilst others are eminently
suitable for implementation in integrated circuitry
The simplest, logic family is known as diode-resistor logic. This type of logic suffers from a number of
drawbacks (e.g. the impossibility of the NOT-function) that can be overcome by the use of an active
element, such as a bipolar transistor. Resistor-transistor logic (RTL) and diode-transistor logic (DTL) can
also be fabricated with discrete components.
When digital integrated circuits became possible, the RTL family was the first to be fabricated in
integrated form and was followed by the DTL family. These early families ofintegrated logic circuits have
since been replaced by the transistor (TTL), emitter-coupled transistor (ECL) and complementary metal-
oxide semiconductor (CMOS) logic families.
The most popular and most widely used circuits in modern digital equipment are in the TTLand CMOS
families. Diode-transistor logicis still available from some manufacturers but it is rarely, if ever, used in
new equipment, while ECL is only used when its special features, i. e. it’s very fast speed of operation, is
of particular interest. The emphasis throughout this course will be on the TTL and the CMOS integrated
logic families.
4.2 POSITIVE AND NEGATIVE LOGIC

64
Positive logic
We talk of positive logic as the more positive voltage level represents logic-1 and the less positive level
giving logic-0.
Negativelogic
We talk about negative logic, if the more negative voltage level represents logic-1 and the less negative
level represent logic-0.
4. 3 TWO STATE DEVICES
A two-state device is one which has only two stable operating conditions, or states. Examples of two
state devices are: a lamp, switch or buzzer. In each case the device is operated or not, i.e. either it is ON
or it is OFF. The two binary conditions 1 and 0 can therefore be represented by a two-state device.
In electronic digital equipment we make use of electronic components like diodes and transistors as two
state devices
The semiconductor diode
A semiconductor diode is able to operate as a two-state device because it offers a low resistance to the
flow of an electric current in one direction and a high resistance in the other. The diode is said to be ON
when it is FORWARD BIASED and OFF when it is REVERSE BIASED. To see how a diode acts as a two-state
device consider the circuit of fig. 2.1 which shows a diode connected in series with a load resistor RL
When terminal 1, is positive with respect to terminal 2, thediode conducts and current flows to develop
a voltage across RL. Neglecting the small voltage drop which must occur across the diode, the voltage
appearing at the output terminals of the circuit will be equal to the voltage applied to terminal 1. In the
reverse condition, the diode will not conduct. The voltage at the output terminal will now be equal to
the voltage at terminal 2. Suppose now the voltages of the same magnitude and polarity are applied to
terminals 1 and 2. The diode will not conduct and the output voltage will be the same as the common
value of the input voltages. The action of the circuit can be expressed by a voltage table, as table 1.
TERMINAL 1 TERMINAL 2 OUTPUT

Positive Negative positive
Negative positive positive

65
Positive positive positive

negative negative negative
Table 1 Voltage table of circuit 3.1
The Transistor
Fig. 2.2 shows a typical set of output characteristics for a transistor. A d.c. load line has been drawn on
the characteristics between the points Vce= -Ecc, Ic = 0 and Ic = Ecc / RL, Vce = 0. When a transistor is
used as a switch, it is rapidly switched between two states.
When the base current is zero, the transistor is held in its OFF condition. In this condition the transistor
conducts a very small collector current, equal to the collector leakage current or less. The voltage
dropped across the collector resistor is negligible and so the voltage across transistor in the OFF state is
equal to the collector supply voltage Ecc.When the transistor is driven into saturation, it is in its ON
state. The voltage across the transistor is now its saturation voltage and this is only a fraction of a
voltage.
The transistor can be switched rapidly between its ON and OFFstates by the application of a rectangular
waveform of sufficient amplitude to its base terminal (Fig.2.3).

66
The voltage at the output terminals of the circuit switches between almost zero volts and -Ecc volts. It
should be noted that when the input signal voltage is negative the output voltage is zero, and when the
input signal voltage is zero the output voltage is -Ecc volts (see fig. 3.4). This means that the input
waveform has been inverted; it will be seen later that this means that the circuit has performed the
logical function NOT. If an NPN switching transistor is considered, a pulse waveform varying between 0
and +V volt must be applied to the base to switch the output voltage between Ecc and 0.
4. 4 ELECTRONIC GATES
An electronic gate is a device which is able to operate on an applied binary signal in a manner
determined by its logical function. A number of different types of gate feature in digital circuitry, the
most common of which are (i) AND-gate, (ii) the OR-gate, (iii) the NOT-gate, (iv) the NAND-gate and (v)
the NOR-gate.
The AND-gate
To illustrate the meaning of the AND logical function we first take a look at a circuit with mechanical
switches. Fig 3.1 shows a lamp L connected in series with two switches, S1 and S2 and a battery. For a
current to flow in this circuit and the lamp to light, it is required that both switches S1 and S2 are closed.
If we denote a switch when, open, or OFF, by logic-0 and when closed, or ON, by logic-1; the lamp, when
lit by logic-1 and when unlit by logic-0, then the operation of the circuit may be described by its so called
truth table. (See table 2).
S1 S2 L
0 0 0

67
0 1 0
1 0 0
1 1 1
Table 2. Truth table of circuit 3.1 (logic AND function)
An AND-gate is the electronic equivalent of switches connectedin series and is a circuit having two or
more input terminalsand one output terminal. The circuit symbol for an 2-inputAND-gate together with
its truth table are given in fig. 3.2.From this table is can be seen, that the output state of anAND-gate is 1
only if all the inputs are 1. In all other cases the output will be 0.
The OR-gate
The circuit of fig. 3.3 is an example of the OR function. It shows a lamp L connected to a battery by
means of two parallel switches S1 and S2. Current will flow in the circuit and light the lamp if either
switch S1 OR S2 OR both S1 and S2 are closed. If we make use of the same logic convention as in the
previous case then table 3 represents the truth table for this circuit, which acts as a 2-input OR-gate.
S1 S2 L
0 0 0
0 1 1
1 0 1
1 1 1
Table 3. Truth table of circuit 3.3 (logic OR function)
An OR-gate is the electronic equivalent of switches connected in parallel and is a circuit having two or
more input terminals and one output terminal.The circuit symbol for an 2-input OR-gate together with

68
its truth table are given in fig. 3.4. From this table it can be seen, that the output state of an OR-gate is 0
only if all the inputs are 0. In all other cases the output will be 1.
The NOT gate
The circuit of fig. 2.3 is able to carry out the NOT logical function. The circuit is also known as an
inverter. The action of the circuit is to invert the input signal; i.e. a logical 1 at the input will give logic-0
at the output and vice versa. The circuit symbol of a NOT-gate or inverter together with its truth table
are given in fig. 3.5.
The NAND-gate
The NOT-AND or NAND-gate performs the same logical operation as an AND-gate followed by a NOT-
gate or inverter. The circuit symbol for a NAND-gate together with its truth table are given in fig. 3.6.
From the table it can be seen, that the output state of an NAND-gate is only 0 if all the inputs are 1. In all
the other cases the output will be 1.

69
The NOR-gate
The NOT-OR or NOR-gate performs the same logical operation as an OR-gate followed by a NOT-gate or
inverter. The circuitsymbol for NOR-gate together with its truth table are given in fig. 3.7. The action of a
NOR-gate is that the output state is 1 only if all the inputs are 0. In all other cases the output will be 0.
4.5 LOGIC FAMILIES
4.5.1 DIODE RESISTOR LOGIC (DRL)
The circuit diagram of a three-input diode logic gate is shown in fig. 4.1. The positive voltage E applied to
the resistor R is normally several times greater than the peak positive voltage V of the pulse waveform
which are applied to input terminals A, Band C. If anyone of the inputs is at zero potential, the
associated diode conducts and the output voltage will fall to about zero.The other two diodes now have
positive voltage V at their cathode and about zero voltage at their anode, and so they do not conduct.
Similarly, if two inputs are at zero potential, the diode associated with the third input will be reverse-
biased and the output voltage will be approximately zero.
The voltage table of the diode logic gate is given by table 4.
A B C O/P
0 0 0 0
0 0 +V 0
0 +V 0 0
+V 0 0 0
0 +V +V 0
+V +V 0 0

70
+V 0 +V 0
+V +V +V +V
Table 4. Voltage table of circuit 4.1
The other diodes then have a negative voltage at their anodes and zero voltage at their cathodes and so
are turned OFF. When all three input pulses are simultaneous at zero volts, the three diodes are
switched ON and the output voltage is clamped to zero potential. Table 5 shows the voltage table for
the circuit. It can be seen that the circuit acts as an OR-gate with positive logic and as an AND-gate with
negative logic.
A B C O/P
0 0 0 0
0 0 -V 0
0 -V 0 0
-V 0 0 0
0 -V -V 0
-V -V 0 0
-V 0 -V 0
-V -V -V -V
4.5.2 DIODE TRANSISTOR LOGIC (DTL)
Diode-resistor logic gates cannot perform the NOT logical function and hence are also unable to provide
either the NAND or the NOR functions. To obtain either of these functions the diode gate must be
followed by an inverting transistor stage as shown in fig. 4.3.

71
A B C (Vb) O/P
0 0 0 0 +E
0 0 +V 0 +E
0 +V 0 0 +E
+V 0 0 0 +E
0 +V +V 0 +E
+V +V 0 0 +E
+V 0 +V 0 +E
+V +V +V +V 0
Whenever the voltage applied to the base of the transistor isat +V volts (see table 4), the transistor will
be driven intosaturation and its collector voltage will be approximately zero. Conversely, when the base
voltage is a 0 V the transistor will be turned OFF and the output voltage will be +E2 volts. The voltage
table for the circuit is given by table 6. From this table it can be recognized that, when positive logic is
used, the circuit performs the NAND function, and when negativelogic is used it behaves like a NOR-
gate.
4.5.3 TRANSISTOR-TRANSISTOR LOGIC (TTL)
The most popular and most widely used logic family is the transistor-transistor or TTL family, which is -
manufactured in integrated circuit form by most semiconductor manufacturers. The popularity of this
logic family arises because it offers fairly high speed (particularly the schottky versions), good fan-in and
fan-out, and is easily interconnected or interfaced with other digital circuitry, all at a relatively low cost.
The standard TTLlogic, known as the 74 series has poor noise immunity and high power consumption.
Low-power versions by different manufacturers may well have different internal circuits but any two
devices with the same number will perform exactly the same logical function.
NAND-gate
The circuit of a standard TTL gate is given in figure 5.1. The input transistor has a number of emitters
equal to the desired fan-in of the circuit; in the figure, a fan-in of 2 has been assumed. In the 74 series,
fan-ins of 2,3,4 and 8 are available.

72
The output stage, consisting of transistors T3 and T4, and diode D1 and known as a totem-pole stage, is
used to provide the circuit with a low output impedance.
When both input terminals are at +5V the emitter /base junction of T 1,is reverse biased but its
collector/base junction is forward biased. Current then flows,from the collector power supply, through
R1, into the base of T2. Transistor T2 turns full ON making the base/emitter potential of T3
approximately zero and so T3 will not conduct. At the same time T4 is turned ON by the voltage
developed across the resistor R3. Thus, when T2 is ON transistor T3 is OFF and T4 is ON; this means that
the potential at the output terminal of the circuit is low and equals the logical 0 state. The fan-out can
be up to about 10 without the saturation voltage of T4 rising above the 0 level.
When either or both of the input terminals is at approximately zero volts, logic 0, the associated
emitter/base junction will be forward biased (its base is more positive than its emitter). The value of
resistor R1 is selected to ensure that T1 is then full ON and so the base voltage of T1 is only VBE1 volts
(app. 0.7V) above earth potential. This potential is insufficient to keep T2 ON and so T2 turns OFF.
When T2 is OFF its collector voltage is +5V and its emitter voltage is 0V. Now T4 is turned OFF and T3
conducts to an extent that is determined by the external load connected to the output terminals of the
circuit. The output voltage is then equal to 5V minus the voltage dropped in T3 and D1, i.e. logic 1.
To protect the circuit from damage by any negative voltage arriving at the input terminals, and also to
improve the noise immunity, a diode can be connected between each input and earth shown dotted in
figure 5.1
Many IC packages contain more than one gate and some examples of NAND gates of the 74 series
together with the pin connections are shown in figure 5.2.

73
NOR Gate
The circuit diagram of a TTL NOT-gate is given by figure 5.3. If either T2 or T3 is turned ON, the base
potential of T5 will fall to very nearly 0V and T5 will turn OFF. Since either T2 or T3 is conducting heavily,
the positive voltage developed across R3 will be large enough to turn T6 ON; the output of the circuit
will be at logical 0.
The output of the circuit will only be at logic 1 when both T2 and T3 are OFF; then the base potential of
T5 is +5V and T5 turns full ON, while T6 is turned OFF because the voltage across R3 is zero. Transistors
T2 and, T3 will be turned ON by a positive voltage at their base terminal and this will happen only when
T1 and/or T4 isconducting, i.e. when input A and/or B is at +5V or logical 1. The circuit therefore
performs the NOR function since the output is at logical 1 only when both inputs A and B are at logical 0.
Some examples of NOR gates of the 74 series together with their pin connections are shown in figure
5.4.

74
Low Power TTL
The series 74L uses the same circuitry as the standard series but all the resistance values are increased
in order to minimize the internal power dissipation.
Schottky TTL
For many applications the (typical) 9 ns propagation delay time of the standard TTL gate is too high and
so a higher speed version has been introduced. This alternative, known as Schottky TTL, series 74S, uses
Schottky transistors as shown in- Figure 5.5.
Excess base current is diverted from the base of the transistor by the Schottky diode which clamps the
base/collector potential to 0.4V. Since this voltage is not large enough to drive the transistor into
saturation, the switching speed is considerably increased without an accompanying increase in the
power dissipation.
Difference between the NAND circuit of Figure 5.5 and the standard gate of Figure 5.1, other than the
use ofSchottky transistors, are that resistor R3 is replaced by transistor T4 and resistors R3 and R5and
D1 is replaced by the transistors T5 and T3 to increase the speed of operation.
Low-Power Schottky TTL

75
A low-power Schottky TTL series is also available and is rapidly becoming the most popular type of gate.
The 75LSseries is faster than the standard series and it alsodissipates less power but it is slower than the
74Sseries.
4.5.4. CMOS LOGIC
The complementary metal-oxide semiconductor, or CMOS, logic family offers the desirable features of
very low power dissipation and good noise immunity. The family finds particularly application when low
power consumption is of prime importance. The main disadvantage associated with this type of gate is
its limited switching speed arising from the very high input impedance of a MOSFET device.
NAND Gate
The circuit of a CMOS NAND-gate is given in Figure 6.1. It can be seen that the N-channel MOSFETS are
connected in series and the p-channel devices are in parallel. The operation of the circuit is as follows. If
either, or both, of the inputs is at logical 0 (0V), then the associated p-channel MOSFETS, T1 and/or T2
are turned ON, while the associated n-channel MOSFETS, T3 and/or T4, are turned OFF. The output
terminal of the circuit is then at +5V minus the saturation voltage of an ON MOSFET. Conversely, if both
inputs are at logical, (+5V), T1 and/or T2 areOFF, and T3 and/or T4 are turned ON. The output of the
circuit is then at approximately 0V or logical 0, so the NAND function is performed.
NOR Gate
Very often protective diodes are connected between theinput terminals and earth to reduce the
possibility of the device being damaged by static charges produced by handling. The protective diodes
are shown in the NOR circuit of Figure 6.2. Note that now the N-channel MOSFETS are connected in
parallel.

76
If either of the input terminals is at logical 1, the associated p-channel MOSFET (T2 and/or T3) is turned
OFF and the associated N-channel MOSFETS (T1 and/or T4) are turned ON. The output voltage of the
circuit is then low so that the NOR function is performed. Only If both inputs are at 1ogical 0will both the
N-channel devices turn OFF, and the p-channel. MOSFETS turn ON so that the output can reach its
logical 1 state.
NOT Gate
The circuit of a CMOS NOT-gate is given in Figure 6.3. It can be seen that two MOSFETS are connected in
series. One n-channel (T1) and the other is P-channel (T2). The operation of the circuit is as follows. If
the input is at logical 0 (0V), then the P-channel (T2) is TURNED ON and the n-channel is turned OFF.
Then the output F is then at +VDD or 1. Conversely, if the input is at logical 1 then p-channel is OFF and
n-channel is on. Then the output is at 0V (Logic 0).
4.5.5. EMITTER-COUPLED LOGIC (ECL)
The main feature of emitter-coupled logic, or ELC, is the very speed of operation that is provided. This
logic family is used when the maximum possible speed is the prime consideration. Very fast, operation is
obtained bydesigning the circuitry to ensure that the transistors do not drive into saturation when
conducting. The basic ECL gate is a combined OR/NOR circuit and this, in common with the rest of the
family, is operated from. a -5.2V supply. This means that logic 1 is represented by -0.9V and logic 0 by -
1.75V.

77
The circuit diagram of an OR/NOR ECL gate is given by Figure 7.1. A reference voltage of -1.30V is
developed by the R7, T4, D1 D2, R8 circuit, and applied to the base terminated of transistor T3. If both
inputs A and B are at logical zero (-1. 75V) then the base potential of T3 is more positive than the base
potentials of either T1or T2, and so T3 conducts whilst T1 and T2 do not. The collector current of T3
develops a voltage of about -1.0V across R5 and this causes T5 to conduct. T5 is connected as an emitter
follower and so its output voltage is -1.0V -VBE5 = -l.7V (approximately) which represents logic 0. The
collector potentials of T1 and T2 are approximately zero hence, the output voltage of T6 is 0V -VBE6 =
-0. 7V approximately which represents logic 1.
If either input A or B is at logical 1, i.e. -0.9V, the associated transistor is turned ON while T3 is turned
OFF. Now the collector potentials of T1/T2 and T3 are reversed compared to the previous case and so
now, T5 output is at logical 1 and T6 output is at logical 0.
When an ECL circuit is to interface with CMOS or TTL circuitry, the connection must be made via a level
Shifting circuit because of the -5.2V supply voltage of ECL.
4.6. COMPARISON BETWEEN INTEGRATED LOGIC FAMILIES
The main characteristics of the various logic families which are available in integrated circuit form are
listed in Table 7.
Family Propagation Power Noise Fan-out Supply Fan-in

delay (ns) dissipation immunity voltage (V)
(mw) (V)
d.t.l 30 8 1 5 5 8
t.t.l. 9 40 0.4 10 5 8
standard
t.t.l schottky 3 40 0.3 10 5 8
t.t.l. low- 8 8 0.3 10 5 8
power
schottky
c.m.o.s. 30 .001 1.5 50 5 8
e.c.l. 1.1 30 0.4 50 -5.2 5

78
Systems such as mainframe computers were the highest possible speed of operation is of the utmost
importance use ECL but most other systems use one form or other of TTL or CMOS.
Recent developments have been the introduction of improved TTL device such as Advanced Schottky
and Advanced Low-power Schottky. These devices provide a much faster speed of operation together
with a lowerpower dissipation. The speed of Advanced Schottky is suchthat it can compete-successfully
with ECL for very-high speed applications.
4.7. EXERCISES
1. What is meant by :-
i) positive logic
ii) negative logic
Illustrate your answer with an example.
2. a. With the aid of a circuit diagramexplain the operation of both Positive-logicand
semiconductor diode AND-logic elements.
b. if a transistor stage is connected to the output of the positive-logic AND-gate drawn for part
(a), sketch the arrangement and explain its operation. What logic function is now being
formed?
3. The voltage table for a logic gate is given below.
A B O/P
-6V -6V -1V
-1V -6V -1V
-6V -1V -1V
-1V -1V -6V
Determine, with the aid of truth tables, which logic function is produced if :-
i. positive logic is used
ii. negative logic is used
iii. positive logic is used at the input and negativelogic at the output, and
iv. negative logic is employed at the input andpositive logic at the output.
4. Fig. 8.1 shows the circuit of a logic gate.
a. State whether the transistor should be a pnp or a npn type and determine the polarities
of the voltages E1 and E2.
b. Describe the operation of the circuit.

79
c. State the logical function of the circuit positive logic is employed.

5. The waveforms shown in Fig. 8.2 are applied to the input of:-
a. a three-input AND-gate, and
b. a three-input OR-gate
For each case determine the output waveform.
6. What are the major disadvantages of diode logic compared with TTL logic?
7. Describe, with the aid of a circuit diagram, the operation of a TTL 3-input NAND gate. Write
down the truth table for the circuit and state how the logical function of the circuit changes if
negative logicused.
8. List the relative advantage of TTL and low-power Schottky logic elements.
9. Describe, with the aid of a circuit diagram the operation of a 3-input CMOS NAND-gate.
10. Draw up a table to show speed, power dissipation and other parameters of low-power TTL
compare with CMOS logic.
11. With the aid of a circuit diagram table explain the operation of an ECL OR/NOR gate.
END

80
COMBINATIONAL LOGICAL CIRCUITRY

CONTENTS
5. 1 .COMPARATORS.
5 .2 .CODE CONVERTERS
5.2.1. DIODE MATRIX.
5.2.2. DECIMAL TO BCD ENCODER
5.2.3. BCD TO DECIMAL DECODER
5.2.4. BCD TO SEVEN SEGMENT DECODER
5.3. ERROR DETECTION -PARITY CHECKING
5.3.1. INTRODUCTION
5.3.2. ERROR DETECTION
5.3.3. PARITY CHECKING
5.3.4. PARITY BIT GENERATOR
5.3.5. PARITY DETECTOR
5.3.6. ERROR DETECTION SYSTEM
5.4. MULTIPLEXERS
5. 5. DEMULTIPLEXERS
5.6. BINARY ADDERS
5.6.1. HALF ADDER
5.6.2. PARALLEL OPERATION
5.6.3. FULL ADDER
5.6.4. SERIAL OPERATION
5.7. BINARY SUBTRACTION
5.7.1. HALF SUBTRACTOR

81
5.7.2. BINARY FULL SUBTRACTOR

82

83
5.1. COMPARATORS
Logic comparators are used to determine whether two digital numbers are equal or not. The output of
the comparator goes to logic 1 when the two numbers are equal. The Boolean logic equation for
comparing two 1- bit numbers is:
𝑇 = 𝐴𝐵 + 𝐴̅𝐵̅ (1)
A magnitude comparator is a circuit that determines whether one binary number A is greater than,
equal to or less than another binary number B. When only single-bit numbers are involved, the exclusive
-OR can be used to decide whether or not two binary numbers A and B are equal to one another. The
output of an exclusive -OR gate will be at logical 0 only When both of its inputs are equal.
The Boolean logic equation for exclusive -OR is:
𝑇 = 𝐴̅𝐵 + 𝐴𝐵̅ (2)
If two n-bit numbers A and B are to have their magnitudes compared, n exclusive -OR gates can be used
whose outputs fan into a single NOR gate to give logical 1 output only when A = B. (See fig. 5.1 which
shows the circuit for the case when n= 4).
If, when A and B are not equal, some indication is required as to whether A > B or A < B, then extra
circuitry is necessary. Fig. 5-2 shows one possible arrangement for a 1-bit comparator. The same
principle can be extended to allow numbers containing any number of bits to have their magnitudes
compared but even for a 4 -bit comparator the circuitry rapidly becomes very complicated. 4-bit
magnitude comparators are available in both the TTL (IC No. 7485) and in CMOS (IC No. 4063) families.
5. 2. CODE CONVERTERS
Many instances arise for a decimal number to be encoded into the corresponding binary or binary coded
decimal {or some other code) number. Similarly, it is often necessary to decode a number from pure
binary or BCD into decimal.
5.2.1. DIODE MATRIX
The conversion of numbers from one code to another can be carried out using a diode matrix.

84
Fig. 5-3 shows one example a decimal-to-BCD converter. A BCD output line, A, B, C, or D will be at the
logical 1 voltage level whenever a decimal input line is at logical 1 and a diode is connected between the
output line and that decimal input line.
For example,
A = 1 + 3+ 5 + 7 + 9
B=2+3+6+7
C=4+5+6+7
D=8+9
When such a matrix is fabricated within an integrated circuit, each diode will probably be the
base/emitter diode junction of an npn transistor with the collector taken directly to +Vcc volts.
The circuit of a diode matrix octal decoder is shown by fig. 5.4. A diode matrix is really a form of read
only memory, (ROM).

85

86
5.2. 2. DECIMAL TO BCD ENCODER
An encoder is a combinational logic circuit that accepts one or more inputs and generates a multi-bit
output code. In a sense, encoders are exactly the opposite of decoders.
A typical application for an encoder is in translating a decimal keyboard input signal into a binary or BCD
-output code.
Fig. 5-5 shows a decimal-to-BCD encoder circuit. The circuit is designed to generate the correct BCD
code words at the outputs A0 - A3, if any of the inputs 1 - 9 receives a high voltage.
In this circuit it is not necessary to build a decimal 0 input, because in case all the inputs 1 - 9 are at low
voltage the binary output will show a 0000 which is the BCD code word for 0. Table 5-1 is the truth table
for a decimal to BCD encoder.

87
INPUT (decimal) OUTPUT (BCD) No

1 2 3 4 5 6 7 8 9 A3 A2 A1 A0
L L L L L L L L L L L L L 0
H L L L L L L L L L L L H 1
L H L L L L L L L L L H L 2
L L H L L L L L L L L H H 3
L L L H L L L L L L H L L 4
L L L L H L L L L L H L H 5
L L L L L H L L L L H H L 6
L L L L L L H L L L H H H 7
L L L L L L L H L H L L L 8
L L L L L L L L H H L L H 9
TABLE 5-1 The truth table decimal to BCD encoder
5.2.3 BCD TO DECIMAL DECODER
Decoders are exactly the opposite of encoders. Decoders detect or identify specific codes while
encoders generate specific codes.
One of the most common applications for decoder circuits is binary-to-decimal conversion. The function
of this decoder, which should convert BCD code to decimal code, can be seen from the truth table.
No BCD input DECIMAL output

A3 A2 A1 A0 0 1 2 3 4 5 6 7 8 9
0 L L L L L H H H H H H H H H
1 L L L H H L H H H H H H H H
2 L L H L H H L H H H H H H H
3 L L H H H H H L H H H H H H
4 L H L L H H H H L H H H H H
5 L H L H H H H H H L H H H H
6 L H H L H H H H H H L H H H
7 L H H H H H H H H H H L H H
8 H L L L H H H H H H H H L H
9 H L L H H H H H H H H H H L
Table 5-2. The truth table Of BCD to decimal decoder
From table 5-2 it can be seen that each BCD code word will cause only one certain output to go low the
other outputs remain in the high state.

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For example the BCD code word LHLH causes the output 5 to go low. If an invalid code word appears at
the inputs the output should all remain high. Invalid code words are the BCD code words HLHL - HHHH.
The circuit in fig. 5.4 shows how this decoding can be established with inverters and NAND-gates.
The four bit BCD number can be applied to the inputs A0 -A3 of the decoder in fig. 5-5. Only in case of a
high input condition of all four inputs to the NAND-gates the output of a certain NAND-gate can reach
the low state. By connecting the inputs via inverters to the NAND-gates the correct code word for a
certain output can be applied the appropriate NAND-gate. The outputs can be connected to indicators
like lighted decimal numbers etc. If a high output level is required the outputs can be inverted by
additional inverters.
5.2.4. BCD TO SEVEN SEGMENT DECODER
A special form of decoder circuit is the popular BCD to 7-segment display decoder/driver. This is a
combinational logic circuit which accepts the BCD code as input and generates a special 7-bit code that
is used to operate the widely used 7-segment decimal readout.
Fig. 5-6 shows such a display built out of LED with common anode.
Fig. 5-7.shows the electrical diagram of the decoder and the LED. The segment is connected to the
decoder/driver circuit.

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5.3. ERROR DETECTION-PARITY CHECKING

5.4.
5.3.1. INTRODUCTION
Digital communication techniques are finding ever increasing application in such areas as transmission
of analogue data, pictures, etc. The transmission of binary data is not for the computer and its
peripherals only.
The main disadvantage of binary data transmission is that it cannot tolerate errors. If data consisting of a
train of bits is transferred by cable or by radio relay links from point to point, interchanging or loss of
bits cannot be accepted because the transmitted information may be distorted beyond recognition.
In the case of operation of a digital computer and thecommunication with it, errors are liable to have
graver effects since a single bit error may cause a mistake in calculations whichcould have serious
consequences.
5.3.2. ERROR DETECTION
When digital data is transmitted over large distances, very littlecan be done to prevent occurrence of
errors during the transmission. Such errors are produced by random interference over which we have
no control. These may be electric discharges in the atmosphere,sudden changes in reception conditions,
electromagnetic inductionetc.
It may be taken for granted that errors will occur. We musttherefore try and prevent interference to
system operation from theoutset.
The first step in solving the Problem must be the detection and identification of errors. After detection,
it will be possible to command the system to ignore the incorrect data and to requestretransmission. In
modern complex systems, this is not consideredsufficient; retransmission of data for every detected
error is liable to be expensive in terms of time. For this reason, systemshave been developed so that
detected errors can be corrected. This causes the system to be more complicated.
The optimum approach lies somewhere between the use of a simple and relatively cheap system which
does not correct detected errors, andthe use of a sophisticated and expensive system capable
ofcorrecting many errors.
5. 3 .3. PARITY CHECKING
A common way to increase the confidence we have in a binary number that has been transmitted or
stored and retrieved is to add another bit to the number so that all stored or transmitted numbers have
some common characteristics. One of the most widespread and basic methods used is the characteristic
of "parity", an even number of 1’s.
To detect errors is then a question of checking for even number of 1's. This is called parity checking.

90
Fig.5.8 shows a digital data transmission/reception system using parity checking to detect errors.
The digital data is produced in the transmission system and is arranged in a register, (digital store),
which contains a certainnumber of bits.
10011101
This eight bit "word" can be a command to perform a given operation in the receiving unit or part of
data used in picture, transmission etc. The word is checked by the parity generator whose task is to
decide the number of "1" s. If there is an even number of “1" s in the word, the parity generator will
generate a "0". If there is an odd number of "1" produced by the parity generator is called the parity bit.
This bit is connected to the data word (generally, as least significant bit) and is transmitted to the
receiving unit. The transmitted word will thus be :
100111011
↖ parity bit
At the receiving unit, the data parity is checked and compared with the parity bit received. If they are
identical, the data is transferred to the processing unit. If there is a discrepancy data transmission ceases
and retransmission is requested.
The parity check can be serial or parallel. Long words are always transmitted serially and then the parity
check is serial. In the case of short words parallel checking is used.
5.3.4. PARITY BIT GENERATOR
An EXCLUSIVE-OR gate is a Parity Generator for a 2-bit number. The truth table for the 2-input
EXCLUSTVE-OR gate tells us that the output, will be a "1" only when the two inputs are different.

91
The output from the Parity Generator (the parity bit) will be transmitted along with the number bits A0
and A1.
Have a look at the example below:
Number Parity Bit Transmission
00 0 000
10 1 011
11 0 110
01 1 011
To make a 4-bit Parity Generator EXCLUSIVE-OR gates can be used. The bits are paired (the order is not
important).
(a) If both pairs do not have parity, the number have parity (even number of 1’s ).
(b) If neither pairs do not have parity, the number have parity.
(c) If only one of the pairs does not have parity, the number does not have parity.
(d) If one pair have parity and the other pair does not haveparity, the number does not have parity.
(e) If one pair does not have parity and the other pair does not have a non-parity, the number does not
have parity.
(f) of course if both pairs parity, the number also will have parity.
In cases (c), (d) and (e) the parity Generator will parity bit.

92
The output from the Parity Generator will be transmitted along with the number bits A0, A1, A2 and A3
(normally as the least significant digit). If A0 is the least significant bit in the data word and P is the parity
bit, the transmitted number will look like this: A3 A2 A1 A0 P.
Again, let us see how the transmitted number will look after the parity bit has been added. See a), b), c)
and d) above.
Number Parity Bit Transmission
a) 01 01 0 01 01 0
b) 00 00 0 00 00 0
c) 01 11 1 01 11 1
d) 11 01 1 11 01 1
e) 01 00 1 01 00 1
f) 11 11 0 11 11 0
5.3.5 PARITY DETECTOR
In an error detection system, a check has to be made at the receiving end to see if there is a discrepancy
between the transmitted parity and the parity generated by the received data. This is achieved by again
checking the parity of the data and comparing it with the parity bit.

93
In Fig 5.11 the comparator produces a "1" at the OK Output if its two inputs are identical -the parity of
the data at the receiver is identical to the parity at the transmitter. If there is a discrepancy between the
received, data parity and the transmitter parity, the Error output will have a "1".
EXCLUSIVE-OR gates can be used for detection of errors by checking for parity in the received data word.
A combination of four EXCLUSIVE-OR gates would check a 5-bit word comprising four data bits and the
parity bit. The output being a "1'" would indicate an error.
5.3.6 ERROR DETECTION SYSTEM
In figure 5.12 a system is shown that transmits and receives binary data, and checks that the data
received is authentic by using aparity check error detection method. Register X (X0, X1, X2 andX3) is the
data source in the transmitter. This data is fedthrough a Parity Generator which generates a parity bit
and passes this along with the data. In the transmission media (the link) there may be errors introduced.
The incoming data to the receiver passes through another parity generator which will produce a parity
bit. This parity bit should be the same as the one produced by the transmit parity generator if no errors
are introduced. The two parity bits are compared in the Parity Check Unit where a “1" at the OK Output
allow the received data from the Receive Register A (A3, A2, A1 and A0) to be transferred to the data
processor.

94
When there is an error, the Parity Check Unit will have a "0 at the OK Output which will prevent the data
from going out, and the Error Output will have a "1" output to activate an eventual re-transmit order to
the transmit side.
The parity check unit is capable of detecting odd number of errors in a word (binary number). If there is
an even number of errors, there will be no error detection.
5.4. MULTIPLEXERS
A multiplexer is a combinational logic circuit that is used to select and route anyone of a number of
input signals to a single output. The simplest form of a multiplexer can be seen in fig. 5.13. This figure
shows a rotary selector switch as a multiplexer. Anyone of the seven input signals of the rotary selector
switch can be connected to the output line simply by adjusting the position of this mechanical selector
switch.
Many applications require the multiplexer to operate at a high speed and be automatically selectable.
Digital multiplexers can solve this application requirements easily.
A very simple multiplexer circuit is shown in fig. 5-14. This digital multiplexer performs the function of a
SPDT (single pole double through) switch.
The input that should be connected to the output in the circuit of fig. 5-14 is selected by the flip-flop.
The AND -gates 1 and 2 receive different binary voltage levels from the outputs of the flip-flop,

95
therefore, either AND -gate 1 or AND -gate 2 will be enabled by a high voltage level at the appropriate
flip-flop output.
Following the same principle as the multiplexer, shown in fig.5.14 multiplexers for more inputs are
constructed.
A commonly used multiplexer circuit is the quad 2 –input multiplexer SN 74157. Fig. 5-15shows the logic
diagram of this multiplexer IC.
The quad 2-input multiplexer can select 4 bits of data from two sources. This multiplexer has two
additional inputs S and E. These inputs control the function of the multiplexer as it can be seen from the
truth table 5-4.
ENABLE SELECT INPUT DATA INPUTS OUTPUT

𝐸̅ S I0 I1 Y
H X X X L
L H X L L
L H X H H
L L L X L
L L H X H
H = HIGH voltage level, L = LOW voltage level X = Don't care .
Table 5-4 The truth table of quad 2 -input multiplexer SN74157
The "E" or "enable" input has to be at low to enable the data transfer from the inputs I0 and I1 to the
output Y according to the voltage level at the "S" or "select" input. If the "E" input is kept high the
outputs Y will always show low. Which inputs are transferred to the outputs depends on the voltage
level at the S input. From table 5-4 it can be seen that a high level at S enables the data at the I1 inputs
to be transferred to the output Y.

96
A low level at S enables the I0 inputs to be transferred to the outputs Y.
Another very important multiplexer IC is the SN 74151 8-input multiplexer. As it can be seen from fig. 5-
16, this multiplexer select one out of eight 1-bit data.
The basic principle for this multiplexer is the same as it is for the multiplexer of fig. 5-15. An enable input
E enables the transfer of data from the input to the output. Which input is selected the "Select inputs",
S0 -S2, determine according to the voltage levels applied to these inputs.
Table 5-5 shows the truth table for this multiplexer.
INPUTS OUTPUTS
𝐸̅ S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 𝑌̅ Y
H X X X X X X X X X X X H L
L L L L L X X X X X X X H L
L L L L H X X X X X X X L H
L L L H X L X X X X X X H L
L L L H X H X X X X X X L H
L L H L X X L X X X X X H L
L L H L X X H X X X X X L H
L L H H X X X L X X X X H L
L L H H X X X H X X X X L H
L H L L X X X X L X X X H L
L H L L X X X X H X X X L H
L H L H X X X X X L X X H L
L H L H X X X X X H X X L H
L H H L X X X X X X L X H L
L H H L X X X X X X H X L H
L H H H X X X X X X X L H L
L H H H X X X X X X X H L H
H = HIGH Voltage level L = LOW Voltage level X = Don't care

97
Table 5-5. The truth table for IC SN 74 151
Multiplexers are used to select one of several inputs to be connected to its single output. Beside this
major application multiplexers are also very frequently used to convert parallel data to serial data and to
generate serial binary data word.
The parallel to serial conversion is simply done if the parallel data word is connected to the data inputs
I0 -I7 and the outputs of a 3 -bit binary counter are connected to the select inputs S0 -S2 (in case of
multiplexer SN 74 151). Fig. 5-17 shows such an arrangement for parallel to serial data conversion.
If the 3-bit binary counter in fig. 5-17 counts upwards the inputs I0, I1, I2, I3, I4, I5, I6 and I7 are
connected one after the other to the output Y. Depending on the clock pulse of the binary counter a
serial data word which represents the parallel data word at the inputs is available at the output Y.
The serial data word generation is in function identically to the parallel to serial data conversion. The
only difference is, the serial data word generator uses a fixed connection of the inputs to certain voltage
levels and should not be changed.
5.5. DEMULTIPLEXERS
Demultiplexer is a logic circuit that is basically the reverse of a multiplexer. Fig. 5-18 shows a mechanical
equivalent of a multiplexer and a demultiplexer.

98
By adjusting the position of the switch of fig. 5-18 the input linecan be connected to any of the 7 output
lines. Since a demultiplexer is distributing data from one input to one of severaloutputs a demultiplexer
is also known as a data distributor.
In a similar way as a multiplexer circuit could be established withdigital components it is also possible to
design a demultiplexer.Fig. 5-19 shows a very simple demultiplexer circuit with only 1input and 2 output
lines. The output to which the input should be connected in fig. 5-19 is selected by the select inputs.
As well as for multiplexer for demultiplexer standard integrated circuits are available. A frequently used
standard integrated IC is the SN 74138 1 of 8 decoder/multiplexer. The name of the SN 74138 is
indicating that a demultiplexer is acting as a decoder, which is decoding a binary code word and
enabling a certain output to be connected to the input line. In fig. 5-20 the internal circuit of the IC SN
14138 is shown.

99
The logic diagram of fig.5-20 shows that the main part of theintegrated demultiplexer is the series of
eight 4-input NAND-gates. The output of each NAND gates represents an output line of the
demultiplexer circuit. The inputs to these NAND-gates corning from the IC inputs A0 -A2 are building
with the inverters the decoder circuit. One input to the NAND -gates is taken from an AND -gate, which
is combining the 3 "E" inputs. Two of these inputs E1 and E2 are active low and the third “E" -input E3 is
active high.
The output of one of these 8 NAND -gates can reach a low voltage only if the 3 -bit binary codeword at
the A inputs fits to the output line and to enable inputs E1 and E2 are at binary 0 and the E3 is at binary
1. In this way the IC SN 74138 can be used as a simple 1 of 8 decoder. To reach a demultiplexer function
one of the 3 Enable inputs must be used as data input. Mostly one of the two active low E inputs E1 and
E2 are taken for this purpose.
The reason for 3 different enable inputs is that these inputs offer the possibility to connect 2 or more
demultiplexer in parallel to achieve a 1 of 16 demultiplexer or even more.
The complete performance of the demultiplexer IC SN 74138 can be seen from table 5-5.
INPUTS OUTPUTS
̅̅̅̅
𝐸1 ̅̅̅̅
𝐸2 ̅̅̅̅
𝐸3 A0 A1 A2 0̅ 1̅ 2̅ 3̅ 4̅ 5̅ 6̅ 7̅
H X X X X X H H H H H H H H
X H X X X X H H H H H H H H
X X L X X X H H H H H H H H
L L H L L L L H H H H H H H
L L H H L L H L H H H H H H
L L H L H L H H L H H H H H
L L H H H L H H H L H H H H
L L H L L H H H H H L H H H

100
L L H H L H H H H H H L H H
L L H L H H H H H H H H L H
L L H H H H H H H H H H H L
H = HIGH voltage level L = LOW voltage level X = Don't care
Table 5-5 The truth table of 1 of 8 decoder/demultiplexer SN 74138
5 .6 .BINARY ADDERS
A digital computer must obviously contain circuits which will perform arithmetic operations, i.e.
addition, multiplication and division. The basic operations are addition and subtraction. Since
multiplication is essentially repeated, addition and division is essentially repeated subtraction. It is
entirely possible to build a computer in which an adder is the only arithmetic unit present.
Multiplication, for example may then be performed by programming i.e. the computer may be
giveninstructions telling it how to use the adder repeatedly to find the product of two numbers.
Suppose we wish to sum two numbers in decimal arithmetic andobtain, say, the hundred digits. We
must add together not onlythe hundred digits of each number but also a carry from the tensdigit if one
exists. Similarly in binary arithmetic we must add not only the digit of like significance of the two
numbers to be summed, but also the carry bit (should one be present) of the next lower significant digit.
This operation may be carried out in two steps :-first, add the two bits corresponding to the 2 digit, and
then add the resultant to the carry from the 2"-1 digit. A two-input adder is-called a half adder, because
to complete and addition requires two such half adders.
We shall show how a half adder is constructed from the basic logic gates and then indicate how the full
or complete, adder is assembled. A half adder has two inputs -A and B- representing the bits to be
added, and two outputs,-D (for the digit of the same significance as A and B represent) and C (for the
carry bit).
5.6.2. PARALLEL OPERATION
Two multi-digit numbers may be added serially (one column at a time) or in parallel (all columns
simultaneously). Consider parallel operation first. For an N-digit binary number there are (in addition to
a common ground) N signal leads in the computer for each number. The ninth line for number 1 (or B) is
excited by 1 (or B). The bit for the 2" digit (n = 0, 1, ..., N-l). A parallel binary adder is indicated in Fig.
5.22. Each digit except the least significant one (2) requires a complete adder consisting of two half
adders in cascade. The sum digit for the 2 bit is S = D of a half adder because there is no carry to be
added to A plus B. The sum S (N = 0) of A + B is made in two steps.
First the digit D is obtained from one half adder, and then D is summed with the Carry C -1 which may
have resulted from the next lower place. As an example, consider N = 2 in Fig. 5.22. There the carry bit
C1 may be the result of the direct sum of A1 plus B1 if each of these is 1. This first carry is called C11 in
Fig. 5.22.. A second possibility is that A1 -1 and B1 = 0 (or vice versa), so that D1 -1, but that there is a

101
carry C0 from the next lower significant bit. The sum of D1 = 1 and C0 = 1 gives rise to the carry bit
designated C12. It should be clear that C11 and C12 cannot both be 1, although they will both be 0 if A1=
0 and B1 = O. Since either C11 or C12 or C12 must be transmitted to the next stage, an OR gate must be
interposed between stages, as indicated in Fig. 5.22.
5.6.3. FULL ADDER
In integrated circuit implementation, addition is performed usinga complete adder, which (for reasons
of economy of components) is not constructed from two half adders. The symbol of the ninth full adder
(FA) agnued B, and the: input carry C-l (from the next lower bit). The outputs are the sum S (sometimes
designated) and the output carry C. A parallel 4-bit adder is indicated in Fig.5.23b. Since FAO represents
the least significant bit (LSB) it has no input to carry, hence C-1 = O.
LINE INPUT OUTPUT

An Bn Cn-1 Sn Cn
0 0 0 0 0 0
1 0 0 1 1 0

102
2 0 1 0 1 0
3 0 1 1 0 1
4 1 0 0 1 0
5 1 0 1 0 1
6 1 1 0 0 1
7 1 1 1 1 1
TABLE 5.7. TRUTH TABLE FOR FULL ADDER
The circuitry within the block FA may be determined from Table 5.7 which is the truth table for adding 3
binary bits. From this table we can verify that the Boolean expressions for Sand C are given by :-
𝑆𝑛 = 𝐴𝑛 𝐵𝑛 𝐶𝑛 − 1 + 𝐴𝑛 𝐵𝑛 𝐶𝑛 − 𝑙 + 𝐴𝑛 𝐵𝑛 𝐶𝑛 − 𝑙 (5-1)
𝐶𝑛 = 𝐴𝑛𝐵𝑛𝐶𝑛 − 𝑙 + 𝐴𝑛𝐵𝑛𝐶𝑛 − 1 + 𝐴𝑛𝐵𝑛𝐶𝑛 − 𝑙 (5-2)
Note that the first term of S corresponds to line 1 of the table, the second term to line 2, the third term
to line 4 and the last term to line 7. (These are the only rows where S = 1). Similarly, the first term of C
corresponds to the line 3 (where C = 1), the second term to the line 5, etc.
The AND operation ABC is sometimes called the product of A and B and C. Also the OR operation, + is
referred to as summation. Hence expressions such as, those in Eqs. Such and equation iscalled a
miniterm. A miniterm contains the product of all Boolean variables or their complements.
The expression for C can be simplified considerably as follows :-
Since Y + Y + Y = Y shown Eq. (17.2) with Y = ABC becomes
Cn + (AnBn Cn-1 + AnBn Cn-1) + (AnBn Cn-1 + AnBn Cn-1) + AnBn Cn-1 + AnBn Cn-1 (5-3)
Since X + X = 1 where X = An for the first parentheses, X = Bn for the second parenthesis, and X = C for
the third parenthesis, then Eq. (5.3)
𝐶𝑛 = 𝐵𝑛 𝐶𝑛 − 1 𝐴𝑛 + 𝐴𝑛 𝐵𝑛 (5-4)
This expression should have been written down directly from the truth table noting that Cn = 1 if and
only if at least two out of the three inputs is 1.
It is interesting to note that if all 1s are changed to 0s and all 0s to 1s, then lines 0 and 7 are
interchanged, as are 1 and 6,2 and 5 and also 3 and 4.
Because this switching of 1s and 0s leaves the truth table unchanged, whatever logic is represented by
table 5.7 is equally valid if all inputs and outputs are complemented. Therefore Eq. 5-3 is true if all
variables are negated, or are complemented. Therefore Eq. 5-3 is true if all variables are negated or
𝐶𝑛 = 𝐵𝑛 𝐶𝑛 − 1 + 𝐶𝑛 − 1 𝐴𝑛 𝐵𝑛 (5-5)

103
This same result is obtained by Boolean manipulation of Eq. 5-4.
By evaluating 𝐷𝑛 = (𝐴𝑛 + 𝐵𝑛 + 𝐶𝑛 − 1) 𝐶𝑛and comparing the result with Eq. 5-4 we find that
𝑆𝑛 = 𝐷𝑛 + 𝐴𝑛 + 𝐵𝑛 + 𝐶𝑛 − 1 or
𝑆𝑛 = 𝐴𝑛 𝐶𝑛. + 𝐵𝑛 • 𝐶𝑛 − 1 𝐶𝑛 + 𝐴𝑛 𝐵𝑛 𝐶𝑛 − 1 (5-6)
Eqs. 5-1 and 5-6 are implemented in Fig. 5.24.
5.6.4. SERIAL OPERATION
In a serial adder the inputs A and B are synchronous pulse trains on two lines in the computer. Fig. 5.25a
and b show typical pulse trains representing respectively the decimal numbers 13 and 11. Pulse trains
representing the sum (24) and difference (2) are shown in Fig. 5.25c and d, respectively. A serial adder is
a device which will take as inputs the two waveforms of Fig. 5.25a and b and deliver the output
waveform in Fig. 5.25s. Similarly a subtractor (sec 57) will yield the output shown in Fig. 5.25d.

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We have already emphasized that the sum of two multi-digit numbers may be formed by adding to the
sum of the digits of like significance they carry (if any) which may have resulted from the next lower
place.
With respect to the pulse trains of Fig. 5.25 the above statement is equivalent to saying that, any instant
of time, we must add (in binary form) to the pulses A and B the carry pulse (if any) which comes from
the resultant formed one period T earlier. The logic outlined above is performed by the full-adder circuit
of Fig. 5.26. This circuit differs from the configuration in the parallel adder of Fig.5.23 by the inclusion of
a time delay TD which is equal to the time T between pulses. Hence the carry pulse is delayed at time T
and added to the digit pulses in A and B, exactly as it should be.
A comparison of Figs. 5.23 and 5.26 indicates that parallel addition is faster than serial because all digits
are added simultaneously in the former, but in sequence in the latter. However, whereas only one full
adder is needed for serial arithmetic, we must use a full adder for each bit in parallel addition is much
more expensive than serial operation.
The time delay unit TD is a type D flip-flop, and the serial AnBnand Sn are stored in shift registers.
5. 7 .BINARY SUBTRACTION

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Tile process of subtraction (minus) is equivalent to the addition if the complement A of the subtrahend
is used.
5 .7 .1 HALF SUBTRACTOR
A half subtractor is a logic circuit with two inputs A and C and two outputs (D and B). The circuit can
subtract two binary one-bit numbers (A-C) to give a different digit (D) and a borrowed digit B as shown
by the truth table 5.8 below.
we can write the Boolean formula for D output terminal D = A.C + A.C. From this formula we can note
the two inputs are connectedto EX-OR to get the output (D). Also the Boolean formula for the B terminal
is B = A.C. this formula is represented by AND gate with one input terminal (A terminal) is inverted as in
Fig. 5.27 a and b.
INPUT OUTPUT
A C D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
TABLE 5.8 TRUTH TABLE FOR HALF SUBTRACTOR
5.7.2. BINARY FULL-SUBTRACTION
Subtraction of positive, multi-digit numbers is performed between two binary numbers, A (the minuend)
and B (the subtrahend) on a digit by digit basis starting with the least significant order. The truth table
for the ninth significant digit is given in Table 5.9.
INPUT OUTPUT
An Cn Bn-1 Dn Bn
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
1 0 0 1 0
0 1 1 0 1

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1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
TABLE 5.9 TRUTH TABLE FOR FULL SUBTRACTOR
is the different digit and Bn is the borrow from the next higher order. Bn-1 is the borrow to the next
lower order and must be subtracted from the minuend. Inspection of the truth table yields the following
relationships for Dn and Bn :-
= 𝐵𝑛 − 1 + 𝐴𝑛 + 𝐵𝑛
= 𝐴𝑛 𝐵𝑛 + 𝐴 + 𝐵𝑛. 𝐵𝑛 − 𝑙

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FLIP FLOPS
CONTENTS
6.1 INTRODUCTION
6.2 THE S-R FLIP FLOP
6.3 THE D FLIP FLOP
6.4 THE J-K FLIP FLOP
6.5 THE J-K MASTER SLAVE FLIP FLOP
6.6 THE T FLIP FLOP
6.7 EDGE TRIGGERED FLIP FLOP
6.1. INTRODUCTION
The logic devices discussed previously are known as "combinational circuits" and their outputs depend
solely on the inputs not on the sequence in which the inputs are applied, or on the state of the before
the inputs are applied. Circuits whose outputs do depend on the sequence in which the inputs are
applied or on the previous state of the circuit are known as "sequential circuit" and fall into two types:
synchronous, where the change in the output is synchronised with clock and asynchronous where the
output is independent of the clock.
To keep track of a sequence of events, a device having the capability to remember things (a memory) is
required. There are many forms of memory or storage such as magnetic core stores, and magnetic tapes
used in computers. The most usual memory device in industrial control systems is an electronic circuit
called a "flip-flop". There are various types of flip-flop, and some of the most important are covered
below.
6.2. THE SET AND RESET FLIP FLOP (S-R FLIP FLOP OR LATCH)
The S-R flip flop is the simplest form of binary storage element.The latchis a static flip flop fig. 6.1 is the
circuit symbol of a latch. Very commonly the name S-R flip-flop is used. The latch has 2 inputs, S and R,
and 2 outputs Q and 𝑄̅ . Applying the appropriate logic signal to either the S or R input will put the latch
into a stable state. The S input is used to set the latch and just on the same line with Q. When a latch is
set, it is said that it is storing a binary 1. The R input is used to reset the latch and on the same line with
𝑄̅ . The stable state in which a latch is one can find at the output. The output Q is the normal output and

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the output 𝑄̅ is the complement output. If a latch is set or storing binary 1 the output Q will show this
binary 1 and the 𝑄̅ output the binary 0 (complement of Q).
If a latch is reset or storing a binary 0, the Q output will show this binary 0 and the 𝑄̅ output binary 1.
Table 6-1 is showing this relationship between the inputs of the flip-flop and the output
S R Q 𝑄̅ state
0 0 No change No change
0 1 0 1 reset
1 0 1 0 set
1 1 indeterminate indeterminate
Table 6-1 The Standard truth table for S-R flip-flop
A latch can be constructed using a combination of NAND-gates or a combination of NOR-gates.
6.2.1. NAND GATES S-R LATCH
The operation of the NAND-gate latch can be seen of the table 6-2 and fig 6-2.
𝑆̅ 𝑅̅ 𝑄𝑛 𝑄̅ 𝑛 𝑄𝑛 + 1 𝑄̅ 𝑛 + 1 STATE
0 0 0 1 1 1 INDETERMINATE
0 0 1 0 1 1
1 0 0 1 0 1 RESET
1 0 1 0 0 1
0 1 0 1 1 0 SET
0 1 1 0 1 0
1 1 0 1 0 1 NO CHANGE
1 1 1 0 1 0
Qn the logic before applying ̅𝑆 − 𝑅̅ logic – Qn + 1 the output after applying ̅𝑆 − 𝑅̅logic.
Table 6-2 the truth table for a NAND S-R latch figure 6-2

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If both inputs (𝑆̅and 𝑅̅) are binary 0 the latch is in a forbidden state. Because both outputs show a binary
1, the output 𝑄̅ is the complement of the output Q. In this case both outputs show the same condition
which is not allowed. Using a latch this conditionmust be avoided because this considered the
disadvantage of the ̅𝑆 − 𝑅̅. If the 𝑆̅ input is binary 0 and the 𝑅̅ input is binary 1 the output Q shows a
binary 1. A binary 1 at Q means the latch is set. A latch built out of Two NAND gates is set if a binary 0 is
applied to the 𝑆̅ input.
If a binary 1 is applied to 𝑆̅ input and a binary 0 to the 𝑅̅ input the output Q will Show binary 0. A binary
0 at Q mean that the latch is in the reset state.
If both input (𝑆̅and 𝑅̅) are binary 1 the condition of the output Q will not change. If output Q was at
binary 1 or 0 it will remain 1 or 0.
As seen from the truth table 6-2 the output Q is different from the standard table 6-1. That means if
binary 1 at 𝑆̅ input and 0 at 𝑅̅ the latch will store 0 and 1 at Q and 𝑄̅ .
To construct latch S-R using NAND gates matching the standardtruth table then two inverter must be
connected to ̅𝑆 − 𝑅̅ terminals. See fig 6-3 and Truth table 6-3.
𝑆 𝑅 𝑆̅ 𝑅̅ 𝑄𝑛 𝑄̅ 𝑛 𝑄𝑛 + 1 𝑄̅ 𝑛 + 1 𝑆𝑇𝐴𝑇𝐸
0 0 1 1 0 1 0 1 NO CHANGE
0 0 1 1 1 0 1 0
1 0 0 1 0 1 1 0 SET
1 0 0 1 1 0 1 0
0 1 1 0 0 1 0 1 RESET
0 1 1 0 1 0 0 1
1 1 0 0 0 1 1 1 INDETERMINATE
1 1 0 0 1 0 1 1
Table 6-3 The truth table of a NAND S-R latch

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Fig 6-4 shows the operation of a latch (NAND-gates) using time chart. The indeterminate state (both
inputs binary 1} is not mentioned in the chart, because this state is not wanted.
6.2.3. NOR GATES S-R LATCH
A latch can be constructed also out of NOR-gates Fig 6.5 shows a latch based on NOR-gates.
Table 6-4 shows the truth table of a latch built out of NOR gates. Fig 6-6 the time chart of a NOR-gate
latch.
INPUTS OUTPUTS STATE

S R Q 𝑄̅
0 0 Q 𝑄̅ NO CHANGE
0 1 0 1 RESET
1 0 1 0 SET
1 1 1 0 INDETERMINATE
Table 6-4 Truth table of a NOR-gate latch.

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Fig. 6-7 shows a typical push button switch and fig. 6-8 shows how a NOR-gate lat.ch can be used to built
a "bounce-less push button switch" .
To avoid the indeterminate state in the latch used in fig. 6-8. A SPDT (SPDT = Single Pole Double
through) must be used which breaks the contact first before making contact. To avoid the indeterminate
state the latch can be controlled by one input only. An inverter is connected between both inputs to
make sure, that the signal at the R input is always the complement of the signal at the S input. fig 6-9
shows the circuit symbol of a NOR gate latch. The two inputs are interconnected via an inverter.

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6.2.4. THE CLOCKED OR GATED SR FLIP FLOP
Fig.6-10 shows how a NAND gate S-R flip-flop can be clocked or gated. Whenever clock is at logical 0, the
output of both theinput NAND-gates must be at logical 1 whatever the logical states of the S and the R
inputs. Suppose the circuit is set, then Q = 1, 𝑄̅ = 0 and so the upper right-hand gate has one input at 1
̅̅̅̅ + 𝐶̅ 𝑆̅) and one at 0 (𝑄̅ ), and hence the Q output remains at 1.The lower right-hand gate has both
(𝐶𝑆
of itsinputs at 1 and so the 𝑄̅ output remains at 0. Only when the clock input is 1 can the appropriate
input gate (S or R = 1) have an input at 0 for a possible switching action to be initiated. This means that,
when the clock is 1, the circuit operates in the same way as the NAND circuit.
6.2.5. Preset and clear for S-R flip-flop
The clocked S-R flip-flop is often provided with clear and preset terminals (fig. 6-10) that allow the
normal inputs to be overridden.
6 .3 THE D FLIP FLOP
The delay type flip-flop has a single input terminal (D). Its constructed from an S-R flip- flop by
connecting an inverter internally between S and R, so that R always carries the complement of the logic
at S. See Fig 6-12 its logical operation is such that its Q output always takes on the same logic state as its
D input. The truth table of a D flip-f1op is given by table 6-5 any change in the output slate occurs when
the clock (CK) is 1 .When the clock is 0 the output isunable to follow the D input and the circuit is said to
be latched,
Fig 6-11 shows the circuit symbol of a D type flip-flop

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𝐶𝐾 𝐷 𝑄𝑛 𝑄̅ 𝑛 𝑄𝑛 + 1 𝑄̅ 𝑛 + 1 𝑆𝑇𝐴𝑇𝐸
0 X 0 1 0 1 NO CHANGE
0 X 1 0 1 0
1 0 0 1 0 1 RESET
1 0 1 0 0 1
1 1 0 1 1 0 SET
1 1 1 0 1 0
X means do not care if it is 0 or 1
Qn, 𝑄̅ 𝑛 logic state before applying input logic
Qn + 1, 𝑄̅ 𝑛 + 1 logic state after applying the input logic
Table .6-5 Truth table for the D flip-flop
The advantage of D type over S-R flip flop
There is no indeterminate state
The disadvantage of D flip flop
There is no (No change) condition that means the D type act as a delay circuit.
6.4. THE J-K FLIP-FLOP

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The J -K flip-flop does not have the indeterminate output state ofS-R flip-flop and the two outputs are
always opposite so that Q and 𝑄̅ are the correct designations.
It can perform all of the function of the S-R flip flop and D flip-flop.
The J-K is constructed using S-R flip flop as shown in Fig. 6.13 band c.
The logical operation is as follows see table 6-6.
INPUT LOGIC FEEDBACK 2 NAND 𝑆̅ – 𝑅̅ FLIP FLOP STATE

𝐶𝐾 𝐽 𝐾 𝑄𝑛 𝑄̅ 𝑛 𝑆̅ 𝑅̅ 𝑄𝑛 + 1 𝑄̅ 𝑛 + 1
0 X X 0 1 1 1 0 1 NO CHANGE
0 X X 1 0 1 1 1 0
1 0 0 0 1 1 1 0 1 NO CHANGE
1 0 0 1 0 1 1 1 0
1 1 0 0 1 0 1 1 0 SET
1 1 0 0 1 1 1 1 0
1 0 1 1 0 1 0 0 1 RESET
1 0 0 0 1 1 1 0 1
1 1 1 1 0 1 0 0 1 Changes Q and 𝑄̅ to the
opposite state
X do not care
Qn and𝑄̅ 𝑛 the output of the flip flop before applying the input logic
Qn+1 and𝑄̅ 𝑛 + 1 the output of the flip flop after applying the input logic
Table 6-6 the truth table of JK flip-flop.
1- If CK = 0, then 𝑆̅ = 𝑅̅ = 1 (what ever the logic at J and K). Since 𝑆̅ = 𝑅̅ = 1 then No change for Q and 𝑄̅ .
2 -If CK = 1 and J = K = 0, then 𝑆̅ = 𝑅̅ = 1. Also No change.
3 -If (a) CK = 1, J = 0, K = 1 and Q = 0. Then 𝑆̅ = 𝑅̅ = 1, that means no change (Q will remain at logic 0).
(b) CK = 1, J = 0, K = 1 and Q = 1 .Then𝑆̅ = 1 and 𝑅̅ = 0. This will be reset the output (Q = 0)
4 -If (a) CK =1, J =1, K=0 and Q=0. Then 𝑆̅=0 and 𝑅̅ = 1. This condition will set the output (Q=1)
(b) CK=1, J = 1, K=0 and Q = 1. Then 𝑆̅ = 1 and 𝑅̅ = 1 that means the output will remain in the set
condition.
5 -If (a) CK = 1, J=K=1 and Q = 0. Then 𝑆̅ = 0 and 𝑅̅ = 1 this set the output (Q = 1 = 𝑄̅ = 0) See table 6-6
(b) CK = 1, J=K=1 and Q = 1. Then 𝑆̅ = 1 and𝑅̅ = 0. The F.F will be rest (Q = 0 and 𝑄̅ = 1) from a)
and b) we can note that the output has changed to the opposite state. See table 6-6.

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6 -4 -2 THE JK PRESET AND CLEAR TERMINALS
The truth table tells us what happens to the output with the application of a clock pilse, as a function of
the data input J and K. However, the value of the output before the pulse is appliedis arbitrary. The
addition of inputs in figure allows the initial state of the flip-flop to be assigned. The two terminals of
preset and clear is connected internally.
The logical operation of the preset and clear terminals is indicated in Table 6-7.
Pr Cr CK J K Q 𝑄̅ STATE
0 1 X X X 1 0 SET
1 0 X X X 0 1 RESET
1 1 Q depend upon CK - J - K logic
Table 6 -7 the truth table of Pr -Cr terminals
6-4-3.The advantage of J-K flip flop
The Principle advantage of J-K Flip-flop is this no indeterminate state.
6.4.4. The disadvantage of J-K flip flop
The Principle advantage of J-K Flip-Flop, arise when J=K=1 and the clock pulse = 1, from the truth table
the output must change to the opposite state and while the clock pulse remain at 1 the output will
change again each 2∆ t (∆ t delay time for each NAND-gate). 11).This situation is called a RACE AROUND
condition. To avoid the RACE AROUND condition the time domain of the clock pulse must be less than
2∆t.
6. 5 THE JK MASTER SLAVE FLIP FLOP
In practice, the simple J-K flip-flop suffers from the disadvantage that if the clock is still high and the J or
K inputs change, the flip-flop will be immediately set or reset. This problem is overcome by using a
master-slave J-K flip-flop. Fornormal operation the set and clear (reset) must be inactive i.e. high or logic

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1; the device will then change state on the negative or trailing edge of the clock. The symbol of the J-K
master-slave flip-flop is given in fig. 6-14.
The circuit of a master-slave bistable or flip-flop is shown in fig, 6-15, The left-hand flip-flop is the master
and the right hand flip-flop is the slave. Suppose that initially the flip-flop is set so that Q = 1. When the
clock is 0, the master will have J= K = 0 and hence its outputs Q and (𝑄̅ ) remain at 1 and 0 respectively.
The clock input to the slave is inverted and so the slave has S = 1, R = 0. This condition sets the slave to
retain Q and 𝑄̅ at 1 and 0 respectively.
When a clock pulse arrives, CK=1, either J or K or both could be at 1. If J = 1, K= 0 bothinputs to the
master are at 0 (since 𝑄̅ = 0) and switching is not initiated. Suppose that now J = 0, K= 1, the three inputs
to the lower input AND gate are all at 1 and the master flip-flop has inputs J = 0, K = 1 applied.
The master therefore changes the state to have Q = 0, (𝑄̅ = 1). However, since the clock is inverted, this
change of state cannotbe passed onto the slave, both of whose inputs remain at 0, so that at the output

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the condition Q = 1, 𝑄̅ = 0 is retained. At the end of the clock pulse CK= 0 and now the lower slave input
AND gate has both its inputs at 1. Therefore the slave has S = 0, R= 1 and switches states to give Q = 0,
𝑄̅ =1. Thus the slave is reset by the trailing edge of the clock pulse. Lastly, consider that J = K = 1. Since
the circuit is set 𝑄̅ = 0 and one of the three inputs to the upper input AND gate is 0 and hence the J input
of the master is also 0. The lower input gate now has all three inputs at 1 when a clock pulse arrives and
so the master has K = 1. Thismeans that the operation when J = K = 1 is the same as for the condition
J=0, K = 1 just described.
Consider now the circuit operation when the flip-flop is initiallyreset, i.e. Q = 0, 𝑄̅ = 1. When J = 1, K = 0,
the J input of the master will become 1 once a clock pulse is present but the K input will be at 0. Hence Q
̅ = 0) but state of Q cannot bepassed onto the slave's J input because the inverted clock pulse
=1, (𝑄
inhibits the slave input AND gates.
When the clock changes from 1 to 0, the S input of the slave willbecome logical 1 and the slave will be
set to have Q = 1, 𝑄̅ = 0. The input state J = 0, K = 1 will not initiate switching since for this condition
neither gate will have all its three inputs at 1.
Master- slave J-K flip-flops are readily available in the TTL and CMOS families and fig. 6-15 shows the pin
connections of the 7476, a TTL circuit providing dual J-K master-slave flip-flops withpreset and clear.
Preset and clear terminals are provided withthis particular integrated circuit and act like set and reset
terminals which can be to control the output of the flip-flopindependently from the J, K and clock inputs.
When the preset and the clear inputs are at logic 1, the clock at1 will enable the J and K inputs. The truth
table describing thelogical operation is given by table 6-7. Also note that the two preset and clear
terminals are connected internally.
In the table the symbol X denotes that the logic level is irrelevant T. E means trailing edge.
PRESET CLEAR CLOCK J K Qn Qn + 1

0 1 X X X 0 1
0 1 X X X 1 1
1 0 X X X 0 0
1 0 X X X 1 0
1 1 T.E. 1 - 0 0 0 0 0
1 1 T.E. 1 - 0 0 0 1 1
1 1 T.E. 1 - 0 1 0 0 1
1 1 T.E. 1 - 0 1 0 1 1
1 1 T.E. 1 - 0 0 1 0 0
1 1 T.E. 1 - 0 0 1 1 0
1 1 T.E. 1 - 0 1 1 1 0
1 1 T.E. 1 - 0 1 1 0 1
1 1 1 X X 0 0
1 1 1 X X 1 1
TABLE 6-8. The table of the Master - Slave J-K flip- flop.

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6 .6 .THE T TYPE FLIP- FLOP
This type changes state with each clock pulse and hence it acts as a toggle switch. If J=K= 1, then
Qn+1=Qn and If J=K= 0, then Qn+1=Qn (No change). The J-K master-slave is converted into T-type by
short circuited J terminals see fig 6-17 andTable 6-9.
CK T Qn + 1
0 X Qn
1 X Qn
T.E 1 𝑄̅ n
T.E 0 Qn
Table 6-9 truth table for T flip-flop
6-7 EDGE TRIGGERED FLIP-FLOP
As an alternative to the use of the master-slave Principle a clocked flip-flop can be edge-triggered. With
a flip-flop of this type, changes outputstates are initiated by changes in the clock pulses. Any change in
the input (J, K or D) that should occur while the clock is steady at logical 1 will not affect the output of
the circuit,whilst the low power schottky (LS- TTL) versions are edge -Triggered.
Edge -triggered flip-flops, both J-K and D, are available in theTTL family, e.g. 7470 is a J-K flip-flop circuit.
and 7474 is a dual D flip-flop.

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COUNTERS
CONTENTS
7 .1.INTRODUCTION.
7.2. NON-SYNCHRONOUS COUNTERS 1
7 .3 .CLOCKS
7 .4 .SHIFT REGISTERS
7 .5 .EXERCISES
7.1. INTRODUCTION
A counter is an electronic circuit that is able to count the number of pulses applied to its input terminals.
The count may be outputted using the straight forward binary code, or be in binary coded decimal, or in
some other version of binary notation. Alternatively, the outputs of a counter may be decoded to
produce a unique output signal to represent each possible count. A counter may also be used as a
frequency divider, in which case only one output terminal is required.
Essentially, a counter consists of the tandem connection of a number of flip-flops, usually of the J-K type
which may be operated either synchronously or non-synchronously. With synchronous operation all the
flip-flops making up the counter operate at the same instant in time under the control of a clock pulse.
In the case of non-synchronous operation each flip-flop operates in turn. The switching of the least
significant flip-flop is initiated by a clock pulse but the remaining flip-flops are each operated by the
preceding flip-flop. This means that each stage must change state before the following stage can do so.
As a result synchronous operation of a counter is much faster and the use of a non- synchronous
counter is only acceptable when the speed of operation is not of particular importance. On the other
hand a synchronous counter is more complex and so is more expensive.
A counter can be constructed by suitably interconnecting a number of integrated circuit J-K flip-flops
and, perhaps, gates; but more conveniently several different types of counter are available in integrated
circuit form.
7.2. NON-SYNCHRONOUS COUNTERS
A single J-K flip-flop will act as a divide-by-two circuit. If its J and K terminals are both held at logical 1
and a clock pulse is applied to its clock input terminal, the flip-flop will toggle and so the Q output will
switch backwards and, forwards between logical 1 and logical 0 (figure 7.1.). The flip-flops used here are
assumed to toggle at the trailing edge of the clock pulse, i.e. as the clock pulse changes from 1 to O.
Clearly the number of pulses per second occurring at the Q terminal is only one-half of the number of

120
clock pulses. For counts in excess of two, a number n of J-K flip-flops must be connected in cascade to
give a maximum count of 2n.
Figure 7.2 shows how a non-synchronous counter can be constructed from four J-K flip-flops. The J and
the K inputs of each flip-flop are permanently connected to the logical 1 voltage level so that each flip-
flop will be toggled by a pulse applied to its clock input. The connections of the J and K terminals to 1 are
not shown in the diagram. The Q output of the first, second, and third stage is connected to the clock
input of the following stage. The Q terminals are left unconnected. Each J-K flip-flop is switched by its
clock input. In the figure the logical state of each stage is indicated by a light emitting diode (LED)
connected from the Q terminal to earth via a current-limiting resistor. A LED is a semiconductor device
which emits visible light when it is forward biased and passes a sufficiently large current. The LED will
visibly glow whenever the associated Q terminal is at logical 1 (+5V).
Suppose that initially each stage is reset, i.e. QA = QB = QC = QD = O. The trailing edge of the first clock
pulse will toggle flip-flop A so that QA becomes logical 1. Only LED D1 will glow and the displayed count
will be 0001 (reading from the right) or decimal 1.
The next clock pulse will toggle flip-flop A and the change of QA from 1 to 0 will set flip-flop B. Thus,
after two clock pulses have been applied to the counter, only LED D2 will glow. The third clock pulse will
set flip-flop A so that Q4 changes from 0 to 1 but such a change will not affect the state of flip-flop B and
so this stage remains set. Now both the first two stages are set, QA = QB = 1, and the last two stages
remain reset, QC = QD = 0. LEDs D1 and D2 are lit and the displayed count is 0011 or decimal 3. When
the fourth clock pulse arrives, the first stage toggles so that QA changes from 1 to 0, and this change
causes flip-flop B to reset.Thus QB changes from 1 to 0 and in so doing sets flip-flop C; now QA = QB =
QD = 0 and QC = 1. This condition is indicated by only LED D3 emitting light. The operation of the
counter as the fifth, sixth, seventh, etc. clock pulses are apl1ied follows the same lines as just described
and can be summarized by the truth table of the counter (see table 7.1.).
CLOCK PULSE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
QB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
QC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
Table 7.1. Counter sequence of 4-stage counter.

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The operation of the counter can be illustrated by the wave forms given in figure 7.3. The Q outputs of
the flip-flops seem to ripple through the circuit and for this reason this type of circuit is often known as a
ripple counter.
The count displayed by the LEDs, is of a binary nature and the counter operates non-synchronously
because the flip-flops operate at different times, shown at the end of the eighth and the sixteenth clock
pulses by the vertical dotted lines. There is a maximum clock frequency that can be used since the
periodic time of the clock waveform must be greater than the sum of propagation times, through the
counter, and the time duration of the output pulse.
Often a binary readout of the count is undesirable; when this is 50 the outputs of the individual flip-flops
of the counter can be decoded so that each count produces a unique output signal. Decoding can be
achieved by connecting the Q and the 𝑄̅ outputs of each flip-flop to the inputs of a number of gates. This
is shown by figure 7.4 for a 2-stage counter. The output of a 2-input AND gate is 1 only when both its
inputs are at 1. Hence the top gate, for example, will only have an output of logical 1 when QA = QB = 1
and the count is 3. Some integrated circuit counters include the decoding circuitry within the package.
7.3. CLOCKS

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Most digital circuits use some form of pulse generator, known as the clock to control the times at which
the various stages change state. At lower frequencies a clock may consist of an astable multivibrator or a
Schmidt trigger oscillator but at higher frequencies the clock is usually some form of crystal oscillator in
order to achieve good frequency stability.
SCHMIDTT TRIGGER
A Schmidtt trigger is a circuit, readily available as an integrated circuit, whose output voltage can have
only one of two possible values. The output voltage will be high, +3.3V for a TTL version, when the input
is greater than a positive going threshold voltage, and will remain at this value until such time as the
input voltage falls below the negative going threshold voltage.
The operation of a Schmidtt trigger circuit is shown by figure 7.4; when the input sinusoidal voltage
becomes more positive than the positive threshold voltage, the output of the circuit switches to become
+3.3V. The output voltage stays at +3.3V until the input voltage falls below the negative threshold
voltage and then the output voltage suddenly switches to very nearly OV. The output voltage will now
stay at OV until the input again becomes more positive than the positive threshold voltage. The
Schmidtt trigger is used to convert signals of varying wave shapes into rectangular pulses of short rise
time and fall time.

123
The symbol for a Schmidtt trigger is shown in figure 7.5a. Also shown in figure 7.5b is a diagram of how a
Schmidtt trigger can be used as a clock oscillator. Note that the Schmidtt trigger symbol indicates that its
output is inverted, i.e. the output is low when' the input is high.
CRYSTAL OSCILLATOR
When a crystal oscillator is used as the clock, it is necessary to convert its sinusoidal output voltage into
the required rectangular waveform; this is easily achieved with the use of a Schmidtt trigger as shown by
figure 7.6.
USING LOGIC GATES
Another way of producing a clock is by the suitable interconnection of logic gates. Since inverters (or a
NAND or NOR gate) include amplification, they can be used to form an oscillatory circuit because
essentially an oscillator is merely an amplifier that provides its own input signal. One way in which
inverters (or a NAND or NOR gate) can be connected to form a clock is shown in figure 7.7a. The
feedback network is provided by capacitor C and resistor R together with inverter B. The amplifier is
provided by the inverter A.
Suppose that initially the capacitor C is discharged so that the clock output is zero. The gate B inverts its
input voltage and so its output voltage is at the logical 1 level. Capacitor C is therefore charged via R
with a time-constant of RC seconds. As C charges, the voltage across it rises until it becomes equal to the
value corresponding to logic 1. Immediately the output of the gate B goes to logical 0 and so the output
of gate A -which is the required clock output -goes to logical 1. Now capacitor C commences to discharge
via R to the output of gate B. Once C has discharged to the level at which the output of gate B switches B
to logical 1, the output of gate A goes to logical O. The frequency of operation of the clock is determined
by the time constant RC.

124
An alternative method of making a clock from invertors is to connect them in an a stable multivibrator
arrangement, a possible circuit being given by figure 7.7b. The operation of a stable multivibrators is
covered by the module 0202-08 (Telecom Elements I) .
7.4. SHIFT REGISTERS
A shift register consists of a number of J-K flip-flops connected in cascade as shown by figure 7.8a. The
connection of QA to JB and so QA to KB and so on ensures that each flip-flop will take up the state, Q = 0
or Q = 1, of the preceding flip-flop at the end of each clock pulse,. Each flip-flop transfers its bit of
information to the following flip-flop whenever a clock pulse occurs. Alternatively, D flip-flops can be
used with Q output of each stage connected to the D input of the next stage (see figure 7.8b). The flip-
flops are usually provided with a clear or reset terminal so that the register" can be cleared or set to 0.
Shift registers in the CMOS family generally use D flip-flops, whereas the TTL versions usually employ S-R
flip-flops.
Suppose that, initially, all four flip-flops are cleared, i.e. QA = QB = QC = QD = 0. If the data to be stored
by the register is applied serially to the input terminal, the input data will shift one stage to the right
each time a clock pulse arrives. This means that, if the data stored in the register is a binary number, the
most significant bit is on the right. If the data applied to the input terminal is 11010, the action of the
circuit is as follows.
At the end of the first clock pulse, QA = 1. After the second pulse QA = 0, QB = 1. The third clock pulse
will cause Qc = QA = 1 but the second flip-flop will now reset to have QB = O. The fourth bit of data is a 1
and this will be stored flip flop A at the end of the fourth clock pulse, when the bits stored by the other
Flip flops all move one place to the right. At this stage the data stored is 1010. There is one more bit, a 1,

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to be applied to the input terminal of the register. At the end of the next clock pulse, flip-flop A sets and
all the other flip-flops take up the state of the preceding stage. Now the complete number is stored by
the register.
The timing diagram illustrating the operation of the register is shown in figure 7.9. Note that the QA
waveform is delayed behind the input data waveform by a time that may not be equal (in the figure it
isn't) to the periodic time of the clock waveform however, the Q waveforms of all the other flip-flops are
delayed behind the Q waveform of the proceeding flip-flop by exactly the clock period.
The shift register can be used to multiply or divide a binary number by a factor of 2 by merely shifting
the number one place to the right or to the left, respectively. In either case any part of the number must
not be shifted right out of the register.
In general, a shift register can be used in anyone of four different ways. These methods are known as:-
1. Serial-in Parallel-out (SIPO)
2. Parallel-in Serial-out (PISO)
3. Serial-in Serial-out (SISO)
4. Parallel-in Parallel-out (PIPO)

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With a serial-in/parallel-out shift register (Fig. 7.10a), data isfed into the register in the manner
previously described and, when the complete word is stored, all the bits can be read off simultaneously
from the Q output of each stage. The register acts to convert data from serial into parallel form.
The parallel-in/serial-out shift register (Fig. 7.10b) operates in exactly the opposite way. The data to be
stored is set up by first clearing all the stages and then applying logic 1 to the preset terminal of each
stage which is to be set. The data can then be shifted out of the register, one bit at a time, under the
control of the clock.
The serial-in/serial-out shift register (Fig. 7.10c) can be used as a delay circuit, or as a short-term store,
but the stored data can only be accessed in the order in which it is stored.
Figure 7.10d shows a parallel-in/parallel-out shift register and this circuit also acts as a short-term store.
Sometimes there is a need for a shift register that has the capability to move data either to the left or to
the right. The circuit of such a register is shown in figure 7.11. There are two data input terminals, one of
which is used for serial data that is to be shifted to the right and the other is for left-shifting data.
The direction in which the data is shifted is determined by the logic levels on the two lines marked,
respectively, as Shift right l/shift left 0 and Shift right O/shift left 1.

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Table 7.3 CMOS shift registers
Number Type Shift

4006 18-stage static SISO Right
4014 8-stage static PISO or SISO Right
4015 dual 4-bit static SIPO Right
4021 8-stage, static PISO or SISO Right
4031 64-stage static S1S0 Right
4035 4-stage static PIPO Right
4062 200-stage dynamic S1S0 Right
40100 32-stage static S1S0 Left and right
40194 4-stage static Universal Left and right
The circuit is arranged so that the signals applied to these two lines are always the complement of one
another. When the top AND gates are enabled, the data-right input is connected to flip-flop A.QA is
connected to flip-flop B and so on, so that the circuit is similar to that given in figure 7.8b.
Conversely, when the lower AND gates are enabled, QD is connected to the D terminal of flip-flop C, Qc
is connected to flip-flop B and so on. The circuit will then shift data entered serially at the data-left
terminal to the left.
Shift registers are manufactured in both the TTL and the CMOS logic families.
7.5. EXERCISES
(1) How must a J-K flip-flop be connected in order for it to act as a toggle? Write down the truth
table of a toggle.
(2) (a) Explain how successive stages of bistable multivibrators like J-K flip-flops can be used to form a
non-synchronous counter.
(b) What is the maximum count obtainable from a ripple counter, with (i) 3, (ii) 5 and (iii) 7
cascaded flip- flops?
(3) Determine with a aid of a truth table, the operation of the counter shown in figure EX.I. Draw its
waveform diagram.
END

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MEMORIES AND REGISTERS

8.1. TYPES OF STORAGE
Many digital systems include a memory or store for the temporary or long-term storage of information.
In a digital computer, this information will include numerical data, the intermediate results of
computations, and the programmes which control the operation of the system. In a telephone
exchange, a memory may be used to store code translations and information about each line, such as its
number and the nature of the equipment connected to it. A memory should have sufficient capacity to
be able to satisfy all the demands made for data and programme storage and should be so fast to
operate that undue delay is not caused to the main processor. It is also desirable for a memory to be of
the minimum possible cost and to be reliable and also for the stored data to be retained if the power
supplies should be shut down. Because of the various demands on a memory a computer employs more
than one kind of store.
A main store contains all the information which must be immediately available, such as the interim and
final results of calculations. A larger-capacity backing store contains most of the data and the
programmes and it is used to hold information that need not be instantly accessed by the central
processor. Short-term memory is provided by registers. Registers are used to store the interim results of
arithmetic processes and for the movement of data between the processor and the main memory. The
memory-address register contains the address of the data held in the memory which is to be involved in
a read, or a write operation. Registers are also involved in the movement of data between the processor
and the input/output devices.
It must be possible both to write information into a memory and to read information out of the
memory. To make this possible a memory consists of a large number of locations in each of which a
small amount of data can be stored. Each location has a unique address so that it can be accessed from
outside the memory. The access time of a memory is the time that is needed to read one word out of
the memory, or to write one word into the memory. The access time of a main store must be measured
in nanoseconds and this means that it must be of the random access type. A random access memory, or
RAM, is one in which any location can be accessed without having to go through all the addresses in
numerical order. Thus the time taken to read from, or to write into, any location is the same as for any
other location. RAMs can be manufactured using large numbers of ferrite cores and are also available in
integrated circuit form.
The backing store is required to hold a large quantity of data at the minimum cost and it is generally
either a magnetic tape or a magnetic disc. Data can only be read out of or written into a tape or a disc as
the appropriate part of the tape (or disc) moves beneath the read and/or write head and this means
that the access time can be relatively long.
The basic requirements of any memory or store are that:-
(a) Any required location in the store can be addressed.

129
(b) Data can be read out of an addressed location.
(c) Data can be written into an addressed location (once only in some cases).
If a memory is able to retain the data stored in it when the power supplies have been switched off, the
memory is said to be nonvolatile. A volatile store will lose the data stored within it if the power supplies
are removed. Magnetic memories are nonvolatile and semiconductor memories are volatile.
Read -only memories, or ROMs, are memories into which data is permanently programmed either at the
time of manufacture or by the user prior to the memory being installed into the equipment. Essentially a
ROM consists of a matrix of conductors some of whose intersections are joined by diodes or transistors.
8.2 SEMICONDUCTOR MEMORIES
Semiconductor memories have now become the predominant memory technology because they are
cheaper, smaller, and faster operating than the magnetic alternatives. A complete random access
memory (RAM) or read only memory (ROM) can be formed within a single integrated circuit chip and
made available in a standard DIL package.
A memory consists of a matrix of memory cells together with digital circuits that provide such functions
as address selection and control. Each memory cell is situated at a matrix location that is identified by a
unique address.
8.2.1. RANDOM ACCESS MEMORIES
The matrix of a random access memory or RAM is organized as m words of n bits each i.e. m x n. The
memory cells are located at the intersections of the m rows and the n columns of the matrix. The idea is
illustrated by fig.8-1a which shows a square matrix in which m = n = 5. This is not a size used in practice
but has been drawn for simplicity. Practical RAMs may use a square matrix, for example 32 words of 32
bits (1024 bits or 1 kilobit) but often employ rectangular matrices; typical examples are 64 x 16 or 256 x4
(both 1 kilobit).

130
To reduce the number of column and row address lines needed, addresses are signaled using the binary
code and are decoded to provide voltages on the selected column and row lines. The arrangement used
is shown in fig. 8-1b. Suppose, for example, that the memory cell located at the intersection of row 2
and column 3 is to be selected. Then the input to the row decoder must be 010 and the input to the
column decoder must be 011.
The diagram also shows blocks marked as control circuitry/write amplifiers and control circuitry/sense
amplifiers. These circuits perform the functions either of writing new data into a location, or of reading
out existing data. The read/write input determines which of the two functions is performed. The chip
select or enable input must (usually) be high to enable the memory; this facility is used when two or
more chips are combined to produce a larger capacity memory.
When the state, 1 or 0, of a memory cell is to be read, the read/(write)* line is set to the logical 1
voltage level, and the address of the required location is fed into the address decoders. The data held at
that location then appears at the data-out terminal(s). The read -out process is non-destructive.
When new data is to be written into the memory, the read/(write)* line is set to the logical 0 voltage
level. The data present at the data-in terminal(s) will then be written into the addressed memory cell(s).
Two kinds of RAM are manufactured, known respectively as the static RAM and the dynamic RAM. In a
static RAM the memory cells are actually flip-flops that can be fabricated using either bipolar transistor
or MOSFET technology. Examples of static RAMs in the TTL family are the 74170 4 x 4 and the 74670 4 x
4, the former having a totem -pole output and the latter having a three –state output. MOS static RAMs
are of larger capacity, such as 4096 x 1 or 16384 x 1, and dissipate less power than the bipolar transistor
versions but, on the other hand, they have greater access time.
A dynamic RAM does not use flip-flops as the memory cells but, instead, data is stored in the stray
capacitances that inevitably exist between the gate and the source of a MOSFET. The dynamic RAM has
the advantages that:

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(i) A larger storage capacity can be provided within a given chip area,
(ii) It is faster to operate and is cheaper to fabricate than a static RAM.
On the other hand the dynamic RAM possesses the disadvantage of needing periodic refreshing of the
stored data.
A large number of static RAM's are available in the TTL family, among the memory capacities provided
are 16 x 4, 16 x 9, 16 x 12, 32 x 8,64 x 4, and 256 x 1.
Dynamic RAMs can only be provided using MOSFET technology, examples are 4K x 1 and 16K x 1.
8.2.2. READ ONLY MEMORIES
A read only memory or ROM has data written into it, in permanent form, by either the manufacturer or
the user. When in use, data can only be read out of the memory; new data cannot be written in. A ROM
is non-volatile.
The organization of a ROM is very similar to that of a RAM. Data is stored at different locations within
the memory matrix and each location has a unique address. When a particular location is addressed, the
data stored at that address is read out of the memory. The read-out is non-destructive.

132
The arrangement of a diode ROM is shown in fig. 8-2. Diodes are connected between some of the row
and some of the column lines. When a decoder line, 0 through 7, goes low, the associated diodes turn
ON. Each output line D0, D1, D2 or D3 connected to an ON diode is then taken low also. When for
example, the input address is A0 = 0, A1 = A2 = 1, line 6 goes low and the output of the ROM is D0 = D1 =
1, D2 = D3 = 0. The Boolean equation describing this action is
𝐹 = ̅̅̅̅
𝐷𝑂 𝐷1 𝐷2 ̅̅̅̅
𝐷3 + 𝐷𝑂 ̅̅̅̅
𝐷1 𝐷2 𝐷3 + 𝐷𝑂 𝐷1 ̅̅̅̅
𝐷2̅̅̅̅
𝐷3 +
̅̅̅̅ 𝐷1 𝐷2
𝐷𝑂 ̅̅̅̅ 𝐷3 + 𝐷𝑂 𝐷1 𝐷2 𝐷3
̅̅̅̅ + 𝐷𝑂 𝐷1 𝐷2
̅̅̅̅𝐷3
̅̅̅̅ +
𝐷𝑂 ̅̅̅̅
𝐷1 𝐷2 ̅̅̅̅
𝐷3 + 𝐷𝑂 ̅̅̅̅
𝐷1 𝐷2 𝐷3
Integrated circuit ROMs may use either bipolar or field effect transistors as the row and column linking
elements.
Typical applications for a ROM are code conversion, mathematical tables and programme controllers.
A ROM is programmed during manufacture and this data cannot be subsequently altered. This means
that the intending user must inform the manufacturer of the particular .data that each location is to
contain. This is alright for the large -scale user but it is much less convenient for the user of much
smaller quantities. To provide some flexibility in the possible applications of ROMs, programmable
devices are generally used.
8.2.3. PROGRAMMABLE ROMS
A programmable read only memory or PROM is designed so that it can be programmed by the user to
suit a specific application for the device. All of the intersections in the memory matrix are linked by a
fusible diode or transistor (see fig. 8-3.) When the RROM is purchased from the manufacturer, all of the
outputs are at the logical a or 1 voltage level. The programming procedure consists of changing the bits
stored at selected locations from 0 to 1 or vice versa.

133
Programming of a PROM is accomplished by addressing a particular location in the memory that is to

store a 1, and then passing a sufficiently large current through the transistor to blow the fuse. The
transistor no longer links the row and column lines at that location.
There are several TTL PROMs available, some examples being 74186 64 x 8, 74199 32 x 8, 74287 256 x 4,
and 74470 256 x 8. ECL devices are also available.
PROMs are widely used in the control of electrical equipment such as washing machines and ovens.
8.2.4. ERASABLE AND ELECTRICALLY ALTERABLE PROMS
Some PROMs can have their programmes altered and a new programme written into the memory. In an
erasable PROM or EPROM the logical 1 state is stored at a location by the storage of an electrical charge
and not by the blowing a fuse. When a programme is to be erased, the chip is exposed to ultra -violet
radiation that is directed through a window in the chip package. This radiation removes the stored
charge at every location in the memory so that all locations store binary O. Re-programming is carried
out by addressing each cell that is to store a logical 1 bit and then causing that cell to store a charge.
An alternative to the EPROM is known as the electrically alterable PROM or EAPROM. Again,
programming a memory cell to store logical 1 is accomplished by charging that cell. With the EAPROM,
however, the erasure procedure is carried out by applying a reverse -polarity voltage to a cell that
removes any storage charge. The EAPROM offers an advantage over the EPROM in that the erasure
process can be applied to an individual cell in the matrix if required.
Both EPROMs and EAPROMs are MOSFET devices but are not in the CMOS family.

134
INTRODUCTION TO MICROCOMPUTERS
CONTENTS
9. 1 .INTRODUCTION
9.2. MODE OF OPERATION
9.3. BASIC STRUCTURE OF COMPUTER SYSTEM
9.4. BASIC FUNCTIONAL UNITS
9.4.1. THE MICROPROCESSOR
9.4.2 MEMORY
9.4.3. HIGHWAY STRUCTURE
9. 4 .4 .ADDRESS CODING
9 .5 .EXERCISES
9.1 INTRODUCTION
The basic structure and' mode of operation of the first digital computer was proposed by the
mathematician Charles Babbage in the late 1830s. However, it was not until transistors were used to
build them did computers become sufficiently reliable for their full potential to begin to be explored.
Since the first transistor-based machine was produced, computers have been used in an increasing
variety of applications. These range from very large system such as those used by banks to maintain
customer accounts to quite small systems that may, for example, be used by an individual so solve a
complex engineering problem. The advent of the microprocessor, however, means that is now possible
to have the power of a computer in a single integrated circuit, and consequently the range of
,applications is now virtually unlimited. It is widely predicted that in the near future computers will be
found in almost every area of human endeavor.
9.2 MODE OF OPERATION
Basically, all digital computers operate in the way which to a large extent is independent of the specific
application to which they are being put. This arises because a computer -large or small -is a flexible
general-purpose machine or device that can be arranged to solve or implement a particular task after it
has been produced by a manufacturer.

135
A task is implemented by deciding the sequence of operations needed to perform it. Consider a basic
electronic calculator which offers the user a variety of operations add, subtract, multiply, etc. It is then
up to the user to select the particular sequence of these operations necessary to solve a specific
problem. Similarly a digital computer can perform a number of basic operations, called machine
instructions, which solves a particular problem. This sequential list of operations is referred to as a
program.
An electronic calculator executes each of its basic operations in typically a few milliseconds.
Consequently the time taken to solve a problem with a calculator is determined primarily by the rate at
which the user keys in the individual operations. The intrinsically high speed of execution of each
operation is therefore lost. A digital computer, however, utilizes the very high speed of execution of
each machine instruction usually a few microseconds by having the required sequence of instructions, or
program, stored within the computer itself. This is known as the stored program control (SPC) and is the
fundamental difference between a basic calculator and a computer system.
BITS AND BYTES
All information within a digital computer is represented in a binary form both the input data to be
manipulated and the coded instructions which control the various machine operations. The number of
binary digits, or bits used to make up the basic unit of information in a computer varies from one
machine to another; for example 4, 8, 16, 24 and 32 bits have all been used in different machines.
Microprocessor systems often use either 8 or 16 bits for the basic unit of information or word. An 8-bit
group is referred to as a byte. So a 16-bit word is equivalent to two bytes.
When examining the operation of a microprocessor system, therefore, binary patterns are always being
considered. This can be very tedious for the programmer who is, when communicating this information,
prone to make errors. It is for these reasons that alternative methods are often used to convey binary
information between humans.
The method used is to group a number of bits together, and then represent that group with an
equivalent coded number or character. The most commonly used method is hexadecimal (base 16)
coding which is based on a 4-bit group. There 3.t'e sixteen combinations of four binary digits and hence
sixteen symbols or characters are required. The sixteen symbols used are the numeric digits 0-9 plus the
six alphabetic characters A-F. The binary codes and corresponding hexadecimal symbols are shown in
table 1.

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4 bit binary pattern Hexadecimal symbol

0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
1010 A
1011 B
1100 C
1101 D
1110 E
1111 F
Table 1 Hexadecimal numbers.
Some examples of binary patterns and their equivalent hexadecimal I (hex) representation are given
below:
0110 1101 = 6D (hex.)
1111 0010 = F2 (hex)
1011 0100 1000 1110 = B48E (hex)
9.3 BASIC STRUCTURE OF COMPUTER SYSTEM
A digital computer executes a list of basic machine instructions (a program) which have been selected
and ordered by the user to solve a particular task. In order to exploit the intrinsic high speed of-
execution of each machine instruction, the program is stored within the computer. In addition, all
information stored within the computer both machine instructions and data is represented in a binary
coded form. Thus a basic digital computer is comprised of a memory, which is primarily used to hold or
store the program, a microprocessor (often referred to it as the central processing unit or CPU) which
executes the individual machine instructions which make up the program, and some input/output ports
(1/0). These ports form the interface between the computer and the source of the input data and the
subsequent output data. The complete combination of microprocessor, memory and input/output ports
is collectively referred to as a micro-computer and is illustrated in figure 9.1.

137
Once the program has been evolved for the task, the computer program is loaded into memory and. is
then executed. During program execution, each machine instruction is accessed sequentially fromthe
memory and then executed by the microprocessor. The microprocessor therefore, operates in a two
phase mode: during the first phase, the fetch cycle, the next instruction is fetched from memory then, in
the second phase or execution cycle the microprocessor executes (or performs) the action specified by
the instruction.
In order to remember which program instruction is to be executed next, the microprocessor contains a
register (or temporary information storage location) called the program counter (PC), the contents of
which points to the next sequential instruction to be fetched and executed. Thus, during a typical
instruction cycle, the next instruction to be executed is read from the memory location indicated by the
contents of the program counter. While this instruction is being executed, the contents of the program
counter is incremented to point to the next instruction. This is summarized in Figure 9.2.

138
Microprocessor instructions often require more than one byte of information usually 1, 2 or 3 bytes are
required. Thus an instruction fetch cycle may consist of up to 3 memory read operations performed on
Successive memory locations. During the execution phase of this instruction, however, the program
counter still points to the address of the first byte of the instruction that would normally be fetched
next.
9. 4 BASIC FUNCTIONAL UNITS
The basic functional units of a micro-computer were indicated in the previous sub-chapter. These
comprise the microprocessor itself (the CPU), the memory which is used. primarily to hold the stored
program, and some input/output ports which are used to interface the microcomputer to the various
input/output devices controlled by it.
9.4.1 THE MICROPROCESSOR
The microprocessor can execute a number of basic machine instructions. Examples are: individual data
byte manipulation instructions (e.g. add, subtract, etc.) and memory transfer instructions (e.g. read data
byte from memory, write data byte to memory, etc.). Information is transferred between external
devices and the computer system via the input and output ports, and consequently the microprocessor
has machine instructions to both read data from a specified port (input) and to write data to a port
(output).
Basically a microprocessor is comprised, as far as a user is concerned, of the three sections shown in
figure 9.3.
The register section contains a number of registers or temporary storage elements which can each hold
or store a single byte or word. The arithmetic logic unit (ALU) performs the actual data manipulation
operations, and the timing and control section co-ordinates the internal operation of the
microprocessor and controls operation of the ALU and registers so that the desired action specified by
an instruction is performed.

139
The microprocessor communicates with the memory, both to obtain the individual instructions which
make up the program and to access and store data, and to transfer data to and from input and output
ports using a highway or bus.
9.4.2 MEMORY
The memory consists of a number of location each individually identified by an address. Each location
contains a binary pattern with a number of bits corresponding to the word length of the computer
(typically 8 bits). The binary pattern stored at an address is referred to as the contents of that address.
In a microcomputer system the memory is usually comprised of two types: random access memory
(RAM) and read only memory (ROM). Basically RAM (more appropriately called read/write memory but
universally referred to as RAM) has the capability of having information both written into and read out
of each location and is often used for storing intermediate results (data) during a computation. ROM has
information fixed into it either during its manufacture or by the user and consequently can only be
operated in a read only mode
For many dedicated microprocessor applications ROM is used to hold the fixed program. It has the
advantage of being non-volatile which means that when its power supplies are removed the stored
information is not lost. RAM is normally volatile unless the special design features of certain types are
exploited.
9.4.3 HIGHWAY STRUCTURE
The computer highway consists of three separate busses: the data bus, the address bus ,and the Control
bus. This is shown in figure 9.4.
The data bus is used to carry the data associated with a memory or input/output transfer and is typically
8 bits wide.
The address bus is used to specify the memory location or input/output port involved in a transfer.
The control bus is made up or the various control lines generated by the microprocessor and other
system components to synchronize transfers.

140
THE DATA BUS
The data bus of many computers and particularly microprocessor based computers is bidirectional. That
is, the processor can write data on to the bus lines to read by, for example, a memory device or it can
read data from the bus presented by such a device. Hence data can be transferred from the processor to
a device or from a device to the processor over a single set of data lines. This is a particularly desirable
mechanism in a microprocessor system since it is not necessary for the microprocessor to have both
data input and output pins. A practical limit to the number of available pairs on a microprocessor
integrated circuit makes it important for the manufacturer to use those available efficiently.
It becomes possible to make a single pin logic input and output by incorporating, within the
microprocessor logic output gates, a third output state in addition to the normal 0 and 1 signals. This
third state is a high impedance condition where the output is effectively switched off. A select input to
the gate is used to force the output to this off state. This is illustrated in fig.9.5.
Devices of this type can be used to form a bidirectional bus. The microprocessor end of the bus can be
either an input or an output (but not both simultaneously) depending on the direction selection control.
The same applies to the memory or input/output end of the bus. Control signals ensure that the
direction of data flow at the end of the bus is synchronized.
THE ADDRESS BUS
The address bus consists typically of 16 lines on which a binary coded address can be presented to a
memory or input/output port.The range of possible addresses is therefore from 0000 (hex) to FFFF
(hex), i.e. 65536 separate addresses. Thus a typical microprocessor can address to 65536 memory
locations each containing 8 bits (or one byte) of information. The size of a computer memory is often
measured in units of 1024 locations this unit is designed 1K. Hence most microprocessor systems can
have a maximum of 64K memory locations.
For many microprocessor applications it is not necessary to use all the possible memory addresses in the
system. The range of addresses that are used and the type of memory in each range is indicated by a
memory map memory map for a small but typical microcomputer system is shown in figure 9.6. The
figure shows that the system has 2K (0000→ 07FF) bytes of ROM and 256 (2000 →20FF) bytes of RAM.

141
THE CONTROL BUS
The control bus incorporates the timing signals which are generated by, the microprocessor to
synchronize information transfers between the microprocessor and a memory or input/output port.
Consider the timing diagram shown in figure 9.7.
The figure illustrates the two control signals -read (RD) and write -(WR) --generated by the
microprocessor during two successive instruction cycles. The example assumes both are single byte
instructions; the first is a memory (or output port) write. The type of transfer -memory or input/output -
will be determined by the memory map and the specific address output by the microprocessor during
each execute cycle.

142
9.4.4 ADDRESS DECODING
Since there are a number of devices connected to the computer highway ROM and RAM chips,
input/output devices, etc. it is necessary to ensure that only the device intended for the data transfer
responds when a request is made by the microprocessor.This is accomplished by the each device
connected to the highway having a chip-select (CS) control input and only when this input is activated
does a device respond to the various requests issued on the control bus.
The memory map is used to define the address range of each device connected to the bus. Each device
therefore, has an additional logic circuit associated with it which detects when an address intended for
that device is present on the bus. This is known an address decoder and its output is used to activate the
chip -select input of the device.
In practice only the most significant address bits need be decoded since the least significant address bits
are used by the device itself to determine, for example, the specific location within the selected memory
device. This is shown in figure 9.8.
9.5 EXERCISES
1) Explain the concept of "stored program control" (SPC).
2) What is meant, by the following terms
(i) Bit
(ii) Byte, and
(iii) Word
with regard to microcomputers.

143
3) Explain the use of hexadecimal coding
4) Convert the following decimal numbers into their equivalent hexadecimal number: 27,96,256,
3334.
5) Convert the following hexadecimal numbers into their equivalent decimal numbers: C3, 2F,
2C9E, B48E.
6) Give an outline of the basic structure of a microcomputer system.
7) Describe the build-up of a microprocessor.
8) Explain the terms ROM and RAM used with computer memories.
9) Determine the maximum memory space for an 8-bit microprocessor which has a 14-bit address
word. Express your answer in K bytes.
10) A microcomputer system requires 4K bytes of f1:0M and 256 bytes of RAM. Determine the start
and end addresses of each memory block if the two memories are to occupy adjacent blocks of
memory starting at address 0000 (hex). Express your answer in hex notation.
11) A microcomputer system has the following memory map:
0000 → OFFF ROM
2000 → 21FF RAM
4000 → 400F I/O
Determine the amount of ROM and RAM memory and the number of I/O ports in the system.
12) Give an outline of the highway structure within a computer system and indicate the use of the
data-, address- and control bus.
END

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1

INTRODUCTION TO DIGITAL TECHNIQUES

1.1. DIFFERENCE BETWEEN ANALOGUE AND DIGITAL SIGNALS

1.2. ADVANTAGES OF DIGITAL TECHNIQUES

1.3. DIGITAL SYSTEMS

1.3.1. THE DIGITAL COMPUTER AND THE MICROPROCESSOR

1.3.2. VARIOUS DIGITAL EQUIPMENT

1.3.3. TELEPHONE TRANSMISSION SYSTEMS

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1.1. DIFFERENCE BETWEEN ANALOGUE AND DIGITAL SIGNALS

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1.2. ADVANTAGES OF DIGITAL TECHNIQUES

1.3. DIGITAL SYSTEMS

1.3.1. THE DIGITAL COMPUTER AND THE MICROPROCESSOR

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1.3.2. VARIOUS DIGITAL EQUIPMENT

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1.3.3. TELEPHONE TRANSMISSION SYSTEMS

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NUMBER SYSTEMS AND CODES

2.1 NUMBER SYSTEMS

3. Octal -it has a base of 8 i.e. uses eight different symbols.

4. hexadecimal -it has a base of 16 i.e. it uses sixteen different symbols.

-decimal system uses powers of 10

-binary system uses powers of 2

-octal system uses powers of 8

-hexadecimal system uses powers of 16

2.2 THE DECIMAL NUMBER SYSTEM

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ii. Position value

Similarly, the number 2573 can be broken down as follows:

2573 = 2 𝑥 103 + 5 𝑥 102 + 7 𝑥 101 + 3 𝑥 100

Again, the number 2573.469 can be written as

2573.469 = 2 𝑥 103 + 5 𝑥 102 + 7 𝑥 101 + 3 𝑥 100 + 4 𝑥 10-1+ 6 𝑥 10-2+ 9 𝑥 10-3

2.3 BINARY SYSTEM

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ii. Position Value

1101.0112 = (1𝑥23) + (1𝑥22) + (0𝑥21) + (1𝑥20) + (0𝑥2-1) + (1𝑥2-2) + (1𝑥2-3)

= 8 + 4 + 0 + 1 + 0 + 1/4 + 1/8 = 13.37510

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2.3.1 BINARY TO DECIMAL CONVERSION

Step 1 Write the binary number i.e. its bit in a row

Step 4 Add the remaining weights to get the decimalequivalent

Example 2.1 Convert 110012 to its equivalent decimal number

The four steps involved in the conversion are as under:

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Decimal Binary Decimal Binary Decimal binary

2.3.2 BINARY FRACTIONS

2-1 2-2 2-3 2-4

The following four steps will be used for this purpose.

Step 4 ½ + 1/8= 0.625

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4 2 1 ½ ¼ 1/8 = 5 + 1/2 +1/8 = 5.625

2.3.3 DOUBLE-DADD METHOD

1. 2x1 = 2 add next bit 1 sothat 2+1 = 3

2. 2x3 = 6 add next bit 1 sothat 6+1 = 7

3. 2x7 = 14 add next bit 0 so that 14+0 = 14

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4. 2x14 = 28 add next bit 1 so that 28+1 = 29

5. 2x29 = 58, add next bit 0 so that 58+0 = 58

2.3.4 DECIMAL TO BINARY CONVERSION

The above process may be simplified as under: